--- zzzz-none-000/linux-5.4.213/drivers/irqchip/irq-gic.c	2022-09-15 10:04:56.000000000 +0000
+++ miami-7690-761/linux-5.4.213/drivers/irqchip/irq-gic.c	2024-05-29 11:19:51.000000000 +0000
@@ -47,6 +47,9 @@
 
 #include "irq-gic-common.h"
 
+#include <avm/power/power.h>
+#include <avm/profile/profile.h>
+
 #ifdef CONFIG_ARM64
 #include <asm/cpufeature.h>
 
@@ -90,7 +93,8 @@
 
 #ifdef CONFIG_BL_SWITCHER
 
-static DEFINE_RAW_SPINLOCK(cpu_map_lock);
+DEFINE_RAW_SPINLOCK(cpu_map_lock);
+EXPORT_SYMBOL(cpu_map_lock);
 
 #define gic_lock_irqsave(f)		\
 	raw_spin_lock_irqsave(&cpu_map_lock, (f))
@@ -156,6 +160,12 @@
 #define gic_set_base_accessor(d, f)
 #endif
 
+struct irq_domain *get_irq_domain( void )
+{
+	struct gic_chip_data *gic = &gic_data[0];
+	return( gic->domain );
+}
+
 static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
@@ -349,11 +359,17 @@
 
 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 {
-	u32 irqstat, irqnr;
+	u32 irq_handled, irqstat, irqnr;
 	struct gic_chip_data *gic = &gic_data[0];
 	void __iomem *cpu_base = gic_data_cpu_base(gic);
 
+	avm_simple_profiling_enter_irq_context(regs->ARM_pc, regs->ARM_lr);
+	avm_cpu_wait_end();  /*auch wenn es wait_irqoff gibt: trotzdem aufrufen, um system-load-Ausgabe zu triggern  */
+	irq_handled = 0;
+
 	do {
+		dsb(sy);
+
 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
 
@@ -362,9 +378,11 @@
 				writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 			isb();
 			handle_domain_irq(gic->domain, irqnr, regs);
+			irq_handled = 1;
 			continue;
 		}
-		if (irqnr < 16) {
+		if (likely(irqnr < 16)) {
+		   /* NON-SECURE IPI */
 			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
 			if (static_branch_likely(&supports_deactivate_key))
 				writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
@@ -377,8 +395,11 @@
 			 * Pairs with the write barrier in gic_raise_softirq
 			 */
 			smp_rmb();
+			avm_simple_profiling_log(avm_profile_data_type_hw_irq_begin, 0, irqnr);
 			handle_IPI(irqnr, regs);
+			avm_simple_profiling_log(avm_profile_data_type_hw_irq_end, 0, irqnr);
 #endif
+			irq_handled = 1;
 			continue;
 		}
 		break;
@@ -394,7 +415,9 @@
 
 	chained_irq_enter(chip, desc);
 
+	_raw_spin_lock(&irq_controller_lock);
 	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
+	_raw_spin_unlock(&irq_controller_lock);
 
 	gic_irq = (status & GICC_IAR_INT_ID_MASK);
 	if (gic_irq == GICC_INT_SPURIOUS)
@@ -820,7 +843,7 @@
 	dmb(ishst);
 
 	/* this always happens on GIC0 */
-	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+        writel_relaxed(map << 16 | (1 << 15) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 
 	gic_unlock_irqrestore(flags);
 }
@@ -1028,6 +1051,24 @@
 	return -EINVAL;
 }
 
+void gic_trigger_irq(unsigned int intr, unsigned int set)
+{
+	struct irq_desc *desc = irq_to_desc(intr);
+	struct irq_data *d = 0;
+	u32 mask = 0;
+
+	if (desc == NULL) return;
+	d = &desc->irq_data;
+	mask = 1 << (d->hwirq % 32);
+
+	if (set) {
+		writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_PENDING_SET + (d->hwirq/ 32) * 4);
+	} else {
+		writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_PENDING_CLEAR + (d->hwirq / 32) * 4);
+	}
+}
+EXPORT_SYMBOL(gic_trigger_irq);
+
 static int gic_starting_cpu(unsigned int cpu)
 {
 	gic_cpu_init(&gic_data[0]);