--- zzzz-none-000/linux-5.4.213/drivers/pinctrl/qcom/pinctrl-msm.c	2022-09-15 10:04:56.000000000 +0000
+++ miami-7690-761/linux-5.4.213/drivers/pinctrl/qcom/pinctrl-msm.c	2024-05-29 11:19:59.000000000 +0000
@@ -522,6 +522,41 @@
 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 }
 
+#ifdef CONFIG_GPIOLIB_AVM_EXTENSION
+static int msm_gpio_set_mux(struct gpio_chip *chip, unsigned int group, unsigned int function)
+{
+	struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
+	const struct msm_pingroup *g;
+
+	if (group >= pctrl->soc->ngroups) {
+		return -EINVAL;
+	}
+
+	g = &pctrl->soc->groups[group];
+
+	if (function >= g->nfuncs)
+		return -EINVAL;
+
+	return msm_pinmux_set_mux(pctrl->pctrl, g->funcs[function], group);
+}
+
+static int msm_gpio_get_func(struct gpio_chip *chip, unsigned int offset)
+{
+	u32 ctl_reg, func;
+	const struct msm_pingroup *g;
+	struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
+
+	if (offset >= pctrl->soc->ngroups)
+		return -EINVAL;
+
+	g = &pctrl->soc->groups[offset];
+	ctl_reg = msm_readl_ctl(pctrl, g);
+	func = (ctl_reg >> g->mux_bit) & 7;
+
+	return (int)func;
+}
+#endif
+
 #ifdef CONFIG_DEBUG_FS
 #include <linux/seq_file.h>
 
@@ -653,6 +688,10 @@
 	.request          = gpiochip_generic_request,
 	.free             = gpiochip_generic_free,
 	.dbg_show         = msm_gpio_dbg_show,
+#ifdef CONFIG_GPIOLIB_AVM_EXTENSION
+	.set_function	  = msm_gpio_set_mux,
+	.get_function	  = msm_gpio_get_func,
+#endif
 };
 
 /* For dual-edge interrupts in software, since some hardware has no
@@ -688,7 +727,7 @@
 
 		pol = msm_readl_intr_cfg(pctrl, g);
 		pol ^= BIT(g->intr_polarity_bit);
-		msm_writel_intr_cfg(pol, pctrl, g);
+		msm_writel_intr_cfg(val, pctrl, g);
 
 		val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
 		intstat = msm_readl_intr_status(pctrl, g);