--- zzzz-none-000/linux-5.4.213/drivers/spi/spi-qup.c	2022-09-15 10:04:56.000000000 +0000
+++ miami-7690-761/linux-5.4.213/drivers/spi/spi-qup.c	2024-05-29 11:20:02.000000000 +0000
@@ -857,7 +857,7 @@
 	timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
 	timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
 				     xfer->len) * 8, timeout);
-	timeout = 100 * msecs_to_jiffies(timeout);
+	timeout = 200 * msecs_to_jiffies(timeout);
 
 	reinit_completion(&controller->done);
 
@@ -1000,8 +1000,8 @@
 	struct resource *res;
 	struct device *dev;
 	void __iomem *base;
-	u32 max_freq, iomode, num_cs;
-	int ret, irq, size;
+	u32 max_freq, iomode, num_cs, cs_select;
+	int ret, irq, size, disable_force_cs = 0;
 
 	dev = &pdev->dev;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1030,6 +1030,14 @@
 		return -ENXIO;
 	}
 
+	/* Use cs-select dt-property to configure QUP SPI chip select.
+	 * Default chip select is 0.
+	 */
+	if (of_property_read_u32(pdev->dev.of_node, "cs-select", &cs_select)) {
+		dev_dbg(dev, "cs-select not found\n");
+		cs_select = 0;
+	}
+
 	ret = clk_prepare_enable(cclk);
 	if (ret) {
 		dev_err(dev, "cannot enable core clock\n");
@@ -1086,8 +1094,12 @@
 
 	controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
 
+	if (of_find_property(dev->of_node, "qcom,disable-force-cs", NULL))
+		disable_force_cs = 1;
+
 	if (!controller->qup_v1)
-		master->set_cs = spi_qup_set_cs;
+		if (!disable_force_cs)
+			master->set_cs = spi_qup_set_cs;
 
 	spin_lock_init(&controller->lock);
 	init_completion(&controller->done);
@@ -1140,7 +1152,8 @@
 			base + QUP_ERROR_FLAGS_EN);
 
 	writel_relaxed(0, base + SPI_CONFIG);
-	writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
+	writel_relaxed(SPI_IO_C_NO_TRI_STATE | SPI_IO_C_CS_SELECT(cs_select),
+		       base + SPI_IO_CONTROL);
 
 	ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
 			       IRQF_TRIGGER_HIGH, pdev->name, controller);