--- zzzz-none-000/linux-5.4.213/include/dt-bindings/clock/qcom,gcc-ipq8074.h	2022-09-15 10:04:56.000000000 +0000
+++ miami-7690-761/linux-5.4.213/include/dt-bindings/clock/qcom,gcc-ipq8074.h	2024-05-29 11:20:02.000000000 +0000
@@ -230,6 +230,21 @@
 #define GCC_GP1_CLK				221
 #define GCC_GP2_CLK				222
 #define GCC_GP3_CLK				223
+#define GCC_CRYPTO_PPE_CLK 			224
+#define PCIE0_RCHNG_CLK_SRC 			225
+#define PCIE0_RCHNG_CLK 			226
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 		227
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 		228
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 		229
+#define GCC_DCC_CLK 				230
+#define ADSS_PWM_CLK_SRC 			231
+#define GCC_ADSS_PWM_CLK 			232
+#define QDSS_TSCTR_CLK_SRC 			233
+#define QDSS_AT_CLK_SRC 			234
+#define GCC_QDSS_AT_CLK 			235
+#define GCC_QDSS_DAP_CLK 			236
+#define AUDIO_PLL                               237
+#define AUDIO_PLL_MAIN                          238
 
 #define GCC_BLSP1_BCR				0
 #define GCC_BLSP1_QUP1_BCR			1
@@ -362,5 +377,21 @@
 #define GCC_PCIE1_AXI_SLAVE_ARES		128
 #define GCC_PCIE1_AHB_ARES			129
 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
+#define GCC_WCSSAON_RESET			131
+#define GCC_PPE_FULL_RESET			132
+#define GCC_UNIPHY0_SOFT_RESET			133
+#define GCC_UNIPHY0_XPCS_RESET			134
+#define GCC_UNIPHY1_SOFT_RESET			135
+#define GCC_UNIPHY1_XPCS_RESET			136
+#define GCC_UNIPHY2_SOFT_RESET			137
+#define GCC_UNIPHY2_XPCS_RESET			138
+#define GCC_EDMA_HW_RESET			139
+#define GCC_NSSPORT1_RESET			140
+#define GCC_NSSPORT2_RESET			141
+#define GCC_NSSPORT3_RESET			142
+#define GCC_NSSPORT4_RESET			143
+#define GCC_NSSPORT5_RESET			144
+#define GCC_NSSPORT6_RESET			145
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 	146
 
 #endif