// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/dts-v1/;

#define __IPQ_MEM_PROFILE_512_MB__ 1

#include "ipq5332-512MB-memory.dtsi"
#include "ipq5332-avm-common.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "FRITZ!Repeater 2400W7";

	avm-wkk-extra-resets {
		compatible = "avm,gpio-aggregator";
		pinctrl-0 = <&avm_wkk_extra_reset_pins>;
		pinctrl-names = "default";

		gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
		gpio-line-names = "wkk_5g_reset";
	};

	avm-hui {
		compatible = "avm,hui";
		pinctrl-names = "default";
		pinctrl-0 = <&avm_connect_gpio>;
		status = "ok";

		repeater-connect {
			compatible = "avm,hui-generic-button-gpio";
			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
		};

		// LEDs use a special byte order, same as FR 3000 AX
		colors {    //  r       b       g
			normal = <0x40>, <0x00>, <0x8C>;
			warn   = <0x8C>, <0x00>, <0x46>;
			error  = <0x8C>, <0x00>, <0x00>;
		};
	};

	soc {
		pinctrl@1000000 {
			/* ina2xx pins*/
			ina2xx_i2c_pins: ina2xx-i2c-pins {
				pins = "gpio43", "gpio45"; /* SCL, SDA */
				function = "blsp2_i2c0";
				drive-strength = <8>;
				bias-disable;
			};

			/* ina2xx alert pin */
			ina2xx_alert_pin: ina2xx-alert-pin {
				pins = "gpio24";
				drive-strength = <8>;
				bias-disable;
			};

			avm_wkk_extra_reset_pins: avm-wkk-extra-reset-pins {
				wkk_5g_pin {
					pins = "gpio49";
					function = "gpio";
					drive-strength = <8>;
					output-high;
				};
			};

			avm_connect_gpio: avm_connect_gpio {
				pins = "gpio23";
				function = "gpio";
				drive-strength = <2>;
				bias-disable;
			};

			mdio1_pins: mdio_pinmux {
				mux_0 {
					pins = "gpio27";
					function = "mdc1";
					drive-strength = <8>;
					bias-disable;
				};
				mux_1 {
					pins = "gpio28";
					function = "mdio1";
					drive-strength = <8>;
					bias-pull-up;
				};
			};

			blsp1_spi1_pins: blsp1_spi1_pins {
				mux {
					pins = "gpio32", "gpio29";
					function = "blsp1_spi1";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		/* BLSP3 which is configured from spi to i2c */
		i2c_2: i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency  = <400000>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
			dma-names = "tx", "rx";

			pinctrl-0 = <&ina2xx_i2c_pins>;
			pinctrl-names = "default";
			status = "ok";

			ina236@40 {
				compatible = "ti,ina236";
				reg = <0x40>;
				pinctrl-0 = <&ina2xx_alert_pin>;
				pinctrl-names = "default";
				shunt-resistor = <15000>;
				interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>;
				interrupt-names = "alert";
				alert-type = <12>; /* bus undervoltage */
				alert-limit = <4500>; /* 4,5V */
			};
		};

		spi1: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		avm_mac_addr_maceth_0: dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a504000 0x4000>;
			qcom,mactype = <1>;
			mac-address = [000000000000];
			mdio-bus = <&mdio>;
			qcom,phy-mdio-addr = <28>;
			qcom,link-poll = <1>;
			devname = "eth0";
			phy-mode = "sgmii";
		};

		mdio:mdio@90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			status = "ok";
			pinctrl-0 = <&mdio1_pins>;
			pinctrl-names = "default";
			/*gpio51 for nappa reset*/
			phy-reset-gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
			phyaddr_fixup = <0xC90F018>;
			uniphyaddr_fixup = <0xC90F014>;
			mdio_clk_fixup; /* MDIO clock sequence fix up flag */

			phy0: ethernet-phy@0 {
				reg = <28>;
			};
		};

		ess-instance {
			num_devices = <0x1>;
			ppe_switch: ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0x4>; /* lan port bitmap */
				switch_wan_bmp = <0x0>; /* wan port bitmap */
				switch_mac_mode = <0x0c>; /* mac mode for uniphy instance0*/
				switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/

				qcom,port_phyinfo {
					port@0 {
						port_id = <2>;
						phy_address = <28>;
					};
				};
			};
		};

		/* EDMA host driver configuration for the board */
		edma@3ab00000 {
			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
					  <12 13 14 15>,	/* MHT-Port1 per-core Tx ring map */
					  <4 5 6 7>,            /* MHT-Port2 per-core Tx ring map/packets from  vp*/
					  <16 17 18 19>,        /* MHT-Port3 per-core Tx ring map */
					  <20 21 22 23>;        /* MHT-Port4 per-core Tx ring map */
			qcom,txdesc-fc-grp-map = <1 2>;		/* Per GMAC flow control group map */
			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
			qcom,rx-queue-start = <0>;		/* Rx queue start */
			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
				   <0 191 4>,			/* Misc error IRQ info */
				<0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
				<0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
				<0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
				<0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
				<0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
				<0 153 4>;			/* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
		};
	};
};

/* nand */
&nand {
	status = "ok";
};

&qpic_bam {
	status = "ok";
};

//TODO: Verify wifi configuration

/* WiFi global memory */
&mlo_global_mem0 {
	reg = <0x0 0x4DB00000 0x0 0x00C00000>;
	status = "ok";
};

&pcie2_phy {
	status = "ok";
};

/* Waikiki 5G */
&pcie2 {
	status = "ok";
	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
};
&pcie2_rp {
	#address-cells = <5>;
	#size-cells = <0>;
	reg = <0 0 0 0 0>;

	wifi@2 {
		reg = <0 0 0 0 0>;
		qrtr_node_id = <0x31>;
		memory-region = <0>,<&mhi_region1>;
		qti,disable-rddm-prealloc;
		qti,rddm-seg-len = <0x1000>;
		status = "ok";
	};
};
&pci2_pin {
	pins = "gpio38";
};

&qcn9224_pcie1 {
	status = "ok";
};

&mhi_region1 {
	status = "ok";
	size = <0x0 0x00f00000>;
};

&wifi2 {
	hremote_node = <&qcn9224_pcie1>;
	board_id = <0x0002>;
	status = "ok";
	qrtr_node_id = <0x30>;
};

&wifi0 {
	status = "ok";
	qcom,rproc = <&q6_wcss_pd1>;
	qcom,rproc_rpd = <&q6v5_wcss>;
	qcom,multipd_arch;
	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
	mem-region = <&q6_region>;
	qcom,board_id = <0x16>;
};

/* Remove unused avm special mac address definitions */
/delete-node/ &avm_mac_addr_macrouter_3;
/delete-node/ &avm_mac_addr_macvoip_0;