// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
#ifndef HW298_DTS_INCLUDED
#define HW298_DTS_INCLUDED
/dts-v1/;

#include "ipq5332-default-memory.dtsi"
#include "ipq5332-avm-common.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "FRITZ!Box 5690 GPON";

	aliases {
		serial1 = &blsp1_uart1;
	};

	avm-wkk-extra-resets {
		compatible = "avm,gpio-aggregator";
		pinctrl-0 = <&avm_wkk_extra_reset_pins>;
		pinctrl-names = "default";

		gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
		gpio-line-names = "wkk_5g_reset";
	};

	/* This is only needed in GPON mode. So it will be explicitly activated in the overlay */
	avm_rtl_gpio: avm-rtl {
		status = "disabled";
		compatible = "avm,gpio-aggregator";
		gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>,
			<&tlmm 47 GPIO_ACTIVE_HIGH>,
			<&tlmm 17 GPIO_ACTIVE_HIGH>;
		gpio-line-names = "rtl-power-on", "alder-rtl-panic", "rtl-alive-panic";
	};

	dect_gpio: dect-gpio {
		compatible = "avm,gpio-aggregator";
		gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>,
			<&tlmm 16 GPIO_ACTIVE_HIGH>;
		gpio-line-names = "DECT_RST", "DECT_RD";
	};

	/* measure clock and fs from tdm-interface (piglet, pcmlink) */
	tdmclkfs_gpio: tdmclkfs-gpio {
		compatible = "avm,gpio-aggregator";
		gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>,
			<&tlmm 36 GPIO_ACTIVE_HIGH>;
		gpio-line-names = "TDM_FS", "TDM_CLK";
	};

	avm-hui {
		compatible = "avm,hui";
		pinctrl-0 = <&avm_led_pins>;
		pinctrl-names = "default";
		status = "ok";

		dim_leds: dim-leds {
			brightness-range = <0>, <255>;
			compatible = "avm,hui-generic-led-pwm";
			led-type = "default-on";
			/* GPIO 29 is channel 3 */
			pwms = <&pwm 3 1000000>;
			dimmable;
		};

		box-power@0 {
			compatible = "avm,hui-generic-led-gpio";
			gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
			location = <1>;
		};

		box-wlan@0 {
			compatible = "avm,hui-generic-led-gpio";
			gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
			location = <2>;
		};

		box-fon-dect@0 {
			compatible = "avm,hui-generic-led-gpio";
			gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
			location = <3>;
		};

		connect@0 {
			compatible = "avm,hui-generic-led-gpio";
			gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
			location = <4>;
		};

		box_info: info {
			compatible = "avm,hui-generic-led-gpio";
			gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>,
					<&tlmm 2 GPIO_ACTIVE_HIGH>;
			location = <5>;
			colors {
					normal = <0x00>, <0xFF>, <0x00>;
					error  = <0xFF>, <0x00>, <0x00>;
			};
		};

		box-wlan@1 {
			compatible = "avm,hui-generic-button-gpio";
			gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
		};

		box-fon@1 {
			compatible = "avm,hui-generic-button-gpio";
			gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
		};

		box-connect@1 {
			compatible = "avm,hui-generic-button-gpio";
			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
		};
	};

	soc {
		pinctrl@1000000 {
			wan_switcher_pin: wan-switcher-pin {
				pins = "gpio14";
				function = "gpio";
				drive-strength = <8>;
				output-low;
			};

			/* The following two nodes will be enabled by the corresponding overlays */
			gpon_on_wan_off_hog: gpon-on-wan-off-hog {
				status = "disabled";
				gpio-hog;
				gpios = <14 GPIO_ACTIVE_HIGH>;
				output-low;
			};

			gpon_off_wan_on_hog: gpon-off-wan-on-hog {
				status = "disabled";
				gpio-hog;
				gpios = <14 GPIO_ACTIVE_HIGH>;
				output-high;
			};

			/* When in wan mode Realtek shall be held in off state */
			rtk_disable: rtk-disable {
				status = "disabled";
				gpio-hog;
				gpios = <48 GPIO_ACTIVE_HIGH>;
				output-low;
			};

			/* ina2xx pins*/
			ina2xx_i2c_pins: ina2xx-i2c-pins {
				pins = "gpio43", "gpio45"; /* SCL, SDA */
				function = "blsp2_i2c0";
				drive-strength = <8>;
				bias-disable;
			};

			/* ina2xx alert pin */
			ina2xx_alert_pin: ina2xx-alert-pin {
				pins = "gpio24";
				drive-strength = <8>;
				bias-disable;
			};

			/* DECT + Fiber RTK */
			serial_1_pins: serial1-pinmux {
					pins = "gpio16", "gpio15";  /* RX, TX */
					function = "blsp1_uart0";
					drive-strength = <8>;
					bias-disable;
			};

			avm_wkk_extra_reset_pins: avm-wkk-extra-reset-pins {
				wkk_5g_pin {
					pins = "gpio44";
					function = "gpio";
					drive-strength = <8>;
					output-high;
				};
			};

			usb_pw_en_pins: usb_pwr_en_pinmux {
				pins = "gpio49";
				function = "gpio";
				drive-strength = <8>;
				bias-disable;
				output-low;
			};

			/* pcmlink */
			audio_pins_pri: audio_pinmux_pri {
				mux_0 {
					pins = "gpio30";        /* TDM-DI */
					function = "audio_pri";
					drive-strength = <8>;
					bias-pull-up;
				};

				mux_1 {
					pins = "gpio31";	 /* TDM-FS */
					function = "audio_pri";
					drive-strength = <8>;
					bias-pull-up;
					input-enable;
				};

				mux_2 {
					pins = "gpio32";         /* TDM-CLK */
					function = "audio_pri";
					drive-strength = <16>;
					bias-pull-up;
					input-enable;
				};
			};

			/* pcmlink */
			audio_pins_sec: audio_pinmux_sec {
				mux_0 {
					pins = "gpio33";	/* TDM-DO */
					function = "audio_sec";
					drive-strength = <16>;
					bias-pull-up;
				};

				mux_1 {
					pins = "gpio35";	/* TDM-FS */
					function = "audio_sec";
					drive-strength = <16>;
					bias-pull-up;
					input-enable;
				};

				mux_2 {
					pins = "gpio36";	/* TDM-CLK */
					function = "audio_sec";
					drive-strength = <16>;
					bias-pull-up;
					input-enable;
				};
			};

			/* This is an MDIO where the Miami is slave */
			mdio0_pins: mdio0_pinmux {
				mux_0 {
					pins = "gpio25";
					function = "mdc0";
					drive-strength = <2>;
					bias-pull-up;
				};
				mux_1 {
					pins = "gpio26";
					function = "mdio0";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			mdio1_pins: mdio_pinmux {
				mux_0 {
					pins = "gpio27";
					function = "mdc1";
					drive-strength = <8>;
					bias-disable;
				};
				mux_1 {
					pins = "gpio28";
					function = "mdio1";
					drive-strength = <8>;
					bias-pull-up;
				};
			};

			avm_pwm_pins: avm_pwm_pins {
				mux {
					pins = "gpio29";
					function = "pwm1";
					drive-strength = <8>;
				};
			};

			avm_led_pins: avm_led_pins {
				mux {
					pins = "gpio0", "gpio2", "gpio3", "gpio4", "gpio6", "gpio7", "gpio23", "gpio34", "gpio50";
					function = "gpio";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		avm-usb-en-gpio {
			compatible = "avm,gpio-aggregator";
			pinctrl-0 = <&usb_pw_en_pins>;
			pinctrl-names = "default";

			gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
			gpio-line-names = "usb-pwr-en";
		};


		/* USB */
		eud@78000 {
			status = "ok";
		};

		usb3@8A00000 {
			status = "ok";
			qcom,multiplexed-phy;
		};

		/* USB */
		hs_m31phy_0: hs_m31phy@7b000 {
			status = "ok";
		};

		/* BLSP3 which is configured from spi to i2c */
		i2c_2: i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency  = <400000>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
			dma-names = "tx", "rx";

			pinctrl-0 = <&ina2xx_i2c_pins>;
			pinctrl-names = "default";
			status = "ok";

			ina236@40 {
				compatible = "ti,ina236";
				reg = <0x40>;
				pinctrl-0 = <&ina2xx_alert_pin>;
				pinctrl-names = "default";
				shunt-resistor = <15000>;
				interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>;
				interrupt-names = "alert";
				alert-type = <12>; /* bus undervoltage */
				alert-limit = <10800>; /* 10,8V */
			};
		};

		pcm_avm: pcm@0xA3C0000{
			compatible = "qca,ipq5332-lpass-pcm_avm";
			reg =  <0xA3C0000 0x23014>;

			pinctrl-0 = <&audio_pins_pri>;
			pinctrl-1 = <&audio_pins_sec>;
			pinctrl-names = "primary", "secondary";
			status = "ok";

			pcm0: pcm0@0 {
				interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "out0";
				status = "ok";
			};

			pcm1: pcm1@1 {
				interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "out1";
				status = "ok";
			};
		};

		avm_mac_addr_maceth_0: dp1 {
			status = "disabled";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a504000 0x4000>;
			qcom,mactype = <1>;
			mac-address = [000000000000];
			mdio-bus = <&mdio>;
			qcom,phy-mdio-addr = <4>;
			qcom,link-poll = <1>;
			devname = "wan";
			phy-mode = "sgmii";
		};

		fiber_port: dp1_fiber {
			status = "disabled";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x3a504000 0x4000>;
			qcom,mactype = <1>;
			mac-address = [1CED6F8C44B7]; /* AVM/TMA: Assigned via JZ-107264 */
			mdio-bus = <&mdio>;
			/delete-property/ qcom,link-poll;
			/delete-property/ qcom,phy-mdio-addr;
			devname = "wanmodem";
			phy-mode = "internal";
		};

		mht_switch_port: dp2 {
			status = "ok";
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x3a500000 0x4000>;
			qcom,mactype = <1>;
			mac-address = [000000000000];
			phy-mode = "sgmii";
			devname = "gmac1";
			avm,no_pa;
			qcom,ppe-offload-disabled = <1>;
			qcom,is_switch_connected = <1>;

			qcom,mht-dev = <1>;
		};

		/* This node can stay the same in both operating modes, as the MDIO lines are not switched */
		mdio:mdio@90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			status = "ok";
			pinctrl-0 = <&mdio1_pins &mdio0_pins>;
			pinctrl-names = "default";
			/*gpio51 for manhattan reset*/
			phy-reset-gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
			phyaddr_fixup = <0xC90F018>;
			uniphyaddr_fixup = <0xC90F014>;
			mdio_clk_fixup; /* MDIO clock sequence fix up flag */

			phy0: ethernet-phy@0 {
				reg = <1>;
				fixup;
			};
			phy1: ethernet-phy@1 {
				reg = <2>;
				fixup;
			};
			phy2: ethernet-phy@2 {
				reg = <3>;
				fixup;
			};
			phy3: ethernet-phy@3 {
				reg = <4>;
				fixup;
			};
		};

		ess_switch: ess-instance {
			status = "ok";
			num_devices = <0x2>;
			ppe_switch: ess-switch@3a000000 {
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0x3E>; /* lan port bitmap */
				switch_wan_bmp = <0x0>; /* wan port bitmap */
				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0*/
				switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
				switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/

				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						forced-speed = <2500>;
						forced-duplex = <1>;
					};
					port@1 {
						port_id = <2>;
						phy_address = <4>;
					};
					mht_port1: port@2 {
						port_id = <3>;
						phy_address = <1>;
					};
					mht_port2: port@3 {
						port_id = <4>;
						phy_address = <2>;
					};
					mht_port3: port@4 {
						port_id = <5>;
						phy_address = <3>;
					};
					/* Normally not enumerated due to *an_bmp */
					mht_port4: port@5 {
						port_id = <6>;
						phy_address = <4>;
					};
				};
			};

			mht_switch: ess-switch1@1 {
				compatible = "qcom,ess-switch-qca8386";
				device_id = <1>;
				switch_access_mode = "mdio";
				mdio-bus = <&mdio>;
				switch_mac_mode = <0xc>; /* mac mode for uniphy instance0 */
				switch_mac_mode1 = <0xff>; /* mac mode1 for uniphy instance1 */
				switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
				switch_lan_bmp = <0xe>; /* lan port bitmap */
				switch_wan_bmp = <0x0>;  /* wan port bitmap */
				link-polling-required = <0>;
				link-intr-gpio = <&tlmm 46 0>;

				qcom,port_phyinfo {
					mht_cpu_link1: port@0 {
						port_id = <0>;
						forced-speed = <2500>;
						forced-duplex = <1>;
					};
					port@1 {
						port_id = <1>;
						phy_address = <1>;
					};
					port@2 {
						port_id = <2>;
						phy_address = <2>;
					};
					port@3 {
						port_id = <3>;
						phy_address = <3>;
					};
				};
			};
		};

		avm_mac_addr_maceth_1: virt-dp1 {
			compatible = "avm,ppe-virtifmgr";
			status = "ok";
			phy-mode = "sgmii";
			devname = "eth2";
			external_port = <1>;
			phy-handle = <&phy0>;
			master-handle = <&mht_switch_port>;
			external-cpu-link-handle = <&mht_cpu_link1>;
			internal-pp-handle = <&mht_port1>;
			mac-address = [000000000000];
			type = <3>;
		};

		avm_mac_addr_maceth_2: virt-dp2 {
			compatible = "avm,ppe-virtifmgr";
			status = "ok";
			phy-mode = "sgmii";
			devname = "eth1";
			external_port = <2>;
			phy-handle = <&phy1>;
			master-handle = <&mht_switch_port>;
			external-cpu-link-handle = <&mht_cpu_link1>;
			internal-pp-handle = <&mht_port2>;
			mac-address = [000000000000];
			type = <3>;
		};

		avm_mac_addr_maceth_3: virt-dp3 {
			compatible = "avm,ppe-virtifmgr";
			status = "ok";
			phy-mode = "sgmii";
			devname = "eth0";
			external_port = <3>;
			phy-handle = <&phy2>;
			master-handle = <&mht_switch_port>;
			external-cpu-link-handle = <&mht_cpu_link1>;
			internal-pp-handle = <&mht_port3>;
			mac-address = [000000000000];
			type = <3>;
		};

		/* This node is only needed in GPON Mode. So only activate it in the correspondig overlay */
		avm_mac_addr_maceth_4: virt-dp4 {
			compatible = "avm,ppe-virtifmgr";
			status = "disabled";
			phy-mode = "sgmii";
			mac-address = [000000000000];
			devname = "wan"; /* name it wan so higher layers can handle it better even though it is an eth port */
			external_port = <4>;
			phy-handle = <&phy3>;
			master-handle = <&mht_switch_port>;
			external-cpu-link-handle = <&mht_cpu_link1>;
			internal-pp-handle = <&mht_port4>;
			type = <3>;
		};

		/* EDMA host driver configuration for the board */
		edma@3ab00000 {
			qcom,txdesc-ring-start = <4>;		/* Tx desc ring start ID */
			qcom,txdesc-rings = <12>;		/* Total number of Tx desc rings to be provisioned */
			qcom,mht-txdesc-rings = <8>;		/* Extra Tx desc rings to be provisioned for MHT SW ports */
			qcom,txcmpl-ring-start = <4>;		/* Tx complete ring start ID */
			qcom,txcmpl-rings = <12>;		/* Total number of Tx complete rings to be provisioned */
			qcom,mht-txcmpl-rings = <8>;		/* Extra Tx complete rings to be provisioned for mht sw ports. */
			qcom,rxfill-ring-start = <4>;		/* Rx fill ring start ID */
			qcom,rxfill-rings = <4>;		/* Total number of Rx fill rings to be provisioned */
			qcom,rxdesc-ring-start = <12>;		/* Rx desc ring start ID */
			qcom,rxdesc-rings = <4>;		/* Total number of Rx desc rings to be provisioned */
			qcom,rx-page-mode = <0>;		/* Rx fill ring page mode */
			qcom,tx-map-priority-level = <1>;	/* Tx priority level per port */
			qcom,rx-map-priority-level = <1>;	/* Rx priority level per core */
			qcom,ppeds-num = <2>;			/* Number of PPEDS nodes */
			/* PPE-DS node format: <Rx-fill Tx-cmpl Rx Tx Queue-base Queue-count> */
			qcom,ppeds-map = <1 1 1 1 32 8>,	/* PPEDS Node#0 ring and queue map */
					<2 2 2 2 40 8>;		/* PPEDS Node#1 ring and queue map */
			qcom,txdesc-map = <8 9 10 11>,		/* Port0 per-core Tx ring map */
					  <12 13 14 15>,	/* MHT-Port1 per-core Tx ring map */
					  <4 5 6 7>,            /* MHT-Port2 per-core Tx ring map/packets from  vp*/
					  <16 17 18 19>,        /* MHT-Port3 per-core Tx ring map */
					  <20 21 22 23>;        /* MHT-Port4 per-core Tx ring map */
			qcom,txdesc-fc-grp-map = <1 2 3 4 5>;		/* Per GMAC flow control group map */
			qcom,rxfill-map = <4 5 6 7>;		/* Per-core Rx fill ring map */
			qcom,rxdesc-map = <12 13 14 15>;	/* Per-core Rx desc ring map */
			qcom,rx-queue-start = <0>;		/* Rx queue start */
			qcom,rx-ring-queue-map = <0 8 16 24>,	/* Priority 0 queues per-core Rx ring map */
						<1 9 17 25>,	/* Priority 1 queues per-core Rx ring map */
						<2 10 18 26>,	/* Priority 2 queues per-core Rx ring map */
						<3 11 19 27>,	/* Priority 3 queues per-core Rx ring map */
						<4 12 20 28>,	/* Priority 4 queues per-core Rx ring map */
						<5 13 21 29>,	/* Priority 5 queues per-core Rx ring map */
						<6 14 22 30>,	/* Priority 6 queues per-core Rx ring map */
						<7 15 23 31>;	/* Priority 7 queues per-core Rx ring map */
			qcom,avm,use-mht-rings;		/* AVM extension to enable MDIO backpressure for MHT */
			interrupts = <0 163 4>,			/* Tx complete ring id #4 IRQ info */
				   <0 164 4>,			/* Tx complete ring id #5 IRQ info */
				   <0 165 4>,			/* Tx complete ring id #6 IRQ info */
				   <0 166 4>,			/* Tx complete ring id #7 IRQ info */
				   <0 167 4>,			/* Tx complete ring id #8 IRQ info */
				   <0 168 4>,			/* Tx complete ring id #9 IRQ info */
				   <0 169 4>,			/* Tx complete ring id #10 IRQ info */
				   <0 170 4>,			/* Tx complete ring id #11 IRQ info */
				   <0 171 4>,			/* Tx complete ring id #12 IRQ info */
				   <0 172 4>,			/* Tx complete ring id #13 IRQ info */
				   <0 173 4>,			/* Tx complete ring id #14 IRQ info */
				   <0 174 4>,			/* Tx complete ring id #15 IRQ info */
				   <0 139 4>,			/* Rx desc ring id #12 IRQ info */
				   <0 140 4>,			/* Rx desc ring id #13 IRQ info */
				   <0 141 4>,			/* Rx desc ring id #14 IRQ info */
				   <0 142 4>,			/* Rx desc ring id #15 IRQ info */
				   <0 191 4>,			/* Misc error IRQ info */
				<0 160 4>,			/* PPEDS Node #1(TxComp ring id #1) TxComplete IRQ info */
				<0 128 4>,			/* PPEDS Node #1(Rx Desc ring id #1) Rx Desc IRQ info */
				<0 152 4>,			/* PPEDS Node #1(RxFill Desc ring id #1) Rx Fill IRQ info */
				<0 161 4>,			/* PPEDS Node #2(TxComp ring id #2) TxComplete IRQ info */
				<0 129 4>,			/* PPEDS Node #2(Rx Desc ring id #2) Rx Desc IRQ info */
				<0 153 4>,			/* PPEDS Node #2(RxFill Desc ring id #2) Rx Fill IRQ info */
				<0 175 4>,			/* MHT port Tx complete ring id #16 IRQ info */
				<0 176 4>,			/* MHT port Tx complete ring id #17 IRQ info */
				<0 177 4>,			/* MHT port Tx complete ring id #18 IRQ info */
				<0 178 4>,			/* MHT port Tx complete ring id #19 IRQ info */
				<0 179 4>,			/* MHT port Tx complete ring id #20 IRQ info */
				<0 180 4>,			/* MHT port Tx complete ring id #21 IRQ info */
				<0 181 4>,			/* MHT port Tx complete ring id #22 IRQ info */
				<0 182 4>;			/* MHT port Tx complete ring id #23 IRQ info */
		};
	};
};

&pwm {
	pinctrl-0 = <&avm_pwm_pins>;
	used-pwm-indices = <0>, <0>, <0>, <1>;
	pinctrl-names = "default";
	#pwm-cells = <2>;
	status = "ok";
};

/* DECT */
&blsp1_uart1 {
	pinctrl-0 = <&serial_1_pins>;
	pinctrl-names = "default";
	status = "ok";

};

/* WiFi global memory */
&mlo_global_mem0 {
	size = <0x0 0xD00000>;
	status = "ok";
};

&pcie0_phy {
	status = "disabled";
};

&pcie1_phy {
	status = "disabled";
};

/* Waikiki 5G */
&pcie2_phy {
	status = "ok";
};

&pcie0 {
	status = "disabled";
};

&pcie1 {
	status = "disabled";
};

/* Waikiki 5G */
&pci2_pin {
	pins = "gpio38";
};

&pcie2 {
	status = "ok";
	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
};

&pcie2_rp {
	#address-cells = <5>;
	#size-cells = <0>;
	reg = <0 0 0 0 0>;

	wifi@2 {
		reg = <0 0 0 0 0>;
		license-file = "qcn9224/license.dat";
		qrtr_node_id = <0x31>;
		memory-region = <0>,<&mhi_region1>;
		qti,disable-rddm-prealloc;
		qti,rddm-seg-len = <0x1000>;
		status = "ok";
	};
};

&qcn9224_pcie1 {
	status = "ok";
};

&mhi_region1 {
	status = "ok";
	size = <0x0 0x00f00000>;
};

&wifi2 {
	hremote_node = <&qcn9224_pcie1>;
	board_id = <0x0002>;
	status = "ok";
};

/* internal wifi */
&wifi0 {
	status = "ok";
	qcom,rproc = <&q6_wcss_pd1>;
	qcom,rproc_rpd = <&q6v5_wcss>;
	qcom,multipd_arch;
	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
	mem-region = <&q6_region>;
	qcom,board_id = <0x16>;
};

/* pcmlink */
&lpass {
	status = "ok";
};

/* emmc */
&sdhc_1 {
	status = "ok";
};

/* Remove unused avm special mac address definitions */
/delete-node/ &avm_mac_addr_macrouter_3;

#endif