--- zzzz-none-000/linux-5.4.213/arch/arm/Kconfig	2022-09-15 10:04:56.000000000 +0000
+++ alder-5690pro-762/linux-5.4.213/arch/arm/Kconfig	2024-08-14 09:01:26.000000000 +0000
@@ -66,11 +66,14 @@
 	select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
 	select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
 	select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
+	select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
 	select HAVE_ARCH_MMAP_RND_BITS if MMU
 	select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
 	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARM_SMCCC if CPU_V7
+	select HAVE_AVM_RTE if AVM_TZ_EXTENSIONS
+	select AVM_FASTIRQ_ARCH_ARM_COMMON
 	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
 	select HAVE_CONTEXT_TRACKING
 	select HAVE_COPY_THREAD_TLS
@@ -112,6 +115,7 @@
 	select HAVE_UID16
 	select HAVE_VIRT_CPU_ACCOUNTING_GEN
 	select IRQ_FORCED_THREADING
+	select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
 	select MODULES_USE_ELF_REL
 	select NEED_DMA_MAP_STATE
 	select OF_EARLY_FLATTREE if OF
@@ -1017,6 +1021,16 @@
 	  relevant cache maintenance functions and sets a specific bit
 	  in the diagnostic control register of the SCU.
 
+config ARM_ERRATA_764369_AVM_A53
+	bool "ARM errata: Special partial implementation of errata 764369 for Cortex-A53"
+	depends on CPU_V7 && SMP
+	help
+	  Despite not being mentioned in the errata notice for the Cortex-A53,
+	  parts of the implementation of erratum 764369 for Cortex-A9 have been
+	  found to be beneficial for Cortex-A53 devices as well, such as the
+	  Hawkeye-based 4060 (see JZ-93302 and #1229). This workaround adds a DSB
+	  instruction before relevant cache maintenance functions.
+
 config ARM_ERRATA_775420
        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
        depends on CPU_V7
@@ -1329,6 +1343,15 @@
 	default 0xB0000000 if VMSPLIT_3G_OPT
 	default 0xC0000000
 
+config KASAN_SHADOW_OFFSET
+	hex
+	depends on KASAN
+	default 0x1f000000 if PAGE_OFFSET=0x40000000
+	default 0x5f000000 if PAGE_OFFSET=0x80000000
+	default 0x9f000000 if PAGE_OFFSET=0xC0000000
+	default 0x8f000000 if PAGE_OFFSET=0xB0000000
+	default 0xffffffff
+
 config NR_CPUS
 	int "Maximum number of CPUs (2-32)"
 	range 2 32
@@ -1711,6 +1734,66 @@
 	  Enable this option to switch to a different method that uses a
 	  different canary value for each task.
 
+config AVM_TZ_EXTENSIONS
+	bool
+
+choice
+	prompt "Choose TrustZone implementation"
+	default AVM_TZ_TYPE_QSDK
+	help
+	  This enables distinguishing between TrustZone implementations
+	  (e.g. ATF or QCA's proprietary implementation) wherever necessary.
+
+config AVM_TZ_TYPE_QSDK
+	bool "Use proprietary QCA SDK TrustZone implementation"
+	help
+	  This option states whether this platform uses the proprietary QCA TrustZone as included in the QSDK.
+
+config AVM_TZ_TYPE_QCA_RTE
+	bool "Use QCA TrustZone with RTE support"
+	depends on ARCH_IPQ8074
+	select AVM_TZ_EXTENSIONS
+	help
+	  This option states whether this platform uses the QCA TrustZone with RTE support.
+
+
+config AVM_TZ_TYPE_ATF_RTE
+	bool "Use ARM Trusted Firmware (ATF) TrustZone with RTE support"
+	depends on (ARCH_IPQ5018 || ARCH_IPQ9574 || ARCH_IPQ5332) && QCOM_SCM
+	select AVM_TZ_EXTENSIONS
+	help
+	  This option states whether this platform uses the ATF TrustZone with RTE support.
+
+endchoice
+
+
+config AVM_FASTIRQ_ARCH_ARM_COMMON
+	bool
+
+config HAVE_AVM_RTE
+	bool
+
+if HAVE_AVM_RTE
+
+config AVM_FASTIRQ
+	def_bool y
+
+config AVM_FASTIRQ_TZ
+	bool "AVM fast interrupt with trust zone support"
+	depends on AVM_FASTIRQ && AVM_TZ_EXTENSIONS
+	default n
+	help
+	  This option enables fast interrupt support via trust zone for cortex boards.
+
+config AVM_FASTIRQ_DEBUG
+	bool "AVM firq protection checking"
+	depends on AVM_FASTIRQ_TZ
+	default n
+	help
+	   Some protection checks by fastirq-usage versus linux-os
+
+endif
+
 endmenu
 
 menu "Boot options"