--- zzzz-none-000/linux-2.6.32.61/arch/mips/kernel/cpu-probe.c	2013-06-10 09:43:48.000000000 +0000
+++ ar10-7272-687/linux-2.6.32.61/arch/mips/kernel/cpu-probe.c	2014-01-08 16:21:32.000000000 +0000
@@ -24,6 +24,14 @@
 #include <asm/system.h>
 #include <asm/watch.h>
 #include <asm/spram.h>
+#if defined(CONFIG_AVM_POWER) 
+#include <linux/avm_power.h>
+#endif /*--- #if defined(CONFIG_AVM_POWER) ---*/ 
+
+#ifdef CONFIG_MACH_FUSIV_MIPS1
+#include <adi6843.h>
+#endif
+
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  * the implementation of the "wait" feature differs between CPU families. This
@@ -59,11 +67,17 @@
 void r4k_wait_irqoff(void)
 {
 	local_irq_disable();
+#if defined(CONFIG_AVM_POWER)
+    avm_cpu_wait_start();
+#endif/*--- #if defined(CONFIG_AVM_POWER) ---*/
 	if (!need_resched())
 		__asm__("	.set	push		\n"
 			"	.set	mips3		\n"
 			"	wait			\n"
 			"	.set	pop		\n");
+#if defined(CONFIG_AVM_POWER)
+    avm_cpu_wait_end();
+#endif/*--- #if defined(CONFIG_AVM_POWER)  ---*/
 	local_irq_enable();
 	__asm__(" 	.globl __pastwait	\n"
 		"__pastwait:			\n");
@@ -170,15 +184,23 @@
 	case CPU_24K:
 	case CPU_34K:
 	case CPU_1004K:
-		cpu_wait = r4k_wait;
-		if (read_c0_config7() & MIPS_CONF7_WII)
-			cpu_wait = r4k_wait_irqoff;
+        if(cpu_wait == NULL) {
+            if (read_c0_config7() & MIPS_CONF7_WII) {
+                printk(KERN_ERR "wait instruction: r4k_wait_irqoff\n");
+                cpu_wait = r4k_wait_irqoff;
+            } else
+                cpu_wait = r4k_wait;
+        } else {
+            printk(KERN_ERR "[%s] cpu_wait already set up %pF\n", __FUNCTION__, cpu_wait);
+        }
 		break;
 
 	case CPU_74K:
 		cpu_wait = r4k_wait;
-		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) {
+            printk(KERN_ERR "wait instruction: r4k_wait_irqoff\n");
 			cpu_wait = r4k_wait_irqoff;
+        }
 		break;
 
 	case CPU_TX49XX:
@@ -580,6 +602,17 @@
 			     MIPS_CPU_32FPR;
 		c->tlbsize = 64;
 		break;
+#ifdef CONFIG_MACH_FUSIV_MIPS1
+	case PRID_IMP_FUSIV_MIPS1:
+		/* CPU ID for Fusiv MIPS1 Lexra */ 
+		c->processor_id = (FUSIV_PRID << 16 )| PRID_IMP_FUSIV_MIPS1;
+		__cpu_name[cpu] = "Fusiv MIPS1";
+		c->cputype = CPU_R3000;
+		c->isa_level = MIPS_CPU_ISA_I;
+		c->options = MIPS_CPU_TLB;
+		c->tlbsize = 64;
+		break;
+#endif
 	}
 }
 
@@ -711,6 +744,12 @@
 	mips_probe_watch_registers(c);
 }
 
+#ifdef CONFIG_CPU_MIPSR2
+extern void spram_config(void);
+#else
+static inline void spram_config(void) {}
+#endif
+
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 {
 	decode_configs(c);