/*
 * Kompatibilitaetsblock, um die Uebersetzbarkeit der AVMnet-Quellen zu gewaehrleisten. Im Zuge der DragonFly-/
 * HoneyBee-Erweiterung des Kernel 3.10 wurden im Code zahlreiche Bezeichner der Atheros-Register vereinheitlicht. 
 * Dieser Kompatibilitaetsblock nimmt die Ruecksubstitution auf die alten Bezeichner vor, damit die Quellen
 * fuer andere SOCs und im Kernel 2.6 uebersetzbar bleiben.
 */

// GPIO

// PLL Control
#define ATH_PLL_SWITCH_CLOCK_CONTROL     SWITCH_CLOCK_SPARE_ADDRESS
#define ATH_PLL_ETH_SGMII                ETH_SGMII_ADDRESS
#define ATH_PLL_ETH_SGMII_SERDES         ETH_SGMII_SERDES_ADDRESS

#define ATH_PLL_SWITCH_CLOCK_CONTROL_USB_REFCLK_FREQ_SEL_MASK  SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK
#define ATH_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL1_1_SET       SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_SET
#define ATH_PLL_SWITCH_CLOCK_CONTROL_OEN_CLK125M_SEL_SET       SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET
#define ATH_PLL_SWITCH_CLOCK_CONTROL_EN_PLL_TOP_SET            SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET
#define ATH_PLL_SWITCH_CLOCK_CONTROL_SWITCHCLK_SEL_SET         SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET

#define ATH_PLL_ETH_XMII_TX_DELAY_SET                          ETH_XMII_TX_DELAY_SET
#define ATH_PLL_ETH_XMII_RX_DELAY_SET                          ETH_XMII_RX_DELAY_SET

#define ATH_PLL_ETH_XMII_TX_INVERT_SET                         ETH_XMII_TX_INVERT_SET
#define ATH_PLL_ETH_XMII_GIGE_SET                              ETH_XMII_GIGE_SET
#define ATH_PLL_ETH_XMII_PHASE0_COUNT_SET                      ETH_XMII_PHASE0_COUNT_SET
#define ATH_PLL_ETH_XMII_PHASE1_COUNT_SET                      ETH_XMII_PHASE1_COUNT_SET

#define ATH_PLL_ETH_SGMII_GIGE_SET                             ETH_SGMII_GIGE_SET
#define ATH_PLL_ETH_SGMII_RX_DELAY_SET                         ETH_SGMII_RX_DELAY_SET
#define ATH_PLL_ETH_SGMII_TX_DELAY_SET                         ETH_SGMII_TX_DELAY_SET
#define ATH_PLL_ETH_SGMII_CLK_SEL_SET                          ETH_SGMII_CLK_SEL_SET
#define ATH_PLL_ETH_SGMII_PHASE1_COUNT_SET                     ETH_SGMII_PHASE1_COUNT_SET
#define ATH_PLL_ETH_SGMII_PHASE0_COUNT_SET                     ETH_SGMII_PHASE0_COUNT_SET

#define ATH_PLL_ETH_SGMII_SERDES_PLL_EN_LOCK_DETECT_SET        ETH_SGMII_SERDES_EN_LOCK_DETECT_SET
#define ATH_PLL_ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK           ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK
#define ATH_PLL_ETH_SGMII_SERDES_PLL_EN_MASK                   ETH_SGMII_SERDES_EN_PLL_MASK
#define ATH_PLL_ETH_SGMII_SERDES_PLL_REFCLK_SEL_SET            ETH_SGMII_SERDES_PLL_REFCLK_SEL_SET
#define ATH_PLL_ETH_SGMII_SERDES_EN_LOCK_DETECT_SET            ETH_SGMII_SERDES_EN_LOCK_DETECT_SET

// Reset
#define ATH_RST_RESET                    ATH_RESET

#define ATH_RESET_ETH_SWITCH_ANALOG_RESET                      RST_RESET_ETH_SWITCH_ANALOG_RESET_RESET  // nur 9561
#define ATH_RESET_ETH_SWITCH_RESET                             RST_RESET_ETH_SWITCH_RESET_RESET         // nur 9561

#define ATH_RESET_REVISION_ID_MAJOR_MASK                       REV_ID_MAJOR_MASK 

// GMAC
#define ATH_GMAC_ETH_CFG                 ETH_CFG_ADDRESS
#define ATH_GMAC_SGMII_RESET             SGMII_RESET_ADDRESS
#define ATH_GMAC_SGMII_SERDES            SGMII_SERDES_ADDRESS
#define ATH_GMAC_MR_AN_CONTROL           MR_AN_CONTROL_ADDRESS
#define ATH_GMAC_SGMII_CONFIG            SGMII_CONFIG_ADDRESS
#define ATH_GMAC_SGMII_DEBUG             SGMII_DEBUG_ADDRESS

#define ATH_GMAC_ETH_CFG_SW_PHY_SWAP_SET                       ETH_CFG_SW_PHY_SWAP_SET
#define ATH_GMAC_ETH_CFG_GE0_SGMII_SET                         ETH_CFG_GE0_SGMII_SET
#define ATH_GMAC_ETH_CFG_SW_ONLY_MODE_SET                      ETH_CFG_SW_ONLY_MODE_SET

#define ATH_GMAC_SGMII_RESET_HW_RX_125M_N_SET                  SGMII_RESET_HW_RX_125M_N_SET
#define ATH_GMAC_SGMII_RESET_TX_125M_N_SET                     SGMII_RESET_TX_125M_N_SET
#define ATH_GMAC_SGMII_RESET_RX_125M_N_SET                     SGMII_RESET_RX_125M_N_SET
#define ATH_GMAC_SGMII_RESET_TX_CLK_N_SET                      SGMII_RESET_TX_CLK_N_SET
#define ATH_GMAC_SGMII_RESET_RX_CLK_N_SET                      SGMII_RESET_RX_CLK_N_SET
#define ATH_GMAC_SGMII_RESET_RX_CLK_N_RESET                    SGMII_RESET_RX_CLK_N_RESET

#define ATH_GMAC_SGMII_SERDES_VCO_FAST_GET                     SGMII_SERDES_VCO_FAST_GET
#define ATH_GMAC_SGMII_SERDES_VCO_SLOW_GET                     SGMII_SERDES_VCO_SLOW_GET

#define ATH_GMAC_SGMII_SERDES_RES_CALIBRATION_MASK             SGMII_SERDES_RES_CALIBRATION_MASK
#define ATH_GMAC_SGMII_SERDES_RES_CALIBRATION_SET              SGMII_SERDES_RES_CALIBRATION_SET

#define ATH_GMAC_SGMII_SERDES_CDR_BW_SET                       SGMII_SERDES_CDR_BW_SET
#define ATH_GMAC_SGMII_SERDES_TX_DR_CTRL_SET                   SGMII_SERDES_TX_DR_CTRL_SET
#define ATH_GMAC_SGMII_SERDES_PLL_BW_SET                       SGMII_SERDES_PLL_BW_SET
#define ATH_GMAC_SGMII_SERDES_EN_SIGNAL_DETECT_SET             SGMII_SERDES_EN_SIGNAL_DETECT_SET

#define ATH_GMAC_SGMII_SERDES_LOCK_DETECT_STATUS_MASK          SGMII_SERDES_LOCK_DETECT_STATUS_MASK

#define ATH_GMAC_SGMII_SERDES_FIBER_SDO_SET                    SGMII_SERDES_FIBER_SDO_SET
#define ATH_GMAC_SGMII_SERDES_VCO_REG_SET                      SGMII_SERDES_VCO_REG_SET

#define ATH_GMAC_MR_AN_CONTROL_POWER_DOWN_SET                  MR_AN_CONTROL_POWER_DOWN_SET
#define ATH_GMAC_MR_AN_CONTROL_PHY_RESET_SET                   MR_AN_CONTROL_PHY_RESET_SET
#define ATH_GMAC_MR_AN_CONTROL_DUPLEX_MODE_SET                 MR_AN_CONTROL_DUPLEX_MODE_SET
#define ATH_GMAC_MR_AN_CONTROL_SPEED_SEL1_SET                  MR_AN_CONTROL_SPEED_SEL1_SET

#define ATH_GMAC_SGMII_CONFIG_MODE_CTRL_SET                    SGMII_CONFIG_MODE_CTRL_SET
#define ATH_GMAC_SGMII_CONFIG_FORCE_SPEED_SET                  SGMII_CONFIG_FORCE_SPEED_SET
#define ATH_GMAC_SGMII_CONFIG_SPEED_SET                        SGMII_CONFIG_SPEED_SET



/****************************************************************************************************************/