#include #include #include #define GIC_DIST_BASE 0x81001000 #define GIC_CPUI_BASE 0x81002000 #define TIMER_HYP_PPI 10 #define TIMER_VIRT_PPI 11 #define TIMER_PHYS_SECURE_PPI 13 #define TIMER_PHYS_NONSECURE_PPI 14 #define GIC_DIST_BASE 0x81001000 #define GIC_CPUI_BASE 0x81002000 #define PMU_CORE0_SPI 7 #define PMU_CORE1_SPI 8 #define PMU_CORE2_SPI 9 #define PMU_CORE3_SPI 10 #define SDIO_EMMC_SPI 86 #define SPU_GMAC_SPI 91 #define ARM_UART0_SPI 32 /dts-v1/; /* For secondary boot area */ /memreserve/ 0x00000000 0x00008000; /* For PMC3 firmware */ #define DEVICE_TREE #include "../../../../../../brcm_sdk/shared/opensource/include/pmc/pmc_firmware_63178.h" /memreserve/ PMC3_RESERVED_MEM_START PMC3_RESERVED_MEM_SIZE; #undef DEVICE_TREE #include "../bcm_963xx_template.dtsi" #include "../bcm_rsvdmem_32.dtsi" / { model = "Broadcom BCM963178"; compatible = "brcm,bcm963178"; interrupt-parent = <&gic>; #address-cells = <1>; #size-cells = <1>; chosen { bootargs = "console=ttyAMA0 earlyprintk debug irqaffinity=0 pci=pcie_bus_safe"; }; cpus { #address-cells = <1>; #size-cells = <0>; CA7_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; next-level-cache = <&L2_0>; }; CA7_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; next-level-cache = <&L2_0>; #if defined (CONFIG_OPTEE) enable-method = "psci"; #else enable-method = "brcm,bca-smp"; #endif }; CA7_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x2>; next-level-cache = <&L2_0>; #if defined (CONFIG_OPTEE) enable-method = "psci"; #else enable-method = "brcm,bca-smp"; #endif }; L2_0: l2-cache0 { compatible = "cache"; }; }; #if defined (CONFIG_OPTEE) psci { compatible = "arm,psci-0.2"; method = "smc"; cpu_off = <1>; cpu_on = <2>; }; firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; #endif gic: interrupt-controller@81000000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = , ; }; timer { compatible = "arm,armv7-timer"; interrupts = , , , ; arm,cpu-registers-not-fw-configured = <1>; }; pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , ; interrupt-affinity = <&CA7_0>, <&CA7_1>; }; uartclk: uartclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; clocks { #address-cells = <1>; #size-cells = <1>; ranges; i2s_clkmclk_syscon: i2s_clkmclk_syscon{ compatible = "brcm,i2s-audio-clkmclk-syscon", "syscon"; reg = <0xFF802080 0x4>; }; osc: oscillator { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <200000000>; /* xpon 200MHz output */ }; i2sclk: i2sclk { #clock-cells = <0>; compatible = "brcm,i2s-clock"; clocks = <&osc>; clk-mclk-syscon = <&i2s_clkmclk_syscon>; clock-output-names = "i2s_clk"; }; }; /* Legacy UBUS base */ ubus@ff800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xff800000 0x7fffff>; nand@ff801800 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1"; reg = <0x1800 0x600>, <0x2000 0x10>; reg-names = "nand", "nand-int-base"; status = "okay"; nandcs@0 { compatible = "brcm,nandcs"; reg = <0>; nand-on-flash-bbt; }; }; watchdog@480 { compatible = "brcm,bcm96xxx-wdt"; reg = <0x480 0x10>; timeout-sec = <80>; }; gpio7: gpio-controller@0xff80051c { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x51c 0x4>, <0x53c 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio6: gpio-controller@0xff800518 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x518 0x4>, <0x538 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio5: gpio-controller@0xff800514 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x514 0x4>, <0x534 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio4: gpio-controller@0xff800510 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x510 0x4>, <0x530 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio3: gpio-controller@0xff80050c { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x50c 0x4>, <0x52c 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio2: gpio-controller@0xff800508 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x508 0x4>, <0x528 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio1: gpio-controller@0xff800504 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x504 0x4>, <0x0 0x524 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; gpio0: gpio-controller@0xff800500 { compatible = "brcm,bcm6345-gpio"; reg-names = "dirout", "dat"; reg = <0x500 0x4>, <0x520 0x4>; ngpios = <32>; #gpio-cells = <2>; gpio-controller; }; i2s: bcm63xx-i2s { compatible = "brcm,bcm63xx-i2s"; reg = <0x2080 0x21>; interrupts = ; clocks = <&i2sclk>, <&osc>; clock-names = "i2sclk","i2sosc"; }; serial@ff812000 { #address-cells = <1>; #size-cells = <1>; compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; interrupts = ; clocks = <&uartclk>, <&uartclk>; clock-names = "uartclk", "apb_pclk"; }; }; brcm-legacy { compatible = "brcm,brcm-legacy"; }; cs4345 { compatible = "crus,cs4345-dac"; }; #if defined(CONFIG_BCM_PCIE_HCD) pcie1: pcie@84000000 { compatible = "brcm,bcm963xx-vpcie"; device_type = "vpci"; reg = <0x84000000 0x01000000>; brcm,coreid = <1>; }; pcie0: pcie@80040000 { compatible = "brcm,bcm963xx-pcie"; device_type = "pci"; reg = <0x80040000 0x0000A000>; #address-cells = <3>; #size-cells = <2>; /* flags, pci_addr, cpu_addr, size */ ranges = <0x02000000 0 0xC0000000 0xC0000000 0 0x10000000>; interrupt-names = "intr"; interrupts = ; /* core error log interrupts */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; brcm,coreid = <0>; }; #endif therm0: brcm-therm { compatible = "brcm,therm"; status = "okay"; }; };