#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/soc/bcm963xx_dt_bindings.h> 

#define GIC_DIST_BASE	0x81001000
#define GIC_CPUI_BASE	0x81002000

#define TIMER_HYP_PPI			10
#define TIMER_VIRT_PPI			11
#define TIMER_PHYS_SECURE_PPI		13
#define TIMER_PHYS_NONSECURE_PPI	14

#define PMU_CORE0_SPI			9
#define PMU_CORE1_SPI			10
#define ARM_UART0_SPI           92
#define PMC3_RESERVED_LOG_SIZE  (0x5000) 
#define PMC3_RESERVED_LOG_START (0x40fb000)
	
/dts-v1/;
/* For secondary boot area */
/memreserve/ 0x00000000 0x00008000;
/memreserve/ PMC3_RESERVED_LOG_START PMC3_RESERVED_LOG_SIZE;

#include "../bcm_rsvdmem_32.dtsi"

/ {
    model = "Broadcom BCM96878";
    compatible = "brcm,bcm96878";
    interrupt-parent = <&gic>;
    #address-cells = <1>;
    #size-cells = <1>;
   
    chosen {
        bootargs = "console=ttyAMA0 earlyprintk debug irqaffinity=0 pci=pcie_bus_safe";
    };

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "brcm,bca-smp";

		CA7_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
		};
		CA7_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@81000000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <GIC_DIST_BASE 0x1000>,
		      <GIC_CPUI_BASE 0x2000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI TIMER_PHYS_SECURE_PPI    (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI TIMER_PHYS_NONSECURE_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI TIMER_VIRT_PPI           (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI TIMER_HYP_PPI            (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		arm,cpu-registers-not-fw-configured = <1>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI PMU_CORE0_SPI IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI PMU_CORE1_SPI IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&CA7_0>,
				     <&CA7_1>; 
	};
	
	brcm-legacy {
		compatible = "brcm,brcm-legacy";
	};

	memory@00000000 {
		device_type = "memory";
		reg = <0x00000000 0x04000000>;  /* 64MBMB */
	};

    uartclk: uartclk {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <50000000>;
    };

	/* Legacy UBUS base */
	ubus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xff800000 0x7fffff>;

		nand@ff801800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
			reg = <0x1800 0x600>, <0x2000 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "okay";

			nandcs@0 {
				compatible = "brcm,nandcs";
				reg = <0>;
				nand-on-flash-bbt;
			};

		};

		watchdog@480 {
			compatible = "brcm,bcm96xxx-wdt";
			reg = <0x480 0x10>;
			timeout-sec = <80>;
		};

		i2c@0xff802100 {
			compatible = "brcm,bcm63000-i2c";
			reg = <0x2100 0x60>;
		};
		
		serial@ff812000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI ARM_UART0_SPI IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uartclk>, <&uartclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		rng: rng@ff800b80 {
			compatible = "brcm,iproc-rng200";
			reg = <0x00000b80 0x28>;
		};
	};

#if defined(CONFIG_BCM_PCIE_HCD)
	pcie1: pcie@84000000 {
		compatible = "brcm,bcm963xx-vpcie";
		device_type = "vpci";
		reg = <0x84000000 0x01000000>;

		brcm,coreid = <1>;
	};

	pcie0: pcie@80040000 {
		compatible = "brcm,bcm963xx-pcie";
		device_type = "pci";
		reg = <0x80040000 0x0000A000>;

		#address-cells = <3>;
		#size-cells = <2>;
		/*        flags,     pci_addr,    cpu_addr,  size */
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000>;

		interrupt-names = "intr";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;   /* core error log interrupts */

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		brcm,coreid = <0>;
	};
#endif

};