--- zzzz-none-000/linux-4.1.52/arch/arm/mm/Kconfig	2018-05-28 02:26:45.000000000 +0000
+++ bcm63-7530ax-731/linux-4.1.52/arch/arm/mm/Kconfig	2022-03-02 11:37:12.000000000 +0000
@@ -384,6 +384,7 @@
 	select CPU_TLB_V6 if MMU
 
 # ARMv7
+if CONFIG_BCM_KF_SPECTRE_PATCH
 config CPU_V7
 	bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
 	select CPU_32v6K
@@ -396,7 +397,25 @@
 	select CPU_CP15_MPU if !MMU
 	select CPU_HAS_ASID if MMU
 	select CPU_PABRT_V7
+	select CPU_SPECTRE if MMU
 	select CPU_TLB_V7 if MMU
+endif
+
+if !CONFIG_BCM_KF_SPECTRE_PATCH
+config CPU_V7
+	bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
+	select CPU_32v6K
+	select CPU_32v7
+	select CPU_ABRT_EV7
+	select CPU_CACHE_V7
+	select CPU_CACHE_VIPT
+	select CPU_COPY_V6 if MMU
+	select CPU_CP15_MMU if MMU
+	select CPU_CP15_MPU if !MMU
+	select CPU_HAS_ASID if MMU
+	select CPU_PABRT_V7
+	select CPU_TLB_V7 if MMU
+endif
 
 # ARMv7M
 config CPU_V7M
@@ -777,6 +796,30 @@
 	help
 	  Say Y here to disable branch prediction.  If unsure, say N.
 
+if CONFIG_BCM_KF_SPECTRE_PATCH
+config CPU_SPECTRE
+	bool
+
+config HARDEN_BRANCH_PREDICTOR
+	bool "Harden the branch predictor against aliasing attacks" if EXPERT
+	depends on CPU_SPECTRE
+	default n
+	help
+	   Speculation attacks against some high-performance processors rely
+	   on being able to manipulate the branch predictor for a victim
+	   context by executing aliasing branches in the attacker context.
+	   Such attacks can be partially mitigated against by clearing
+	   internal branch predictor state and limiting the prediction
+	   logic in some situations.
+
+	   This config option will take CPU-specific actions to harden
+	   the branch predictor against aliasing attacks and may rely on
+	   specific instruction sequences or control bits being set by
+	   the system firmware.
+
+	   If unsure, say Y.
+endif
+
 config TLS_REG_EMUL
 	bool
 	select NEED_KUSER_HELPERS
@@ -861,11 +904,22 @@
 config OUTER_CACHE
 	bool
 
+if CONFIG_BCM_KF_SPECTRE_PATCH
+config OUTER_CACHE_SYNC
+	bool
+	select ARM_HEAVY_MB
+	help
+	  The outer cache has a outer_cache_fns.sync function pointer
+	  that can be used to drain the write buffer of the outer cache.
+endif
+
+if !CONFIG_BCM_KF_SPECTRE_PATCH
 config OUTER_CACHE_SYNC
 	bool
 	help
 	  The outer cache has a outer_cache_fns.sync function pointer
 	  that can be used to drain the write buffer of the outer cache.
+endif
 
 config CACHE_FEROCEON_L2
 	bool "Enable the Feroceon L2 cache controller"
@@ -973,11 +1027,21 @@
 	help
 	  This option enables the L2 cache on XScale3.
 
+if !BCM_KF_ARM_BCM963XX
 config ARM_L1_CACHE_SHIFT_6
 	bool
 	default y if CPU_V7
 	help
 	  Setting ARM L1 cache line size to 64 Bytes.
+endif
+
+if BCM_KF_ARM_BCM963XX
+config ARM_L1_CACHE_SHIFT_6
+	bool
+	default y if CPU_V7 && !ARCH_BCM63XX
+	help
+	  Setting ARM L1 cache line size to 64 Bytes.
+endif
 
 config ARM_L1_CACHE_SHIFT
 	int
@@ -1011,6 +1075,11 @@
 	  This option allows the use of custom mandatory barriers
 	  included via the mach/barriers.h file.
 
+if CONFIG_BCM_KF_SPECTRE_PATCH
+config ARM_HEAVY_MB
+	bool
+endif
+
 config ARCH_SUPPORTS_BIG_ENDIAN
 	bool
 	help