--- zzzz-none-000/linux-4.1.52/arch/arm64/kernel/perf_event.c 2018-05-28 02:26:45.000000000 +0000 +++ bcm63-7530ax-731/linux-4.1.52/arch/arm64/kernel/perf_event.c 2022-03-02 11:37:12.000000000 +0000 @@ -699,6 +699,10 @@ ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19, ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A, ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D, +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + ARMV8_PMUV3_PERFCTR_STALL_FRONTEND = 0x23, + ARMV8_PMUV3_PERFCTR_STALL_BACKEND = 0x24, +#endif }; /* PMUv3 HW events mapping. */ @@ -707,11 +711,21 @@ [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED, [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS, [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL, +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE, +#else [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED, +#endif [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED, +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND, + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND, +#else [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, +#endif }; static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] @@ -733,8 +747,13 @@ }, [C(L1I)] = { [C(OP_READ)] = { +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS, + [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL, +#else [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, +#endif }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -747,12 +766,22 @@ }, [C(LL)] = { [C(OP_READ)] = { +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS, + [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL, +#else [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, +#endif }, [C(OP_WRITE)] = { +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS, + [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL, +#else [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, +#endif }, [C(OP_PREFETCH)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -762,7 +791,11 @@ [C(DTLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_DTLB_REFILL, +#else [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, +#endif }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, @@ -776,7 +809,11 @@ [C(ITLB)] = { [C(OP_READ)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, +#if defined(CONFIG_BCM_KF_MISC_BACKPORTS) + [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_ITLB_REFILL, +#else [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, +#endif }, [C(OP_WRITE)] = { [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,