/* Copyright (c) 2015 Broadcom Corporation All Rights Reserved <:label-BRCM:2015:DUAL/GPL:standard This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License, version 2, as published by the Free Software Foundation (the "GPL"). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. :> */ #ifndef _BCM6858_A0_AG_H_ #define _BCM6858_A0_AG_H_ #include "ru.h" /****************************************************************************** * BCM6858_A0 Fields ******************************************************************************/ extern const ru_field_rec LPORT_XLMAC_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_CTRL_RESERVED0_FIELD_MASK 0xffffffffffff8000UL #define LPORT_XLMAC_CTRL_RESERVED0_FIELD_WIDTH 49 #define LPORT_XLMAC_CTRL_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD; #define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_MASK 0x0000000000004000UL #define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_EXTENDED_HIG2_EN_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD; #define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_MASK 0x0000000000002000UL #define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_LINK_STATUS_SELECT_FIELD_SHIFT 13 extern const ru_field_rec LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD; #define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_MASK 0x0000000000001000UL #define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_SW_LINK_STATUS_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD; #define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_MASK 0x0000000000000800UL #define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_SHIFT 11 extern const ru_field_rec LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD; #define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_MASK 0x0000000000000400UL #define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_RS_SOFT_RESET_FIELD_SHIFT 10 extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_5_FIELD; #define LPORT_XLMAC_CTRL_RSVD_5_FIELD_MASK 0x0000000000000200UL #define LPORT_XLMAC_CTRL_RSVD_5_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_RSVD_5_FIELD_SHIFT 9 extern const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD; #define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_MASK 0x0000000000000100UL #define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_4_FIELD; #define LPORT_XLMAC_CTRL_RSVD_4_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_CTRL_RSVD_4_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_RSVD_4_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_CTRL_SOFT_RESET_FIELD; #define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD; #define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_LAG_FAILOVER_EN_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD; #define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_REMOVE_FAILOVER_LPBK_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_CTRL_RSVD_1_FIELD; #define LPORT_XLMAC_CTRL_RSVD_1_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_CTRL_RSVD_1_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_RSVD_1_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD; #define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_LOCAL_LPBK_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_CTRL_RX_EN_FIELD; #define LPORT_XLMAC_CTRL_RX_EN_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_CTRL_RX_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_RX_EN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_CTRL_TX_EN_FIELD; #define LPORT_XLMAC_CTRL_TX_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_CTRL_TX_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_CTRL_TX_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_MODE_RESERVED0_FIELD; #define LPORT_XLMAC_MODE_RESERVED0_FIELD_MASK 0xffffffffffffff80UL #define LPORT_XLMAC_MODE_RESERVED0_FIELD_WIDTH 57 #define LPORT_XLMAC_MODE_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_MODE_SPEED_MODE_FIELD; #define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_MASK 0x0000000000000070UL #define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_WIDTH 3 #define LPORT_XLMAC_MODE_SPEED_MODE_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD; #define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_WIDTH 1 #define LPORT_XLMAC_MODE_NO_SOP_FOR_CRC_HG_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_MODE_HDR_MODE_FIELD; #define LPORT_XLMAC_MODE_HDR_MODE_FIELD_MASK 0x0000000000000007UL #define LPORT_XLMAC_MODE_HDR_MODE_FIELD_WIDTH 3 #define LPORT_XLMAC_MODE_HDR_MODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_SPARE0_RESERVED0_FIELD; #define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_WIDTH 32 #define LPORT_XLMAC_SPARE0_RESERVED0_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_SPARE0_RSVD_FIELD; #define LPORT_XLMAC_SPARE0_RSVD_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_SPARE0_RSVD_FIELD_WIDTH 32 #define LPORT_XLMAC_SPARE0_RSVD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_SPARE1_RESERVED0_FIELD; #define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_SPARE1_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_SPARE1_RSVD_FIELD; #define LPORT_XLMAC_SPARE1_RSVD_FIELD_MASK 0x0000000000000003UL #define LPORT_XLMAC_SPARE1_RSVD_FIELD_WIDTH 2 #define LPORT_XLMAC_SPARE1_RSVD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_MASK 0xfffffc0000000000UL #define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_WIDTH 22 #define LPORT_XLMAC_TX_CTRL_RESERVED0_FIELD_SHIFT 42 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD; #define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_MASK 0x000003c000000000UL #define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_XLMAC_TX_CTRL_TX_THRESHOLD_FIELD_SHIFT 38 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD; #define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_MASK 0x0000002000000000UL #define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CTRL_EP_DISCARD_FIELD_SHIFT 37 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD; #define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_MASK 0x0000001e00000000UL #define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_WIDTH 4 #define LPORT_XLMAC_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_SHIFT 33 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD; #define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_MASK 0x00000001fe000000UL #define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_WIDTH 8 #define LPORT_XLMAC_TX_CTRL_THROT_DENOM_FIELD_SHIFT 25 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD; #define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_MASK 0x0000000001f80000UL #define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_WIDTH 6 #define LPORT_XLMAC_TX_CTRL_THROT_NUM_FIELD_SHIFT 19 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD; #define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_MASK 0x000000000007f000UL #define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_WIDTH 7 #define LPORT_XLMAC_TX_CTRL_AVERAGE_IPG_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD; #define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_MASK 0x0000000000000fe0UL #define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_WIDTH 7 #define LPORT_XLMAC_TX_CTRL_PAD_THRESHOLD_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD; #define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CTRL_PAD_EN_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD; #define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CTRL_TX_ANY_START_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_DISCARD_FIELD; #define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CTRL_DISCARD_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD; #define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_MASK 0x0000000000000003UL #define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_WIDTH 2 #define LPORT_XLMAC_TX_CTRL_CRC_MODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_MASK 0xfffffc0000000000UL #define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 22 #define LPORT_XLMAC_TX_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 42 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD; #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_MASK 0x000003ff00000000UL #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_WIDTH 10 #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD; #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_TX_CTRL_OVERLAY_XLMAC_TX_CTRL_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD; #define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_TX_MAC_SA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD; #define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_WIDTH 48 #define LPORT_XLMAC_TX_MAC_SA_CTRL_SA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD; #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK 0x0000ffff00000000UL #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH 16 #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD; #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_MASK 0xffffffffffff0000UL #define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_WIDTH 48 #define LPORT_XLMAC_RX_CTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD; #define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_MASK 0x0000000000008000UL #define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RX_PASS_PFC_FIELD_SHIFT 15 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD; #define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_MASK 0x0000000000004000UL #define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RX_PASS_PAUSE_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD; #define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_MASK 0x0000000000002000UL #define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RX_PASS_CTRL_FIELD_SHIFT 13 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD; #define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_MASK 0x0000000000001000UL #define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RSVD_3_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD; #define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_MASK 0x0000000000000800UL #define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RSVD_2_FIELD_SHIFT 11 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD; #define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_MASK 0x00000000000007f0UL #define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_WIDTH 7 #define LPORT_XLMAC_RX_CTRL_RUNT_THRESHOLD_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD; #define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_STRICT_PREAMBLE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD; #define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_STRIP_CRC_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD; #define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RX_ANY_START_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD; #define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CTRL_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD; #define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_RX_MAC_SA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD; #define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_WIDTH 48 #define LPORT_XLMAC_RX_MAC_SA_RX_SA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD; #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_MASK 0x0000ffff00000000UL #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_WIDTH 16 #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD; #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_SA_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD; #define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_MASK 0xffffffffffffc000UL #define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_WIDTH 50 #define LPORT_XLMAC_RX_MAX_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD; #define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_MASK 0x0000000000003fffUL #define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_WIDTH 14 #define LPORT_XLMAC_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD; #define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_MASK 0xfffffffc00000000UL #define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_WIDTH 30 #define LPORT_XLMAC_RX_VLAN_TAG_RESERVED0_FIELD_SHIFT 34 extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD; #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_MASK 0x0000000200000000UL #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_SHIFT 33 extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD; #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_MASK 0x0000000100000000UL #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD; #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_MASK 0x00000000ffff0000UL #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_WIDTH 16 #define LPORT_XLMAC_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD; #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_WIDTH 16 #define LPORT_XLMAC_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffff00UL #define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_WIDTH 56 #define LPORT_XLMAC_RX_LSS_CTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD; #define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8UL #define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61 #define LPORT_XLMAC_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD; #define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD; #define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD; #define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8UL #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61 #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD; #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD; #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD; #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_MASK 0xffffffe000000000UL #define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_WIDTH 27 #define LPORT_XLMAC_PAUSE_CTRL_RESERVED0_FIELD_SHIFT 37 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_MASK 0x0000001fffe00000UL #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_SHIFT 21 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_MASK 0x0000000000100000UL #define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_WIDTH 1 #define LPORT_XLMAC_PAUSE_CTRL_RSVD_2_FIELD_SHIFT 20 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_MASK 0x0000000000080000UL #define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_WIDTH 1 #define LPORT_XLMAC_PAUSE_CTRL_RSVD_1_FIELD_SHIFT 19 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_MASK 0x0000000000040000UL #define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PAUSE_CTRL_RX_PAUSE_EN_FIELD_SHIFT 18 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_MASK 0x0000000000020000UL #define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PAUSE_CTRL_TX_PAUSE_EN_FIELD_SHIFT 17 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_MASK 0x0000000000010000UL #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_MASK 0xffffffe000000000UL #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 27 #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 37 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_MASK 0x0000001f00000000UL #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_WIDTH 5 #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD; #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_XLMAC_PAUSE_CTRL_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_MASK 0xffffffc000000000UL #define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_WIDTH 26 #define LPORT_XLMAC_PFC_CTRL_RESERVED0_FIELD_SHIFT 38 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD; #define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_MASK 0x0000002000000000UL #define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_TX_PFC_EN_FIELD_SHIFT 37 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD; #define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_MASK 0x0000001000000000UL #define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_RX_PFC_EN_FIELD_SHIFT 36 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD; #define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_MASK 0x0000000800000000UL #define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_PFC_STATS_EN_FIELD_SHIFT 35 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_RSVD_FIELD; #define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_MASK 0x0000000400000000UL #define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_RSVD_FIELD_SHIFT 34 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD; #define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_MASK 0x0000000200000000UL #define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_FORCE_PFC_XON_FIELD_SHIFT 33 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD; #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_MASK 0x0000000100000000UL #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_EN_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD; #define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_MASK 0x00000000ffff0000UL #define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_CTRL_PFC_XOFF_TIMER_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD; #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_MASK 0xfffffffe00000000UL #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 31 #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 33 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD; #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_MASK 0x0000000100000000UL #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_EN_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD; #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_MASK 0x00000000ffff0000UL #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_CTRL_OVERLAY_RESERVED1_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD; #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_CTRL_OVERLAY_LLFC_REFRESH_TIMER_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_MASK 0xffffffffffff0000UL #define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_WIDTH 48 #define LPORT_XLMAC_PFC_TYPE_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD; #define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_TYPE_PFC_ETH_TYPE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_MASK 0xffffffffffff0000UL #define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_WIDTH 48 #define LPORT_XLMAC_PFC_OPCODE_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD; #define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_OPCODE_PFC_OPCODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_DA_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_DA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD; #define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_WIDTH 48 #define LPORT_XLMAC_PFC_DA_PFC_MACDA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_DA_OVERLAY_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD; #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_MASK 0x0000ffff00000000UL #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_WIDTH 16 #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD; #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_PFC_DA_OVERLAY_PFC_MACDA_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffc000UL #define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_WIDTH 50 #define LPORT_XLMAC_LLFC_CTRL_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD; #define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_MASK 0x0000000000003fc0UL #define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_WIDTH 8 #define LPORT_XLMAC_LLFC_CTRL_LLFC_IMG_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD; #define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD; #define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD; #define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD; #define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD; #define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_RX_LLFC_EN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD; #define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_LLFC_CTRL_TX_LLFC_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD; #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK 0xfffffffff0000000UL #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 36 #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD; #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_MASK 0x000000000ffff000UL #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_WIDTH 16 #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD; #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK 0x0000000000000f00UL #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4 #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD; #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK 0x00000000000000ffUL #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8 #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK 0xffffffffff000000UL #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 40 #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_MASK 0x0000000000f00000UL #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_WIDTH 4 #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_SHIFT 20 extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_MASK 0x00000000000ff000UL #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_WIDTH 8 #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK 0x0000000000000f00UL #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4 #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK 0x00000000000000ffUL #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8 #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_MASK 0xfffe000000000000UL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_WIDTH 15 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_SHIFT 49 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_MASK 0x0001000000000000UL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_MASK 0x0000ffff00000000UL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_WIDTH 16 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_WIDTH 32 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8UL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_WIDTH 61 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_MASK 0x0000000000000007UL #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_WIDTH 3 #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffe00UL #define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_WIDTH 55 #define LPORT_XLMAC_FIFO_STATUS_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD; #define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_MASK 0x0000000000000100UL #define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_LINK_STATUS_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD; #define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD; #define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1 #define LPORT_XLMAC_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_MASK 0xffffffffffffff00UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 56 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD; #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_WIDTH 1 #define LPORT_XLMAC_LAG_FAILOVER_STATUS_RSVD_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD; #define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_WIDTH 1 #define LPORT_XLMAC_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_EEE_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_RSVD_FIELD; #define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_WIDTH 1 #define LPORT_XLMAC_EEE_CTRL_RSVD_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD; #define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_EEE_CTRL_EEE_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD; #define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_MASK 0xffff000000000000UL #define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_WIDTH 16 #define LPORT_XLMAC_EEE_TIMERS_EEE_REF_COUNT_FIELD_SHIFT 48 extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD; #define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_MASK 0x0000ffff00000000UL #define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_WIDTH 16 #define LPORT_XLMAC_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD; #define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_WIDTH 32 #define LPORT_XLMAC_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD; #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD; #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_XLMAC_EEE_TIMERS_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD; #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_MASK 0xffffffffff000000UL #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_WIDTH 40 #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD; #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_MASK 0x0000000000ffffffUL #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_WIDTH 24 #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD; #define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_WIDTH 64 #define LPORT_XLMAC_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD; #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD; #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_HIGIG_HDR_0_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD; #define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_WIDTH 64 #define LPORT_XLMAC_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD; #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD; #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_HIGIG_HDR_1_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffe0000UL #define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_WIDTH 47 #define LPORT_XLMAC_GMII_EEE_CTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD; #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_MASK 0x0000000000010000UL #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD; #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_WIDTH 16 #define LPORT_XLMAC_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD; #define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_MASK 0xffffffffffff0000UL #define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_WIDTH 48 #define LPORT_XLMAC_TIMESTAMP_ADJUST_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD; #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_MASK 0x0000000000008000UL #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_WIDTH 1 #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_SHIFT 15 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD; #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_MASK 0x0000000000007e00UL #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_WIDTH 6 #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_SHIFT 9 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD; #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_MASK 0x00000000000001ffUL #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_WIDTH 9 #define LPORT_XLMAC_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_MASK 0xffffffffffc00000UL #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_WIDTH 42 #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_MASK 0x0000000000200000UL #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 21 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_MASK 0x00000000001ff800UL #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10 #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_SHIFT 11 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_MASK 0x0000000000000400UL #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 10 extern const ru_field_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_MASK 0x00000000000003ffUL #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10 #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_MASK 0xfffffff800000000UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_WIDTH 29 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_SHIFT 35 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_MASK 0x00000007fffffff8UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_WIDTH 32 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_MASK 0xfffffff800000000UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_WIDTH 29 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_RESERVED0_FIELD_SHIFT 35 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_MASK 0x0000000700000000UL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_WIDTH 3 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_XLMAC_TX_CRC_CORRUPT_CTRL_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffffe0UL #define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_WIDTH 59 #define LPORT_XLMAC_E2E_CTRL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD; #define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD; #define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD; #define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD; #define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_WIDTH 1 #define LPORT_XLMAC_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD; #define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_WIDTH 1 #define LPORT_XLMAC_E2E_CTRL_E2E_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_WIDTH 64 #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_E2ECC_MODULE_HDR_0_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_WIDTH 64 #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD; #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_E2ECC_MODULE_HDR_1_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_WIDTH 64 #define LPORT_XLMAC_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_E2ECC_DATA_HDR_0_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_WIDTH 64 #define LPORT_XLMAC_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD; #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_E2ECC_DATA_HDR_1_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_WIDTH 64 #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_E2EFC_MODULE_HDR_0_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_WIDTH 64 #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD; #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_E2EFC_MODULE_HDR_1_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_WIDTH 64 #define LPORT_XLMAC_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_E2EFC_DATA_HDR_0_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_MASK 0xffffffffffffffffUL #define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_WIDTH 64 #define LPORT_XLMAC_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_MASK 0xffffffff00000000UL #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_HI_FIELD_SHIFT 32 extern const ru_field_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD; #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_MASK 0x00000000ffffffffUL #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_WIDTH 32 #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_E2EFC_DATA_HDR_1_LO_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD; #define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_MASK 0xffffffffffffffc0UL #define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_WIDTH 58 #define LPORT_XLMAC_TXFIFO_CELL_CNT_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD; #define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_MASK 0x000000000000003fUL #define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_WIDTH 6 #define LPORT_XLMAC_TXFIFO_CELL_CNT_CELL_CNT_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD; #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_MASK 0xffffffffffffffc0UL #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_WIDTH 58 #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD; #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_MASK 0x000000000000003fUL #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_WIDTH 6 #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_MASK 0xffffffffff000000UL #define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_WIDTH 40 #define LPORT_XLMAC_MEM_CTRL_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD; #define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_MASK 0x0000000000fff000UL #define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12 #define LPORT_XLMAC_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD; #define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_MASK 0x0000000000000fffUL #define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12 #define LPORT_XLMAC_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD; #define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_ECC_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD; #define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD; #define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD; #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD; #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcUL #define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62 #define LPORT_XLMAC_TX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff0UL #define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_WIDTH 60 #define LPORT_XLMAC_CLEAR_ECC_STATUS_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD; #define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_MASK 0xffffffffffffc000UL #define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_WIDTH 50 #define LPORT_XLMAC_INTR_STATUS_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_MASK 0x0000000000002000UL #define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_SHIFT 13 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000001000UL #define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000800UL #define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_SHIFT 11 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000400UL #define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_SHIFT 10 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000200UL #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000100UL #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD; #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD; #define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_MASK 0xffffffffffffc000UL #define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_WIDTH 50 #define LPORT_XLMAC_INTR_ENABLE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_MASK 0x0000000000002000UL #define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_SHIFT 13 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000001000UL #define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000800UL #define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_SHIFT 11 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000400UL #define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_SHIFT 10 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000200UL #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000100UL #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000080UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000040UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020UL #define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000010UL #define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_SHIFT 4 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000008UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000004UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000002UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD; #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000001UL #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define LPORT_XLMAC_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_SHIFT 0 extern const ru_field_rec LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD; #define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_MASK 0xffffffffffff0000UL #define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_WIDTH 48 #define LPORT_XLMAC_VERSION_ID_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD; #define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_MASK 0x000000000000ffffUL #define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_WIDTH 16 #define LPORT_XLMAC_VERSION_ID_XLMAC_VERSION_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX64_COUNT40_FIELD; #define LPORT_MIB_GRX64_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX64_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX64_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX127_COUNT40_FIELD; #define LPORT_MIB_GRX127_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX127_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX127_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX255_COUNT40_FIELD; #define LPORT_MIB_GRX255_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX255_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX255_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX511_COUNT40_FIELD; #define LPORT_MIB_GRX511_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX511_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX511_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX1023_COUNT40_FIELD; #define LPORT_MIB_GRX1023_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX1023_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX1023_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX1518_COUNT40_FIELD; #define LPORT_MIB_GRX1518_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX1518_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX1518_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX1522_COUNT40_FIELD; #define LPORT_MIB_GRX1522_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX1522_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX1522_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX2047_COUNT40_FIELD; #define LPORT_MIB_GRX2047_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX2047_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX2047_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX4095_COUNT40_FIELD; #define LPORT_MIB_GRX4095_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX4095_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX4095_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX9216_COUNT40_FIELD; #define LPORT_MIB_GRX9216_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX9216_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX9216_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRX16383_COUNT40_FIELD; #define LPORT_MIB_GRX16383_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRX16383_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRX16383_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPKT_COUNT40_FIELD; #define LPORT_MIB_GRXPKT_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPKT_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXUCA_COUNT40_FIELD; #define LPORT_MIB_GRXUCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXUCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXUCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXMCA_COUNT40_FIELD; #define LPORT_MIB_GRXMCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXMCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXMCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXBCA_COUNT40_FIELD; #define LPORT_MIB_GRXBCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXBCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXBCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXFCS_COUNT40_FIELD; #define LPORT_MIB_GRXFCS_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXFCS_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXCF_COUNT40_FIELD; #define LPORT_MIB_GRXCF_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXCF_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXCF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPF_COUNT40_FIELD; #define LPORT_MIB_GRXPF_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPF_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPP_COUNT40_FIELD; #define LPORT_MIB_GRXPP_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPP_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPP_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXUO_COUNT40_FIELD; #define LPORT_MIB_GRXUO_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXUO_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXUO_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXUDA_COUNT40_FIELD; #define LPORT_MIB_GRXUDA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXUDA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXUDA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXWSA_COUNT40_FIELD; #define LPORT_MIB_GRXWSA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXWSA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXWSA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXALN_COUNT40_FIELD; #define LPORT_MIB_GRXALN_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXALN_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXALN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXFLR_COUNT40_FIELD; #define LPORT_MIB_GRXFLR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXFLR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXFLR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXFRERR_COUNT40_FIELD; #define LPORT_MIB_GRXFRERR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXFRERR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXFRERR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXFCR_COUNT40_FIELD; #define LPORT_MIB_GRXFCR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXFCR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXFCR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXOVR_COUNT40_FIELD; #define LPORT_MIB_GRXOVR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXOVR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXOVR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXJBR_COUNT40_FIELD; #define LPORT_MIB_GRXJBR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXJBR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXJBR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXMTUE_COUNT40_FIELD; #define LPORT_MIB_GRXMTUE_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXMTUE_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXMTUE_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXMCRC_COUNT40_FIELD; #define LPORT_MIB_GRXMCRC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXMCRC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXMCRC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPRM_COUNT40_FIELD; #define LPORT_MIB_GRXPRM_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPRM_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPRM_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXVLN_COUNT40_FIELD; #define LPORT_MIB_GRXVLN_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXVLN_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXDVLN_COUNT40_FIELD; #define LPORT_MIB_GRXDVLN_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXDVLN_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXDVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXTRFU_COUNT40_FIELD; #define LPORT_MIB_GRXTRFU_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXTRFU_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXTRFU_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPOK_COUNT40_FIELD; #define LPORT_MIB_GRXPOK_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPOK_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPOK_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD; #define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCOFF7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP0_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP1_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP2_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP3_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP4_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP5_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP6_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPFCP7_COUNT40_FIELD; #define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPFCP7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXSCHCRC_COUNT40_FIELD; #define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXSCHCRC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXBYT_COUNT48_FIELD; #define LPORT_MIB_GRXBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_MIB_GRXBYT_COUNT48_FIELD_WIDTH 48 #define LPORT_MIB_GRXBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXRPKT_COUNT40_FIELD; #define LPORT_MIB_GRXRPKT_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXRPKT_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXRPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXUND_COUNT40_FIELD; #define LPORT_MIB_GRXUND_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXUND_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXUND_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXFRG_COUNT40_FIELD; #define LPORT_MIB_GRXFRG_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXFRG_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXFRG_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXRBYT_COUNT48_FIELD; #define LPORT_MIB_GRXRBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_MIB_GRXRBYT_COUNT48_FIELD_WIDTH 48 #define LPORT_MIB_GRXRBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX64_COUNT40_FIELD; #define LPORT_MIB_GTX64_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX64_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX64_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX127_COUNT40_FIELD; #define LPORT_MIB_GTX127_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX127_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX127_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX255_COUNT40_FIELD; #define LPORT_MIB_GTX255_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX255_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX255_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX511_COUNT40_FIELD; #define LPORT_MIB_GTX511_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX511_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX511_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX1023_COUNT40_FIELD; #define LPORT_MIB_GTX1023_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX1023_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX1023_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX1518_COUNT40_FIELD; #define LPORT_MIB_GTX1518_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX1518_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX1518_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX1522_COUNT40_FIELD; #define LPORT_MIB_GTX1522_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX1522_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX1522_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX2047_COUNT40_FIELD; #define LPORT_MIB_GTX2047_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX2047_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX2047_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX4095_COUNT40_FIELD; #define LPORT_MIB_GTX4095_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX4095_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX4095_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX9216_COUNT40_FIELD; #define LPORT_MIB_GTX9216_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX9216_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX9216_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTX16383_COUNT40_FIELD; #define LPORT_MIB_GTX16383_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTX16383_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTX16383_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPOK_COUNT40_FIELD; #define LPORT_MIB_GTXPOK_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPOK_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPOK_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPKT_COUNT40_FIELD; #define LPORT_MIB_GTXPKT_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPKT_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXUCA_COUNT40_FIELD; #define LPORT_MIB_GTXUCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXUCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXUCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXMCA_COUNT40_FIELD; #define LPORT_MIB_GTXMCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXMCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXMCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXBCA_COUNT40_FIELD; #define LPORT_MIB_GTXBCA_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXBCA_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXBCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPF_COUNT40_FIELD; #define LPORT_MIB_GTXPF_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPF_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFC_COUNT40_FIELD; #define LPORT_MIB_GTXPFC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXJBR_COUNT40_FIELD; #define LPORT_MIB_GTXJBR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXJBR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXJBR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXFCS_COUNT40_FIELD; #define LPORT_MIB_GTXFCS_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXFCS_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXCF_COUNT40_FIELD; #define LPORT_MIB_GTXCF_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXCF_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXCF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXOVR_COUNT40_FIELD; #define LPORT_MIB_GTXOVR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXOVR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXOVR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXDFR_COUNT40_FIELD; #define LPORT_MIB_GTXDFR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXDFR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXDFR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXEDF_COUNT40_FIELD; #define LPORT_MIB_GTXEDF_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXEDF_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXEDF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXSCL_COUNT40_FIELD; #define LPORT_MIB_GTXSCL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXSCL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXSCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXMCL_COUNT40_FIELD; #define LPORT_MIB_GTXMCL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXMCL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXMCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXLCL_COUNT40_FIELD; #define LPORT_MIB_GTXLCL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXLCL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXLCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXXCL_COUNT40_FIELD; #define LPORT_MIB_GTXXCL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXXCL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXXCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXFRG_COUNT40_FIELD; #define LPORT_MIB_GTXFRG_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXFRG_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXFRG_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXERR_COUNT40_FIELD; #define LPORT_MIB_GTXERR_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXERR_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXERR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXVLN_COUNT40_FIELD; #define LPORT_MIB_GTXVLN_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXVLN_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXDVLN_COUNT40_FIELD; #define LPORT_MIB_GTXDVLN_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXDVLN_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXDVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXRPKT_COUNT40_FIELD; #define LPORT_MIB_GTXRPKT_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXRPKT_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXRPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXUFL_COUNT40_FIELD; #define LPORT_MIB_GTXUFL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXUFL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXUFL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP0_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP1_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP2_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP3_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP4_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP5_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP6_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXPFCP7_COUNT40_FIELD; #define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXPFCP7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXNCL_COUNT40_FIELD; #define LPORT_MIB_GTXNCL_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXNCL_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXNCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXBYT_COUNT48_FIELD; #define LPORT_MIB_GTXBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffUL #define LPORT_MIB_GTXBYT_COUNT48_FIELD_WIDTH 48 #define LPORT_MIB_GTXBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXLPI_COUNT32_FIELD; #define LPORT_MIB_GRXLPI_COUNT32_FIELD_MASK 0x00000000ffffffffUL #define LPORT_MIB_GRXLPI_COUNT32_FIELD_WIDTH 32 #define LPORT_MIB_GRXLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXDLPI_COUNT32_FIELD; #define LPORT_MIB_GRXDLPI_COUNT32_FIELD_MASK 0x00000000ffffffffUL #define LPORT_MIB_GRXDLPI_COUNT32_FIELD_WIDTH 32 #define LPORT_MIB_GRXDLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXLPI_COUNT32_FIELD; #define LPORT_MIB_GTXLPI_COUNT32_FIELD_MASK 0x00000000ffffffffUL #define LPORT_MIB_GTXLPI_COUNT32_FIELD_WIDTH 32 #define LPORT_MIB_GTXLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXDLPI_COUNT32_FIELD; #define LPORT_MIB_GTXDLPI_COUNT32_FIELD_MASK 0x00000000ffffffffUL #define LPORT_MIB_GTXDLPI_COUNT32_FIELD_WIDTH 32 #define LPORT_MIB_GTXDLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXPTLLFC_COUNT40_FIELD; #define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXPTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXLTLLFC_COUNT40_FIELD; #define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXLTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD; #define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GRXLLFCFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MIB_GTXLTLLFC_COUNT40_FIELD; #define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffUL #define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_WIDTH 40 #define LPORT_MIB_GTXLTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD; #define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_WIDTH 16 #define LPORT_SRDS_DUAL_SERDES_REVISION_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD; #define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_WIDTH 16 #define LPORT_SRDS_DUAL_SERDES_REVISION_SERDES_REV_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK 0x0000000000020000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT 17 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK 0x0000000000010000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK 0x00000000ffffffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH 32 #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK 0x0000000000020000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT 17 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK 0x0000000000010000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK 0x00000000ffffffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH 32 #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_ERR_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_MASK 0x0000000000020000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_START_BUSY_FIELD_SHIFT 17 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_MASK 0x0000000000010000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_R_W_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_DATA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_MASK 0x00000000ffffffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_WIDTH 32 #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_ERR_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_MASK 0x0000000000020000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_START_BUSY_FIELD_SHIFT 17 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_MASK 0x0000000000010000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_WIDTH 1 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_R_W_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_DATA_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_MASK 0x00000000ffffffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_WIDTH 32 #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_MASK 0x000000000000ffffUL #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_WIDTH 16 #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_TEST_EN_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_MASK 0x000000000003e000UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH 5 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT 13 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_MASK 0x0000000000001f00UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_WIDTH 5 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_PRTAD_FIELD_SHIFT 8 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_MASK 0x00000000000000c0UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED1_FIELD_SHIFT 6 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_MASK 0x0000000000000038UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_WIDTH 3 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_RESERVED2_FIELD_SHIFT 3 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_MASK 0x0000000000000004UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_SERDES_RESET_FIELD_SHIFT 2 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_MASK 0x0000000000000002UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REFCLK_RESET_FIELD_SHIFT 1 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_MASK 0x0000000000000001UL #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_IDDQ_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_MASK 0x00000000fffff800UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_WIDTH 21 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_MASK 0x0000000000000600UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_MOD_DEF0_FIELD_SHIFT 9 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_MASK 0x0000000000000180UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_EXT_SIG_DET_FIELD_SHIFT 7 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_MASK 0x0000000000000040UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_PLL_LOCK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_MASK 0x0000000000000030UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_LINK_STATUS_FIELD_SHIFT 4 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_MASK 0x000000000000000cUL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_CDR_LOCK_FIELD_SHIFT 2 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_MASK 0x0000000000000003UL #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_0_STATUS_RX_SIGDET_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_WIDTH 13 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_MASK 0x0000000000040000UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_TEST_EN_FIELD_SHIFT 18 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_MASK 0x000000000003e000UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_WIDTH 5 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_LN_OFFSET_FIELD_SHIFT 13 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_MASK 0x0000000000001f00UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_WIDTH 5 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_PRTAD_FIELD_SHIFT 8 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_MASK 0x00000000000000c0UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED1_FIELD_SHIFT 6 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_MASK 0x0000000000000038UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_WIDTH 3 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_RESERVED2_FIELD_SHIFT 3 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_MASK 0x0000000000000004UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_SERDES_RESET_FIELD_SHIFT 2 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_MASK 0x0000000000000002UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REFCLK_RESET_FIELD_SHIFT 1 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_MASK 0x0000000000000001UL #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_IDDQ_FIELD_SHIFT 0 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_MASK 0x00000000fffff800UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_WIDTH 21 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_MASK 0x0000000000000600UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_MOD_DEF0_FIELD_SHIFT 9 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_MASK 0x0000000000000180UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_EXT_SIG_DET_FIELD_SHIFT 7 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_MASK 0x0000000000000040UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_WIDTH 1 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_PLL_LOCK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_MASK 0x0000000000000030UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_LINK_STATUS_FIELD_SHIFT 4 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_MASK 0x000000000000000cUL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_CDR_LOCK_FIELD_SHIFT 2 extern const ru_field_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_MASK 0x0000000000000003UL #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_WIDTH 2 #define LPORT_SRDS_DUAL_SERDES_1_STATUS_RX_SIGDET_FIELD_SHIFT 0 extern const ru_field_rec LPORT_LED_CNTRL_RESERVED0_FIELD; #define LPORT_LED_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_LED_CNTRL_RESERVED0_FIELD_WIDTH 16 #define LPORT_LED_CNTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD; #define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_MASK 0x0000000000008000UL #define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_LNK_OVRD_EN_FIELD_SHIFT 15 extern const ru_field_rec LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD; #define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_MASK 0x0000000000004000UL #define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPD_OVRD_EN_FIELD_SHIFT 14 extern const ru_field_rec LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD; #define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_MASK 0x0000000000002000UL #define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_LNK_STATUS_OVRD_FIELD_SHIFT 13 extern const ru_field_rec LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD; #define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_MASK 0x0000000000001c00UL #define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_WIDTH 3 #define LPORT_LED_CNTRL_LED_SPD_OVRD_FIELD_SHIFT 10 extern const ru_field_rec LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD; #define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_MASK 0x0000000000000200UL #define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_ACT_LED_POL_SEL_FIELD_SHIFT 9 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_MASK 0x0000000000000100UL #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_POL_SEL_FIELD_SHIFT 8 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_MASK 0x0000000000000080UL #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_MASK 0x0000000000000040UL #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL_FIELD_SHIFT 6 extern const ru_field_rec LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD; #define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_MASK 0x0000000000000020UL #define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_ACT_LED_ACT_SEL_FIELD_SHIFT 5 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_MASK 0x0000000000000010UL #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED2_ACT_SEL_FIELD_SHIFT 4 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_MASK 0x0000000000000008UL #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED1_ACT_SEL_FIELD_SHIFT 3 extern const ru_field_rec LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD; #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_MASK 0x0000000000000004UL #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_SPDLNK_LED0_ACT_SEL_FIELD_SHIFT 2 extern const ru_field_rec LPORT_LED_CNTRL_TX_ACT_EN_FIELD; #define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_MASK 0x0000000000000002UL #define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_TX_ACT_EN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_LED_CNTRL_RX_ACT_EN_FIELD; #define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_WIDTH 1 #define LPORT_LED_CNTRL_RX_ACT_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_MASK 0x00000000ff000000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_WIDTH 8 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_MASK 0x0000000000e00000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_2_FIELD_SHIFT 21 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_MASK 0x00000000001c0000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_RSVD_SEL_SPD_ENCODE_1_FIELD_SHIFT 18 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_MASK 0x0000000000038000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10G_ENCODE_FIELD_SHIFT 15 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_MASK 0x0000000000007000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_2500M_ENCODE_FIELD_SHIFT 12 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_MASK 0x0000000000000e00UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_1000M_ENCODE_FIELD_SHIFT 9 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_MASK 0x00000000000001c0UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_100M_ENCODE_FIELD_SHIFT 6 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_MASK 0x0000000000000038UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_10M_ENCODE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_MASK 0x0000000000000007UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_SEL_NO_LINK_ENCODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_MASK 0x00000000ff000000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_WIDTH 8 #define LPORT_LED_LINK_AND_SPEED_ENCODING_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_MASK 0x0000000000e00000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_2_FIELD_SHIFT 21 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_MASK 0x00000000001c0000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_RSVD_SPD_ENCODE_1_FIELD_SHIFT 18 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_MASK 0x0000000000038000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10G_ENCODE_FIELD_SHIFT 15 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_MASK 0x0000000000007000UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_M2500_ENCODE_FIELD_SHIFT 12 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_MASK 0x0000000000000e00UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_M1000_ENCODE_FIELD_SHIFT 9 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_MASK 0x00000000000001c0UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_M100_ENCODE_FIELD_SHIFT 6 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_MASK 0x0000000000000038UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_M10_ENCODE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD; #define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_MASK 0x0000000000000007UL #define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_WIDTH 3 #define LPORT_LED_LINK_AND_SPEED_ENCODING_NO_LINK_ENCODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD; #define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_WIDTH 13 #define LPORT_LED_AGGREGATE_LED_CNTRL_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD; #define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_MASK 0x0000000000040000UL #define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_AGGREGATE_LED_CNTRL_LNK_POL_SEL_FIELD_SHIFT 18 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD; #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_MASK 0x0000000000020000UL #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_WIDTH 1 #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_POL_SEL_FIELD_SHIFT 17 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD; #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_MASK 0x0000000000010000UL #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_WIDTH 1 #define LPORT_LED_AGGREGATE_LED_CNTRL_ACT_SEL_FIELD_SHIFT 16 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD; #define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_MASK 0x000000000000ffffUL #define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_WIDTH 16 #define LPORT_LED_AGGREGATE_LED_CNTRL_PORT_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD; #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK 0x00000000ffff0000UL #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16 #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16 extern const ru_field_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD; #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK 0x000000000000ffffUL #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16 #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD; #define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffff800UL #define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_WIDTH 21 #define LPORT_CTRL_LPORT_CNTRL_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD; #define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_MASK 0x0000000000000400UL #define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_TIMEOUT_RST_DISABLE_FIELD_SHIFT 10 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD; #define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_MASK 0x0000000000000200UL #define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_P4_MODE_FIELD_SHIFT 9 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD; #define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_MASK 0x0000000000000100UL #define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_P0_MODE_FIELD_SHIFT 8 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_MASK 0x0000000000000080UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_7_FIELD_SHIFT 7 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_MASK 0x0000000000000040UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_6_FIELD_SHIFT 6 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_MASK 0x0000000000000020UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_5_FIELD_SHIFT 5 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_MASK 0x0000000000000010UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_4_FIELD_SHIFT 4 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_MASK 0x0000000000000008UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_3_FIELD_SHIFT 3 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_MASK 0x0000000000000004UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_2_FIELD_SHIFT 2 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_MASK 0x0000000000000002UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_1_FIELD_SHIFT 1 extern const ru_field_rec LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD; #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_MASK 0x0000000000000001UL #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_WIDTH 1 #define LPORT_CTRL_LPORT_CNTRL_GPORT_SEL_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD; #define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_WIDTH 16 #define LPORT_CTRL_LPORT_REVISION_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD; #define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_MASK 0x000000000000ffffUL #define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_WIDTH 16 #define LPORT_CTRL_LPORT_REVISION_LPORT_REV_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD; #define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_WIDTH 16 #define LPORT_CTRL_QEGPHY_REVISION_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD; #define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_MASK 0x000000000000ffffUL #define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_WIDTH 16 #define LPORT_CTRL_QEGPHY_REVISION_QUAD_PHY_REV_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffffffc0UL #define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_WIDTH 26 #define LPORT_CTRL_QEGPHY_TEST_CNTRL_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_MASK 0x0000000000000030UL #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_WIDTH 2 #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_REFCLK_SEL_FIELD_SHIFT 4 extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_MASK 0x000000000000000cUL #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_WIDTH 2 #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_SEL_DIV5_FIELD_SHIFT 2 extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_MASK 0x0000000000000002UL #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PLL_CLK125_250_SEL_FIELD_SHIFT 1 extern const ru_field_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_TEST_CNTRL_PHY_TEST_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffe0000UL #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_WIDTH 15 #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_MASK 0x000000000001f000UL #define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_WIDTH 5 #define LPORT_CTRL_QEGPHY_CNTRL_PHY_PHYAD_FIELD_SHIFT 12 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_MASK 0x0000000000000e00UL #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_WIDTH 3 #define LPORT_CTRL_QEGPHY_CNTRL_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_MASK 0x0000000000000100UL #define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_CNTRL_PHY_RESET_FIELD_SHIFT 8 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_MASK 0x0000000000000080UL #define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_CNTRL_CK25_EN_FIELD_SHIFT 7 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_MASK 0x0000000000000040UL #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_GLOBAL_PWR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_MASK 0x0000000000000020UL #define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_CNTRL_FORCE_DLL_EN_FIELD_SHIFT 5 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_MASK 0x000000000000001eUL #define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_WIDTH 4 #define LPORT_CTRL_QEGPHY_CNTRL_EXT_PWR_DOWN_FIELD_SHIFT 1 extern const ru_field_rec LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD; #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_MASK 0x0000000000000001UL #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_CNTRL_IDDQ_BIAS_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_WIDTH 18 #define LPORT_CTRL_QEGPHY_STATUS_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_MASK 0x0000000000002000UL #define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_STATUS_GPHY_TEST_STATUS_FIELD_SHIFT 13 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_MASK 0x0000000000001e00UL #define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_WIDTH 4 #define LPORT_CTRL_QEGPHY_STATUS_RECOVERED_CLK_LOCK_FIELD_SHIFT 9 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_MASK 0x0000000000000100UL #define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_WIDTH 1 #define LPORT_CTRL_QEGPHY_STATUS_PLL_LOCK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_MASK 0x00000000000000f0UL #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_WIDTH 4 #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_APD_FIELD_SHIFT 4 extern const ru_field_rec LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD; #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_MASK 0x000000000000000fUL #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_WIDTH 4 #define LPORT_CTRL_QEGPHY_STATUS_ENERGY_DET_MASKED_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD; #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_MASK 0x00000000ffff0000UL #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_WIDTH 16 #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_ON_TIME_FIELD_SHIFT 16 extern const ru_field_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD; #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_MASK 0x000000000000ffffUL #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_WIDTH 16 #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_LED_OFF_TIME_FIELD_SHIFT 0 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_MASK 0x00000000fe000000UL #define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_WIDTH 7 #define LPORT_CTRL_LED_SERIAL_CNTRL_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_MASK 0x0000000001800000UL #define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_WIDTH 2 #define LPORT_CTRL_LED_SERIAL_CNTRL_SMODE_FIELD_SHIFT 23 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_MASK 0x0000000000400000UL #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_WIDTH 1 #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_FREQUENCY_FIELD_SHIFT 22 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_MASK 0x0000000000200000UL #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_WIDTH 1 #define LPORT_CTRL_LED_SERIAL_CNTRL_SLED_CLK_POL_FIELD_SHIFT 21 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_MASK 0x00000000001f0000UL #define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_WIDTH 5 #define LPORT_CTRL_LED_SERIAL_CNTRL_REFRESH_PERIOD_FIELD_SHIFT 16 extern const ru_field_rec LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD; #define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_MASK 0x000000000000ffffUL #define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_WIDTH 16 #define LPORT_CTRL_LED_SERIAL_CNTRL_PORT_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_CNTRL_RESERVED0_FIELD; #define LPORT_RGMII_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_RGMII_CNTRL_RESERVED0_FIELD_WIDTH 16 #define LPORT_RGMII_CNTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD; #define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_MASK 0x0000000000008000UL #define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_COL_CRS_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD; #define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_MASK 0x0000000000004000UL #define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_RX_ERR_MASK_FIELD_SHIFT 14 extern const ru_field_rec LPORT_RGMII_CNTRL_LPI_COUNT_FIELD; #define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_MASK 0x0000000000003e00UL #define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_WIDTH 5 #define LPORT_RGMII_CNTRL_LPI_COUNT_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD; #define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_MASK 0x0000000000000100UL #define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_TX_CLK_STOP_EN_FIELD_SHIFT 8 extern const ru_field_rec LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD; #define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_MASK 0x0000000000000080UL #define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_TX_PAUSE_EN_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD; #define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_RX_PAUSE_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD; #define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_MASK 0x0000000000000020UL #define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_RVMII_REF_SEL_FIELD_SHIFT 5 extern const ru_field_rec LPORT_RGMII_CNTRL_PORT_MODE_FIELD; #define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_MASK 0x000000000000001cUL #define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_WIDTH 3 #define LPORT_RGMII_CNTRL_PORT_MODE_FIELD_SHIFT 2 extern const ru_field_rec LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD; #define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_MASK 0x0000000000000002UL #define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_ID_MODE_DIS_FIELD_SHIFT 1 extern const ru_field_rec LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD; #define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_MASK 0x0000000000000001UL #define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_WIDTH 1 #define LPORT_RGMII_CNTRL_RGMII_MODE_EN_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_IB_STATUS_RESERVED0_FIELD; #define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffffe0UL #define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_WIDTH 27 #define LPORT_RGMII_IB_STATUS_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD; #define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_MASK 0x0000000000000010UL #define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_WIDTH 1 #define LPORT_RGMII_IB_STATUS_IB_STATUS_OVRD_FIELD_SHIFT 4 extern const ru_field_rec LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD; #define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_MASK 0x0000000000000008UL #define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_WIDTH 1 #define LPORT_RGMII_IB_STATUS_LINK_DECODE_FIELD_SHIFT 3 extern const ru_field_rec LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD; #define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_MASK 0x0000000000000004UL #define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_WIDTH 1 #define LPORT_RGMII_IB_STATUS_DUPLEX_DECODE_FIELD_SHIFT 2 extern const ru_field_rec LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD; #define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_MASK 0x0000000000000003UL #define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_WIDTH 2 #define LPORT_RGMII_IB_STATUS_SPEED_DECODE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffffe00UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_WIDTH 23 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_MASK 0x0000000000000100UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_WIDTH 1 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_RESET_FIELD_SHIFT 8 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_MASK 0x0000000000000080UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_WIDTH 1 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_WIDTH 1 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_MASK 0x0000000000000020UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_WIDTH 1 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_SHIFT 5 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_MASK 0x0000000000000010UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_WIDTH 1 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_SHIFT 4 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_MASK 0x000000000000000cUL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_WIDTH 2 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_SHIFT 2 extern const ru_field_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_MASK 0x0000000000000003UL #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_WIDTH 2 #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_WIDTH 4 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_MASK 0x0000000008000000UL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_SHIFT 27 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_MASK 0x0000000004000000UL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_SHIFT 26 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_MASK 0x0000000003fc0000UL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_WIDTH 8 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD; #define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_MASK 0x00000000fffc0000UL #define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_WIDTH 14 #define LPORT_RGMII_ATE_RX_EXP_DATA_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD; #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD; #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_WIDTH 13 #define LPORT_RGMII_ATE_RX_STATUS_0_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_MASK 0x0000000000040000UL #define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_RX_STATUS_0_RX_OK_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_MASK 0x00000000fffc0000UL #define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_WIDTH 14 #define LPORT_RGMII_ATE_RX_STATUS_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD; #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_WIDTH 4 #define LPORT_RGMII_ATE_TX_CNTRL_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_MASK 0x000000000fc00000UL #define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_WIDTH 6 #define LPORT_RGMII_ATE_TX_CNTRL_PKT_IPG_FIELD_SHIFT 22 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_MASK 0x00000000003ff800UL #define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_WIDTH 11 #define LPORT_RGMII_ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_SHIFT 11 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_MASK 0x00000000000007f8UL #define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_WIDTH 8 #define LPORT_RGMII_ATE_TX_CNTRL_PKT_CNT_FIELD_SHIFT 3 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_MASK 0x0000000000000004UL #define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_TX_CNTRL_PKT_GEN_EN_FIELD_SHIFT 2 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_MASK 0x0000000000000002UL #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_FIELD_SHIFT 1 extern const ru_field_rec LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD; #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_MASK 0x0000000000000001UL #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_WIDTH 1 #define LPORT_RGMII_ATE_TX_CNTRL_START_STOP_OVRD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD; #define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_MASK 0x00000000fffc0000UL #define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_WIDTH 14 #define LPORT_RGMII_ATE_TX_DATA_0_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD; #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD; #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_TX_DATA_0_TX_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD; #define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_MASK 0x00000000fffc0000UL #define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_WIDTH 14 #define LPORT_RGMII_ATE_TX_DATA_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD; #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_MASK 0x000000000003fe00UL #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD; #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_MASK 0x00000000000001ffUL #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_WIDTH 9 #define LPORT_RGMII_ATE_TX_DATA_1_TX_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD; #define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_MASK 0x00000000ffff0000UL #define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_WIDTH 16 #define LPORT_RGMII_ATE_TX_DATA_2_ETHER_TYPE_FIELD_SHIFT 16 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD; #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_MASK 0x000000000000ff00UL #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_WIDTH 8 #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_5_FIELD_SHIFT 8 extern const ru_field_rec LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD; #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_MASK 0x00000000000000ffUL #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_WIDTH 8 #define LPORT_RGMII_ATE_TX_DATA_2_TX_DATA_4_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4 #define LPORT_RGMII_TX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_MASK 0x0000000008000000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_MASK 0x0000000007e00000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_MASK 0x0000000000100000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_MASK 0x00000000000fc000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_MASK 0x0000000000002000UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_MASK 0x0000000000001f80UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_MASK 0x000000000000003fUL #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK 0x00000000fffe0000UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 15 #define LPORT_RGMII_TX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_MASK 0x0000000000010000UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_SHIFT 16 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_MASK 0x000000000000f000UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_WIDTH 4 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_SHIFT 12 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_MASK 0x0000000000000800UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_SHIFT 11 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_MASK 0x0000000000000780UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_WIDTH 4 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD; #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_MASK 0x000000000000003fUL #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_MASK 0x0000000008000000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_MASK 0x0000000007e00000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_MASK 0x0000000000100000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_MASK 0x00000000000fc000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_MASK 0x0000000000002000UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_MASK 0x0000000000001f80UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_MASK 0x000000000000003fUL #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 4 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_MASK 0x0000000008000000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_MASK 0x0000000007e00000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_MASK 0x0000000000100000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_MASK 0x00000000000fc000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_MASK 0x0000000000002000UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_MASK 0x0000000000001f80UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_MASK 0x000000000000003fUL #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_MASK 0x00000000fff80000UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_WIDTH 13 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_MASK 0x0000000000040000UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_SHIFT 18 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_MASK 0x000000000003c000UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_WIDTH 4 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_MASK 0x0000000000002000UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_MASK 0x0000000000001f80UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_MASK 0x0000000000000040UL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_WIDTH 1 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD; #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_MASK 0x000000000000003fUL #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_WIDTH 6 #define LPORT_RGMII_RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD; #define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32 #define XLMAC_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD; #define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32 #define XLMAC_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK 0x00000000ffffe000UL #define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19 #define XLMAC_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK 0x0000000000001000UL #define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK 0x0000000000000800UL #define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK 0x0000000000000400UL #define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK 0x0000000000000300UL #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2 #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK 0x00000000000000ffUL #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8 #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD; #define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32 #define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD; #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32 #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK 0x00000000ffffe000UL #define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19 #define XLMAC_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK 0x0000000000001000UL #define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK 0x0000000000000800UL #define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK 0x0000000000000400UL #define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1 #define XLMAC_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK 0x0000000000000300UL #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2 #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD; #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK 0x00000000000000ffUL #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8 #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD; #define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32 #define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD; #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK 0x00000000ffffffffUL #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32 #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_CONFIG_RESERVED0_FIELD; #define XLMAC_CONF_CONFIG_RESERVED0_FIELD_MASK 0x00000000fffffc00UL #define XLMAC_CONF_CONFIG_RESERVED0_FIELD_WIDTH 22 #define XLMAC_CONF_CONFIG_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD; #define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_MASK 0x0000000000000200UL #define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_XLMAC_RESET_FIELD_SHIFT 9 extern const ru_field_rec XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD; #define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_MASK 0x0000000000000100UL #define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_SHIFT 8 extern const ru_field_rec XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD; #define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_MASK 0x0000000000000080UL #define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_SHIFT 7 extern const ru_field_rec XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD; #define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_MASK 0x0000000000000040UL #define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_SHIFT 6 extern const ru_field_rec XLMAC_CONF_CONFIG_MAC_MODE_FIELD; #define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_MASK 0x0000000000000038UL #define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_WIDTH 3 #define XLMAC_CONF_CONFIG_MAC_MODE_FIELD_SHIFT 3 extern const ru_field_rec XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD; #define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_MASK 0x0000000000000004UL #define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_OSTS_TIMER_DISABLE_FIELD_SHIFT 2 extern const ru_field_rec XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD; #define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_MASK 0x0000000000000002UL #define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_BYPASS_OSTS_FIELD_SHIFT 1 extern const ru_field_rec XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD; #define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_MASK 0x0000000000000001UL #define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_WIDTH 1 #define XLMAC_CONF_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD; #define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_MASK 0x00000000fffffff0UL #define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_WIDTH 28 #define XLMAC_CONF_INTERRUPT_CHECK_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD; #define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_MASK 0x000000000000000fUL #define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_WIDTH 4 #define XLMAC_CONF_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD; #define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000UL #define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XLMAC_CONF_PORT_0_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffUL #define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XLMAC_CONF_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD; #define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000UL #define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XLMAC_CONF_PORT_1_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffUL #define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XLMAC_CONF_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD; #define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000UL #define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XLMAC_CONF_PORT_2_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffUL #define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XLMAC_CONF_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD; #define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000UL #define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XLMAC_CONF_PORT_3_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffUL #define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XLMAC_CONF_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD; #define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32 #define MIB_CONF_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD; #define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32 #define MIB_CONF_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK 0x00000000ffffe000UL #define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19 #define MIB_CONF_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_MASK 0x0000000000001000UL #define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK 0x0000000000000800UL #define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_MASK 0x0000000000000400UL #define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK 0x0000000000000300UL #define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2 #define MIB_CONF_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK 0x00000000000000ffUL #define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8 #define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD; #define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32 #define MIB_CONF_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD; #define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32 #define MIB_CONF_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK 0x00000000ffffe000UL #define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19 #define MIB_CONF_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_MASK 0x0000000000001000UL #define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK 0x0000000000000800UL #define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_MASK 0x0000000000000400UL #define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1 #define MIB_CONF_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK 0x0000000000000300UL #define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2 #define MIB_CONF_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD; #define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK 0x00000000000000ffUL #define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8 #define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD; #define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32 #define MIB_CONF_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD; #define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK 0x00000000ffffffffUL #define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32 #define MIB_CONF_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_CNTRL_RESERVED0_FIELD; #define MIB_CONF_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define MIB_CONF_CNTRL_RESERVED0_FIELD_WIDTH 16 #define MIB_CONF_CNTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD; #define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_MASK 0x000000000000f000UL #define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_WIDTH 4 #define MIB_CONF_CNTRL_EEE_CNT_MODE_FIELD_SHIFT 12 extern const ru_field_rec MIB_CONF_CNTRL_SATURATE_EN_FIELD; #define MIB_CONF_CNTRL_SATURATE_EN_FIELD_MASK 0x0000000000000f00UL #define MIB_CONF_CNTRL_SATURATE_EN_FIELD_WIDTH 4 #define MIB_CONF_CNTRL_SATURATE_EN_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_CNTRL_COR_EN_FIELD; #define MIB_CONF_CNTRL_COR_EN_FIELD_MASK 0x00000000000000f0UL #define MIB_CONF_CNTRL_COR_EN_FIELD_WIDTH 4 #define MIB_CONF_CNTRL_COR_EN_FIELD_SHIFT 4 extern const ru_field_rec MIB_CONF_CNTRL_CNT_RST_FIELD; #define MIB_CONF_CNTRL_CNT_RST_FIELD_MASK 0x000000000000000fUL #define MIB_CONF_CNTRL_CNT_RST_FIELD_WIDTH 4 #define MIB_CONF_CNTRL_CNT_RST_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD; #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffffff00UL #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_WIDTH 24 #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD; #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_MASK 0x00000000000000ffUL #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_WIDTH 8 #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD; #define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define MIB_CONF_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffUL #define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define MIB_CONF_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD; #define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define MIB_CONF_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffUL #define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define MIB_CONF_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD; #define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define MIB_CONF_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffUL #define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define MIB_CONF_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD; #define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define MIB_CONF_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffUL #define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define MIB_CONF_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_ECC_CNTRL_RESERVED0_FIELD; #define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffffffcUL #define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_WIDTH 30 #define MIB_CONF_ECC_CNTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD; #define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_WIDTH 1 #define MIB_CONF_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD; #define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_WIDTH 1 #define MIB_CONF_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_MASK 0x00000000fffffe00UL #define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_WIDTH 23 #define MIB_CONF_FORCE_SB_ECC_ERR_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_MASK 0x0000000000000100UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_MASK 0x0000000000000080UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_MASK 0x0000000000000040UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_SHIFT 6 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_MASK 0x0000000000000020UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_SHIFT 5 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_MASK 0x0000000000000010UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_SHIFT 4 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_MASK 0x0000000000000008UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD; #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_MASK 0x00000000fffffe00UL #define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_WIDTH 23 #define MIB_CONF_FORCE_DB_ECC_ERR_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_MASK 0x0000000000000100UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_SHIFT 8 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_MASK 0x0000000000000080UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_MASK 0x0000000000000040UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_SHIFT 6 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_MASK 0x0000000000000020UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_SHIFT 5 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_MASK 0x0000000000000010UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_SHIFT 4 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_MASK 0x0000000000000008UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD; #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_WIDTH 1 #define MIB_CONF_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD; #define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80UL #define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define MIB_CONF_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD; #define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078UL #define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define MIB_CONF_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004UL #define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002UL #define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD; #define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001UL #define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define MIB_CONF_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MDIO_CMD_RESERVED0_FIELD; #define LPORT_MDIO_CMD_RESERVED0_FIELD_MASK 0x00000000c0000000UL #define LPORT_MDIO_CMD_RESERVED0_FIELD_WIDTH 2 #define LPORT_MDIO_CMD_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec LPORT_MDIO_CMD_START_BUSY_FIELD; #define LPORT_MDIO_CMD_START_BUSY_FIELD_MASK 0x0000000020000000UL #define LPORT_MDIO_CMD_START_BUSY_FIELD_WIDTH 1 #define LPORT_MDIO_CMD_START_BUSY_FIELD_SHIFT 29 extern const ru_field_rec LPORT_MDIO_CMD_FAIL_FIELD; #define LPORT_MDIO_CMD_FAIL_FIELD_MASK 0x0000000010000000UL #define LPORT_MDIO_CMD_FAIL_FIELD_WIDTH 1 #define LPORT_MDIO_CMD_FAIL_FIELD_SHIFT 28 extern const ru_field_rec LPORT_MDIO_CMD_OP_CODE_FIELD; #define LPORT_MDIO_CMD_OP_CODE_FIELD_MASK 0x000000000c000000UL #define LPORT_MDIO_CMD_OP_CODE_FIELD_WIDTH 2 #define LPORT_MDIO_CMD_OP_CODE_FIELD_SHIFT 26 extern const ru_field_rec LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD; #define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_MASK 0x0000000003e00000UL #define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_WIDTH 5 #define LPORT_MDIO_CMD_PHY_PRT_ADDR_FIELD_SHIFT 21 extern const ru_field_rec LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD; #define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_MASK 0x00000000001f0000UL #define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_WIDTH 5 #define LPORT_MDIO_CMD_REG_DEV_ADDR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_MDIO_CMD_DATA_ADDR_FIELD; #define LPORT_MDIO_CMD_DATA_ADDR_FIELD_MASK 0x000000000000ffffUL #define LPORT_MDIO_CMD_DATA_ADDR_FIELD_WIDTH 16 #define LPORT_MDIO_CMD_DATA_ADDR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MDIO_CFG_RESERVED0_FIELD; #define LPORT_MDIO_CFG_RESERVED0_FIELD_MASK 0x00000000ffffc000UL #define LPORT_MDIO_CFG_RESERVED0_FIELD_WIDTH 18 #define LPORT_MDIO_CFG_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD; #define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_MASK 0x0000000000002000UL #define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_WIDTH 1 #define LPORT_MDIO_CFG_FREE_RUN_CLK_ENABLE_FIELD_SHIFT 13 extern const ru_field_rec LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD; #define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_MASK 0x0000000000001000UL #define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_WIDTH 1 #define LPORT_MDIO_CFG_SUPRESS_PREAMBLE_FIELD_SHIFT 12 extern const ru_field_rec LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD; #define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_MASK 0x0000000000000ff0UL #define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_WIDTH 8 #define LPORT_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_SHIFT 4 extern const ru_field_rec LPORT_MDIO_CFG_RESERVED2_FIELD; #define LPORT_MDIO_CFG_RESERVED2_FIELD_MASK 0x000000000000000eUL #define LPORT_MDIO_CFG_RESERVED2_FIELD_WIDTH 3 #define LPORT_MDIO_CFG_RESERVED2_FIELD_SHIFT 1 extern const ru_field_rec LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD; #define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_MASK 0x0000000000000001UL #define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_WIDTH 1 #define LPORT_MDIO_CFG_MDIO_CLAUSE_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_STATUS_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_STATUS_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_STATUS_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_STATUS_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_SET_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_SET_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_SET_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_SET_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_SET_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_SET_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_CLEAR_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_CLEAR_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_SET_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_CPU_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_STATUS_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_STATUS_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_STATUS_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_STATUS_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_STATUS_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_SET_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_SET_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_SET_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_SET_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_SET_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_SET_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_SET_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_CLEAR_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_MASK 0x000000007f800000UL #define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_CLEAR_XLMAC_INTR_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_OFF_INTR_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_CLEAR_QGPHY_ENERGY_ON_INTR_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_CLEAR_MDIO_ERR_INTR_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_CLEAR_MDIO_DONE_INTR_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD; #define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_STATUS_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_STATUS_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_SET_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_SET_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_SET_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_SET_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK 0x0000000080000000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000060000000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 29 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000018000000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_RX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 27 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000006000000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_SINGLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 25 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_MASK 0x0000000001800000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_TX_CDC_DOUBLE_BIT_ERR_INTR_MASK_FIELD_SHIFT 23 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x00000000007f8000UL #define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_0_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 15 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_MASK 0x0000000000007800UL #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_OFF_INTR_MASK_FIELD_SHIFT 11 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_MASK 0x0000000000000780UL #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_WIDTH 4 #define LPORT_INTR_0_PCI_MASK_CLEAR_QGPHY_ENERGY_ON_INTR_MASK_FIELD_SHIFT 7 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_MASK 0x0000000000000040UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_ERR_INTR_MASK_FIELD_SHIFT 6 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_MASK 0x0000000000000020UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_CLEAR_MDIO_DONE_INTR_MASK_FIELD_SHIFT 5 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000018UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000006UL #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_0_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD; #define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001UL #define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define LPORT_INTR_0_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_STATUS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_SET_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_SET_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_SET_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_SET_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_SET_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_CLEAR_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_CLEAR_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_CPU_MASK_SET_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_CPU_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_CPU_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_STATUS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_STATUS_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_STATUS_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_SET_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_SET_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_SET_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_SET_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_SET_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_SET_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_MASK 0x00000000f0000000UL #define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_CLEAR_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_MASK 0x000000000c000000UL #define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_CLEAR_RX_REMOTE_FAULT_INTR_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD; #define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_CLEAR_LINK_UP_INTR_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_MASK_STATUS_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_STATUS_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_PCI_MASK_SET_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_MASK_SET_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_SET_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK 0x00000000fc000000UL #define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH 6 #define LPORT_INTR_1_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_MASK 0x0000000003000000UL #define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_WIDTH 2 #define LPORT_INTR_1_PCI_MASK_CLEAR_RX_REMOTE_FAULT_INTR_MASK_FIELD_SHIFT 24 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_MASK 0x0000000000f00000UL #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_OFF_INTR_FIELD_SHIFT 20 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_MASK 0x00000000000f0000UL #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_WIDTH 4 #define LPORT_INTR_1_PCI_MASK_CLEAR_DSERDES_SD_ON_INTR_FIELD_SHIFT 16 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK 0x000000000000ff00UL #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD; #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK 0x00000000000000ffUL #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 8 #define LPORT_INTR_1_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED0_FIELD; #define LPORT_MAB_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffe0000UL #define LPORT_MAB_CNTRL_RESERVED0_FIELD_WIDTH 15 #define LPORT_MAB_CNTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD; #define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_MASK 0x0000000000010000UL #define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_WIDTH 1 #define LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_SHIFT 16 extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED1_FIELD; #define LPORT_MAB_CNTRL_RESERVED1_FIELD_MASK 0x000000000000e000UL #define LPORT_MAB_CNTRL_RESERVED1_FIELD_WIDTH 3 #define LPORT_MAB_CNTRL_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD; #define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_MASK 0x0000000000001000UL #define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_WIDTH 1 #define LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_SHIFT 12 extern const ru_field_rec LPORT_MAB_CNTRL_GMII_TX_RST_FIELD; #define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_MASK 0x0000000000000f00UL #define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_WIDTH 4 #define LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_SHIFT 8 extern const ru_field_rec LPORT_MAB_CNTRL_RESERVED2_FIELD; #define LPORT_MAB_CNTRL_RESERVED2_FIELD_MASK 0x00000000000000e0UL #define LPORT_MAB_CNTRL_RESERVED2_FIELD_WIDTH 3 #define LPORT_MAB_CNTRL_RESERVED2_FIELD_SHIFT 5 extern const ru_field_rec LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD; #define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_MASK 0x0000000000000010UL #define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_WIDTH 1 #define LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_SHIFT 4 extern const ru_field_rec LPORT_MAB_CNTRL_GMII_RX_RST_FIELD; #define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_MASK 0x000000000000000fUL #define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_WIDTH 4 #define LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD; #define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_MASK 0x00000000fffe0000UL #define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_WIDTH 15 #define LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD; #define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_MASK 0x0000000000010000UL #define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_WIDTH 1 #define LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_SHIFT 16 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD; #define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_MASK 0x000000000000f000UL #define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_WIDTH 4 #define LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_SHIFT 12 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD; #define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_MASK 0x0000000000000f00UL #define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_WIDTH 4 #define LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_SHIFT 8 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD; #define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_MASK 0x00000000000000f0UL #define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_WIDTH 4 #define LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_SHIFT 4 extern const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD; #define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_MASK 0x000000000000000fUL #define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_WIDTH 4 #define LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD; #define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_MASK 0x00000000fff00000UL #define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_WIDTH 12 #define LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD; #define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_MASK 0x00000000000f0000UL #define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_SHIFT 16 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD; #define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_MASK 0x000000000000f000UL #define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_SHIFT 12 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD; #define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_MASK 0x0000000000000f00UL #define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_SHIFT 8 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD; #define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_MASK 0x00000000000000f0UL #define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_SHIFT 4 extern const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD; #define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_MASK 0x000000000000000fUL #define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_WIDTH 4 #define LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD; #define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_MASK 0x00000000fffffe00UL #define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_WIDTH 23 #define LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD; #define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_MASK 0x0000000000000100UL #define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_WIDTH 1 #define LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_SHIFT 8 extern const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD; #define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_MASK 0x00000000000000ffUL #define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_WIDTH 8 #define LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_SHIFT 0 extern const ru_field_rec LPORT_MAB_STATUS_RESERVED0_FIELD; #define LPORT_MAB_STATUS_RESERVED0_FIELD_MASK 0x00000000ffff0000UL #define LPORT_MAB_STATUS_RESERVED0_FIELD_WIDTH 16 #define LPORT_MAB_STATUS_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD; #define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_MASK 0x0000000000008000UL #define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_WIDTH 1 #define LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_SHIFT 15 extern const ru_field_rec LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD; #define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_MASK 0x0000000000007800UL #define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_WIDTH 4 #define LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_SHIFT 11 extern const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD; #define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_MASK 0x0000000000000400UL #define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_WIDTH 1 #define LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_SHIFT 10 extern const ru_field_rec LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD; #define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_MASK 0x0000000000000200UL #define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_WIDTH 1 #define LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_SHIFT 9 extern const ru_field_rec LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD; #define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_MASK 0x00000000000001e0UL #define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_WIDTH 4 #define LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_SHIFT 5 extern const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD; #define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_MASK 0x0000000000000010UL #define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_WIDTH 1 #define LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_SHIFT 4 extern const ru_field_rec LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD; #define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_MASK 0x000000000000000fUL #define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_WIDTH 4 #define LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_SHIFT 0 /****************************************************************************** * BCM6858_A0 Registers ******************************************************************************/ extern const ru_reg_rec LPORT_XLMAC_CTRL_REG; #define LPORT_XLMAC_CTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_XLMAC_MODE_REG; #define LPORT_XLMAC_MODE_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_XLMAC_SPARE0_REG; #define LPORT_XLMAC_SPARE0_REG_OFFSET 0x00000010 extern const ru_reg_rec LPORT_XLMAC_SPARE1_REG; #define LPORT_XLMAC_SPARE1_REG_OFFSET 0x00000018 extern const ru_reg_rec LPORT_XLMAC_TX_CTRL_REG; #define LPORT_XLMAC_TX_CTRL_REG_OFFSET 0x00000020 extern const ru_reg_rec LPORT_XLMAC_TX_CTRL_OVERLAY_REG; #define LPORT_XLMAC_TX_CTRL_OVERLAY_REG_OFFSET 0x00000020 extern const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_REG; #define LPORT_XLMAC_TX_MAC_SA_REG_OFFSET 0x00000028 extern const ru_reg_rec LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG; #define LPORT_XLMAC_TX_MAC_SA_OVERLAY_REG_OFFSET 0x00000028 extern const ru_reg_rec LPORT_XLMAC_RX_CTRL_REG; #define LPORT_XLMAC_RX_CTRL_REG_OFFSET 0x00000030 extern const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_REG; #define LPORT_XLMAC_RX_MAC_SA_REG_OFFSET 0x00000038 extern const ru_reg_rec LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG; #define LPORT_XLMAC_RX_MAC_SA_OVERLAY_REG_OFFSET 0x00000038 extern const ru_reg_rec LPORT_XLMAC_RX_MAX_SIZE_REG; #define LPORT_XLMAC_RX_MAX_SIZE_REG_OFFSET 0x00000040 extern const ru_reg_rec LPORT_XLMAC_RX_VLAN_TAG_REG; #define LPORT_XLMAC_RX_VLAN_TAG_REG_OFFSET 0x00000048 extern const ru_reg_rec LPORT_XLMAC_RX_LSS_CTRL_REG; #define LPORT_XLMAC_RX_LSS_CTRL_REG_OFFSET 0x00000050 extern const ru_reg_rec LPORT_XLMAC_RX_LSS_STATUS_REG; #define LPORT_XLMAC_RX_LSS_STATUS_REG_OFFSET 0x00000058 extern const ru_reg_rec LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG; #define LPORT_XLMAC_CLEAR_RX_LSS_STATUS_REG_OFFSET 0x00000060 extern const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_REG; #define LPORT_XLMAC_PAUSE_CTRL_REG_OFFSET 0x00000068 extern const ru_reg_rec LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG; #define LPORT_XLMAC_PAUSE_CTRL_OVERLAY_REG_OFFSET 0x00000068 extern const ru_reg_rec LPORT_XLMAC_PFC_CTRL_REG; #define LPORT_XLMAC_PFC_CTRL_REG_OFFSET 0x00000070 extern const ru_reg_rec LPORT_XLMAC_PFC_CTRL_OVERLAY_REG; #define LPORT_XLMAC_PFC_CTRL_OVERLAY_REG_OFFSET 0x00000070 extern const ru_reg_rec LPORT_XLMAC_PFC_TYPE_REG; #define LPORT_XLMAC_PFC_TYPE_REG_OFFSET 0x00000078 extern const ru_reg_rec LPORT_XLMAC_PFC_OPCODE_REG; #define LPORT_XLMAC_PFC_OPCODE_REG_OFFSET 0x00000080 extern const ru_reg_rec LPORT_XLMAC_PFC_DA_REG; #define LPORT_XLMAC_PFC_DA_REG_OFFSET 0x00000088 extern const ru_reg_rec LPORT_XLMAC_PFC_DA_OVERLAY_REG; #define LPORT_XLMAC_PFC_DA_OVERLAY_REG_OFFSET 0x00000088 extern const ru_reg_rec LPORT_XLMAC_LLFC_CTRL_REG; #define LPORT_XLMAC_LLFC_CTRL_REG_OFFSET 0x00000090 extern const ru_reg_rec LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG; #define LPORT_XLMAC_TX_LLFC_MSG_FIELDS_REG_OFFSET 0x00000098 extern const ru_reg_rec LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG; #define LPORT_XLMAC_RX_LLFC_MSG_FIELDS_REG_OFFSET 0x000000a0 extern const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_DATA_REG_OFFSET 0x000000a8 extern const ru_reg_rec LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG; #define LPORT_XLMAC_TX_TIMESTAMP_FIFO_STATUS_REG_OFFSET 0x000000b0 extern const ru_reg_rec LPORT_XLMAC_FIFO_STATUS_REG; #define LPORT_XLMAC_FIFO_STATUS_REG_OFFSET 0x000000b8 extern const ru_reg_rec LPORT_XLMAC_CLEAR_FIFO_STATUS_REG; #define LPORT_XLMAC_CLEAR_FIFO_STATUS_REG_OFFSET 0x000000c0 extern const ru_reg_rec LPORT_XLMAC_LAG_FAILOVER_STATUS_REG; #define LPORT_XLMAC_LAG_FAILOVER_STATUS_REG_OFFSET 0x000000c8 extern const ru_reg_rec LPORT_XLMAC_EEE_CTRL_REG; #define LPORT_XLMAC_EEE_CTRL_REG_OFFSET 0x000000d0 extern const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_REG; #define LPORT_XLMAC_EEE_TIMERS_REG_OFFSET 0x000000d8 extern const ru_reg_rec LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG; #define LPORT_XLMAC_EEE_TIMERS_OVERLAY_REG_OFFSET 0x000000d8 extern const ru_reg_rec LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG; #define LPORT_XLMAC_EEE_1_SEC_LINK_STATUS_TIMER_REG_OFFSET 0x000000e0 extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_REG; #define LPORT_XLMAC_HIGIG_HDR_0_REG_OFFSET 0x000000e8 extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG; #define LPORT_XLMAC_HIGIG_HDR_0_OVERLAY_REG_OFFSET 0x000000e8 extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_REG; #define LPORT_XLMAC_HIGIG_HDR_1_REG_OFFSET 0x000000f0 extern const ru_reg_rec LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG; #define LPORT_XLMAC_HIGIG_HDR_1_OVERLAY_REG_OFFSET 0x000000f0 extern const ru_reg_rec LPORT_XLMAC_GMII_EEE_CTRL_REG; #define LPORT_XLMAC_GMII_EEE_CTRL_REG_OFFSET 0x000000f8 extern const ru_reg_rec LPORT_XLMAC_TIMESTAMP_ADJUST_REG; #define LPORT_XLMAC_TIMESTAMP_ADJUST_REG_OFFSET 0x00000100 extern const ru_reg_rec LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG; #define LPORT_XLMAC_TIMESTAMP_BYTE_ADJUST_REG_OFFSET 0x00000108 extern const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_REG_OFFSET 0x00000110 extern const ru_reg_rec LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG; #define LPORT_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY_REG_OFFSET 0x00000110 extern const ru_reg_rec LPORT_XLMAC_E2E_CTRL_REG; #define LPORT_XLMAC_E2E_CTRL_REG_OFFSET 0x00000118 extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG; #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_REG_OFFSET 0x00000120 extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG; #define LPORT_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY_REG_OFFSET 0x00000120 extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG; #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_REG_OFFSET 0x00000128 extern const ru_reg_rec LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG; #define LPORT_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY_REG_OFFSET 0x00000128 extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_REG; #define LPORT_XLMAC_E2ECC_DATA_HDR_0_REG_OFFSET 0x00000130 extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG; #define LPORT_XLMAC_E2ECC_DATA_HDR_0_OVERLAY_REG_OFFSET 0x00000130 extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_REG; #define LPORT_XLMAC_E2ECC_DATA_HDR_1_REG_OFFSET 0x00000138 extern const ru_reg_rec LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG; #define LPORT_XLMAC_E2ECC_DATA_HDR_1_OVERLAY_REG_OFFSET 0x00000138 extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG; #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_REG_OFFSET 0x00000140 extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG; #define LPORT_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY_REG_OFFSET 0x00000140 extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG; #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_REG_OFFSET 0x00000148 extern const ru_reg_rec LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG; #define LPORT_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY_REG_OFFSET 0x00000148 extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_REG; #define LPORT_XLMAC_E2EFC_DATA_HDR_0_REG_OFFSET 0x00000150 extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG; #define LPORT_XLMAC_E2EFC_DATA_HDR_0_OVERLAY_REG_OFFSET 0x00000150 extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_REG; #define LPORT_XLMAC_E2EFC_DATA_HDR_1_REG_OFFSET 0x00000158 extern const ru_reg_rec LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG; #define LPORT_XLMAC_E2EFC_DATA_HDR_1_OVERLAY_REG_OFFSET 0x00000158 extern const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_CNT_REG; #define LPORT_XLMAC_TXFIFO_CELL_CNT_REG_OFFSET 0x00000160 extern const ru_reg_rec LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG; #define LPORT_XLMAC_TXFIFO_CELL_REQ_CNT_REG_OFFSET 0x00000168 extern const ru_reg_rec LPORT_XLMAC_MEM_CTRL_REG; #define LPORT_XLMAC_MEM_CTRL_REG_OFFSET 0x00000170 extern const ru_reg_rec LPORT_XLMAC_ECC_CTRL_REG; #define LPORT_XLMAC_ECC_CTRL_REG_OFFSET 0x00000178 extern const ru_reg_rec LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG; #define LPORT_XLMAC_ECC_FORCE_DOUBLE_BIT_ERR_REG_OFFSET 0x00000180 extern const ru_reg_rec LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG; #define LPORT_XLMAC_ECC_FORCE_SINGLE_BIT_ERR_REG_OFFSET 0x00000188 extern const ru_reg_rec LPORT_XLMAC_RX_CDC_ECC_STATUS_REG; #define LPORT_XLMAC_RX_CDC_ECC_STATUS_REG_OFFSET 0x00000190 extern const ru_reg_rec LPORT_XLMAC_TX_CDC_ECC_STATUS_REG; #define LPORT_XLMAC_TX_CDC_ECC_STATUS_REG_OFFSET 0x00000198 extern const ru_reg_rec LPORT_XLMAC_CLEAR_ECC_STATUS_REG; #define LPORT_XLMAC_CLEAR_ECC_STATUS_REG_OFFSET 0x000001a0 extern const ru_reg_rec LPORT_XLMAC_INTR_STATUS_REG; #define LPORT_XLMAC_INTR_STATUS_REG_OFFSET 0x000001a8 extern const ru_reg_rec LPORT_XLMAC_INTR_ENABLE_REG; #define LPORT_XLMAC_INTR_ENABLE_REG_OFFSET 0x000001b0 extern const ru_reg_rec LPORT_XLMAC_VERSION_ID_REG; #define LPORT_XLMAC_VERSION_ID_REG_OFFSET 0x000001b8 extern const ru_reg_rec LPORT_MIB_GRX64_REG; #define LPORT_MIB_GRX64_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_MIB_GRX127_REG; #define LPORT_MIB_GRX127_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_MIB_GRX255_REG; #define LPORT_MIB_GRX255_REG_OFFSET 0x00000010 extern const ru_reg_rec LPORT_MIB_GRX511_REG; #define LPORT_MIB_GRX511_REG_OFFSET 0x00000018 extern const ru_reg_rec LPORT_MIB_GRX1023_REG; #define LPORT_MIB_GRX1023_REG_OFFSET 0x00000020 extern const ru_reg_rec LPORT_MIB_GRX1518_REG; #define LPORT_MIB_GRX1518_REG_OFFSET 0x00000028 extern const ru_reg_rec LPORT_MIB_GRX1522_REG; #define LPORT_MIB_GRX1522_REG_OFFSET 0x00000030 extern const ru_reg_rec LPORT_MIB_GRX2047_REG; #define LPORT_MIB_GRX2047_REG_OFFSET 0x00000038 extern const ru_reg_rec LPORT_MIB_GRX4095_REG; #define LPORT_MIB_GRX4095_REG_OFFSET 0x00000040 extern const ru_reg_rec LPORT_MIB_GRX9216_REG; #define LPORT_MIB_GRX9216_REG_OFFSET 0x00000048 extern const ru_reg_rec LPORT_MIB_GRX16383_REG; #define LPORT_MIB_GRX16383_REG_OFFSET 0x00000050 extern const ru_reg_rec LPORT_MIB_GRXPKT_REG; #define LPORT_MIB_GRXPKT_REG_OFFSET 0x00000058 extern const ru_reg_rec LPORT_MIB_GRXUCA_REG; #define LPORT_MIB_GRXUCA_REG_OFFSET 0x00000060 extern const ru_reg_rec LPORT_MIB_GRXMCA_REG; #define LPORT_MIB_GRXMCA_REG_OFFSET 0x00000068 extern const ru_reg_rec LPORT_MIB_GRXBCA_REG; #define LPORT_MIB_GRXBCA_REG_OFFSET 0x00000070 extern const ru_reg_rec LPORT_MIB_GRXFCS_REG; #define LPORT_MIB_GRXFCS_REG_OFFSET 0x00000078 extern const ru_reg_rec LPORT_MIB_GRXCF_REG; #define LPORT_MIB_GRXCF_REG_OFFSET 0x00000080 extern const ru_reg_rec LPORT_MIB_GRXPF_REG; #define LPORT_MIB_GRXPF_REG_OFFSET 0x00000088 extern const ru_reg_rec LPORT_MIB_GRXPP_REG; #define LPORT_MIB_GRXPP_REG_OFFSET 0x00000090 extern const ru_reg_rec LPORT_MIB_GRXUO_REG; #define LPORT_MIB_GRXUO_REG_OFFSET 0x00000098 extern const ru_reg_rec LPORT_MIB_GRXUDA_REG; #define LPORT_MIB_GRXUDA_REG_OFFSET 0x000000a0 extern const ru_reg_rec LPORT_MIB_GRXWSA_REG; #define LPORT_MIB_GRXWSA_REG_OFFSET 0x000000a8 extern const ru_reg_rec LPORT_MIB_GRXALN_REG; #define LPORT_MIB_GRXALN_REG_OFFSET 0x000000b0 extern const ru_reg_rec LPORT_MIB_GRXFLR_REG; #define LPORT_MIB_GRXFLR_REG_OFFSET 0x000000b8 extern const ru_reg_rec LPORT_MIB_GRXFRERR_REG; #define LPORT_MIB_GRXFRERR_REG_OFFSET 0x000000c0 extern const ru_reg_rec LPORT_MIB_GRXFCR_REG; #define LPORT_MIB_GRXFCR_REG_OFFSET 0x000000c8 extern const ru_reg_rec LPORT_MIB_GRXOVR_REG; #define LPORT_MIB_GRXOVR_REG_OFFSET 0x000000d0 extern const ru_reg_rec LPORT_MIB_GRXJBR_REG; #define LPORT_MIB_GRXJBR_REG_OFFSET 0x000000d8 extern const ru_reg_rec LPORT_MIB_GRXMTUE_REG; #define LPORT_MIB_GRXMTUE_REG_OFFSET 0x000000e0 extern const ru_reg_rec LPORT_MIB_GRXMCRC_REG; #define LPORT_MIB_GRXMCRC_REG_OFFSET 0x000000e8 extern const ru_reg_rec LPORT_MIB_GRXPRM_REG; #define LPORT_MIB_GRXPRM_REG_OFFSET 0x000000f0 extern const ru_reg_rec LPORT_MIB_GRXVLN_REG; #define LPORT_MIB_GRXVLN_REG_OFFSET 0x000000f8 extern const ru_reg_rec LPORT_MIB_GRXDVLN_REG; #define LPORT_MIB_GRXDVLN_REG_OFFSET 0x00000100 extern const ru_reg_rec LPORT_MIB_GRXTRFU_REG; #define LPORT_MIB_GRXTRFU_REG_OFFSET 0x00000108 extern const ru_reg_rec LPORT_MIB_GRXPOK_REG; #define LPORT_MIB_GRXPOK_REG_OFFSET 0x00000110 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF0_REG; #define LPORT_MIB_GRXPFCOFF0_REG_OFFSET 0x00000118 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF1_REG; #define LPORT_MIB_GRXPFCOFF1_REG_OFFSET 0x00000120 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF2_REG; #define LPORT_MIB_GRXPFCOFF2_REG_OFFSET 0x00000128 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF3_REG; #define LPORT_MIB_GRXPFCOFF3_REG_OFFSET 0x00000130 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF4_REG; #define LPORT_MIB_GRXPFCOFF4_REG_OFFSET 0x00000138 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF5_REG; #define LPORT_MIB_GRXPFCOFF5_REG_OFFSET 0x00000140 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF6_REG; #define LPORT_MIB_GRXPFCOFF6_REG_OFFSET 0x00000148 extern const ru_reg_rec LPORT_MIB_GRXPFCOFF7_REG; #define LPORT_MIB_GRXPFCOFF7_REG_OFFSET 0x00000150 extern const ru_reg_rec LPORT_MIB_GRXPFCP0_REG; #define LPORT_MIB_GRXPFCP0_REG_OFFSET 0x00000158 extern const ru_reg_rec LPORT_MIB_GRXPFCP1_REG; #define LPORT_MIB_GRXPFCP1_REG_OFFSET 0x00000160 extern const ru_reg_rec LPORT_MIB_GRXPFCP2_REG; #define LPORT_MIB_GRXPFCP2_REG_OFFSET 0x00000168 extern const ru_reg_rec LPORT_MIB_GRXPFCP3_REG; #define LPORT_MIB_GRXPFCP3_REG_OFFSET 0x00000170 extern const ru_reg_rec LPORT_MIB_GRXPFCP4_REG; #define LPORT_MIB_GRXPFCP4_REG_OFFSET 0x00000178 extern const ru_reg_rec LPORT_MIB_GRXPFCP5_REG; #define LPORT_MIB_GRXPFCP5_REG_OFFSET 0x00000180 extern const ru_reg_rec LPORT_MIB_GRXPFCP6_REG; #define LPORT_MIB_GRXPFCP6_REG_OFFSET 0x00000188 extern const ru_reg_rec LPORT_MIB_GRXPFCP7_REG; #define LPORT_MIB_GRXPFCP7_REG_OFFSET 0x00000190 extern const ru_reg_rec LPORT_MIB_GRXSCHCRC_REG; #define LPORT_MIB_GRXSCHCRC_REG_OFFSET 0x00000198 extern const ru_reg_rec LPORT_MIB_GRXBYT_REG; #define LPORT_MIB_GRXBYT_REG_OFFSET 0x000001a0 extern const ru_reg_rec LPORT_MIB_GRXRPKT_REG; #define LPORT_MIB_GRXRPKT_REG_OFFSET 0x000001a8 extern const ru_reg_rec LPORT_MIB_GRXUND_REG; #define LPORT_MIB_GRXUND_REG_OFFSET 0x000001b0 extern const ru_reg_rec LPORT_MIB_GRXFRG_REG; #define LPORT_MIB_GRXFRG_REG_OFFSET 0x000001b8 extern const ru_reg_rec LPORT_MIB_GRXRBYT_REG; #define LPORT_MIB_GRXRBYT_REG_OFFSET 0x000001c0 extern const ru_reg_rec LPORT_MIB_GTX64_REG; #define LPORT_MIB_GTX64_REG_OFFSET 0x000001c8 extern const ru_reg_rec LPORT_MIB_GTX127_REG; #define LPORT_MIB_GTX127_REG_OFFSET 0x000001d0 extern const ru_reg_rec LPORT_MIB_GTX255_REG; #define LPORT_MIB_GTX255_REG_OFFSET 0x000001d8 extern const ru_reg_rec LPORT_MIB_GTX511_REG; #define LPORT_MIB_GTX511_REG_OFFSET 0x000001e0 extern const ru_reg_rec LPORT_MIB_GTX1023_REG; #define LPORT_MIB_GTX1023_REG_OFFSET 0x000001e8 extern const ru_reg_rec LPORT_MIB_GTX1518_REG; #define LPORT_MIB_GTX1518_REG_OFFSET 0x000001f0 extern const ru_reg_rec LPORT_MIB_GTX1522_REG; #define LPORT_MIB_GTX1522_REG_OFFSET 0x000001f8 extern const ru_reg_rec LPORT_MIB_GTX2047_REG; #define LPORT_MIB_GTX2047_REG_OFFSET 0x00000200 extern const ru_reg_rec LPORT_MIB_GTX4095_REG; #define LPORT_MIB_GTX4095_REG_OFFSET 0x00000208 extern const ru_reg_rec LPORT_MIB_GTX9216_REG; #define LPORT_MIB_GTX9216_REG_OFFSET 0x00000210 extern const ru_reg_rec LPORT_MIB_GTX16383_REG; #define LPORT_MIB_GTX16383_REG_OFFSET 0x00000218 extern const ru_reg_rec LPORT_MIB_GTXPOK_REG; #define LPORT_MIB_GTXPOK_REG_OFFSET 0x00000220 extern const ru_reg_rec LPORT_MIB_GTXPKT_REG; #define LPORT_MIB_GTXPKT_REG_OFFSET 0x00000228 extern const ru_reg_rec LPORT_MIB_GTXUCA_REG; #define LPORT_MIB_GTXUCA_REG_OFFSET 0x00000230 extern const ru_reg_rec LPORT_MIB_GTXMCA_REG; #define LPORT_MIB_GTXMCA_REG_OFFSET 0x00000238 extern const ru_reg_rec LPORT_MIB_GTXBCA_REG; #define LPORT_MIB_GTXBCA_REG_OFFSET 0x00000240 extern const ru_reg_rec LPORT_MIB_GTXPF_REG; #define LPORT_MIB_GTXPF_REG_OFFSET 0x00000248 extern const ru_reg_rec LPORT_MIB_GTXPFC_REG; #define LPORT_MIB_GTXPFC_REG_OFFSET 0x00000250 extern const ru_reg_rec LPORT_MIB_GTXJBR_REG; #define LPORT_MIB_GTXJBR_REG_OFFSET 0x00000258 extern const ru_reg_rec LPORT_MIB_GTXFCS_REG; #define LPORT_MIB_GTXFCS_REG_OFFSET 0x00000260 extern const ru_reg_rec LPORT_MIB_GTXCF_REG; #define LPORT_MIB_GTXCF_REG_OFFSET 0x00000268 extern const ru_reg_rec LPORT_MIB_GTXOVR_REG; #define LPORT_MIB_GTXOVR_REG_OFFSET 0x00000270 extern const ru_reg_rec LPORT_MIB_GTXDFR_REG; #define LPORT_MIB_GTXDFR_REG_OFFSET 0x00000278 extern const ru_reg_rec LPORT_MIB_GTXEDF_REG; #define LPORT_MIB_GTXEDF_REG_OFFSET 0x00000280 extern const ru_reg_rec LPORT_MIB_GTXSCL_REG; #define LPORT_MIB_GTXSCL_REG_OFFSET 0x00000288 extern const ru_reg_rec LPORT_MIB_GTXMCL_REG; #define LPORT_MIB_GTXMCL_REG_OFFSET 0x00000290 extern const ru_reg_rec LPORT_MIB_GTXLCL_REG; #define LPORT_MIB_GTXLCL_REG_OFFSET 0x00000298 extern const ru_reg_rec LPORT_MIB_GTXXCL_REG; #define LPORT_MIB_GTXXCL_REG_OFFSET 0x000002a0 extern const ru_reg_rec LPORT_MIB_GTXFRG_REG; #define LPORT_MIB_GTXFRG_REG_OFFSET 0x000002a8 extern const ru_reg_rec LPORT_MIB_GTXERR_REG; #define LPORT_MIB_GTXERR_REG_OFFSET 0x000002b0 extern const ru_reg_rec LPORT_MIB_GTXVLN_REG; #define LPORT_MIB_GTXVLN_REG_OFFSET 0x000002b8 extern const ru_reg_rec LPORT_MIB_GTXDVLN_REG; #define LPORT_MIB_GTXDVLN_REG_OFFSET 0x000002c0 extern const ru_reg_rec LPORT_MIB_GTXRPKT_REG; #define LPORT_MIB_GTXRPKT_REG_OFFSET 0x000002c8 extern const ru_reg_rec LPORT_MIB_GTXUFL_REG; #define LPORT_MIB_GTXUFL_REG_OFFSET 0x000002d0 extern const ru_reg_rec LPORT_MIB_GTXPFCP0_REG; #define LPORT_MIB_GTXPFCP0_REG_OFFSET 0x000002d8 extern const ru_reg_rec LPORT_MIB_GTXPFCP1_REG; #define LPORT_MIB_GTXPFCP1_REG_OFFSET 0x000002e0 extern const ru_reg_rec LPORT_MIB_GTXPFCP2_REG; #define LPORT_MIB_GTXPFCP2_REG_OFFSET 0x000002e8 extern const ru_reg_rec LPORT_MIB_GTXPFCP3_REG; #define LPORT_MIB_GTXPFCP3_REG_OFFSET 0x000002f0 extern const ru_reg_rec LPORT_MIB_GTXPFCP4_REG; #define LPORT_MIB_GTXPFCP4_REG_OFFSET 0x000002f8 extern const ru_reg_rec LPORT_MIB_GTXPFCP5_REG; #define LPORT_MIB_GTXPFCP5_REG_OFFSET 0x00000300 extern const ru_reg_rec LPORT_MIB_GTXPFCP6_REG; #define LPORT_MIB_GTXPFCP6_REG_OFFSET 0x00000308 extern const ru_reg_rec LPORT_MIB_GTXPFCP7_REG; #define LPORT_MIB_GTXPFCP7_REG_OFFSET 0x00000310 extern const ru_reg_rec LPORT_MIB_GTXNCL_REG; #define LPORT_MIB_GTXNCL_REG_OFFSET 0x00000318 extern const ru_reg_rec LPORT_MIB_GTXBYT_REG; #define LPORT_MIB_GTXBYT_REG_OFFSET 0x00000320 extern const ru_reg_rec LPORT_MIB_GRXLPI_REG; #define LPORT_MIB_GRXLPI_REG_OFFSET 0x00000328 extern const ru_reg_rec LPORT_MIB_GRXDLPI_REG; #define LPORT_MIB_GRXDLPI_REG_OFFSET 0x00000330 extern const ru_reg_rec LPORT_MIB_GTXLPI_REG; #define LPORT_MIB_GTXLPI_REG_OFFSET 0x00000338 extern const ru_reg_rec LPORT_MIB_GTXDLPI_REG; #define LPORT_MIB_GTXDLPI_REG_OFFSET 0x00000340 extern const ru_reg_rec LPORT_MIB_GRXPTLLFC_REG; #define LPORT_MIB_GRXPTLLFC_REG_OFFSET 0x00000348 extern const ru_reg_rec LPORT_MIB_GRXLTLLFC_REG; #define LPORT_MIB_GRXLTLLFC_REG_OFFSET 0x00000350 extern const ru_reg_rec LPORT_MIB_GRXLLFCFCS_REG; #define LPORT_MIB_GRXLLFCFCS_REG_OFFSET 0x00000358 extern const ru_reg_rec LPORT_MIB_GTXLTLLFC_REG; #define LPORT_MIB_GTXLTLLFC_REG_OFFSET 0x00000360 extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_REVISION_REG; #define LPORT_SRDS_DUAL_SERDES_REVISION_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_0_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_0_REG_OFFSET 0x0000000c extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_CNTRL_1_REG_OFFSET 0x00000010 extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014 extern const ru_reg_rec LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG; #define LPORT_SRDS_SERDES_0_INDIR_ACC_MASK_1_REG_OFFSET 0x00000018 extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_0_REG_OFFSET 0x0000001c extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000020 extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_0_REG_OFFSET 0x00000024 extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_CNTRL_1_REG_OFFSET 0x00000028 extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_ADDR_1_REG_OFFSET 0x0000002c extern const ru_reg_rec LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG; #define LPORT_SRDS_SERDES_1_INDIR_ACC_MASK_1_REG_OFFSET 0x00000030 extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG; #define LPORT_SRDS_DUAL_SERDES_0_CNTRL_REG_OFFSET 0x00000040 extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_0_STATUS_REG; #define LPORT_SRDS_DUAL_SERDES_0_STATUS_REG_OFFSET 0x00000044 extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG; #define LPORT_SRDS_DUAL_SERDES_1_CNTRL_REG_OFFSET 0x00000048 extern const ru_reg_rec LPORT_SRDS_DUAL_SERDES_1_STATUS_REG; #define LPORT_SRDS_DUAL_SERDES_1_STATUS_REG_OFFSET 0x0000004c extern const ru_reg_rec LPORT_LED_CNTRL_REG; #define LPORT_LED_CNTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG; #define LPORT_LED_LINK_AND_SPEED_ENCODING_SEL_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_LED_LINK_AND_SPEED_ENCODING_REG; #define LPORT_LED_LINK_AND_SPEED_ENCODING_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_LED_AGGREGATE_LED_CNTRL_REG; #define LPORT_LED_AGGREGATE_LED_CNTRL_REG_OFFSET 0x00000018 extern const ru_reg_rec LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG; #define LPORT_LED_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x0000001c extern const ru_reg_rec LPORT_CTRL_LPORT_CNTRL_REG; #define LPORT_CTRL_LPORT_CNTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_CTRL_LPORT_REVISION_REG; #define LPORT_CTRL_LPORT_REVISION_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_CTRL_QEGPHY_REVISION_REG; #define LPORT_CTRL_QEGPHY_REVISION_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_CTRL_QEGPHY_TEST_CNTRL_REG; #define LPORT_CTRL_QEGPHY_TEST_CNTRL_REG_OFFSET 0x00000040 extern const ru_reg_rec LPORT_CTRL_QEGPHY_CNTRL_REG; #define LPORT_CTRL_QEGPHY_CNTRL_REG_OFFSET 0x00000044 extern const ru_reg_rec LPORT_CTRL_QEGPHY_STATUS_REG; #define LPORT_CTRL_QEGPHY_STATUS_REG_OFFSET 0x00000048 extern const ru_reg_rec LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG; #define LPORT_CTRL_LED_BLINK_RATE_CNTRL_REG_OFFSET 0x000000d4 extern const ru_reg_rec LPORT_CTRL_LED_SERIAL_CNTRL_REG; #define LPORT_CTRL_LED_SERIAL_CNTRL_REG_OFFSET 0x000000d8 extern const ru_reg_rec LPORT_RGMII_CNTRL_REG; #define LPORT_RGMII_CNTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_RGMII_IB_STATUS_REG; #define LPORT_RGMII_IB_STATUS_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG; #define LPORT_RGMII_RX_CLOCK_DELAY_CNTRL_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG; #define LPORT_RGMII_ATE_RX_CNTRL_EXP_DATA_REG_OFFSET 0x0000004c extern const ru_reg_rec LPORT_RGMII_ATE_RX_EXP_DATA_1_REG; #define LPORT_RGMII_ATE_RX_EXP_DATA_1_REG_OFFSET 0x00000050 extern const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_0_REG; #define LPORT_RGMII_ATE_RX_STATUS_0_REG_OFFSET 0x00000054 extern const ru_reg_rec LPORT_RGMII_ATE_RX_STATUS_1_REG; #define LPORT_RGMII_ATE_RX_STATUS_1_REG_OFFSET 0x00000058 extern const ru_reg_rec LPORT_RGMII_ATE_TX_CNTRL_REG; #define LPORT_RGMII_ATE_TX_CNTRL_REG_OFFSET 0x0000005c extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_0_REG; #define LPORT_RGMII_ATE_TX_DATA_0_REG_OFFSET 0x00000060 extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_1_REG; #define LPORT_RGMII_ATE_TX_DATA_1_REG_OFFSET 0x00000064 extern const ru_reg_rec LPORT_RGMII_ATE_TX_DATA_2_REG; #define LPORT_RGMII_ATE_TX_DATA_2_REG_OFFSET 0x00000068 extern const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_0_REG; #define LPORT_RGMII_TX_DELAY_CNTRL_0_REG_OFFSET 0x00000094 extern const ru_reg_rec LPORT_RGMII_TX_DELAY_CNTRL_1_REG; #define LPORT_RGMII_TX_DELAY_CNTRL_1_REG_OFFSET 0x00000098 extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_0_REG; #define LPORT_RGMII_RX_DELAY_CNTRL_0_REG_OFFSET 0x0000009c extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_1_REG; #define LPORT_RGMII_RX_DELAY_CNTRL_1_REG_OFFSET 0x000000a0 extern const ru_reg_rec LPORT_RGMII_RX_DELAY_CNTRL_2_REG; #define LPORT_RGMII_RX_DELAY_CNTRL_2_REG_OFFSET 0x000000a4 extern const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_WRITE_REG; #define XLMAC_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000 extern const ru_reg_rec XLMAC_CONF_DIR_ACC_DATA_READ_REG; #define XLMAC_CONF_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004 extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_0_REG; #define XLMAC_CONF_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008 extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG; #define XLMAC_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG; #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010 extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_ADDR_1_REG; #define XLMAC_CONF_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014 extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG; #define XLMAC_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018 extern const ru_reg_rec XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG; #define XLMAC_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c extern const ru_reg_rec XLMAC_CONF_CONFIG_REG; #define XLMAC_CONF_CONFIG_REG_OFFSET 0x00000020 extern const ru_reg_rec XLMAC_CONF_INTERRUPT_CHECK_REG; #define XLMAC_CONF_INTERRUPT_CHECK_REG_OFFSET 0x00000024 extern const ru_reg_rec XLMAC_CONF_PORT_0_RXERR_MASK_REG; #define XLMAC_CONF_PORT_0_RXERR_MASK_REG_OFFSET 0x00000028 extern const ru_reg_rec XLMAC_CONF_PORT_1_RXERR_MASK_REG; #define XLMAC_CONF_PORT_1_RXERR_MASK_REG_OFFSET 0x0000002c extern const ru_reg_rec XLMAC_CONF_PORT_2_RXERR_MASK_REG; #define XLMAC_CONF_PORT_2_RXERR_MASK_REG_OFFSET 0x00000030 extern const ru_reg_rec XLMAC_CONF_PORT_3_RXERR_MASK_REG; #define XLMAC_CONF_PORT_3_RXERR_MASK_REG_OFFSET 0x00000034 extern const ru_reg_rec MIB_CONF_DIR_ACC_DATA_WRITE_REG; #define MIB_CONF_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000 extern const ru_reg_rec MIB_CONF_DIR_ACC_DATA_READ_REG; #define MIB_CONF_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004 extern const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_0_REG; #define MIB_CONF_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008 extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_0_REG; #define MIB_CONF_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG; #define MIB_CONF_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010 extern const ru_reg_rec MIB_CONF_INDIR_ACC_ADDR_1_REG; #define MIB_CONF_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014 extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_LOW_1_REG; #define MIB_CONF_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018 extern const ru_reg_rec MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG; #define MIB_CONF_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c extern const ru_reg_rec MIB_CONF_CNTRL_REG; #define MIB_CONF_CNTRL_REG_OFFSET 0x00000020 extern const ru_reg_rec MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG; #define MIB_CONF_EEE_PULSE_DURATION_CNTRL_REG_OFFSET 0x00000024 extern const ru_reg_rec MIB_CONF_GPORT0_MAX_PKT_SIZE_REG; #define MIB_CONF_GPORT0_MAX_PKT_SIZE_REG_OFFSET 0x00000028 extern const ru_reg_rec MIB_CONF_GPORT1_MAX_PKT_SIZE_REG; #define MIB_CONF_GPORT1_MAX_PKT_SIZE_REG_OFFSET 0x0000002c extern const ru_reg_rec MIB_CONF_GPORT2_MAX_PKT_SIZE_REG; #define MIB_CONF_GPORT2_MAX_PKT_SIZE_REG_OFFSET 0x00000030 extern const ru_reg_rec MIB_CONF_GPORT3_MAX_PKT_SIZE_REG; #define MIB_CONF_GPORT3_MAX_PKT_SIZE_REG_OFFSET 0x00000034 extern const ru_reg_rec MIB_CONF_ECC_CNTRL_REG; #define MIB_CONF_ECC_CNTRL_REG_OFFSET 0x00000038 extern const ru_reg_rec MIB_CONF_FORCE_SB_ECC_ERR_REG; #define MIB_CONF_FORCE_SB_ECC_ERR_REG_OFFSET 0x0000003c extern const ru_reg_rec MIB_CONF_FORCE_DB_ECC_ERR_REG; #define MIB_CONF_FORCE_DB_ECC_ERR_REG_OFFSET 0x00000040 extern const ru_reg_rec MIB_CONF_RX_MEM0_ECC_STATUS_REG; #define MIB_CONF_RX_MEM0_ECC_STATUS_REG_OFFSET 0x00000044 extern const ru_reg_rec MIB_CONF_RX_MEM1_ECC_STATUS_REG; #define MIB_CONF_RX_MEM1_ECC_STATUS_REG_OFFSET 0x00000048 extern const ru_reg_rec MIB_CONF_RX_MEM2_ECC_STATUS_REG; #define MIB_CONF_RX_MEM2_ECC_STATUS_REG_OFFSET 0x0000004c extern const ru_reg_rec MIB_CONF_RX_MEM3_ECC_STATUS_REG; #define MIB_CONF_RX_MEM3_ECC_STATUS_REG_OFFSET 0x00000050 extern const ru_reg_rec MIB_CONF_RX_MEM4_ECC_STATUS_REG; #define MIB_CONF_RX_MEM4_ECC_STATUS_REG_OFFSET 0x00000054 extern const ru_reg_rec MIB_CONF_TX_MEM0_ECC_STATUS_REG; #define MIB_CONF_TX_MEM0_ECC_STATUS_REG_OFFSET 0x00000058 extern const ru_reg_rec MIB_CONF_TX_MEM1_ECC_STATUS_REG; #define MIB_CONF_TX_MEM1_ECC_STATUS_REG_OFFSET 0x0000005c extern const ru_reg_rec MIB_CONF_TX_MEM2_ECC_STATUS_REG; #define MIB_CONF_TX_MEM2_ECC_STATUS_REG_OFFSET 0x00000060 extern const ru_reg_rec MIB_CONF_TX_MEM3_ECC_STATUS_REG; #define MIB_CONF_TX_MEM3_ECC_STATUS_REG_OFFSET 0x00000064 extern const ru_reg_rec LPORT_MDIO_CMD_REG; #define LPORT_MDIO_CMD_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_MDIO_CFG_REG; #define LPORT_MDIO_CFG_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_INTR_0_CPU_STATUS_REG; #define LPORT_INTR_0_CPU_STATUS_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_INTR_0_CPU_SET_REG; #define LPORT_INTR_0_CPU_SET_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_INTR_0_CPU_CLEAR_REG; #define LPORT_INTR_0_CPU_CLEAR_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_STATUS_REG; #define LPORT_INTR_0_CPU_MASK_STATUS_REG_OFFSET 0x0000000c extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_SET_REG; #define LPORT_INTR_0_CPU_MASK_SET_REG_OFFSET 0x00000010 extern const ru_reg_rec LPORT_INTR_0_CPU_MASK_CLEAR_REG; #define LPORT_INTR_0_CPU_MASK_CLEAR_REG_OFFSET 0x00000014 extern const ru_reg_rec LPORT_INTR_0_PCI_STATUS_REG; #define LPORT_INTR_0_PCI_STATUS_REG_OFFSET 0x00000018 extern const ru_reg_rec LPORT_INTR_0_PCI_SET_REG; #define LPORT_INTR_0_PCI_SET_REG_OFFSET 0x0000001c extern const ru_reg_rec LPORT_INTR_0_PCI_CLEAR_REG; #define LPORT_INTR_0_PCI_CLEAR_REG_OFFSET 0x00000020 extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_STATUS_REG; #define LPORT_INTR_0_PCI_MASK_STATUS_REG_OFFSET 0x00000024 extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_SET_REG; #define LPORT_INTR_0_PCI_MASK_SET_REG_OFFSET 0x00000028 extern const ru_reg_rec LPORT_INTR_0_PCI_MASK_CLEAR_REG; #define LPORT_INTR_0_PCI_MASK_CLEAR_REG_OFFSET 0x0000002c extern const ru_reg_rec LPORT_INTR_1_CPU_STATUS_REG; #define LPORT_INTR_1_CPU_STATUS_REG_OFFSET 0x00000100 extern const ru_reg_rec LPORT_INTR_1_CPU_SET_REG; #define LPORT_INTR_1_CPU_SET_REG_OFFSET 0x00000104 extern const ru_reg_rec LPORT_INTR_1_CPU_CLEAR_REG; #define LPORT_INTR_1_CPU_CLEAR_REG_OFFSET 0x00000108 extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_STATUS_REG; #define LPORT_INTR_1_CPU_MASK_STATUS_REG_OFFSET 0x0000010c extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_SET_REG; #define LPORT_INTR_1_CPU_MASK_SET_REG_OFFSET 0x00000110 extern const ru_reg_rec LPORT_INTR_1_CPU_MASK_CLEAR_REG; #define LPORT_INTR_1_CPU_MASK_CLEAR_REG_OFFSET 0x00000114 extern const ru_reg_rec LPORT_INTR_1_PCI_STATUS_REG; #define LPORT_INTR_1_PCI_STATUS_REG_OFFSET 0x00000118 extern const ru_reg_rec LPORT_INTR_1_PCI_SET_REG; #define LPORT_INTR_1_PCI_SET_REG_OFFSET 0x0000011c extern const ru_reg_rec LPORT_INTR_1_PCI_CLEAR_REG; #define LPORT_INTR_1_PCI_CLEAR_REG_OFFSET 0x00000120 extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_STATUS_REG; #define LPORT_INTR_1_PCI_MASK_STATUS_REG_OFFSET 0x00000124 extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_SET_REG; #define LPORT_INTR_1_PCI_MASK_SET_REG_OFFSET 0x00000128 extern const ru_reg_rec LPORT_INTR_1_PCI_MASK_CLEAR_REG; #define LPORT_INTR_1_PCI_MASK_CLEAR_REG_OFFSET 0x0000012c extern const ru_reg_rec LPORT_MAB_CNTRL_REG; #define LPORT_MAB_CNTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec LPORT_MAB_TX_WRR_CTRL_REG; #define LPORT_MAB_TX_WRR_CTRL_REG_OFFSET 0x00000004 extern const ru_reg_rec LPORT_MAB_TX_THRESHOLD_REG; #define LPORT_MAB_TX_THRESHOLD_REG_OFFSET 0x00000008 extern const ru_reg_rec LPORT_MAB_LINK_DOWN_TX_DATA_REG; #define LPORT_MAB_LINK_DOWN_TX_DATA_REG_OFFSET 0x0000000c extern const ru_reg_rec LPORT_MAB_STATUS_REG; #define LPORT_MAB_STATUS_REG_OFFSET 0x00000010 /****************************************************************************** * BCM6858_A0 Blocks ******************************************************************************/ extern const ru_block_rec LPORT_XLMAC_BLOCK; extern const ru_block_rec LPORT_MIB_BLOCK; extern const ru_block_rec LPORT_SRDS_BLOCK; extern const ru_block_rec LPORT_LED_BLOCK; extern const ru_block_rec LPORT_CTRL_BLOCK; extern const ru_block_rec LPORT_RGMII_BLOCK; extern const ru_block_rec XLMAC_CONF_BLOCK; extern const ru_block_rec MIB_CONF_BLOCK; extern const ru_block_rec LPORT_MDIO_BLOCK; extern const ru_block_rec LPORT_INTR_BLOCK; extern const ru_block_rec LPORT_MAB_BLOCK; extern const ru_block_rec *RU_LPORT_BLOCKS[]; #define RU_BLK_COUNT 11 #define RU_REG_COUNT 300 #define RU_FLD_COUNT 1041 #endif /* End of file BCM6858_A0.h */