/* <:copyright-BRCM:2013:DUAL/GPL:standard Copyright (c) 2013 Broadcom All Rights Reserved This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License, version 2, as published by the Free Software Foundation (the "GPL"). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. :> */ #ifndef __BCM4908_MAP_PART_H #define __BCM4908_MAP_PART_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #include "bcm_io_map.h" #define CHIP_FAMILY_ID_HEX 0x4908 #ifndef __ASSEMBLER__ enum { PERF_IDX, PERF1_IDX, NANDFLASH_IDX, MEMC_IDX, PMC_IDX, PROC_MON_IDX, GMAC_IDX, RDP_IDX, SWITCH_IDX, SATA_IDX, USBH_IDX, URB_IDX, PCM_IDX, UBUS_IDX, LAST_IDX }; #endif /* Perf block base address and size */ #define PERF_PHYS_BASE 0xff800000 #define PERF_SIZE 0x3000 /* perf block offset */ #define PERF_OFFSET 0x0000 /* chip control */ #define TIMR_OFFSET 0x0400 /* timer registers */ #define GPIO_OFFSET 0x0500 /* gpio registers */ #define UART_OFFSET 0x0640 /* uart registers */ #define LED_OFFSET 0x0800 /* led registers */ #define RNG_OFFSET 0x0b80 /* rng registers */ #define SOTP_OFFSET 0x0c00 /* SOTP register */ #define PKA_OFFSET 0x0cc0 #define AES0_OFFSET 0x0d00 #define AES1_OFFSET 0x0d80 #define JTAG_OTP_OFFSET 0x0e00 #define JTAG_IOTP_OFFSET 0x0e80 #define HSSPIM_OFFSET 0x1000 /* High-Speed SPI registers */ #define NAND_REG_OFFSET 0x1800 /* nand interrupt control */ #define NAND_CACHE_OFFSET 0x1c00 /* NAND cache register */ #define NAND_INTR_OFFSET 0x2000 /* NAND int register */ #define I2S_OFFSET 0x2080 /* I2S regsiters */ #define I2C_OFFSET 0x2100 /* I2C regsiters */ #define M2M_OFFSET 0x2200 /* M2M DMA regsiters */ #define MISC_OFFSET 0x2600 /* Miscellaneous Registers */ #define TIMR_PHYS_BASE (PERF_PHYS_BASE+TIMR_OFFSET) #define GPIO_PHYS_BASE (PERF_PHYS_BASE+GPIO_OFFSET) #define UART_PHYS_BASE (PERF_PHYS_BASE+UART_OFFSET) #define LED_PHYS_BASE (PERF_PHYS_BASE+LED_OFFSET) #define RNG_PHYS_BASE (PERF_PHYS_BASE+RNG_OFFSET) #define SOTP_PHYS_BASE (PERF_PHYS_BASE+SOTP_OFFSET) #define PKA_PHYS_BASE (PERF_PHYS_BASE+PKA_OFFSET) #define AES0_PHYS_BASE (PERF_PHYS_BASE+AES0_OFFSET) #define AES1_PHYS_BASE (PERF_PHYS_BASE+AES1_OFFSET) #define JTAG_OTP_PHYS_BASE (PERF_PHYS_BASE+JTAG_OTP_OFFSET) #define JTAG_IOTP_PHYS_BASE (PERF_PHYS_BASE+JTAP_IOTP_OFFSET) #define HSSPIM_PHYS_BASE (PERF_PHYS_BASE+HSSPIM_OFFSET) #define NAND_REG_PHYS_BASE (PERF_PHYS_BASE+NAND_REG_OFFSET) #define NAND_CACHE_PHYS_BASE (PERF_PHYS_BASE+NAND_CACHE_OFFSET) #define NAND_INTR_PHYS_BASE (PERF_PHYS_BASE+NAND_INTR_OFFSET) #define I2S_PHYS_BASE (PERF_PHYS_BASE+I2S_OFFSET) #define I2C_PHYS_BASE (PERF_PHYS_BASE+I2C_OFFSET) #define M2M_PHYS_BASE (PERF_PHYS_BASE+M2M_OFFSET) #define MISC_PHYS_BASE (PERF_PHYS_BASE+MISC_OFFSET) /* Perf1 block base address and size */ #define PERF1_PHYS_BASE 0xff858000 #define PERF1_SIZE 0x3000 /* perf1 block offset */ #define EMMC_HOSTIF_OFFSET 0x0000 #define EMMC_TOP_CFG_OFFSET 0x0100 #define EMMC_BOOT_OFFSET 0x0200 #define AHBSS_CTRL_OFFSET 0x0300 #define HS_UART_OFFSET 0x0400 #define PL081_DMA_OFFSET 0x1000 #define TOP_CONTROL_OFFSET 0x2000 /* EMMC direct access window */ #define EMMCFLASH_PHYS_BASE 0xffc00000 #define EMMCFLASH_SIZE 0x100000 #define EMMCFLASH_OFFSET 0x0000 /* SPI NOR direct access window */ #define SPIFLASH_PHYS_BASE 0xffd00000 #define SPIFLASH_SIZE 0x100000 #define SPIFLASH_OFFSET 0x0000 /* nand flash direct access address */ #define NANDFLASH_PHYS_BASE 0xffe00000 #define NANDFLASH_SIZE 0x100000 #define NANDFLASH_OFFSET 0x0000 #define GMAC_PHYS_BASE 0x80002000 #define GMAC_SIZE 0x1000 #define GMAC_INTF_OFFSET 0x0000 #define GMAC_MIB_OFFSET 0x0200 #define GMAC_MAC_OFFSET 0x0400 #define GMAC_DMA_OFFSET 0x0800 #define MEMC_PHYS_BASE 0x80018000 /* DDR IO Buf Control */ #define MEMC_SIZE 0x4000 #define MEMC_OFFSET 0x0000 #define PCIE0_PHYS_BASE 0x80040000 #define PCIE0_SIZE 0x0000A000 #define PCIE1_PHYS_BASE 0x80050000 #define PCIE1_SIZE 0x0000A000 #define PCIE2_PHYS_BASE 0x80060000 #define PCIE2_SIZE 0x0000A000 #define PCIE0_MEM_PHYS_BASE 0xc0000000 #define PCIE0_MEM_SIZE 0x10000000 #define PCIE1_MEM_PHYS_BASE 0xd0000000 #define PCIE1_MEM_SIZE 0x10000000 #define PCIE2_MEM_PHYS_BASE 0xe0000000 #define PCIE2_MEM_SIZE 0x10000000 #define PMC_PHYS_BASE 0x80200000 #define PMC_SIZE 0x5000 #define PMC_OFFSET 0x0000 #define PROC_MON_PHYS_BASE 0x80280000 #define PROC_MON_SIZE 0x1000 #define PROC_MON_OFFSET 0x0000 #define RDP_PHYS_BASE 0x82200000 #define RDP_SIZE 0x100000 #define RDP_OFFSET 0x0000 #define RDP_UMAC_0_CFG_OFFSET 0xd4000 #define RDP_UMAC_CFG_MIB_0_OFFSET 0xda000 #define RDP_UMAC_MISC_TOP_1_OFFSET 0xdb800 /* definition for impl7 unimac_drv.h */ #define UNIMAC_CFG_BASE RDP_UMAC_0_CFG_OFFSET #define UNIMAC_MIB_BASE RDP_UMAC_CFG_MIB_0_OFFSET #define UNIMAC_TOP_BASE RDP_UMAC_MISC_TOP_1_OFFSET #define FPM_PHYS_BASE 0x82c00000 #define FPM_SIZE 0x80000 #define FPM_OFFSET 0x0000 #define FPM_BPM_PHYS_BASE 0x82c30000 #define FPM_BPM_SIZE 0x0134 #define FPM_BPM_OFFSET 0x0000 #define SWITCH_PHYS_BASE 0x80080000 #define SWITCH_SIZE 0x50000 #define SWITCH_CORE_OFFSET 0x00000 #define SWITCH_REG_OFFSET 0x40000 #define SWITCH_MDIO_OFFSET 0x405c0 #define SWITCH_FCB_OFFSET 0x40600 #define SWITCH_ACB_OFFSET 0x40800 #define SATA_PHYS_BASE 0x80008000 #define SATA_SIZE 0x3fff #define SATA_OFFSET 0x0000 #define USBH_PHYS_BASE 0x8000c000 #define USBH_SIZE 0x3fff #define USBH_OFFSET 0x0000 #define CFG_OFFSET 0x200 #define EHCI_OFFSET 0x300 /* USB host registers */ #define OHCI_OFFSET 0x400 /* USB host registers */ #define XHCI_OFFSET 0x1000 /* USB host registers */ #define XHCI_EC_OFFSET 0x1900 /* USB host registers */ #define PCM_PHYS_BASE 0x80100000 #define UBUS_PHYS_BASE 0x80010000 #define PCM_CORE_OFFSET 0x00000C00 #define PCM_DMA_OFFSET 0x00001000 #define PCM_SIZE 0x2000 #define UBUS_SIZE 0x1000 /* to support non-DT pltaform device add below defs */ #define USB_EHCI_PHYS_BASE (USBH_PHYS_BASE+EHCI_OFFSET) #define USB_OHCI_PHYS_BASE (USBH_PHYS_BASE+OHCI_OFFSET) #define USB_XHCI_PHYS_BASE (USBH_PHYS_BASE+XHCI_OFFSET) #define URB_PHYS_BASE 0x81060000 #define URB_SIZE 0x4000 #define URB_OFFSET 0x0000 #define URB_BIUARCH_OFFSET 0x1000 #define URB_BIUCTRL_OFFSET 0x2000 #define GIC_PHYS_BASE 0x81000000 #define GIC_SIZE 0x10000 #define GIC_OFFSET 0x0000 #define GICD_OFFSET 0x1000 #define GICC_OFFSET 0x2000 /* Physical and access(could be virtual or physical) bases address for * all the registers */ #define PERF_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, PERF_OFFSET) #define TIMR_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, TIMR_OFFSET) #define GPIO_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, GPIO_OFFSET) #define UART_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, UART_OFFSET) #define LED_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, LED_OFFSET) #define RNG_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, RNG_OFFSET) #define SOTP_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, SOTP_OFFSET) #define PKA_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, PKA_OFFSET) #define AES0_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, AES0_OFFSET) #define AES1_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, AES1_OFFSET) #define JTAG_OTP_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, JTAG_OTP_OFFSET) #define JTAG_IOTP_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, JTAG_IOTP_OFFSET) #define HSSPIM_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, HSSPIM_OFFSET) #define NAND_REG_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_REG_OFFSET) #define NAND_CACHE_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_CACHE_OFFSET) #define NAND_INTR_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_INTR_OFFSET) #define I2S_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, I2S_OFFSET) #define I2C_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, I2C_OFFSET) #define M2M_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, M2M_OFFSET) #define MISC_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, MISC_OFFSET) #define PERF1_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_HOSTIF_OFFSET) #define EMMC_HOSTIF_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_HOSTIF_OFFSET) #define EMMC_TOP_CFG_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_TOP_CFG_OFFSET) #define EMMC_BOOT_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_BOOT_OFFSET) #define AHBSS_CTRL_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, AHBSS_CTRL_OFFSET) #define HS_UART_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, HS_UART_OFFSET) #define PL081_DMA_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, PL081_DMA_OFFSET) #define TOP_CONTROL_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, TOP_CONTROL_OFFSET) #define NANDFLASH_BASE BCM_IO_MAP(NANDFLASH_IDX, NANDFLASH_PHYS_BASE, NANDFLASH_OFFSET) #define GMAC_BASE BCM_IO_MAP(GMAC_IDX, GMAC_PHYS_BASE, GMAC_INTF_OFFSET) #define GMAC_INTF_BASE BCM_IO_MAP(GMAC_IDX, GMAC_PHYS_BASE, GMAC_INTF_OFFSET) #define GMAC_MIB_BASE BCM_IO_MAP(GMAC_IDX, GMAC_PHYS_BASE, GMAC_MIB_OFFSET) #define GMAC_MAC_BASE BCM_IO_MAP(GMAC_IDX, GMAC_PHYS_BASE, GMAC_MAC_OFFSET) #define GMAC_DMA_BASE BCM_IO_MAP(GMAC_IDX, GMAC_PHYS_BASE, GMAC_DMA_OFFSET) #define MEMC_BASE BCM_IO_MAP(MEMC_IDX, MEMC_PHYS_BASE, MEMC_OFFSET) #define PMC_BASE BCM_IO_MAP(PMC_IDX, PMC_PHYS_BASE, PMC_OFFSET) #define PROC_MON_BASE BCM_IO_MAP(PROC_MON_IDX, PROC_MON_PHYS_BASE, PROC_MON_OFFSET) #define RDP_BASE BCM_IO_MAP(RDP_IDX, RDP_PHYS_BASE, RDP_OFFSET) #define SWITCH_CORE_BASE BCM_IO_MAP(SWITCH_IDX, SWITCH_PHYS_BASE, SWITCH_CORE_OFFSET) #define SWITCH_REG_BASE BCM_IO_MAP(SWITCH_IDX, SWITCH_PHYS_BASE, SWITCH_REG_OFFSET) #define SWITCH_MDIO_BASE BCM_IO_MAP(SWITCH_IDX, SWITCH_PHYS_BASE, SWITCH_MDIO_OFFSET) #define SWITCH_FCB_BASE BCM_IO_MAP(SWITCH_IDX, SWITCH_PHYS_BASE, SWITCH_FCB_OFFSET) #define SWITCH_ACB_BASE BCM_IO_MAP(SWITCH_IDX, SWITCH_PHYS_BASE, SWITCH_ACB_OFFSET) #define UMAC_0_CFG_BASE BCM_IO_MAP(RDP_IDX, RDP_PHYS_BASE, RDP_UMAC_0_CFG_OFFSET) #define UMAC_CFG_MIB_0_BASE BCM_IO_MAP(RDP_IDX, RDP_PHYS_BASE, RDP_UMAC_CFG_MIB_0_OFFSET) #define UMAC_MISC_TOP_1_BASE BCM_IO_MAP(RDP_IDX, RDP_PHYS_BASE, RDP_UMAC_MISC_TOP_1_OFFSET) #define SATA_BASE BCM_IO_MAP(SATA_IDX, SATA_PHYS_BASE, SATA_OFFSET) #define USBH_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, USBH_OFFSET) #define USBH_CFG_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, CFG_OFFSET) #define USBH_EHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, EHCI_OFFSET) #define USBH_OHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, OHCI_OFFSET) #define USBH_XHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, XHCI_OFFSET) #define USBH_XHCI_EC_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, XHCI_EC_OFFSET) /*TODO : fix the names of usb register base's to be same across all platforms */ #define USB_XHCI_BASE USBH_XHCI_BASE #define URB_BASE BCM_IO_MAP(URB_IDX, URB_PHYS_BASE, URB_OFFSET) #define BIUARCH_BASE BCM_IO_MAP(URB_IDX, URB_PHYS_BASE, URB_BIUARCH_OFFSET) #define BIUCTRL_BASE BCM_IO_MAP(URB_IDX, URB_PHYS_BASE, URB_BIUCTRL_OFFSET) /* Definition to satisfy legacy code usage */ #define SWITCH_BASE (SWITCH_CORE_BASE) #define SWITCH_DIRECT_DATA_WR_REG (SWITCH_REG_BASE + 0x00008UL) #define SWITCH_DIRECT_DATA_RD_REG (SWITCH_REG_BASE + 0x0000cUL) #define SWITCH_CROSSBAR_REG (SWITCH_REG_BASE + 0x000c8UL) #define PCM_BASE BCM_IO_MAP(PCM_IDX, PCM_PHYS_BASE, PCM_CORE_OFFSET) #define PCM_DMA_BASE BCM_IO_MAP(PCM_IDX, PCM_PHYS_BASE, PCM_DMA_OFFSET) /* These block uses DT or not used by linux at all, no need to map for the legacy support */ #define GIC_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GIC_OFFSET) #define GICC_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GICC_OFFSET) #define GICD_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GICD_OFFSET) #define SPIFLASH_BASE BCM_IO_NOMAP(-1, SPIFLASH_PHYS_BASE, SPIFLASH_OFFSET) #define EMMCFLASH_BASE BCM_IO_NOMAP(-1, EMMCFLASH_PHYS_BASE, EMMCFLASH_OFFSET) #ifndef __ASSEMBLER__ #ifdef __BOARD_DRV_AARCH64__ // add here any legacy driver's (driver that have no device tree node) IO memory to be mapped BCM_IO_BLOCKS bcm_io_blocks[] = { {PERF_IDX, PERF_SIZE, PERF_PHYS_BASE}, {PERF1_IDX, PERF1_SIZE, PERF1_PHYS_BASE}, {NANDFLASH_IDX, NANDFLASH_SIZE, NANDFLASH_PHYS_BASE}, {GMAC_IDX, GMAC_SIZE, GMAC_PHYS_BASE}, {MEMC_IDX, MEMC_SIZE, MEMC_PHYS_BASE}, {PMC_IDX, PMC_SIZE, PMC_PHYS_BASE}, {PROC_MON_IDX, PROC_MON_SIZE, PROC_MON_PHYS_BASE}, {RDP_IDX, RDP_SIZE, RDP_PHYS_BASE}, {SWITCH_IDX, SWITCH_SIZE, SWITCH_PHYS_BASE}, {SATA_IDX, SATA_SIZE, SATA_PHYS_BASE}, {USBH_IDX, USBH_SIZE, USBH_PHYS_BASE}, {URB_IDX, URB_SIZE, URB_PHYS_BASE}, {PCM_IDX, PCM_SIZE, PCM_PHYS_BASE}, {UBUS_IDX, UBUS_SIZE, UBUS_PHYS_BASE}, }; unsigned long bcm_io_block_address[LAST_IDX]; #else extern BCM_IO_BLOCKS bcm_io_blocks[]; extern unsigned long bcm_io_block_address[]; #endif typedef struct UBUSInterface { uint32 CFG; /* 0x00 */ uint32 ESRCID_CFG; /* 0x04 */ #define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT 0x0 #define UBUSIF_CFG_WRITE_REPLY_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT) #define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT 0x1 #define UBUSIF_CFG_WRITE_BURST_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT) #define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT 0x2 #define UBUSIF_CFG_INBAND_ERR_MASK_MASK (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT) #define UBUSIF_CFG_OOB_ERR_MASK_SHIFT 0x3 #define UBUSIF_CFG_OOB_ERR_MASK_MASK (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT) uint32 SRC_QUEUE_CTRL[8]; /* 0x08 - 0x24 */ uint32 REP_ARB_MODE; /* 0x28 */ #define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0 #define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK (0x1<> 5) & 0x0f) : (0)) #define GPIO_NUM_TO_MASK(X) ((((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << (((X) & BP_GPIO_NUM_MASK) & 0x1f)) : (0)) #define GPIO_NUM_TO_ARRAY_SHIFT(X) (((X) & BP_GPIO_NUM_MASK) & 0x1f) /* * Misc Register Set Definitions. */ typedef struct Misc { uint32 miscStrapBus; /* 0x00 */ #define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 #define MISC_STRAP_BUS_BOOT_SEL_MASK (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NOR (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_EMMC (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NAND (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_512_PAGE (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_B53_BOOT_N (0x1 << 6) #define MISC_STRAP_BUS_BOOTROM_BOOT_N (0x1 << 7) #define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE (0x1 << 8) #define MISC_STRAP_BUS_PMC_BOOT_AVS (0x1 << 9) #define MISC_STRAP_BUS_PMC_BOOT_FLASH (0x1 << 10) #define MISC_STRAP_BUS_PMC_ROM_BOOT (0x1 << 11) #define MISC_STRAP_BUS_PCIE0_RC_MODE (0x1 << 12) #define MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT 13 #define MISC_STRAP_BUS_RESET_OUT_DELAY_MASK (0x1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_RESET_OUT_DELAY_20US (0x1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_RESET_OUT_DELAY_10MS (0x0 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_XTAL_BYPASS_N (0x1 << 14) #define MISC_STRAP_BUS_UBUS_CLOCK_SHIFT 15 #define MISC_STRAP_BUS_UBUS_CLOCK_MASK (0x1 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT) #define MISC_STRAP_BUS_UBUS_CLOCK_400MHZ (0x1 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT) #define MISC_STRAP_BUS_UBUS_CLOCK_50MHZ (0x0 << MISC_STRAP_BUS_UBUS_CLOCK_SHIFT) #define MISC_STRAP_BUS_CPU_SLOW_FREQ (0x1 << 16) #define MISC_STRAP_BUS_SW_RESERVE_MASK (0x3 << 17) uint32 miscStrapOverride; /* 0x04 */ uint32 miscSoftwareDebug[6]; /* 0x08 */ uint32 miscWDResetCtrl; /* 0x20 */ uint32 miscSWdebugNW[2]; /* 0x24 */ uint32 miscSoftResetB; /* 0x2c */ uint32 miscQAMPllStatus; /* 0x30 */ uint32 miscRsvd1; /* 0x34 */ uint32 miscSpiMasterCtrl; /* 0x38 */ uint32 miscAltBootVector; /* 0x3c */ uint32 miscPeriphCtrl; /* 0x40 */ #define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK (0x7) uint32 miscPCIECtrl; /* 0x44 */ uint32 miscAdsl_clock_sample; /* 0x48 */ uint32 miscRngCtrl; /* 0x4c */ uint32 miscMbox_data[4]; /* 0x50 */ uint32 miscMbox_ctrl; /* 0x60 */ uint32 miscxMIIPadCtrl[4]; /* 0x64 */ #define MISC_XMII_PAD_MODEHV (1 << 6) #define MISC_XMII_PAD_SEL_GMII (1 << 4) #define MISC_XMII_PAD_AMP_EN (1 << 3) uint32 miscxMIIPullCtrl[4]; /* 0x74 */ uint32 miscWDResetEn; /* 0x84 */ uint32 miscBootOverlayEn; /* 0x88 */ uint32 miscSGMIIFiberDetect; /* 0x8c */ #define MISC_SGMII_FIBER_GPIO36 (1<<0) uint32 miscUniMacCtrl; /* 0x90 */ uint32 miscMaskUBUSErr; /* 0x94 */ uint32 miscTOSsync; /* 0x98 */ uint32 miscPM0_1_status; /* 0x9c */ uint32 miscPM2_3_status; /* 0xa0 */ uint32 miscSGB_status; /* 0xa4 */ uint32 miscPM0_1_config; /* 0xa8 */ uint32 miscPM2_3_config; /* 0xac */ uint32 miscSGB_config; /* 0xb0 */ uint32 miscPM0_1_tmon_config; /* 0xb4 */ uint32 miscPM2_3_tmon_config; /* 0xb8 */ uint32 miscSGB_tmon_config; /* 0xbc */ uint32 miscMDIOmasterSelect; /* 0xc0 */ uint32 miscUSIMCtrl; /* 0xc4 */ uint32 miscUSIMPadCtrl; /* 0xc8 */ uint32 miscPerSpareReg[3]; /* 0xcc - 0xd4 */ uint32 miscDgSensePadCtrl; /* 0xd8 */ #define DG_CTRL_SHIFT 4 #define DG_EN_SHIFT 3 #define DG_TRIM_SHIFT 0 uint32 miscPeriphMiscCtrl; /* 0xdc */ uint32 miscPeriphMiscStat; /* 0xe0 */ } Misc; #define MISC ((volatile Misc * const) MISC_BASE) typedef struct Rng { uint32 ctrl0; /* 0x00 */ uint32 rngSoftReset; /* 0x04 */ uint32 rbgSoftReset; /* 0x08 */ uint32 totalBitCnt; /* 0x0c */ uint32 totalBitCntThreshold; /* 0x10 */ uint32 revId; /* 0x14 */ uint32 intStatus; /* 0x18 */ #define RNG_INT_STATUS_NIST_FAIL (0x1<<5) #define RNG_INT_STATUS_FIFO_FULL (0x1<<2) uint32 intEn; /* 0x1c */ uint32 rngFifoData; /* 0x20 */ uint32 fifoCnt; /* 0x24 */ #define RNG_PERM_ALLOW_SECURE_ACCESS 0xCC #define RNG_PERM_ALLOW_NONSEC_ACCESS 0x33 uint32 perm; /* 0x28 */ } Rng; #define RNG ((volatile Rng * const) RNG_BASE) /* * UART Peripheral */ typedef struct UartChannel { byte fifoctl; /* 0x00 */ #define RSTTXFIFOS 0x80 #define RSTRXFIFOS 0x40 /* 5-bit TimeoutCnt is in low bits of this register. * This count represents the number of characters * idle times before setting receive Irq when below threshold */ byte config; #define XMITBREAK 0x40 #define BITS5SYM 0x00 #define BITS6SYM 0x10 #define BITS7SYM 0x20 #define BITS8SYM 0x30 #define ONESTOP 0x07 #define TWOSTOP 0x0f /* 4-LSBS represent STOP bits/char * in 1/8 bit-time intervals. Zero * represents 1/8 stop bit interval. * Fifteen represents 2 stop bits. */ byte control; #define BRGEN 0x80 /* Control register bit defs */ #define TXEN 0x40 #define RXEN 0x20 #define LOOPBK 0x10 #define TXPARITYEN 0x08 #define TXPARITYEVEN 0x04 #define RXPARITYEN 0x02 #define RXPARITYEVEN 0x01 byte unused0; uint32 baudword; /* 0x04 */ /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate */ /* 0x08 */ byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) * if these bits are also enabled to * GPIO_o */ #define ARMUARTEN 0x04 #define RTSEN 0x02 #define DTREN 0x01 byte fifocfg; /* Upper 4-bits are TxThresh, Lower are * RxThreshold. Irq can be asserted * when rx fifo> thresh, txfifosingle_serdes_stat) #define SWITCH_REG_SSER_LINK_STAT (1<<0) #define SWITCH_REG_SSER_RXSIG_DET (1<<1) #define SWITCH_REG_SSER_RXSIG_1G (1<<2) #define SWITCH_REG_SSER_SGMII (1<<3) #define SWITCH_REG_SSER_SYNC_STAT (1<<4) #define SWITCH_REG_SSER_POLL_LOCK (1<<5) #define SWITCH_REG_SSER_EXTFB_DET (1<<6) #define SWITCH_REG_SINGLE_SERDES_CNTRL (ÐSW_REG->single_serdes_ctrl) #define SWITCH_REG_SERDES_IDDQ (1<<0) #define SWITCH_REG_SERDES_PWRDWN (1<<1) #define SWITCH_REG_SERDES_RESETPLL (1<<3) #define SWITCH_REG_SERDES_RESETMDIO (1<<4) #define SWITCH_REG_SERDES_RESET (1<<5) #define SERDES_2P5G_CAPABLE 1 #define SWITCH_REG_LED_WAN_CNTRL_LED (ÐSW_REG->led_wan_ctrl) #define SWITCH_REG_LED_WAN_TX_EN (1<<1) #define SWITCH_REG_LED_WAN_RX_EN (1<<0) /* ** Eth Switch Registers */ typedef struct { unsigned int led_f; unsigned int reserved; } LED_F; typedef struct EthernetSwitchCore { unsigned int port_traffic_ctrl[9]; /* 0x00 - 0x08 */ unsigned int reserved1[2]; /* 0x09 - 0x0a */ unsigned int switch_mode; /* 0x0b */ #define ETHSW_SM_RETRY_LIMIT_DIS 0x04 #define ETHSW_SM_FORWARDING_EN 0x02 #define ETHSW_SM_MANAGED_MODE 0x01 unsigned int pause_quanta; /* 0x0c */ unsigned int reserved33; unsigned int imp_port_state; /*0x0e */ #define ETHSW_IPS_USE_MII_HW_STS 0x00 #define ETHSW_IPS_USE_REG_CONTENTS 0x80 #define ETHSW_IPS_GMII_SPEED_UP_NORMAL 0x00 #define ETHSW_IPS_GMII_SPEED_UP_2G 0x40 #define ETHSW_IPS_TXFLOW_NOT_PAUSE_CAPABLE 0x00 #define ETHSW_IPS_TXFLOW_PAUSE_CAPABLE 0x20 #define ETHSW_IPS_RXFLOW_NOT_PAUSE_CAPABLE 0x00 #define ETHSW_IPS_RXFLOW_PAUSE_CAPABLE 0x10 #define ETHSW_IPS_SW_PORT_SPEED_1000M_2000M 0x08 #define ETHSW_IPS_DUPLEX_MODE 0x02 #define ETHSW_IPS_LINK_FAIL 0x00 #define ETHSW_IPS_LINK_PASS 0x01 unsigned int led_refresh; /* 0x0f */ LED_F led_function[2]; /* 0x10 */ unsigned int led_function_map; /* 0x14 */ unsigned int reserved14; unsigned int led_enable_map; /* 0x16 */ unsigned int reserved15; unsigned int led_mode_map0; /* 0x18 */ unsigned int reserved16; unsigned int led_function_map1; /* 0x1a */ unsigned int reserved17; unsigned int reserved2[5]; /* 0x1c - 0x20 */ unsigned int port_forward_ctrl; /* 0x21 */ unsigned int switch_ctrl; /* 0x22 */ #define ETHSW_SC_MII_DUMP_FORWARDING_EN 0x40 #define ETHSW_SC_MII2_VOL_SEL 0x02 unsigned int reserved3; /* 0x23 */ unsigned int protected_port_selection; /* 0x24 */ unsigned int reserved18; unsigned int wan_port_select; /* 0x26 */ unsigned int reserved19; unsigned int pause_capability; /* 0x28 */ unsigned int reserved20[3]; unsigned int reserved4[3]; /* 0x2c - 0x2e */ unsigned int reserved_multicast_control; /* 0x2f */ unsigned int reserved5; /* 0x30 */ unsigned int txq_flush_mode_control; /* 0x31 */ unsigned int ulf_forward_map; /* 0x32 */ unsigned int reserved21; unsigned int mlf_forward_map; /* 0x34 */ unsigned int reserved22; unsigned int mlf_impc_forward_map; /* 0x36 */ unsigned int reserved23; unsigned int pause_pass_through_for_rx; /* 0x38 */ unsigned int reserved24; unsigned int pause_pass_through_for_tx; /* 0x3a */ unsigned int reserved25; unsigned int disable_learning; /* 0x3c */ unsigned int reserved26; unsigned int reserved6[26]; /* 0x3e - 0x57 */ unsigned int port_state_override[8]; /* 0x58 - 0x5f */ #define ETHSW_PS_SW_OVERRIDE 0x40 #define ETHSW_PS_SW_TX_FLOW_CTRL_EN 0x20 #define ETHSW_PS_SW_RX_FLOW_CTRL_EN 0x10 #define ETHSW_PS_SW_PORT_SPEED_1000M 0x08 #define ETHSW_PS_SW_PORT_SPEED_100M 0x04 #define ETHSW_PS_SW_PORT_SPEED_10M 0x00 #define ETHSW_PS_DUPLEX_MODE 0x02 #define ETHSW_PS_LINK_DOWN 0x00 #define ETHSW_PS_LINK_UP 0x01 unsigned int reserved7[4]; /* 0x60 - 0x63 */ unsigned int imp_rgmii_ctrl_p4; /* 0x64 */ unsigned int imp_rgmii_ctrl_p5; /* 0x65 */ unsigned int reserved8[6]; /* 0x66 - 0x6b */ unsigned int rgmii_timing_delay_p4; /* 0x6c */ unsigned int gmii_timing_delay_p5; /* 0x6d */ unsigned int reserved9[11]; /* 0x6e - 0x78 */ unsigned int software_reset; /* 0x79 */ unsigned int reserved13[6]; /* 0x7a - 0x7f */ unsigned int pause_frame_detection; /* 0x80 */ unsigned int reserved10[7]; /* 0x81 - 0x87 */ unsigned int fast_aging_ctrl; /* 0x88 */ unsigned int fast_aging_port; /* 0x89 */ unsigned int fast_aging_vid; /* 0x8a */ unsigned int anonymous1[376]; /* 0x8b */ unsigned int brcm_hdr_ctrl; /* 0x203 */ unsigned int anonymous2[0x2efc]; /* 0x204 */ unsigned int port_vlan_ctrl[9*2]; /* 0x3100 */ } EthernetSwitchCore; #define PBMAP_MIPS 0x100 #define ETHSW_CORE ((volatile EthernetSwitchCore * const) SWITCH_CORE_BASE) typedef struct { uint32 led_ctrl; uint32 led_encoding_sel; uint32 led_encoding; }LED_CFG; typedef struct EthernetSwitchReg { uint32 switch_ctrl; /* 0x0000 */ uint32 switch_status; /* 0x0004 */ uint32 dir_data_write_reg; /* 0x0008 */ uint32 dir_data_read_reg; /* 0x000c */ uint32 switch_rev; /* 0x0010 */ uint32 phy_rev; /* 0x0014 */ uint32 phy_test_ctrl; /* 0x0018 */ uint32 qphy_ctrl; /* 0x001c */ #define ETHSW_QPHY_CTRL_PHYAD_BASE_SHIFT 12 #define ETHSW_QPHY_CTRL_PHYAD_BASE_MASK (0x1f<phy_test_ctrl)) #define SPHY_CNTRL ((volatile unsigned int*)(ÐSW_REG->sphy_ctrl)) #define QPHY_CNTRL ((volatile unsigned int*)(ÐSW_REG->qphy_ctrl)) typedef struct EthernetSwitchMDIO { uint32 mdio_cmd; /* 0x0000 */ #define ETHSW_MDIO_BUSY (1 << 29) #define ETHSW_MDIO_FAIL (1 << 28) #define ETHSW_MDIO_CMD_SHIFT 26 #define ETHSW_MDIO_CMD_MASK (0x3<