/* Copyright 2000-2010 Broadcom Corporation <:label-BRCM:2011:DUAL/GPL:standard This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License, version 2, as published by the Free Software Foundation (the "GPL"). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. :> */ #ifndef __BCM6838_MAP_PART_H #define __BCM6838_MAP_PART_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #if !defined(REG_BASE) #define REG_BASE 0xa0000000 #endif #define CHIP_FAMILY_ID_HEX 0x6838 #define MEMC_BASE ( REG_BASE + 0x12000000 ) /* DDR Memory Controller base */ #define PCIE_0_BASE ( REG_BASE + 0x12800000 ) /* PCIe-0 Top */ #define PCIE_1_BASE ( REG_BASE + 0x12a00000 ) /* PCIe-1 Top */ #define APM_BASE ( REG_BASE + 0x13a00000 ) /* APM Control block */ #define BMU_BASE ( REG_BASE + 0x13a01000 ) /* BMU Control Block */ #define PMC_BASE ( REG_BASE + 0x13e00000 ) /* PMC Block */ #define PROC_MON_BASE ( REG_BASE + 0x13e80000 ) /* PMC Process Monitor Block */ #define IC_BASE ( REG_BASE + 0x14e00000 ) /* chip control interrupt register */ /* Blocks of PERIPHERAL BLOCK IC has the base of PERF_BASE */ #define PERF_BASE ( REG_BASE + 0x14e00000 ) /* INTERRUPT registers */ #define TIMR_BASE ( REG_BASE + 0x14e000c0 ) /* TIMER registers */ #define NAND_INTR_BASE ( REG_BASE + 0x14e000f0 ) /* NAND Flash Interrupt base */ #define GPIO_BASE ( REG_BASE + 0x14e00100 ) /* GPIO registers */ #define PG_CONTROL_PER ( REG_BASE + 0x14e002bc ) /* VIPER alternate boot vector register */ #define PLL_CONTROL_REG ( REG_BASE + 0x14e002c0 ) /* PLL control */ #define WATCHDOG_BASE ( REG_BASE + 0x14e002d0 ) /* WATCHDOG registers */ #define PERF_EXT_INT ( REG_BASE + 0x14e00304 ) /* Peripheral Extended interrupt register*/ #define DBG_PERF ( REG_BASE + 0x14e003e0 ) /* Software debug register per*/ #define OTP_BASE ( REG_BASE + 0x14e00400 ) /* OTP registers */ #define UART_BASE ( REG_BASE + 0x14e00500 ) /* UART 0 registers */ #define UART1_BASE ( REG_BASE + 0x14e00520 ) /* UART 1 registers */ #define UART2_BASE ( REG_BASE + 0x14e00540 ) /* UART 2 registers */ #define MDIO_EXT_BASE ( REG_BASE + 0x14e00600 ) /* External MDIO Registers PER*/ #define MDIO_EGPHY_BASE ( REG_BASE + 0x14e00610 ) /* EGPHY MDIO Registers PER*/ #define MDIO_SATA_BASE ( REG_BASE + 0x14e00620 ) /* SATA MDIO register per*/ #define MDIO_AE_BASE ( REG_BASE + 0x14e00630 ) /* AE PCS MDIO Registers PER*/ #define USIM_BASE ( REG_BASE + 0x14e00700 ) /* USIM interface registers*/ #define I2C_BASE ( REG_BASE + 0x14e00e00 ) /* I2C interface register*/ #define LED_BASE ( REG_BASE + 0x14e00f00 ) /* LED control register*/ #define HSSPIM_BASE ( REG_BASE + 0x14e01000 ) /* High Speed SPI Master registes*/ #define NAND_REG_BASE ( REG_BASE + 0x14e02200 ) /* NAND flash controller registers*/ #define NAND_CACHE_BASE ( REG_BASE + 0x14e02600 ) /* NAND flash cache buffer */ #define USBH_BASE ( REG_BASE + 0x15400000 ) /* USBH control block*/ #define USBD_BASE ( REG_BASE + 0x15600000 ) /* USBD control block*/ #define UBUS2_ERROR ( REG_BASE + 0x15e00000 ) /* UBUS Error block*/ #define PSRAM_BASE 0xb30a0000 #define PSRAM_BASE_KSEG0 0x930a0000 #define PSRAM_SIZE 0x20000 /* 128KB */ #define HIGH_MEM_PHYS_ADDRESS 0x20000000 #ifndef __ASSEMBLER__ /***********************************************************/ /* MEMC block definition */ /***********************************************************/ typedef struct DDRPhyControl { uint32 REVISION; /* 0x00 */ uint32 CLK_PM_CTRL; /* 0x04 */ uint32 unused0[2]; /* 0x08-0x10 */ uint32 PLL_STATUS; /* 0x10 */ uint32 PLL_CONFIG; /* 0x14 */ uint32 PLL_CONTROL; /* 0x18 */ uint32 PLL_DIVIDER; /* 0x1c */ uint32 AUX_CONTROL; /* 0x20 */ uint32 unused1[3]; /* 0x24-0x30 */ uint32 VDL_OVERRIDE_BYTE; /* 0x30 */ uint32 VDL_OVERRIDE_BIT; /* 0x34 */ uint32 IDLE_PAD_CONTROL; /* 0x38 */ uint32 ZQ_PVT_COMP; /* 0x3c */ uint32 DRIVE_PAD; /* 0x40 */ uint32 VDL_RD_DATA_DELAY_STATUS; /* 0x44 */ uint32 VDL_CALIBRATE; /* 0x48 */ uint32 VDL_CALIB_STATUS; /* 0x4c */ uint32 VDL_DQ_CALIB_STATUS; /* 0x50*/ uint32 VDL_WR_CHAN_CALIB_STATUS; /* 0x54 */ uint32 VDL_RD_EN_CALIB_STATUS; /* 0x58 */ uint32 VIRTUAL_VTT_CONTROL; /* 0x5c */ uint32 VIRTUAL_VTT_STATUS; /* 0x60 */ uint32 VIRTUAL_VTT_CONNECTIONS; /* 0x64 */ uint32 VIRTUAL_OVERRIDE; /* 0x68 */ uint32 VREF_DAC_CONTROL; /* 0x6c */ uint32 PHYBIST_CNTRL; /* 0x70 */ uint32 PHYBIST_SEED; /* 0x74 */ uint32 PHYBIST_STATUS; /* 0x78 */ uint32 PHYBIST_CTL_STATUS; /* 0x7c */ uint32 PHYBIST_DQ_STATUS; /* 0x80 */ uint32 PHYBIST_MISC_STATUS; /* 0x84 */ uint32 unused2[2]; /* 0x88-0x90 */ uint32 COMMAND_REG; /* 0x90 */ uint32 MODE_REG0; /* 0x94 */ uint32 MODE_REG1; /* 0x98 */ uint32 MODE_REG2; /* 0x9c */ uint32 MODE_REG3; /* 0xa0 */ uint32 STANDBY_CONTROL; /* 0xa4 */ uint32 unused3[2]; /* 0xa8-0xb0 */ uint32 STRAP_CONTROL; /* 0xb0 */ uint32 STRAP_CONTROL2; /* 0xb4 */ uint32 STRAP_STATUS; /* 0xb8 */ uint32 STRAP_STATUS2; /* 0xbc */ uint32 DEBUG_FREEZ_ENABLE; /* 0xc0 */ uint32 DATAPATH_LOOPBACK ; /* 0xc4 */ } DDRPhyControl; typedef struct DDRPhyByteLaneControl { uint32 VDL_OVRIDE_BYTE_RD_EN; /*0x400 */ uint32 VDL_OVRIDE_BYTE0_W; /*0x404*/ uint32 VDL_OVRIDE_BYTE0_R_P; /*0x408*/ uint32 VDL_OVRIDE_BYTE0_R_N; /*0x40c*/ uint32 VDL_OVRIDE_BYTE0_BIT0_W; /*0x410*/ uint32 VDL_OVRIDE_BYTE0_BIT1_W; /*0x414*/ uint32 VDL_OVRIDE_BYTE0_BIT2_W; /*0x418*/ uint32 VDL_OVRIDE_BYTE0_BIT3_W; /*0x41c*/ uint32 VDL_OVRIDE_BYTE0_BIT4_W; /*0x420*/ uint32 VDL_OVRIDE_BYTE0_BIT5_W; /*0x424*/ uint32 VDL_OVRIDE_BYTE0_BIT6_W; /*0x428*/ uint32 VDL_OVRIDE_BYTE0_BIT7_W; /*0x42c*/ uint32 VDL_OVRIDE_BYTE0_DM_W; /*0x430*/ uint32 VDL_OVRIDE_BYTE0_BIT0_R_P; /*0x434*/ uint32 VDL_OVRIDE_BYTE0_BIT0_R_N; /*0x438*/ uint32 VDL_OVRIDE_BYTE0_BIT1_R_P; /*0x43c*/ uint32 VDL_OVRIDE_BYTE0_BIT1_R_N; /*0x440*/ uint32 VDL_OVRIDE_BYTE0_BIT2_R_P; /*0x444*/ uint32 VDL_OVRIDE_BYTE0_BIT2_R_N; /*0x448*/ uint32 VDL_OVRIDE_BYTE0_BIT3_R_P; /*0x44c*/ uint32 VDL_OVRIDE_BYTE0_BIT3_R_N; /*0x450*/ uint32 VDL_OVRIDE_BYTE0_BIT4_R_P; /*0x454*/ uint32 VDL_OVRIDE_BYTE0_BIT4_R_N; /*0x458*/ uint32 VDL_OVRIDE_BYTE0_BIT5_R_P; /*0x45c*/ uint32 VDL_OVRIDE_BYTE0_BIT5_R_N; /*0x460*/ uint32 VDL_OVRIDE_BYTE0_BIT6_R_P; /*0x464*/ uint32 VDL_OVRIDE_BYTE0_BIT6_R_N; /*0x468*/ uint32 VDL_OVRIDE_BYTE0_BIT7_R_P; /*0x46c*/ uint32 VDL_OVRIDE_BYTE0_BIT7_R_N; /*0x470*/ uint32 VDL_OVRIDE_BYTE0_BIT_RD_EN; /*0x474*/ uint32 unused[11]; uint32 VDL_OVRIDE_BYTE1_W; /*0x4a4*/ uint32 VDL_OVRIDE_BYTE1_R_P; /*0x4a8*/ uint32 VDL_OVRIDE_BYTE1_R_N; /*0x4ac*/ uint32 VDL_OVRIDE_BYTE1_BIT0_W; /*0x4b0*/ uint32 VDL_OVRIDE_BYTE1_BIT1_W; /*0x4b4*/ uint32 VDL_OVRIDE_BYTE1_BIT2_W; /*0x4b8*/ uint32 VDL_OVRIDE_BYTE1_BIT3_W; /*0x4bc*/ uint32 VDL_OVRIDE_BYTE1_BIT4_W; /*0x4c0*/ uint32 VDL_OVRIDE_BYTE1_BIT5_W; /*0x4c4*/ uint32 VDL_OVRIDE_BYTE1_BIT6_W; /*0x4c8*/ uint32 VDL_OVRIDE_BYTE1_BIT7_W; /*0x4cc*/ uint32 VDL_OVRIDE_BYTE1_DM_W; /*0x4d0*/ uint32 VDL_OVRIDE_BYTE1_BIT0_R_P; /*0x4d4*/ uint32 VDL_OVRIDE_BYTE1_BIT0_R_N; /*0x4d8*/ uint32 VDL_OVRIDE_BYTE1_BIT1_R_P; /*0x4dc*/ uint32 VDL_OVRIDE_BYTE1_BIT1_R_N; /*0x4e0*/ uint32 VDL_OVRIDE_BYTE1_BIT2_R_P; /*0x4e4*/ uint32 VDL_OVRIDE_BYTE1_BIT2_R_N; /*0x4e8*/ uint32 VDL_OVRIDE_BYTE1_BIT3_R_P; /*0x4ec*/ uint32 VDL_OVRIDE_BYTE1_BIT3_R_N; /*0x4f0*/ uint32 VDL_OVRIDE_BYTE1_BIT4_R_P; /*0x4f4*/ uint32 VDL_OVRIDE_BYTE1_BIT4_R_N; /*0x4f8*/ uint32 VDL_OVRIDE_BYTE1_BIT5_R_P; /*0x4fc*/ uint32 VDL_OVRIDE_BYTE1_BIT5_R_N; /*0x500*/ uint32 VDL_OVRIDE_BYTE1_BIT6_R_P; /*0x504*/ uint32 VDL_OVRIDE_BYTE1_BIT6_R_N; /*0x508*/ uint32 VDL_OVRIDE_BYTE1_BIT7_R_P; /*0x50c*/ uint32 VDL_OVRIDE_BYTE1_BIT7_R_N; /*0x510*/ uint32 VDL_OVRIDE_BYTE1_BIT_RD_EN; /*0x514*/ uint32 unused1[4]; uint32 DYN_VDL_OVRIDE_BYTE0_R_P; /*0x528*/ uint32 DYN_VDL_OVRIDE_BYTE0_R_N; /*0x52c*/ uint32 DYN_VDL_OVRIDE_BYTE0_BIT_R_P;/*0x530*/ uint32 DYN_VDL_OVRIDE_BYTE0_BIT_R_N;/*0x534*/ uint32 DYN_VDL_OVRIDE_BYTE0_W; /*0x538*/ uint32 DYN_VDL_OVRIDE_BYTE0_BIT_W; /*0x53c*/ uint32 unused2[2]; uint32 DYN_VDL_OVRIDE_BYTE1_R_P; /*0x548*/ uint32 DYN_VDL_OVRIDE_BYTE1_R_N; /*0x54c*/ uint32 DYN_VDL_OVRIDE_BYTE1_BIT_R_P;/*0x550*/ uint32 DYN_VDL_OVRIDE_BYTE1_BIT_R_N;/*0x554*/ uint32 DYN_VDL_OVRIDE_BYTE1_W; /*0x558*/ uint32 DYN_VDL_OVRIDE_BYTE1_BIT_W; /*0x55c*/ uint32 READ_DATA_DLY; /*0x560*/ uint32 READ_CONTROL; /*0x564*/ uint32 unused3[2]; uint32 READ_FIFO_DATA_BL0_0; /*0x570*/ uint32 READ_FIFO_DATA_BL0_1; /*0x574*/ uint32 READ_FIFO_DATA_BL0_2; /*0x578*/ uint32 READ_FIFO_DATA_BL0_3; /*0x57c*/ uint32 READ_FIFO_DATA_BL1_0; /*0x580*/ uint32 READ_FIFO_DATA_BL1_1; /*0x584*/ uint32 READ_FIFO_DATA_BL1_2; /*0x588*/ uint32 READ_FIFO_DATA_BL1_3; /*0x58c*/ uint32 READ_FIFO_STATUS; /*0x590*/ uint32 READ_FIFO_CLEAR; /*0x594*/ uint32 unused4[2]; uint32 IDLE_PAD_CONTROL; /*0x5a0*/ uint32 DRIVE_PAD_CTL; /*0x5a4*/ uint32 CLOCK_PAD_DISABLE; /*0x5a8*/ uint32 WR_PREAMBLE_MODE; /*0x5ac*/ uint32 PHYBIST_VDL_ADJ; /*0x5b0*/ } DDRPhyByteLaneControl; typedef struct MEMCControl { uint32 CNFG; /* 0x000 */ uint32 CSST; /* 0x004 */ uint32 CSEND; /* 0x008 */ uint32 unused; /* 0x00c */ uint32 ROW00_0; /* 0x010 */ uint32 ROW00_1; /* 0x014 */ uint32 ROW01_0; /* 0x018 */ uint32 ROW01_1; /* 0x01c */ uint32 unused0[4]; /* 0x20- 0x30 */ uint32 ROW20_0; /* 0x030 */ uint32 ROW20_1; /* 0x034 */ uint32 ROW21_0; /* 0x038 */ uint32 ROW21_1; /* 0x03c */ uint32 unused1[4]; uint32 COL00_0; /* 0x050 */ uint32 COL00_1; /* 0x054 */ uint32 COL01_0; /* 0x058 */ uint32 COL01_1; /* 0x05c */ uint32 unused2[4]; uint32 COL20_0; /* 0x070 */ uint32 COL20_1; /* 0x074 */ uint32 COL21_0; /* 0x078 */ uint32 COL21_1; /* 0x07c */ uint32 unused3[4]; uint32 BNK10; /* 0x090 */ uint32 BNK32; /* 0x094 */ uint32 unused4[26]; uint32 DCMD; /* 0x100 */ #define DCMD_CS1 (1 << 9) #define DCMD_CS0 (1 << 8) #define DCMD_SET_SREF 4 uint32 DMODE_0; /* 0x104 */ uint32 DMODE_1; /* 0x108 */ #define DMODE_1_DRAMSLEEP (1 << 11) uint32 CLKS; /* 0x10c */ uint32 ODT; /* 0x110 */ uint32 TIM1_0; /* 0x114 */ uint32 TIM1_1; /* 0x118 */ uint32 TIM2; /* 0x11c */ uint32 CTL_CRC; /* 0x120 */ uint32 DOUT_CRC; /* 0x124 */ uint32 DIN_CRC; /* 0x128 */ uint32 CRC_CTRL; /* 0x12c */ uint32 PHY_ST; /* 0x130 */ uint32 DRAM_CFG; /* 0x134 */ uint32 STAT; /* 0x138 */ uint32 unused5[49]; /* 0x13c-0x200*/ DDRPhyControl PhyControl; /* 0x200 */ uint32 unused6[14]; /*0x2c8 - 0x300*/ DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ uint32 unused7[147]; uint32 GCFG; /* 0x800 */ uint32 unused8; /* 0x804 */ uint32 unused9; /* 0x808 */ uint32 ARB; /* 0x80c */ uint32 PI_GCF; /* 0x810 */ uint32 PI_UBUS_CTL; /* 0x814 */ uint32 PI_MIPS_CTL; /* 0x818 */ uint32 PI_DSL_MIPS_CTL; /* 0x81c */ uint32 PI_DSL_PHY_CTL; /* 0x820 */ uint32 PI_UBUS_ST; /* 0x824 */ uint32 PI_MIPS_ST; /* 0x828 */ uint32 PI_DSL_MIPS_ST; /* 0x82c */ uint32 PI_DSL_PHY_ST; /* 0x830 */ uint32 PI_UBUS_SMPL; /* 0x834 */ uint32 TESTMODE; /* 0x838 */ uint32 TEST_CFG1; /* 0x83c */ uint32 TEST_PAT; /* 0x840 */ uint32 TEST_COUNT; /* 0x844 */ uint32 TEST_CURR_COUNT; /* 0x848 */ uint32 TEST_ADDR_UPDT; /* 0x84c */ uint32 TEST_ADDR; /* 0x850 */ uint32 TEST_DATA0_0; /* 0x854 */ uint32 TEST_DATA0_1; /* 0x858 */ uint32 TEST_DATA0_2; /* 0x85c */ uint32 TEST_DATA0_3; /* 0x860 */ uint32 TEST_DATA1_0; /* 0x864 */ uint32 TEST_DATA1_1; /* 0x868 */ uint32 TEST_DATA1_2; /* 0x86c */ uint32 TEST_DATA1_3; /* 0x870 */ uint32 REPLY_DATA0; /* 0x874 */ uint32 REPLY_DATA1; /* 0x878 */ uint32 REPLY_DATA2; /* 0x87c */ uint32 REPLY_DATA3; /* 0x880 */ uint32 REPLY_STAT; /* 0x884 */ } MEMCControl; #define MEMC ((volatile MEMCControl * const) MEMC_BASE) /********************** MEMC block end *********************/ /***********************************************************/ /* PCIE block definition */ /***********************************************************/ #define PCIE_BASE PCIE_0_BASE #define UBUS2_PCIE typedef struct PcieRegs{ uint32 devVenID; uint16 command; uint16 status; uint32 revIdClassCode; /* 0x08 */ uint32 headerTypeLatCacheLineSize; uint32 bar1; uint32 bar2; uint32 priSecBusNo; /* 0x18 */ #define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK 0x00ff0000 #define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT 16 #define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK 0x0000ff00 #define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT 8 #define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK 0x000000ff uint16 ioBaseLimit; uint16 secStatus; uint32 rcMemBaseLimit; uint32 rcPrefBaseLimit; uint32 rcPrefBaseHi; uint32 rcPrefLimitHi; uint32 rcIoBaseLimit; uint32 capPointer; uint32 expRomBase; uint16 brdigeCtrlIntPinIntLine; uint16 bridgeCtrl;/* 0x03c */ uint32 unused1[2]; uint32 pm_cap; /* 0x048 */ uint32 pm_csr; /* 0x04c */ uint32 unused2[23]; /* PcieExpressCtrlRegs */ uint16 pciExpressCap; /* 0x0ac */ uint16 pcieCapabilitiy; uint32 deviceCapability; uint16 deviceControl; uint16 deviceStatus; uint32 linkCapability; uint16 linkControl; uint16 linkStatus; uint32 slotCapability; uint16 slotControl; uint16 slotStatus; uint16 rootControl; uint16 rootCap; uint32 rootStatus; uint32 deviceCapability2; uint16 deviceControl2; uint16 deviceStatus2; uint32 linkCapability2; uint16 linkControl2; uint16 linkStatus2; uint32 slotCapability2; uint16 slotControl2; uint16 slotStatus2; uint32 unused3[6]; /* 0x0e8 */ /* PcieErrorRegs */ uint16 advErrCapId; /* 0x100 */ uint16 advErrCapOff; uint32 ucErrStatus; uint32 ucorrErrMask; uint32 ucorrErrSevr; uint32 corrErrStatus; uint32 corrErrMask; uint32 advErrCapControl; uint32 headerLog1; uint32 headerLog2; uint32 headerLog3; uint32 headerLog4; uint32 rootErrorCommand; uint32 rootErrorStatus; uint32 rcCorrId; uint32 unused4[10]; /* 0x138 */ /* PcieVcRegs */ uint16 vcCapId; /* 0x160 */ uint16 vcCapOffset; uint32 prtVcCapability; uint32 portVcCapability2; uint16 portVcControl; uint16 portVcCtatus; uint32 portArbStatus; uint32 vcRsrcControl; uint32 vcRsrcStatus; uint32 unused5[1]; /* 0x17c */ } PcieRegs; typedef struct PcieRcCfgVendorRegs{ uint32 vendorCap; uint32 specificHeader; uint32 specificReg1; #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR1_SHIFT 0 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 2 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR3_SHIFT 4 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_WORD_ALIGN 0x0 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_HWORD_ALIGN 0x1 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BYTE_ALIGN 0x2 }PcieRcCfgVendorRegs; typedef struct PcieBlk404Regs{ uint32 unused; /* 0x404 */ uint32 config2; /* 0x408 */ #define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK 0x0000000f #define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE 0 uint32 config3; /* 0x40c */ uint32 pmDataA; /* 0x410 */ uint32 pmDataB; /* 0x414 */ } PcieBlk404Regs; typedef struct PcieBlk428Regs{ uint32 vpdIntf; /* 0x428 */ uint16 unused_g; /* 0x42c */ uint16 vpdAddrFlag; /* 0x42e */ uint32 vpdData; /* 0x430 */ uint32 idVal1; /* 0x434 */ uint32 idVal2; /* 0x438 */ uint32 idVal3; /* 0x43c */ #define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK 0xff000000 #define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT 24 #define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK 0x00ffffff #define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT 16 #define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT 8 uint32 idVal4; uint32 idVal5; uint32 unused_h; uint32 idVal6; uint32 msiData; uint32 msiAddr_h; uint32 msiAddr_l; uint32 msiMask; uint32 msiPend; uint32 pmData_c; uint32 msixControl; uint32 msixTblOffBir; uint32 msixPbaOffBit; uint32 unused_k; uint32 pcieCapability; uint32 deviceCapability; uint32 deviceControl; uint32 linkCapability; uint32 bar2Config; uint32 pcieDeviceCapability2; uint32 pcieLinkCapability2; uint32 pcieLinkControl; uint32 pcieLinkCapabilityRc; uint32 bar3Config; uint32 rootCap; uint32 devSerNumCapId; uint32 lowerSerNum; uint32 upperSerNum; uint32 advErrCap; uint32 pwrBdgtData0; uint32 pwrBdgtData1; uint32 pwrBdgtData2; uint32 pwdBdgtData3; uint32 pwrBdgtData4; uint32 pwrBdgtData5; uint32 pwrBdgtData6; uint32 pwrBdgtData7; uint32 ext2CapAddr; uint32 pwrBdgtData8; uint32 pwrBdgtCapability; uint32 vsecHdr; uint32 rcUserMemLo1; uint32 rcUserMemHi1; uint32 rcUserMemLo2; uint32 rcUserMemHi2; uint32 tphCap; uint32 resizebarCap; uint32 ariCap; uint32 initvf; uint32 vfOffset; uint32 vfBarReg; uint32 vfSuppPageSize; uint32 vfCap_en; uint32 vfMsixTblBirOff; uint32 vfMsixPbaOffBit; uint32 vfMsixControl; uint32 vfBar4Reg; uint32 pfInitvf; uint32 vfNsp; uint32 atsInldQueueDepth; } PcieBlk428Regs; typedef struct PcieBlk800Regs{ #define NUM_PCIE_BLK_800_CTRL_REGS 6 uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS]; uint32 tlL1Ctrl; #define NUM_PCIE_BLK_800_USER_CTRL_REGS 7 uint32 tlUserControl[NUM_PCIE_BLK_800_USER_CTRL_REGS]; uint32 crsClearTimer; uint32 tlFunc345Mask; uint32 tlFunc345Stat; uint32 tlFunc678_mask; uint32 tlFunc678Stat; uint32 funcIntSel; uint32 tlObffCtrl; uint32 tlCtlStat0; uint32 pmStatus0; uint32 pmStatus1; #define NUM_PCIE_BLK_800_TAGS 32 uint32 tlStatus[NUM_PCIE_BLK_800_TAGS]; uint32 tlHdrFcStatus; uint32 tlDataFcStatus; uint32 tlHdrFcconStatus; uint32 tlDataFcconStatus; uint32 tlTargetCreditStatus; uint32 tlCreditAllocStatus; uint32 tlSmlogicStatus; } PcieBlk800Regs; typedef struct PcieBlk1000Regs{ #define NUM_PCIE_BLK_1000_PDL_CTRL_REGS 16 uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS]; uint32 dlattnVec; uint32 dlAttnMask; uint32 dlStatus; /* 0x1048 */ #define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK 0x00002000 #define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT 13 uint32 dlTxChecksum; uint32 dlForcedUpdateGen1; uint32 dlReg_spare0; uint32 dlErrStatistic_ctl; uint32 dlErrStatistic; uint32 reserved[40]; uint32 mdioAddr; uint32 mdioWrData; uint32 mdioRdData; uint32 dlAteTlpHdr_0; uint32 dlAteTlpHdr_1; uint32 dlAteTlpHdr_2; uint32 dlAteTlpHdr_3; uint32 dlAteTlpCfg; uint32 dlAteTlpCtl; uint32 dlRxPFcCl; uint32 dlRxCFcCl; uint32 dlRxAckNack; uint32 dlTxRxSeqnb; uint32 dlTxPFcAl; uint32 dlTxNpFcAl; uint32 regDlSpare; uint32 dlRegSpare; uint32 dlTxRxSeq; uint32 dlRxNpFcCl; } PcieBlk1000Regs; typedef struct PcieBlk1800Regs{ #define NUM_PCIE_BLK_1800_PHY_CTRL_REGS 8 uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS]; #define REG_POWERDOWN_P1PLL_ENA (1<<12) uint32 phyErrorAttnVec; uint32 phyErrorAttnMask; uint32 reserved; uint32 phyCtl8; /* 0x1830 */ uint32 reserved1[243]; uint32 phyReceivedMcpErrors; /* 0x1c00 */ uint32 reserved2[3]; uint32 phyTransmittedMcpErrors;/* 0x1c10 */ uint32 reserved3[3]; uint32 rxFtsLimit; /* 0x1c20 */ uint32 reserved4[46]; uint32 ftsHist; /* 0x1cd8 */ uint32 phyGenDebug; uint32 phyRecoveryHist; #define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS 5 uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS]; #define NUM_PCIE_BLK_1800_PHY_DBG_REGS 11 uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS]; uint32 phyAteLoopbkInfo; /* 0x1d30 */ uint32 reserved5[55]; #define NUM_PCIE_BLK_1800_PHY_DBG_CLK_REGS 4 uint32 phyDbgClk[NUM_PCIE_BLK_1800_PHY_DBG_CLK_REGS]; /* 0x1e10 */ } PcieBlk1800Regs; typedef struct PcieMiscRegs{ uint32 reset_ctrl; /* 4000 Reset Control Register */ uint32 eco_ctrl_core; /* 4004 ECO Core Reset Control Register */ uint32 misc_ctrl; /* 4008 MISC Control Register */ #define PCIE_MISC_CTRL_CFG_READ_UR_MODE (1<<13) uint32 cpu_2_pcie_mem_win0_lo; /* 400c CPU to PCIe Memory Window 0 Low */ #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_ADDR_MASK 0xfff00000 #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_ADDR_SHIFT 20 #define PCIE_MISC_CPU_2_PCIE_MEM_ENDIAN_MODE_NO_SWAP 0 #define PCIE_MISC_CPU_2_PCIE_MEM_ENDIAN_MODE_HALF_WORD_SWAP 1 #define PCIE_MISC_CPU_2_PCIE_MEM_ENDIAN_MODE_HALF_BYTE_SWAP 2 uint32 cpu_2_pcie_mem_win0_hi; /* 4010 CPU to PCIe Memory Window 0 High */ uint32 cpu_2_pcie_mem_win1_lo; /* 4014 CPU to PCIe Memory Window 1 Low */ uint32 cpu_2_pcie_mem_win1_hi; /* 4018 CPU to PCIe Memory Window 1 High */ uint32 cpu_2_pcie_mem_win2_lo; /* 401c CPU to PCIe Memory Window 2 Low */ uint32 cpu_2_pcie_mem_win2_hi; /* 4020 CPU to PCIe Memory Window 2 High */ uint32 cpu_2_pcie_mem_win3_lo; /* 4024 CPU to PCIe Memory Window 3 Low */ uint32 cpu_2_pcie_mem_win3_hi; /* 4028 CPU to PCIe Memory Window 3 High */ uint32 rc_bar1_config_lo; /* 402c RC BAR1 Configuration Low Register */ #define PCIE_MISC_RC_BAR_CONFIG_LO_MATCH_ADDRESS_MASK 0xfff00000 #define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_256MB 0xd #define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MAX 0x11 /* max is 4GB */ uint32 rc_bar1_config_hi; /* 4030 RC BAR1 Configuration High Register */ uint32 rc_bar2_config_lo; /* 4034 RC BAR2 Configuration Low Register */ uint32 rc_bar2_config_hi; /* 4038 RC BAR2 Configuration High Register */ uint32 rc_bar3_config_lo; /* 403c RC BAR3 Configuration Low Register */ uint32 rc_bar3_config_hi; /* 4040 RC BAR3 Configuration High Register */ uint32 msi_bar_config_lo; /* 4044 Message Signaled Interrupt Base Address Low Register */ uint32 msi_bar_config_hi; /* 4048 Message Signaled Interrupt Base Address High Register */ uint32 msi_data_config; /* 404c Message Signaled Interrupt Data Configuration Register */ uint32 rc_bad_address_lo; /* 4050 RC Bad Address Register Low */ uint32 rc_bad_address_hi; /* 4054 RC Bad Address Register High */ uint32 rc_bad_data; /* 4058 RC Bad Data Register */ uint32 rc_config_retry_timeout; /* 405c RC Configuration Retry Timeout Register */ uint32 eoi_ctrl; /* 4060 End of Interrupt Control Register */ uint32 pcie_ctrl; /* 4064 PCIe Control */ uint32 pcie_status; /* 4068 PCIe Status */ uint32 revision; /* 406c PCIe Revision */ uint32 cpu_2_pcie_mem_win0_base_limit;/* 4070 CPU to PCIe Memory Window 0 base/limit */ #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_LIMIT_LIMIT_MASK 0xfff00000 #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_LIMIT_LIMIT_SHIFT 20 #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_LIMIT_BASE_MASK 0x0000fff0 #define PCIE_MISC_CPU_2_PCI_MEM_WIN_LO_BASE_LIMIT_BASE_SHIFT 4 uint32 cpu_2_pcie_mem_win1_base_limit;/* 4074 CPU to PCIe Memory Window 1 base/limit */ uint32 cpu_2_pcie_mem_win2_base_limit;/* 4078 CPU to PCIe Memory Window 2 base/limit */ uint32 cpu_2_pcie_mem_win3_base_limit;/* 407c CPU to PCIe Memory Window 3 base/limit */ uint32 ubus_ctrl; /* 4080 UBUS Control */ uint32 ubus_timeout; /* 4084 UBUS Timeout */ uint32 ubus_bar1_config_remap; /* 4088 UBUS BAR1 System Bus Address Remap Register */ #define PCIE_MISC_UBUS_BAR_CONFIG_OFFSET_MASK 0xfff00000 #define PCIE_MISC_UBUS_BAR_CONFIG_ACCESS_EN 1 uint32 ubus_bar2_config_remap; /* 408c UBUS BAR2 System Bus Address Remap Register */ uint32 ubus_bar3_config_remap; /* 4090 UBUS BAR3 System Bus Address Remap Register */ uint32 ubus_status; /* 4094 UBUS Status */ } PcieMiscRegs; typedef struct PcieMiscPerstRegs{ uint32 perst_eco_ctrl_perst; /* 4100 ECO PCIE Reset Control Register */ uint32 perst_eco_cce_status; /* 4104 Config Copy Engine Status */ } PcieMiscPerstRegs; typedef struct PcieMiscHardRegs{ uint32 hard_eco_ctrl_hard; /* 4200 ECO Hard Reset Control Register */ uint32 hard_pcie_hard_debug; /* 4204 PCIE Hard Debug Register */ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ (1<<23) #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE (1<<1) } PcieMiscHardRegs; typedef struct PcieL2IntrControl{ uint32 Intr2CpuStatus; uint32 Intr2CpuSet; uint32 Intr2CpuClear; uint32 Intr2CpuMask_status; uint32 Intr2CpuMask_set; uint32 Intr2CpuMask_clear; uint32 Intr2PciStatus; uint32 Intr2PciSet; uint32 Intr2PciClear; uint32 Intr2PciMask_status; uint32 Intr2PciMask_set; uint32 Intr2PciMask_clear; } PcieL2IntrControl; typedef struct PcieDMAregs{ uint32 TxFirstDesc_l_AddrList0; uint32 TxFirstDesc_u_AddrList0; uint32 TxFirstDesc_l_AddrList1; uint32 TxFirstDesc_u_AddrList1; uint32 TxSwDescListCtrlSts; uint32 TxWakeCtrl; uint32 TxErrorStatus; uint32 TxList0CurDesc_l_Addr; uint32 TxList0CurDesc_u_Addr; uint32 TxList0CurByteCnt; uint32 TxList1CurDesc_l_Addr; uint32 TxList1CurDesc_u_Addr; uint32 TxList1CurByteCnt; uint32 RxFirstDesc_l_AddrList0; uint32 RxFirstDesc_u_AddrList0; uint32 RxFirstDesc_l_AddrList1; uint32 RxFirstDesc_u_AddrList1; uint32 RxSwDescListCtrlSts; uint32 RxWakeCtrl; uint32 RxErrorStatus; uint32 RxList0CurDesc_l_Addr; uint32 RxList0CurDesc_u_Addr; uint32 RxList0CurByteCnt; uint32 RxList1CurDesc_l_Addr; uint32 RxList1CurDesc_u_Addr; uint32 RxList1CurByteCnt; uint32 Dma_debug_options_reg; uint32 ReadChannelErrorStatus; } PcieDMAregs; typedef struct PcieUBUSL2IntrControl{ uint32 UBUSIntr2CPUStatus; uint32 UBUSIntr2CPUSet; uint32 UBUSIntr2CPUClear; uint32 UBUSIntr2CPUMaskStatus; uint32 UBUSIntr2CPUMaskSet; uint32 UBUSIntr2CPUMaskClear; uint32 UBUSIntr2PCIStatus; uint32 UBUSIntr2PCISet; uint32 UBUSIntr2PCIClear; uint32 UBUSIntr2PCIMaskStatus; uint32 UBUSIntr2PCIMaskSet; uint32 UBUSIntr2PCIMaskClear; } PcieUBUSL2IntrControl; typedef struct PcieIPIL2IntrControl{ uint32 IPIIntr2CPUStatus; uint32 IPIIntr2CPUSet; uint32 IPIIntr2CPUClear; uint32 IPIIntr2CPUMask_status; uint32 IPIIntr2CPUMask_set; uint32 IPIIntr2CPUMask_clear; uint32 IPIIntr2PCIStatus; uint32 IPIIntr2PCISet; uint32 IPIIntr2PCIClear; uint32 IPIIntr2PCIMask_status; uint32 IPIIntr2PCIMask_set; uint32 IPIIntr2PCIMask_clear; } PcieIPIL2IntrControl; typedef struct PcieCpuIntr1Regs{ uint32 status; #define PCIE_CPU_INTR1_IPI_CPU_INTR (1<<8) #define PCIE_CPU_INTR1_PCIE_UBUS_CPU_INTR (1<<7) #define PCIE_CPU_INTR1_PCIE_NMI_CPU_INTR (1<<6) #define PCIE_CPU_INTR1_PCIE_INTR_CPU_INTR (1<<5) #define PCIE_CPU_INTR1_PCIE_INTD_CPU_INTR (1<<4) #define PCIE_CPU_INTR1_PCIE_INTC_CPU_INTR (1<<3) #define PCIE_CPU_INTR1_PCIE_INTB_CPU_INTR (1<<2) #define PCIE_CPU_INTR1_PCIE_INTA_CPU_INTR (1<<1) #define PCIE_CPU_INTR1_PCIE_ERR_ATTN_CPU_INTR (1<<0) uint32 maskStatus; uint32 maskSet; uint32 maskClear; } PcieCpuIntr1Regs; typedef struct PcieExtCfgRegs{ uint32 index; #define PCIE_EXT_CFG_BUS_NUM_MASK 0x0ff00000 #define PCIE_EXT_CFG_BUS_NUM_SHIFT 20 #define PCIE_EXT_CFG_DEV_NUM_MASK 0x000f0000 #define PCIE_EXT_CFG_DEV_NUM_SHIFT 15 #define PCIE_EXT_CFG_FUNC_NUM_MASK 0x00007000 #define PCIE_EXT_CFG_FUNC_NUM_SHIFT 12 uint32 data; uint32 scratch; } PcieExtCfgRegs; typedef struct PcieExtCfgDirectAccess{ uint32 ExtCfgDataExtCfgData_0[1024]; uint32 ExtCfgDataExtCfgData_1023; } PcieExtCfgDirectAccess; #define PCIEH ((volatile uint32 * const) PCIE_0_BASE) #define PCIEH_REGS ((volatile PcieRegs * const) PCIE_0_BASE) #define PCIEH_RC_CFG_VENDOR_REGS ((volatile PcieRcCfgVendorRegs * const) \ (PCIE_0_BASE+0x180)) #define PCIEH_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ (PCIE_0_BASE+0x404)) #define PCIEH_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ (PCIE_0_BASE+0x428)) #define PCIEH_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ (PCIE_0_BASE+0x800)) #define PCIEH_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ (PCIE_0_BASE+0x1000)) #define PCIEH_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ (PCIE_0_BASE+0x1800)) #define PCIEH_MISC_REGS ((volatile PcieMiscRegs * const) \ (PCIE_0_BASE+0x4000)) #define PCIEH_MISC_PERST_REGS ((volatile PcieMiscPerstRegs * const) \ (PCIE_0_BASE+0x4100)) #define PCIEH_MISC_HARD_REGS ((volatile PcieMiscHardRegs * const) \ (PCIE_0_BASE+0x4200)) #define PCIEH_L2_INTR_CTRL_REGS ((volatile PcieL2IntrControl * const) \ (PCIE_0_BASE+0x4300)) #define PCIEH_DMA_REGS ((volatile PcieDMAregs * const) \ (PCIE_0_BASE+0x4400)) #define PCIEH_UBUS_L2_INTR_CTRL_REGS ((volatile PcieUBUSL2IntrControl * const) \ (PCIE_0_BASE+0x8000)) #define PCIEH_IPI_L2_INTR_CTRL_REGS ((volatile PcieIPIL2IntrControl * const) \ (PCIE_0_BASE+0x8100)) #define PCIEH_CPU_INTR1_REGS ((volatile PcieCpuIntr1Regs * const) \ (PCIE_0_BASE+0x8300)) #define PCIEH_PCIE_EXT_CFG_REGS ((volatile PcieExtCfgRegs * const) \ (PCIE_0_BASE+0x8400)) #define PCIEH_EXT_CFG_DIRECT_REGS ((volatile PcieExtCfgDirectAccess * const) \ (PCIE_0_BASE+0x9000)) #define PCIEH_1 ((volatile uint32 * const) PCIE_1_BASE) #define PCIEH_1_REGS ((volatile PcieRegs * const) PCIE_1_BASE) #define PCIEH_1_RC_CFG_VENDOR_REGS ((volatile PcieRcCfgVendorRegs * const) \ (PCIE_1_BASE+0x180)) #define PCIEH_1_BLK_404_REGS ((volatile PcieBlk404Regs * const) \ (PCIE_1_BASE+0x404)) #define PCIEH_1_BLK_428_REGS ((volatile PcieBlk428Regs * const) \ (PCIE_1_BASE+0x428)) #define PCIEH_1_BLK_800_REGS ((volatile PcieBlk800Regs * const) \ (PCIE_1_BASE+0x800)) #define PCIEH_1_BLK_1000_REGS ((volatile PcieBlk1000Regs * const) \ (PCIE_1_BASE+0x1000)) #define PCIEH_1_BLK_1800_REGS ((volatile PcieBlk1800Regs * const) \ (PCIE_1_BASE+0x1800)) #define PCIEH_1_MISC_REGS ((volatile PcieMiscRegs * const) \ (PCIE_1_BASE+0x4000)) #define PCIEH_1_MISC_PERST_REGS ((volatile PcieMiscPerstRegs * const) \ (PCIE_1_BASE+0x4100)) #define PCIEH_1_MISC_HARD_REGS ((volatile PcieMiscHardRegs * const) \ (PCIE_1_BASE+0x4200)) #define PCIEH_1_L2_INTR_CTRL_REGS ((volatile PcieL2IntrControl * const) \ (PCIE_1_BASE+0x4300)) #define PCIEH_1_DMA_REGS ((volatile PcieDMAregs * const) \ (PCIE_1_BASE+0x4400)) #define PCIEH_1_UBUS_L2_INTR_CTRL_REGS ((volatile PcieUBUSL2IntrControl * const) \ (PCIE_1_BASE+0x8000)) #define PCIEH_1_IPI_L2_INTR_CTRL_REGS ((volatile PcieIPIL2IntrControl * const) \ (PCIE_1_BASE+0x8100)) #define PCIEH_1_CPU_INTR1_REGS ((volatile PcieCpuIntr1Regs * const) \ (PCIE_1_BASE+0x8300)) #define PCIEH_1_PCIE_EXT_CFG_REGS ((volatile PcieExtCfgRegs * const) \ (PCIE_1_BASE+0x8400)) #define PCIEH_1_EXT_CFG_DIRECT_REGS ((volatile PcieExtCfgDirectAccess * const) \ (PCIE_1_BASE+0x9000)) #define PCIEH_DEV_OFFSET 0x9000 #define PCIEH_MEM1_BASE 0xd0000000 #define PCIEH_MEM1_SIZE 0x10000000 #define PCIEH_0_MEM1_BASE PCIEH_MEM1_BASE #define PCIEH_0_MEM1_SIZE PCIEH_MEM1_SIZE #define PCIEH_1_MEM1_BASE 0xe0000000 #define PCIEH_1_MEM1_SIZE 0x10000000 #define DDR_UBUS_ADDRESS_BASE 0 /********************** PCIE block end **********************/ /* ** DMA Buffer */ typedef struct DmaDesc { union { struct { uint16 length; /* in bytes of data in buffer */ #define DMA_DESC_USEFPM 0x8000 #define DMA_DESC_MULTICAST 0x4000 #define DMA_DESC_BUFLENGTH 0x0fff uint16 status; /* buffer status */ #define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ #define DMA_EOP 0x4000 /* last buffer in packet */ #define DMA_SOP 0x2000 /* first buffer in packet */ #define DMA_WRAP 0x1000 /* */ #define DMA_PRIO 0x0C00 /* Prio for Tx */ #define DMA_APPEND_BRCM_TAG 0x0200 #define DMA_APPEND_CRC 0x0100 #define USB_ZERO_PKT (1<< 0) // Set to send zero length packet }; uint32 word0; }; uint32 address; /* address of data */ } DmaDesc; /* ** 16 Byte DMA Buffer */ typedef struct DmaDesc16 { union { struct { uint16 length; /* in bytes of data in buffer */ #define DMA_DESC_USEFPM 0x8000 #define DMA_DESC_MULTICAST 0x4000 #define DMA_DESC_BUFLENGTH 0x0fff uint16 status; /* buffer status */ #define DMA_OWN 0x8000 /* cleared by DMA, set by SW */ #define DMA_EOP 0x4000 /* last buffer in packet */ #define DMA_SOP 0x2000 /* first buffer in packet */ #define DMA_WRAP 0x1000 /* */ #define DMA_PRIO 0x0C00 /* Prio for Tx */ #define DMA_APPEND_BRCM_TAG 0x0200 #define DMA_APPEND_CRC 0x0100 #define USB_ZERO_PKT (1<< 0) // Set to send zero length packet }; uint32 word0; }; uint32 address; /* address of data */ uint32 control; #define GEM_ID_MASK 0x001F uint32 reserved; } DmaDesc16; /********************** APM block end **********************/ #define IRQ_BITS 32 typedef struct { uint32 IrqMask; uint32 IrqStatus; } IrqControl_t; /***********************************************************/ /* IC block definition (PERF) */ /***********************************************************/ typedef struct PerfControl { uint32 RevID; /* (00) word 0 */ #define CHIP_ID_SHIFT 0x4 #define CHIP_ID_MASK (0xf << CHIP_ID_SHIFT) #define REV_ID_MASK 0xf uint32 Unused[3]; /* (04) word 1 */ uint32 TimerControl; /* (10) word 4 */ #define SOFT_RESET_0 0x00000001 // viper watchdog #define SOFT_RESET_1 0x00000002 // PMC watchdog uint32 RsvdIrqMask0; /* (14) word 5 */ uint32 RsvdIrqStatus0; /* (18) word 6 */ uint32 RsvdrqMask1; /* (1c) word 7 */ uint32 RsvdIrqStatus1; /* (20) word 8 */ uint32 RsvdIrqMask2; /* (24) word 9 */ uint32 RsvdIrqStatus2; /* (28) word 10 */ uint32 unused2c; /* (2c) word 11 */ uint32 PeriphIrqMask0; /* (30) word 12 */ #define WAN_GPON_TX_IRQ (1 << 31) #define WAN_GPON_RX_IRQ (1 << 30) #define WAN_EPON_IRQ (1 << 29) #define WAN_NCO_8KHZ_IRQ (1 << 28) #define RDP_UBUS_ERR_PORT_IRQ (1 << 27) #define RDP_UBUS_ERROR_IRQ (1 << 26) #define RDP_RUNNER_IRQ_OFFSET 16 #define RDP_RUNNER_IRQ_MASK 0x3FF00000 #define EXT_IRQ (1 << 15) #define DSCRAM_RNG_READY_IRQ (1 << 10) #define DSCRAM_KEYDONE_IRQ (1 << 9) #define UART2_IRQ (1 << 8) #define UBUS_REQOUT_ERR_IRQ (1 << 7) #define PERIPH_ERROR_DET_IRQ (1 << 6) #define HSSPI_IRQ (1 << 5) #define I2CIRQ (1 << 4) #define NAND_FLASH_IRQ (1 << 3) #define UART1_IRQ (1 << 2) #define UART_IRQ (1 << 1) #define TIMRIRQ (1 << 0) uint32 PeriphIrqStatus0; /* (34) word 13 */ uint32 PeriphIrqMask1; /* (38) word 14 */ uint32 PeriphIrqStatus1; /* (3c) word 15 */ union { struct { uint32 PeriphIrqMask2; /* (40) word 16 */ uint32 PeriphIrqStatus2; /* (44) word 17 */ uint32 PeriphIrqMask3; /* (48) word 18 */ uint32 PeriphIrqStatus3; /* (4c) word 19 */ }; IrqControl_t IrqControl[2]; /* (40) (48)*/ }; uint32 IopIrqMask0; /* (50) word 20 */ #define PMCIRQ_TP0 (1 << 5) #define PMCIRQ_TP1 (1 << 13) uint32 IopIrqStatus0; /* (54) word 21 */ uint32 IopIrqMask1; /* (58) word 22 */ uint32 IopIrqStatus1; /* (5c) word 23 */ uint32 Rsvd0IrqSense; /* (60) word 24 */ uint32 PeriphIrqSense; /* (64) word 25 */ uint32 IopIrqSense; /* (68) word 26 */ uint32 ExtIrqCfg; /* (6c) word 27 */ #define EI_SENSE_SHFT 0 #define EI_STATUS_SHFT 6 #define EI_CLEAR_SHFT 6 #define EI_MASK_SHFT 12 #define EI_INSENS_SHFT 18 #define EI_LEVEL_SHFT 24 #define EI_STATUS_MASK 0xfc0 #define EI_CLEAR_MASK EI_STATUS_MASK #define EI_MASK_MASK 0x3f000 uint32 ExtIrqCfg1; /* (70) word 28 */ uint32 ExtIrqCfg2; /* (74) word 29 */ uint32 IrqOutMask; /* (78) word 30 */ #define SYSIRQ_OUT_IRQ0_IOP (1 << 0) #define SYSIRQ_OUT_IRQ1_IOP (1 << 1) #define SYSIRQ_OUT_IRQ0_PERIPH (1 << 2) #define SYSIRQ_OUT_IRQ1_PERIPH (1 << 3) #define SYSIRQ_OUT_IRQ2_PERIPH (1 << 4) #define SYSIRQ_OUT_IRQ0_DOCSIS (1 << 5) #define SYSIRQ_OUT_IRQ1_DOCSIS (1 << 6) #define SYSIRQ_OUT_IRQ2_DOCSIS (1 << 7) #define TESTBUS_OUT_IRQ0_IOP (1 << 8) #define TESTBUS_OUT_IRQ1_IOP (1 << 9) #define TESTBUS_OUT_IRQ0_PERIPH (1 << 10) #define TESTBUS_OUT_IRQ1_PERIPH (1 << 11) #define TESTBUS_OUT_IRQ2_PERIPH (1 << 12) #define TESTBUS_OUT_IRQ0_DOCSIS (1 << 13) #define TESTBUS_OUT_IRQ1_DOCSIS (1 << 14) #define TESTBUS_OUT_IRQ2_DOCSIS (1 << 15) #define UBUSCAPTURE_OUT_IRQ0_IOP (1 << 16) #define UBUSCAPTURE_OUT_IRQ1_IOP (1 << 17) #define UBUSCAPTURE_OUT_IRQ0_PERIPH (1 << 18) #define UBUSCAPTURE_OUT_IRQ1_PERIPH (1 << 19) #define UBUSCAPTURE_OUT_IRQ2_PERIPH (1 << 20) #define UBUSCAPTURE_OUT_IRQ0_DOCSIS (1 << 21) #define UBUSCAPTURE_OUT_IRQ1_DOCSIS (1 << 22) #define UBUSCAPTURE_OUT_IRQ2_DOCSIS (1 << 23) #define PCIE_OUT_IRQ0_IOP (1 << 24) #define PCIE_OUT_IRQ1_IOP (1 << 25) #define PCIE_OUT_IRQ0_PERIPH (1 << 26) #define PCIE_OUT_IRQ1_PERIPH (1 << 27) #define PCIE_OUT_IRQ2_PERIPH (1 << 28) #define PCIE_OUT_IRQ0_DOCSIS (1 << 29) #define PCIE_OUT_IRQ1_DOCSIS (1 << 30) #define PCIE_OUT_IRQ2_DOCSIS (1 << 31) uint32 diagSelControl; /* (7c) word 31 */ #define DIAG_HI_SEL_MASK 0x0000ff00 #define DIAG_HI_SEL_SHFT 8 #define DIAG_LO_SEL_MASK 0x000000ff #define DIAG_LO_SEL_SHFT 0 #define DIAG_CLK_PHS_MASK 0x003f0000 #define DIAG_CLK_PHS_SHIFT 16 #define DIAG_LO_ENABLED (1 << 24) #define DIAG_CLK_LO_ENABLED (1 << 25) #define DIAG_HI_ENABLED (1 << 26) #define DIAG_CLK_HI_ENABLED (1 << 27) #define DIAG_UBUS_OBS_ENABLED (1 << 28) #define DIAG_PINMUX_OVERRIDE (1 << 29) #define DIAG_SPI_OVERRIDE (1 << 31) uint32 diagReadBack; /* (80) word 32 */ uint32 diagReadBackHi; /* (84) word 33 */ uint32 diagMiscControl; /* (88) word 34 */ uint32 pcie_softResetB_lo; /* (8c) word 35 */ #define SOFT_RST_PCIE1_CORE (1 << 1) #define SOFT_RST_PCIE0_CORE (1 << 0) uint32 mdio_irq; /* (90) word 36 */ #define MDIO_EXT_DONE_IRQ (1 << 0) #define MDIO_EXT_ERR_IRQ (1 << 1) #define EGPHY_EXT_DONE_IRQ (1 << 2) #define EGPHY_EXT_ERR_IRQ (1 << 3) #define MDIO_SATA_DONE_IRQ (1 << 4) #define MDIO_SATA_ERR_IRQ (1 << 5) #define MDIO_AE_DONE_IRQ (1 << 6) #define MDIO_AE_ERR_IRQ (1 << 7) #define MDIO_EXT_DONE_IEN (1 << 8) #define MDIO_EXT_ERR_IEN (1 << 9) #define EGPHY_EXT_DONE_IEN (1 << 10) #define EGPHY_EXT_ERR_IEN (1 << 11) #define MDIO_SATA_DONE_IEN (1 << 12) #define MDIO_SATA_ERR_IEN (1 << 13) #define MDIO_AE_DONE_IEN (1 << 14) #define MDIO_AE_ERR_IEN (1 << 15) uint32 dsramIrqStatus; /* (94) word 37 */ uint32 ext_irq_muxsel0; /* (98) word 38 */ #define EXT_IRQ5_SEL 0x3E000000 #define EXT_IRQ4_SEL 0x01F00000 #define EXT_IRQ3_SEL 0x000F8000 #define EXT_IRQ2_SEL 0x00007C00 #define EXT_IRQ1_SEL 0x000002E0 #define EXT_IRQ0_SEL 0x0000001F #define EXT_IRQ_MASK_LOW 0x0000001F #define EXT_IRQ_OFF_LOW 5 uint32 IntPeriphIrqStatus; /* (9C) word 39 */ #define DIAG_IRQ 0x00000100 #define RBUS_ERR_IRQ 0x00000080 #define BRIDGE_TO_ERR_IRQ 0x00000040 #define REQOUT_PLEN_ERR_IRQ 0x00000020 #define U2R_REPOUT_ERR_IRQ 0x00000010 #define BRIDGE_UBUS_ERR_IRQ 0x00000008 #define DEVTIMEOUT_IRQ 0x00000004 #define ERROR_PORT_IRQ 0x00000002 #define BAD_BOOT_LOC_IRQ 0x00000001 uint32 IntPeriphIrqMask; /* (A0) word 40 */ uint32 spare[6]; uint32 soft_no_watchdog_reset_b; /* (BC) word 47 */ }PerfControl; #define PERF ((volatile PerfControl * const) PERF_BASE) /********************** IC block end ***********************/ /***********************************************************/ /* Timer block definition(PERF) */ /***********************************************************/ typedef struct Timer { uint16 unused0; byte TimerMask; #define TIMER0EN 0x01 #define TIMER1EN 0x02 #define TIMER2EN 0x04 byte TimerInts; #define TIMER0 0x01 #define TIMER1 0x02 #define TIMER2 0x04 #define WATCHDOG0 0x08 #define WATCHDOG WATCHDOG0 /* compatible with other chips */ #define WATCHDOG1 0x10 uint32 TimerCtl0; uint32 TimerCtl1; uint32 TimerCtl2; #define TIMERENABLE 0x80000000 #define RSTCNTCLR 0x40000000 uint32 TimerCnt0; uint32 TimerCnt1; uint32 TimerCnt2; #define TIMER_COUNT_MASK 0x3FFFFFFF uint32 TimerMemTm; //unused uint32 TimerEphyTestCtrl; } Timer; #define TIMER ((volatile Timer * const) TIMR_BASE) /********************** Timer block end ********************/ /***********************************************************/ /* Watchdog block definition(PERF) */ /***********************************************************/ typedef struct Watchdog { uint32 WD0DefCount; /* Write 0xff00 0x00ff to Start timer * Write 0xee00 0x00ee to Stop and re-load default count * Read from this register returns current watch dog count */ uint32 WD0Ctl; /* Number of 50-MHz ticks for WD Reset pulse to last */ uint32 WD0ResetCount; uint32 WD1DefCount; uint32 WD1Ctl; uint32 WD1ResetCount; } Watchdog; #define WDTIMER ((volatile Watchdog * const) WATCHDOG_BASE) /********************** Watchdog block end *****************/ /***********************************************************/ /* NAND Intr block definition(PERF) */ /***********************************************************/ typedef struct NandIntrReg { uint32 NandInt; // nand flash Interrupt uint32 NandIntBase_0; // nand flash Base Address 0 uint32 NandIntBase_1; // nand flash Base Address 1 uint32 NandIntSoftnowatchdogreset; //Soft No Watchdog Reset Register } NandIntrReg; #define NANINTR ((volatile NandIntrReg * const) NAND_INTR_BASE) /********************** NAND Intr block end *****************/ /***********************************************************/ /* GPIO block definition(PERF) */ /***********************************************************/ typedef struct GpioControl { /* High in bit location enables output */ uint32 GPIODir_low; // 0 uint32 GPIODir_mid0; // 4 uint32 GPIODir_mid1; // 8 uint32 reserved_GPIODir[7];// c uint32 unused0; // 24 uint32 GPIOData_low; // 2C; uint32 GPIOData_mid0; // 30 : uint32 GPIOData_mid1; // 34: uint32 resered_GPIOData[7];// 38 uint32 unused1; // 54; #define USB1_PULLUP (1 << 23) #define USB1_PULLDOWN (1 << 22) #define USB1_DISABLE_INPUT (1 << 21) #define USB1_HYS_ENABLE (1 << 20) #define USB0_PULLUP (1 << 19) #define USB0_PULLDOWN (1 << 18) #define USB0_DISABLE_INPUT (1 << 17) #define USB0_HYS_ENABLE (1 << 16) uint32 PadControl; // 58: uint32 SpiSlaveCfg; // 5C uint32 reserved_diag1[3]; // 60 uint32 TestControl; // 6C uint32 USimControl; // 70 uint32 reserved_diag2[8]; // 74 uint32 strap_bus; // 94 #define MISC_STRAP_BUS_BOOT_SEL_MASK 0x000003800 #define MISC_STRAP_BUS_BOOT_SEL_SHIFT 11 #define MISC_STRAP_SPI_3BYTE_ADDR_MASK 0x4 #define MISC_STRAP_SPI_4BYTE_ADDR_MASK 0x5 #define MISC_STRAP_BUS_SPI_NAND_BOOT 1 #define MISC_STRAP_BUS_BOOT_CFG_MASK (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_PAGE_SIZE_SHIFT 9 #define MISC_STRAP_BUS_PAGE_SIZE_MASK (0x3 << MISC_STRAP_BUS_PAGE_SIZE_SHIFT) uint32 strap_override; // 98 uint32 qam_pll_status; // 9C - reserved uint32 strap_out_bus; // A0 uint32 led_input_xor; // A4 uint32 reserved_diag3[12]; // A8 uint32 ddr_pll_override; // D8 uint32 diag_kick_timer; // DC: uint32 DieRevID; // E0: #define DIEID 0x00000047 uint32 spi_master_control; // E4 uint32 clk_rst_misc; // E8 - reserved uint32 dg_control; // EC #define DG_IRQ_SHIFT 6 #define DG_TRIM_SHIFT 3 #define DG_CTRL_SHIFT 1 #define DG_EN_SHIFT 0 uint32 reserved_diag4[36]; // F0 uint32 IRQ_out_mask1; // 180 uint32 sdram_space; // 184 uint32 ddr_16_en; // 188 uint32 memc_phy_control; // 18C uint32 memc_control; // 190 uint32 port_reg_tpIn1; // 194 uint32 port_reg_tpIn2; // 198 uint32 port_block_en1; // 19C uint32 port_block_en2; // 1A0 uint32 port_block_data1; // 1A4 uint32 port_block_data2; // 1A8 #define PINMUX_DATA_SHIFT 12 #define PINMUX_0 0 #define PINMUX_1 1 #define PINMUX_2 2 #define PINMUX_3 3 #define PINMUX_4 4 #define PINMUX_5 5 #define PINMUX_6 6 #define PINMUX_7 7 #define PINMUX_8 8 #define PINMUX_14 14 #define PINMUX_15 15 #define PINMUX_16 16 #define PINMUX_17 17 #define PINMUX_18 18 #define PINMUX_35 35 #define PINMUX_36 36 #define PINMUX_37 37 #define PINMUX_39 39 #define PINMUX_SIM_FUNC 3 #define PINMUX_GPIO_FUNC 5 #define PINMUX_MSPI PINMUX_1 #define PINMUX_PCM PINMUX_1 #define PINMUX_APM PINMUX_1 #define PINMUX_ZAR_IF_D PINMUX_2 #define PINMUX_ZAR_IF_E PINMUX_2 #define PINMUX_ZAR_IF_C PINMUX_3 #define PINMUX_GPIO PINMUX_5 #define PINMUX_SIM_DAT PINMUX_6 #define PINMUX_ZAR_IF_A PINMUX_7 #define PINMUX_ZAR_IF_B PINMUX_7 #define PINMUX_SIM_CLK PINMUX_7 #define PINMUX_SIM_PRESENCE PINMUX_8 #define PINMUX_SIM_A_VCC_EN_PIN PINMUX_14 #define PINMUX_SIM_A_VCC_VOL_SEL_PIN PINMUX_15 #define PINMUX_SIM_A_VCC_RST_PIN PINMUX_16 #define PINMUX_SIM_A_VPP_EN_PIN PINMUX_17 #define PINMUX_SIM_B_VCC_EN_PIN PINMUX_35 #define PINMUX_SIM_B_VCC_VOL_SEL_PIN PINMUX_36 #define PINMUX_SIM_B_VCC_RST_PIN PINMUX_37 #define PINMUX_SIM_B_VPP_EN_PIN PINMUX_39 uint32 port_command; // 1AC #define LOAD_MUX_REG_CMD 0x21 } GpioControl; #define GPIO ((volatile GpioControl * const) GPIO_BASE) #define GPIO_NUM_MAX 74 #define USIM_CTRL &GPIO->USimControl #define GPIO_NUM_TO_MASK(X) ((uint32)1 << (X)) /********************** GPIO block end ********************/ /***********************************************************/ /* PageControl block definition(PERF) */ /***********************************************************/ typedef struct PageControl { uint32 AltBootConfig; #define ALT_BOOT_MASK 0xFFF00000 #define ALT_BOOT_EN (1 << 19) } PageControl; #define PGCTRL ((volatile PageControl * const) PG_CONTROL_PER) /********************** PageControl block end **************/ /***********************************************************/ /* PLL Control block definition(PERF) */ /***********************************************************/ typedef struct PLLControl { uint32 PllControlReg; uint32 PllControlOsc; #define PLL_DIV2_SEL_MASK (1 << 22) #define PWR_DN_CML (1 << 21) #define PWR_SAVE (1 << 20) } PLLControl; #define PLLCTRL ((volatile PLLControl * const) PLL_CONTROL_REG) /********************** PLL Control block end **************/ /***********************************************************/ /* Perf ext intr block definition(PERF) */ /***********************************************************/ typedef struct ExtIntr { uint32 ExtRsvd0irqmask3; //rsVD0 Interrupt Mask Register3 uint32 ExtRsvd0irqstatus3; //RSVD0 Interrupt Status Register3 uint32 ExtIopirqmask2; //iop Interrupt Mask Register2 uint32 ExtIopirqstatus2; //ioP Interrupt Status Register2 uint32 ExtRsvd0irqmask0_2; //RSVD0 Interrupt Mask Register0_2 uint32 ExtRsvd0irqstatus0_2; //RSVD0 Interrupt Status Register0_2 uint32 ExtRsvd0irqmask1_2; //RSVD0 Interrupt Mask Register1_2 uint32 ExtRsvd0irqstatus1_2; //RSVD0 Interrupt Status Register1_2 uint32 ExtRsvd0irqmask2_2; //RSVD0 Interrupt Mask Register2_2 uint32 ExtRsvd0irqstatus2_2; //RSVD0 Interrupt Status Register2_2 uint32 ExtRsvd0irqmask3_2; //RSVD0 Interrupt Mask Register3_2 uint32 ExtRsvd0irqstatus3_2; //RSVD0 Interrupt Status Register3_2 uint32 ExtRsvd0irqsense2; //rSVD0 Interrupt Sense Register2 uint32 ExtPeriphirqmask0_2; //Periph Interrupt Mask Register0_2 uint32 ExtPeriphirqstatus0_2; //Periph Interrupt Status Register0_2 uint32 ExtPeriphirqmask1_2; //Periph Interrupt Mask Register1_2 uint32 ExtPeriphirqstatus1_2; //Periph Interrupt Status Register1_2 union { struct { uint32 ExtPeriphirqmask2_2; //Periph Interrupt Mask Register2_2 uint32 ExtPeriphirqstatus2_2; //Periph Interrupt Status Register2_2 uint32 ExtPeriphirqmask3_2; //RSVD0 Interrupt Mask Register3_2 uint32 ExtPeriphirqstatus3_2; //Periph Interrupt Status Register3_2 }; IrqControl_t IrqControl[2]; /* (40) (48)*/ }; uint32 ExtPeriphirqsense2; //Periph Interrupt Sense Register2 } ExtIntr; #define PERFEXT ((volatile ExtIntr * const) PERF_EXT_INT) /********************** Perf ext intr block end **************/ /***********************************************************/ /* Dbg perf block definition(PERF) */ /***********************************************************/ typedef struct DebugPerf { uint32 Dbg_Features; // Features Register for Software debug uint32 Dbg_SoftwareDebug1; // Software debug register 1 uint32 Dbg_SoftwareDebug2; // Software debug register 2 uint32 Dbg_SoftwareDebug3; // Software debug register 3 uint32 Dbg_SoftwareDebug4; // Software debug register 4 uint32 Dbg_extirqmuxsel0_1; // ExtIrq Mux select 1 #define EXT_IRQ_MASK_HIGH 0x000001E0 #define EXT_IRQ_OFF_HIGH 4 } DebugPerf; #define DBGPERF ((volatile DebugPerf * const) DBG_PERF) /********************** Dbg perf block end **************/ /***********************************************************/ /* UART block definition(PERF) */ /***********************************************************/ typedef struct Uart { byte unused0; byte control; #define BRGEN 0x80 /* Control register bit defs */ #define TXEN 0x40 #define RXEN 0x20 #define LOOPBK 0x10 #define TXPARITYEN 0x08 #define TXPARITYEVEN 0x04 #define RXPARITYEN 0x02 #define RXPARITYEVEN 0x01 byte config; #define XMITBREAK 0x40 #define BITS5SYM 0x00 #define BITS6SYM 0x10 #define BITS7SYM 0x20 #define BITS8SYM 0x30 #define ONESTOP 0x07 #define TWOSTOP 0x0f /* 4-LSBS represent STOP bits/char * in 1/8 bit-time intervals. Zero * represents 1/8 stop bit interval. * Fifteen represents 2 stop bits. */ byte fifoctl; #define RSTTXFIFOS 0x80 #define RSTRXFIFOS 0x40 #define RSTTXCHARDONE 0x20 #define UART_RXTIMEOUT 0x1f /* 5-bit TimeoutCnt is in low bits of this register. * This count represents the number of characters * idle times before setting receive Irq when below threshold */ uint32 baudword; /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate */ byte txf_levl; /* Read-only fifo depth */ byte rxf_levl; /* Read-only fifo depth */ byte fifocfg; /* Upper 4-bits are TxThresh, Lower are * RxThreshold. Irq can be asserted * when rx fifo> thresh, txfifoBrcmBits[((x)/32)] >> ((x) % 32)) & 1) #define OTP_GET_USER_BIT(x) ((OTP->UserBits >> ((x) % 32)) & 1) /* Extract manufacturer ID from OTP bits */ #define OTP_GET_MFG_ID() ((OTP->dbgPER & 0x0F000000) >> 24) #define MFG_ID_TSMC 0x0 #define MFG_ID_UMC 0xA #endif /* __ASSEMBLER__ */ /* Bootrom specifics */ #define OTP_SHADOW_ADDR_BTRM_ENABLE_BTRM_ROW 0x4c #define OTP_BRCM_BTRM_BOOT_ENABLE_ROW OTP_SHADOW_ADDR_BTRM_ENABLE_BTRM_ROW #define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT 28 #define OTP_BRCM_BTRM_BOOT_ENABLE_MASK (0x1 << OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT) #define OTP_SHADOW_ADDR_BTRM_ENABLE_CUST_ROW 0x60 #define OTP_CUST_BTRM_BOOT_ENABLE_ROW OTP_SHADOW_ADDR_BTRM_ENABLE_BTRM_ROW #define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT 4 #define OTP_CUST_BTRM_BOOT_ENABLE_MASK (0x1 << OTP_CUST_BTRM_BOOT_ENABLE_SHIFT) #define OTP_SHADOW_ADDR_MARKET_ID_CUST_ROW 0x6c #define OTP_MFG_MRKTID_OTP_BITS_SHIFT 0 #define OTP_MFG_MRKTID_OTP_BITS_MASK (0xffff << OTP_MFG_MRKTID_OTP_BITS_SHIFT) #define OTP_CUST_MFG_MRKTID_ROW OTP_SHADOW_ADDR_MARKET_ID_CUST_ROW #define OTP_CUST_MFG_MRKTID_SHIFT 0 #define OTP_CUST_MFG_MRKTID_MASK (0xffff << OTP_CUST_MFG_MRKTID_SHIFT) #define OTP_CUST_OP_MRKTID_ROW OTP_SHADOW_ADDR_MARKET_ID_CUST_ROW #define OTP_CUST_OP_MRKTID_SHIFT 16 #define OTP_CUST_OP_MRKTID_MASK (0xffff << OTP_CUST_OP_MRKTID_SHIFT) #ifndef __ASSEMBLER__ /* WAN Block */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_WAN_CFG 0xb30f8000 /* WAN_CFG Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_SATA_CFG 0xb30f8004 /* SATA_CFG Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_SATA_STAT 0xb30f8008 /* SATA_STAT Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_PCS_CFG 0xb30f800c /* PCS_CFG Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_PCS_STAT 0xb30f8010 /* PCS_STAT Register */ #define ESERDES_STAT_WAN_GPIO_PER_REG 0xb4e001e0 /* ESERDES_STAT_WAN_GPIO_PER_REG */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_SW_RESET 0xb30f8014 /* GPON_GEARBOX_SW_RESET Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0 0xb30f8018 /* GPON_GEARBOX_FIFO_CFG_0 Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1 0xb30f801c /* GPON_GEARBOX_FIFO_CFG_1 Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_2 0xb30f8020 /* GPON_GEARBOX_FIFO_CFG_2 Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_FIFO_STATUS 0xb30f8024 /* GPON_GEARBOX_FIFO_STATUS Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1 0xb30f8028 /* GPON_GEARBOX_PATTERN_CFG1 Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2 0xb30f802c /* GPON_GEARBOX_PATTERN_CFG2 Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_BURST_CFG 0xb30f8030 /* GPON_GEARBOX_BURST_CFG Register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_GPON_GEARBOX_BURST_STATUS 0xb30f8034 /* GPON_GEARBOX_BURST_STATUS Register */ #define PERIPH_BLOCK_PLLCNTRL_PER_OSC_CTRL 0xB4E002C4 /*PERIPH_BLOCK.PLLNTRL_PER_OSC_CTRL register */ #define WAN_MISC_RDP_WAN_TOP_WAN_MISC_EARLY_TXEN_CFG 0xb30f8038 /* EARLY_TXEN_CFG Register */ #endif #ifdef __cplusplus } #endif #endif