/* <:copyright-BRCM:2015:DUAL/GPL:standard Copyright (c) 2015 Broadcom All Rights Reserved This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License, version 2, as published by the Free Software Foundation (the "GPL"). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. :> */ #ifndef __BCM6848_MAP_PART_H #define __BCM6848_MAP_PART_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #if !defined(REG_BASE) #define REG_BASE 0xb0000000 #endif #define CHIP_FAMILY_ID_HEX 0x6848 #define MEMC_BASE (REG_BASE + 0x00014000) #define USBD_BASE (REG_BASE + 0x00009000) /* USB 2.0 device control */ #define USB_DMA_BASE (REG_BASE + 0x00009800) /* USB 2.0 device DMA regiseters */ #define USBH_BASE (REG_BASE + 0x0000c000) /* USBH control block*/ #define USBH_CFG_BASE (REG_BASE + 0x0000c200) /* Since USB is faked as PCIE interface, pcie driver needs physical address * for EHCI & OHCI */ #ifdef __KERNEL__ #define USB_EHCI_BASE 0x1000c300 /* USB host registers */ #define USB_OHCI_BASE 0x1000c400 /* USB host registers */ #endif #define PCM_BASE (REG_BASE + 0x00010c00) /* PCM registers */ #define PCM_DMA_BASE (REG_BASE + 0x00011000) /* PCM DMA registers */ #define PMC_BASE (REG_BASE + 0x00200000) /* PMC register */ #define PROC_MON_BASE (REG_BASE + 0x00280000) /* Process Monitor register */ #define PCIE_BASE (REG_BASE + 0x00020000) #define PERF_BASE (REG_BASE + 0x00800000) /* chip control */ #define GENINT_BASE (REG_BASE + 0x00800000) /* general interrupt controller */ #define INT0_BASE (REG_BASE + 0x00800100) /* interrupts */ #define INT1_BASE (REG_BASE + 0x00800200) /* unused in 6848 */ #define INT2_BASE (REG_BASE + 0x00800300) /* unused in 6848 */ #define TIMR_BASE (REG_BASE + 0x00800400) /* timer registers */ #define GPIO_BASE (REG_BASE + 0x00800500) /* gpio registers */ #define UART_BASE (REG_BASE + 0x00800640) /* uart 0 registers */ #define UART1_BASE (REG_BASE + 0x00800660) /* uart 1 registers */ #define LED_BASE (REG_BASE + 0x00800800) /* LED control registers */ #define JTAG_OTP_BASE (REG_BASE + 0x00800e00) /* OTP control registers */ #define HSSPIM_BASE (REG_BASE + 0x00801000) /* High-Speed SPI registers */ #define NAND_REG_BASE (REG_BASE + 0x00801800) /* nand control register */ #define NAND_INTR_BASE (REG_BASE + 0x00802000) /* nand interrupt control */ #define NAND_CACHE_BASE (REG_BASE + 0x00801C00) /* nand flash cache buffer */ #define MDIO_BASE (REG_BASE + 0x008020c0) /* MDIO controller registers */ #define I2C_BASE (REG_BASE + 0x00802100) /* I2C interface register*/ #define MISC_BASE (REG_BASE + 0x00802600) /* Miscellaneous Registers */ #define USIM_BASE (REG_BASE + 0x00854000) /* SIM CARD interface registers*/ #define TOP_CNTRL_BASE (REG_BASE + 0x0085a000) /* chip top control registers*/ #define PSRAM_BASE 0xb30a0000 #define PSRAM_BASE_KSEG0 0x930a0000 #define PSRAM_SIZE 0x20000 /* 128KB */ #ifndef __ASSEMBLER__ /* ** Peripheral Controller */ #define IRQ_BITS 64 typedef struct { uint64 IrqMask; uint64 ExtIrqMask; } IrqControl_t; typedef struct PerfControl { uint32 RevID; /* (00) word 0 */ #define CHIP_ID_SHIFT 12 #define CHIP_ID_MASK (0xffff << CHIP_ID_SHIFT) #define REV_ID_MASK 0xff uint32 ExtIrqCfg; /* (04) word 1 */ uint32 ExtIrqSts; /* (08) word 2 */ uint32 Ext1IrqCfg; /* (0c) word 3 */ uint32 Ext1IrqSts; /* (10) word 4 */ #define EI_CLEAR_SHFT 0 #define EI_SENSE_SHFT 8 #define EI_INSENS_SHFT 16 #define EI_LEVEL_SHFT 24 #define EI_STATUS_SHFT 0 #define EI_MASK_SHFT 16 uint64 IrqOutMask; /* (14) word 5 */ uint64 ExtIrqMux; /* (1c) word 7 */ uint32 IrqPeriphStatus; /* (24) */ uint32 IrqPeriphMask; /* (28) */ uint32 reserved[8]; /* (2c - 48) */ uint32 reserved1[45]; /* (4c - fc) */ uint64 sense[2]; /* (100 - 10c) */ IrqControl_t IrqControl[4]; /* (110 - 14c) */ uint64 IrqStatus; /* (150) */ uint64 ExtIrqStatus; /* (158) */ } __attribute__((packed, aligned(4))) PerfControl; #define PERF ((volatile PerfControl * const) PERF_BASE) /* ** Timer */ typedef struct Timer { uint32 TimerCtl0; uint32 TimerCtl1; uint32 TimerCtl2; uint32 TimerCtl3; #define TIMERENABLE 0x80000000 #define RSTCNTCLR 0x40000000 uint32 TimerCnt0; uint32 TimerCnt1; uint32 TimerCnt2; uint32 TimerCnt3; #define TIMER_COUNT_MASK 0x3FFFFFFF uint32 TimerMask; #define TIMER0EN 0x01 #define TIMER1EN 0x02 #define TIMER2EN 0x04 #define TIMER3EN 0x08 uint32 TimerInts; #define TIMER0 0x01 #define TIMER1 0x02 #define TIMER2 0x04 #define TIMER3 0x08 #define WATCHDOG 0x10 uint32 WatchDogDefCount; /* Write 0xff00 0x00ff to Start timer * Write 0xee00 0x00ee to Stop and re-load default count * Read from this register returns current watch dog count */ uint32 WatchDogCtl; /* Number of 50-MHz ticks for WD Reset pulse to last */ uint32 WDResetCount; uint32 SoftRst; #define SOFT_RESET 0x00000001 // 0 uint32 ResetStatus; #define PCIE_RESET_STATUS 0x10000000 #define SW_RESET_STATUS 0x20000000 #define HW_RESET_STATUS 0x40000000 #define POR_RESET_STATUS 0x80000000 #define RESET_STATUS_MASK 0xF0000000 uint32 ResetReason; #define SW_INI_RESET 0x00000001 uint32 spare[3]; } Timer; #define TIMER ((volatile Timer * const) TIMR_BASE) /* ** UART */ typedef struct UartChannel { byte unused0; byte control; #define BRGEN 0x80 /* Control register bit defs */ #define TXEN 0x40 #define RXEN 0x20 #define LOOPBK 0x10 #define TXPARITYEN 0x08 #define TXPARITYEVEN 0x04 #define RXPARITYEN 0x02 #define RXPARITYEVEN 0x01 byte config; #define XMITBREAK 0x40 #define BITS5SYM 0x00 #define BITS6SYM 0x10 #define BITS7SYM 0x20 #define BITS8SYM 0x30 #define ONESTOP 0x07 #define TWOSTOP 0x0f /* 4-LSBS represent STOP bits/char * in 1/8 bit-time intervals. Zero * represents 1/8 stop bit interval. * Fifteen represents 2 stop bits. */ byte fifoctl; #define RSTTXFIFOS 0x80 #define RSTRXFIFOS 0x40 /* 5-bit TimeoutCnt is in low bits of this register. * This count represents the number of characters * idle times before setting receive Irq when below threshold */ uint32 baudword; /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate */ byte txf_levl; /* Read-only fifo depth */ byte rxf_levl; /* Read-only fifo depth */ byte fifocfg; /* Upper 4-bits are TxThresh, Lower are * RxThreshold. Irq can be asserted * when rx fifo> thresh, txfifo> 5) & 0x0f) : (0)) #define GPIO_NUM_TO_MASK(X) (((X & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X & BP_GPIO_NUM_MASK) & 0x1f)) : (0)) #define GPIO_NUM_TO_ARRAY_SHIFT(X) (((X) & BP_GPIO_NUM_MASK) & 0x1f) /* ** Misc Register Set Definitions. */ typedef struct Misc { uint32 miscStrapBus; /* 0x00 */ #define MISC_STRAP_BUS_BOOT_SEL_SHIFT 0 #define MISC_STRAP_BUS_BOOT_SEL_MASK (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NOR (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NAND (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_CLOCK_SEL_SHIFT 6 #define MISC_STRAP_CLOCK_SEL_MASK (0x7 << MISC_STRAP_CLOCK_SEL_SHIFT) #define MISC_STRAP_CLOCK_SEL_400 0x2 #define MISC_STRAP_DDR_FREQ_SHIFT 12 #define MISC_STRAP_DDR_FREQ_MASK (0x3 << MISC_STRAP_DDR_FREQ_SHIFT) #define MISC_STRAP_DDR_533MHZ_MASK 0x3 #define MISC_STRAP_DDR_400MHZ_MASK 0x1 #define MISC_STRAP_DDR_333MHZ_MASK 0x2 #define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT 9 #define MISC_STRAP_BUS_PMC_ROM_BOOT (0x1 << MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT) #define MISC_STRAP_PMC_BOOT_AVS 11 #define MISC_STRAP_GPON_TX_EN 15 #define MISC_STRAP_SPI_FLASH_ADDR24 16 #define MISC_STRAP_BYP_CLK_DISABLE 17 #define MISC_STRAP_DDR_256M_EN_SHIFT 22 #define MISC_STRAP_DDR_256M_EN_MASK (1<miscUSIMCtrl /* ** High-Speed SPI Controller */ #define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) typedef struct HsSpiControl { uint32 hs_spiGlobalCtrl; // 0x0000 #define HS_SPI_MOSI_IDLE (1 << 18) #define HS_SPI_CLK_POLARITY (1 << 17) #define HS_SPI_CLK_GATE_SSOFF (1 << 16) #define HS_SPI_PLL_CLK_CTRL (8) #define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) #define HS_SPI_SS_POLARITY (0) #define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) uint32 hs_spiExtTrigCtrl; // 0x0004 #define HS_SPI_TRIG_RAW_STATE (24) #define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) #define HS_SPI_TRIG_LATCHED (16) #define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) #define HS_SPI_TRIG_SENSE (8) #define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) #define HS_SPI_TRIG_TYPE (0) #define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) #define HS_SPI_TRIG_TYPE_EDGE (0) #define HS_SPI_TRIG_TYPE_LEVEL (1) uint32 hs_spiIntStatus; // 0x0008 #define HS_SPI_IRQ_PING1_USER (28) #define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) #define HS_SPI_IRQ_PING0_USER (24) #define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) #define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) uint32 hs_spiIntStatusMasked; // 0x000C #define HS_SPI_IRQSM__PING1_USER (28) #define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) #define HS_SPI_IRQSM__PING0_USER (24) #define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) #define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) #define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) #define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) uint32 hs_spiIntMask; // 0x0010 #define HS_SPI_IRQM_PING1_USER (28) #define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) #define HS_SPI_IRQM_PING0_USER (24) #define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) #define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) #define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) uint32 hs_spiFlashCtrl; // 0x0014 #define HS_SPI_FCTRL_MB_ENABLE (23) #define HS_SPI_FCTRL_SS_NUM (20) #define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) #define HS_SPI_FCTRL_PROFILE_NUM (16) #define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) #define HS_SPI_FCTRL_DUMMY_BYTES (10) #define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES (8) #define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES_2 (0) #define HS_SPI_FCTRL_ADDR_BYTES_3 (1) #define HS_SPI_FCTRL_ADDR_BYTES_4 (2) #define HS_SPI_FCTRL_READ_OPCODE (0) #define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) uint32 hs_spiFlashAddrBase; // 0x0018 } HsSpiControl; typedef struct HsSpiPingPong { uint32 command; #define HS_SPI_SS_NUM (12) #define ZSI_SPI_DEV_ID 5 // SS_N[5] connected to APM/PCM block for use by MSIF/ZDS interfaces #define HS_SPI_PROFILE_NUM (8) #define HS_SPI_TRIGGER_NUM (4) #define HS_SPI_COMMAND_VALUE (0) #define HS_SPI_COMMAND_NOOP (0) #define HS_SPI_COMMAND_START_NOW (1) #define HS_SPI_COMMAND_START_TRIGGER (2) #define HS_SPI_COMMAND_HALT (3) #define HS_SPI_COMMAND_FLUSH (4) uint32 status; #define HS_SPI_ERROR_BYTE_OFFSET (16) #define HS_SPI_WAIT_FOR_TRIGGER (2) #define HS_SPI_SOURCE_BUSY (1) #define HS_SPI_SOURCE_GNT (0) uint32 fifo_status; uint32 control; uint32 PingPongReserved[12]; } HsSpiPingPong; typedef struct HsSpiProfile { uint32 clk_ctrl; #define HS_SPI_ACCUM_RST_ON_LOOP (15) #define HS_SPI_SPI_CLK_2X_SEL (14) #define HS_SPI_FREQ_CTRL_WORD (0) uint32 signal_ctrl; #define HS_SPI_ASYNC_INPUT_PATH (1 << 16) #define HS_SPI_LAUNCH_RISING (1 << 13) #define HS_SPI_LATCH_RISING (1 << 12) uint32 mode_ctrl; #define HS_SPI_PREPENDBYTE_CNT (24) #define HS_SPI_MODE_ONE_WIRE (20) #define HS_SPI_MULTIDATA_WR_SIZE (18) #define HS_SPI_MULTIDATA_RD_SIZE (16) #define HS_SPI_MULTIDATA_WR_STRT (12) #define HS_SPI_MULTIDATA_RD_STRT (8) #define HS_SPI_FILLBYTE (0) uint32 polling_config; uint32 polling_and_mask; uint32 polling_compare; uint32 polling_timeout; uint32 reserved; } HsSpiProfile; #define HS_SPI_OP_CODE 13 #define HS_SPI_OP_SLEEP (0) #define HS_SPI_OP_READ_WRITE (1) #define HS_SPI_OP_WRITE (2) #define HS_SPI_OP_READ (3) #define HS_SPI_OP_SETIRQ (4) #define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) #define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) #define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) #define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) #define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) #define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) typedef struct NandCtrlRegs { uint32 NandRevision; /* 0x00 */ uint32 NandCmdStart; /* 0x04 */ #define NCMD_MASK 0x0000001f #define NCMD_BLOCK_ERASE_MULTI 0x15 #define NCMD_PROGRAM_PAGE_MULTI 0x13 #define NCMD_STS_READ_MULTI 0x12 #define NCMD_PAGE_READ_MULTI 0x11 #define NCMD_LOW_LEVEL_OP 0x10 #define NCMD_PARAM_CHG_COL 0x0f #define NCMD_PARAM_READ 0x0e #define NCMD_BLK_LOCK_STS 0x0d #define NCMD_BLK_UNLOCK 0x0c #define NCMD_BLK_LOCK_DOWN 0x0b #define NCMD_BLK_LOCK 0x0a #define NCMD_FLASH_RESET 0x09 #define NCMD_BLOCK_ERASE 0x08 #define NCMD_DEV_ID_READ 0x07 #define NCMD_COPY_BACK 0x06 #define NCMD_PROGRAM_SPARE 0x05 #define NCMD_PROGRAM_PAGE 0x04 #define NCMD_STS_READ 0x03 #define NCMD_SPARE_READ 0x02 #define NCMD_PAGE_READ 0x01 uint32 NandCmdExtAddr; /* 0x08 */ uint32 NandCmdAddr; /* 0x0c */ uint32 NandCmdEndAddr; /* 0x10 */ uint32 NandIntfcStatus; /* 0x14 */ #define NIS_CTLR_READY (1 << 31) #define NIS_FLASH_READY (1 << 30) #define NIS_CACHE_VALID (1 << 29) #define NIS_SPARE_VALID (1 << 28) #define NIS_FLASH_STS_MASK 0x000000ff #define NIS_WRITE_PROTECT 0x00000080 #define NIS_DEV_READY 0x00000040 #define NIS_PGM_ERASE_ERROR 0x00000001 uint32 NandNandBootConfig; /* 0x18 */ #define NBC_CS_LOCK (1 << 31) #define NBC_AUTO_DEV_ID_CFG (1 << 30) #define NBC_WR_PROT_BLK0 (1 << 28) #define NBC_EBI_CS7_USES_NAND (1<<15) #define NBC_EBI_CS6_USES_NAND (1<<14) #define NBC_EBI_CS5_USES_NAND (1<<13) #define NBC_EBI_CS4_USES_NAND (1<<12) #define NBC_EBI_CS3_USES_NAND (1<<11) #define NBC_EBI_CS2_USES_NAND (1<<10) #define NBC_EBI_CS1_USES_NAND (1<< 9) #define NBC_EBI_CS0_USES_NAND (1<< 8) #define NBC_EBC_CS7_SEL (1<< 7) #define NBC_EBC_CS6_SEL (1<< 6) #define NBC_EBC_CS5_SEL (1<< 5) #define NBC_EBC_CS4_SEL (1<< 4) #define NBC_EBC_CS3_SEL (1<< 3) #define NBC_EBC_CS2_SEL (1<< 2) #define NBC_EBC_CS1_SEL (1<< 1) #define NBC_EBC_CS0_SEL (1<< 0) uint32 NandCsNandXor; /* 0x1c */ uint32 NandLlOpNand; /* 0x20 */ uint32 NandMplaneBaseExtAddr; /* 0x24 */ uint32 NandMplaneBaseAddr; /* 0x28 */ uint32 NandReserved1[9]; /* 0x2c-0x4f */ uint32 NandAccControl; /* 0x50 */ #define NAC_RD_ECC_EN (1 << 31) #define NAC_WR_ECC_EN (1 << 30) #define NAC_CE_CARE_EN (1 << 28) #define NAC_RD_ERASED_ECC_EN (1 << 27) #define NAC_PARTIAL_PAGE_EN (1 << 26) #define NAC_WR_PREEMPT_EN (1 << 25) #define NAC_PAGE_HIT_EN (1 << 24) #define NAC_PREFETCH_EN (1 << 23) #define NAC_CACHE_MODE_EN (1 << 22) #define NAC_ECC_LVL_SHIFT 16 #define NAC_ECC_LVL_MASK 0x001f0000 #define NAC_ECC_LVL_DISABLE 0 #define NAC_ECC_LVL_BCH_1 1 #define NAC_ECC_LVL_BCH_2 2 #define NAC_ECC_LVL_BCH_3 3 #define NAC_ECC_LVL_BCH_4 4 #define NAC_ECC_LVL_BCH_5 5 #define NAC_ECC_LVL_BCH_6 6 #define NAC_ECC_LVL_BCH_7 7 #define NAC_ECC_LVL_BCH_8 8 #define NAC_ECC_LVL_BCH_9 9 #define NAC_ECC_LVL_BCH_10 10 #define NAC_ECC_LVL_BCH_11 11 #define NAC_ECC_LVL_BCH_12 12 #define NAC_ECC_LVL_BCH_13 13 #define NAC_ECC_LVL_BCH_14 14 #define NAC_ECC_LVL_HAMMING 15 /* Hamming if spare are size = 16, BCH15 otherwise */ #define NAC_ECC_LVL_BCH15 15 #define NAC_ECC_LVL_BCH_16 16 #define NAC_ECC_LVL_BCH_17 17 /* BCH18 to 30 for sector size = 1K. To be added when we need it */ #define NAC_SECTOR_SIZE_1K (1 << 7) #define NAC_SPARE_SZ_SHIFT 0 #define NAC_SPARE_SZ_MASK 0x0000007f uint32 NandConfigExt; /* 0x54 */ /* Nand Flash Config Ext*/ #define NC_BLK_SIZE_MASK (0xff << 4) #define NC_BLK_SIZE_8192K (0xa << 4) #define NC_BLK_SIZE_4096K (0x9 << 4) #define NC_BLK_SIZE_2048K (0x8 << 4) #define NC_BLK_SIZE_1024K (0x7 << 4) #define NC_BLK_SIZE_512K (0x6 << 4) #define NC_BLK_SIZE_256K (0x5 << 4) #define NC_BLK_SIZE_128K (0x4 << 4) #define NC_BLK_SIZE_64K (0x3 << 4) #define NC_BLK_SIZE_32K (0x2 << 4) #define NC_BLK_SIZE_16K (0x1 << 4) #define NC_BLK_SIZE_8K (0x0 << 4) #define NC_PG_SIZE_MASK (0xf << 0) #define NC_PG_SIZE_16K (0x5 << 0) #define NC_PG_SIZE_8K (0x4 << 0) #define NC_PG_SIZE_4K (0x3 << 0) #define NC_PG_SIZE_2K (0x2 << 0) #define NC_PG_SIZE_1K (0x1 << 0) #define NC_PG_SIZE_512B (0x0 << 0) uint32 NandConfig; /* 0x58 */ /* Nand Flash Config */ #define NC_CONFIG_LOCK (1 << 31) #define NC_DEV_SIZE_SHIFT 24 #define NC_DEV_SIZE_MASK (0x0f << NC_DEV_SIZE_SHIFT) #define NC_DEV_WIDTH_MASK (1 << 23) #define NC_DEV_WIDTH_16 (1 << 23) #define NC_DEV_WIDTH_8 (0 << 23) #define NC_FUL_ADDR_SHIFT 16 #define NC_FUL_ADDR_MASK (0x7 << NC_FUL_ADDR_SHIFT) #define NC_BLK_ADDR_SHIFT 8 #define NC_BLK_ADDR_MASK (0x07 << NC_BLK_ADDR_SHIFT) uint32 NandTiming1; /* 0x5c */ /* Nand Flash Timing Parameters 1 */ #define NT_TREH_MASK 0x000f0000 #define NT_TREH_SHIFT 16 #define NT_TRP_MASK 0x00f00000 #define NT_TRP_SHIFT 20 uint32 NandTiming2; /* 0x60 */ /* Nand Flash Timing Parameters 2 */ #define NT_TREAD_MASK 0x0000000f #define NT_TREAD_SHIFT 0 /* 0x64 */ uint32 NandAccControlCs1; /* Nand Flash Access Control */ uint32 NandConfigExtCs1; /* Nand Flash Config Ext*/ uint32 NandConfigCs1; /* Nand Flash Config */ uint32 NandTiming1Cs1; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs1; /* Nand Flash Timing Parameters 2 */ /* 0x78 */ uint32 NandAccControlCs2; /* Nand Flash Access Control */ uint32 NandConfigExtCs2; /* Nand Flash Config Ext*/ uint32 NandConfigCs2; /* Nand Flash Config */ uint32 NandTiming1Cs2; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs2; /* Nand Flash Timing Parameters 2 */ /* 0x8c */ uint32 NandAccControlCs3; /* Nand Flash Access Control */ uint32 NandConfigExtCs3; /* Nand Flash Config Ext*/ uint32 NandConfigCs3; /* Nand Flash Config */ uint32 NandTiming1Cs3; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs3; /* Nand Flash Timing Parameters 2 */ /* 0xa0 */ uint32 NandAccControlCs4; /* Nand Flash Access Control */ uint32 NandConfigExtCs4; /* Nand Flash Config Ext*/ uint32 NandConfigCs4; /* Nand Flash Config */ uint32 NandTiming1Cs4; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs4; /* Nand Flash Timing Parameters 2 */ /* 0xb4 */ uint32 NandAccControlCs5; /* Nand Flash Access Control */ uint32 NandConfigExtCs5; /* Nand Flash Config Ext*/ uint32 NandConfigCs5; /* Nand Flash Config */ uint32 NandTiming1Cs5; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs5; /* Nand Flash Timing Parameters 2 */ /* 0xc8 */ uint32 NandAccControlCs6; /* Nand Flash Access Control */ uint32 NandConfigExtCs6; /* Nand Flash Config Ext*/ uint32 NandConfigCs6; /* Nand Flash Config */ uint32 NandTiming1Cs6; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs6; /* Nand Flash Timing Parameters 2 */ /* 0xdc */ uint32 NandCorrStatThreshold; /* Correctable Error Reporting Threshold */ uint32 NandCorrStatThresholdExt; /* Correctable Error Reporting * Threshold */ uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ /* for EBI_CS0b */ uint32 NandMplaneOpcode1; /* 0xec */ uint32 NandMplaneOpcode2; uint32 NandMplaneCtrl; uint32 NandReserved2[2]; /* 0xf4-0xfb */ uint32 NandUncorrErrorCount; /* 0xfc */ /* 0x100 */ uint32 NandCorrErrorCount; uint32 NandReadErrorCount; /* Read Error Count */ uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ /* 0x110 */ uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ /* 0x120 */ uint32 NandFlashReadAddr; /* Flash Read Data Address */ uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ uint32 NandProgramPageAddr; /* Page Program Address */ uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ /* 0x130 */ uint32 NandCopyBackAddr; /* Copy Back Address */ uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ uint32 NandBlockEraseAddr; /* Block Erase Address */ uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ /* 0x140 */ uint32 NandInvReadAddr; /* Flash Invalid Data Address */ uint32 NandInitStatus; uint32 NandOnfiStatus; /* ONFI Status */ uint32 NandOnfiDebugData; /* ONFI Debug Data */ uint32 NandSemaphore; /* 0x150 */ /* Semaphore */ uint32 NandReserved3[16]; /* 0x154-0x193 */ /* 0x194 */ uint32 NandFlashDeviceId; /* Nand Flash Device ID */ uint32 NandFlashDeviceIdExt; /* Nand Flash Extended Device ID */ uint32 NandLlRdData; /* Nand Flash Low Level Read Data */ uint32 NandReserved4[24]; /* 0x1a0 - 0x1ff */ /* 0x200 */ uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ /* 0x210 */ uint32 NandSpareAreaReadOfs10; /* Nand Flash Spare Area Read Bytes 16-19 */ uint32 NandSpareAreaReadOfs14; /* Nand Flash Spare Area Read Bytes 20-23 */ uint32 NandSpareAreaReadOfs18; /* Nand Flash Spare Area Read Bytes 24-27 */ uint32 NandSpareAreaReadOfs1C; /* Nand Flash Spare Area Read Bytes 28-31*/ /* 0x220 */ uint32 NandSpareAreaReadOfs20; /* Nand Flash Spare Area Read Bytes 32-35 */ uint32 NandSpareAreaReadOfs24; /* Nand Flash Spare Area Read Bytes 36-39 */ uint32 NandSpareAreaReadOfs28; /* Nand Flash Spare Area Read Bytes 40-43 */ uint32 NandSpareAreaReadOfs2C; /* Nand Flash Spare Area Read Bytes 44-47*/ /* 0x230 */ uint32 NandSpareAreaReadOfs30; /* Nand Flash Spare Area Read Bytes 48-51 */ uint32 NandSpareAreaReadOfs34; /* Nand Flash Spare Area Read Bytes 52-55 */ uint32 NandSpareAreaReadOfs38; /* Nand Flash Spare Area Read Bytes 56-59 */ uint32 NandSpareAreaReadOfs3C; /* Nand Flash Spare Area Read Bytes 60-63*/ uint32 NandReserved5[16]; /* 0x240-0x27f */ /* 0x280 */ uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11 */ uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes 12-15 */ /* 0x290 */ uint32 NandSpareAreaWriteOfs10; /* Nand Flash Spare Area Write Bytes 16-19 */ uint32 NandSpareAreaWriteOfs14; /* Nand Flash Spare Area Write Bytes 20-23 */ uint32 NandSpareAreaWriteOfs18; /* Nand Flash Spare Area Write Bytes 24-27 */ uint32 NandSpareAreaWriteOfs1C; /* Nand Flash Spare Area Write Bytes 28-31 */ /* 0x2a0 */ uint32 NandSpareAreaWriteOfs20; /* Nand Flash Spare Area Write Bytes 32-35 */ uint32 NandSpareAreaWriteOfs24; /* Nand Flash Spare Area Write Bytes 36-39 */ uint32 NandSpareAreaWriteOfs28; /* Nand Flash Spare Area Write Bytes 40-43 */ uint32 NandSpareAreaWriteOfs2C; /* Nand Flash Spare Area Write Bytes 44-47 */ /* 0x2b0 */ uint32 NandSpareAreaWriteOfs30; /* Nand Flash Spare Area Write Bytes 48-51 */ uint32 NandSpareAreaWriteOfs34; /* Nand Flash Spare Area Write Bytes 52-55 */ uint32 NandSpareAreaWriteOfs38; /* Nand Flash Spare Area Write Bytes 56-59 */ uint32 NandSpareAreaWriteOfs3C; /* Nand Flash Spare Area Write Bytes 60-63 */ /* 0x2c0 */ uint32 NandDdrTiming; uint32 NandDdrNcdlCalibCtl; uint32 NandDdrNcdlCalibPeriod; uint32 NandDdrNcdlCalibStat; /* 0x2d0 */ uint32 NandDdrNcdlMode; uint32 NandDdrNcdlOffset; uint32 NandDdrPhyCtl; uint32 NandDdrPhyBistCtl; /* 0x2e0 */ uint32 NandDdrPhyBistStat; uint32 NandDdrDiagStat0; uint32 NandDdrDiagStat1; uint32 NandReserved6[69]; /* 0x2ec-0x3ff */ /* 0x400 */ uint32 NandFlashCache[128]; /* 0x400-0x5ff */ } NandCtrlRegs; #define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) #define NAND_CACHE_BUFFER ((volatile uint8 * const) NAND_CACHE_BASE); /* ** Misc (Top) registers control */ typedef struct TopControl { uint32 PeriphClkCtrl; /* 0x00 */ uint32 WanClkCtrl; /* 0x04 */ uint32 MipsClkCtrl; /* 0x08 */ uint32 UsbClkCtrl; /* 0x0c */ uint32 PcmClkCtrl; /* 0x10 */ uint32 RdpClkCtrl; /* 0x14 */ uint32 DdrClkCtrl; /* 0x18 */ uint32 PmcClkCtrl; /* 0x1c */ uint32 PcieClkCtrl; /* 0x20 */ uint32 ClkgenCtr3; /* 0x24 */ #define CLKGEN3_SSB_MASTER_SHIFT 25 #define CLKGEN3_MDIO_MASTER_SHIFT 24 uint32 DgSensePadCtrl; /* 0x28 */ #define DG_CTRL_SHIFT 4 #define DG_EN_SHIFT 3 #define DG_TRIM_SHIFT 0 uint32 Reg2P5VLDOCtrlEnable;/* 0x2c */ uint32 Reg1P0VLDOCtrl; uint32 Reg1P0VLDOCtrlEnable; uint32 SwRegCtrl; uint32 RescalIpCtrl; uint32 RgmiiCtrl; /* 0x40 */ #define RSW_RGMII_PADS_ENABLE (1<<1) #define RSW_RGMII_PAD_MODEHV_CTRL (1<<0) uint32 TpDirOverride[2]; /* 0x44 */ uint32 RescalReadData[2]; /* 0x4c */ } TopControl; #define MISC_REG ((volatile TopControl * const) TOP_CNTRL_BASE) typedef struct UsimBase { uint32 UsimScr; //sim Control Register uint32 UsimSsr; //sim Status Register uint32 UsimSdr; //sim Data Register uint32 UsimSier; //siM Interrupt Enable Register uint32 UsimSfcr; //siM FIFO Control Register uint32 UsimSecgtr; //SIM Extra Character Guard Time Register uint32 UsimStgtr; //sIM Turnaround Guard Time Register uint32 UsimSgccr; //sIM Generic Counter Compare Register uint32 UsimSgcvr; //sIM Generic Counter Value Register uint32 UsimScdr; //siM Clock Divide Register uint32 UsimSfdrr; //sIM F/D Ratio Register uint32 UsimSesr; //siM Extra Sample Register uint32 UsimSimdebug; //SIM Debug Register uint32 UsimSrtor; //sIM Received Time Out Register uint32 UsimReserved[4]; uint32 UsimSipver; //SIM Controller IP version - 0x4c uint32 UsimReserved1[4]; uint32 UsimSesdcr; //SIM Card Detection and Emergency Shutdown Control Register - 0x60 uint32 UsimSesdisr; //SIM Card Detection and Emergency Shutdown Interrupt Status Register uint32 UsimScardsr; //SIM Card Status Control and Status Register uint32 UsimSldocr; //SIM LDO Controler Register } UsimBase; #define USIM ((volatile UsimBase * const) USIM_BASE) typedef struct MDIOBase { uint32 MDIO_PerCmd; //MDIO Command Register uint32 MDIO_PerCfg; //MDIO Configuration Register } MDIOBase; #define MDIO ((volatile MDIOBase * const) MDIO_BASE) typedef struct I2CControl { uint32 ChipAddress; /* 0x0 */ #define I2C_CHIP_ADDRESS_MASK 0x000000f7 #define I2C_CHIP_ADDRESS_SHIFT 0x1 uint32 DataIn0; /* 0x4 */ uint32 DataIn1; /* 0x8 */ uint32 DataIn2; /* 0xc */ uint32 DataIn3; /* 0x10 */ uint32 DataIn4; /* 0x14 */ uint32 DataIn5; /* 0x18 */ uint32 DataIn6; /* 0x1c */ uint32 DataIn7; /* 0x20 */ uint32 CntReg; /* 0x24 */ #define I2C_CNT_REG1_SHIFT 0x0 #define I2C_CNT_REG2_SHIFT 0x6 uint32 CtlReg; /* 0x28 */ #define I2C_CTL_REG_DTF_MASK 0x00000003 #define I2C_CTL_REG_DTF_WRITE 0x0 #define I2C_CTL_REG_DTF_READ 0x1 #define I2C_CTL_REG_DTF_READ_AND_WRITE 0x2 #define I2C_CTL_REG_DTF_WRITE_AND_READ 0x3 #define I2C_CTL_REG_DEGLITCH_DISABLE 0x00000004 #define I2C_CTL_REG_DELAY_DISABLE 0x00000008 #define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 #define I2C_CTL_REG_SCL_CLK_375KHZ 0x00000000 #define I2C_CTL_REG_SCL_CLK_390KHZ 0x00000010 #define I2C_CTL_REG_SCL_CLK_187_5KHZ 0x00000020 #define I2C_CTL_REG_SCL_CLK_200KHZ 0x00000030 #define I2C_CTL_REG_INT_ENABLE 0x00000040 #define I2C_CTL_REG_DIV_CLK 0x00000080 uint32 IICEnable; /* 0x2c */ #define I2C_IIC_ENABLE 0x00000001 #define I2C_IIC_INTRP 0x00000002 #define I2C_IIC_NO_ACK 0x00000004 #define I2C_IIC_NO_STOP 0x00000010 #define I2C_IIC_NO_START 0x00000020 uint32 DataOut0; /* 0x30 */ uint32 DataOut1; /* 0x34 */ uint32 DataOut2; /* 0x38 */ uint32 DataOut3; /* 0x3c */ uint32 DataOut4; /* 0x40 */ uint32 DataOut5; /* 0x44 */ uint32 DataOut6; /* 0x48 */ uint32 DataOut7; /* 0x4c */ uint32 CtlHiReg; /* 0x50 */ #define I2C_CTLHI_REG_WAIT_DISABLE 0x00000001 #define I2C_CTLHI_REG_IGNORE_ACK 0x00000002 #define I2C_CTLHI_REG_DATA_REG_SIZE 0x00000040 uint32 SclParam; /* 0x54 */ } I2CControl; #define I2C ((volatile I2CControl * const) I2C_BASE) /* * Power Management Control */ typedef struct PmcCtrlReg { /* 0x00 */ uint32 l1Irq4keMask; uint32 l1Irq4keStatus; uint32 l1IrqMipsMask; uint32 l1IrqMipsStatus; /* 0x10 */ uint32 l2IrqGpMask; uint32 l2IrqGpStatus; uint32 gpTmr0Ctl; uint32 gpTmr0Cnt; /* 0x20 */ uint32 gpTmr1Ctl; uint32 gpTmr1Cnt; uint32 hostMboxIn; uint32 hostMboxOut; /* 0x30 */ #define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 uint32 gpOut; uint32 gpIn; uint32 gpInIrqMask; uint32 gpInIrqStatus; /* 0x40 */ uint32 dmaCtrl; uint32 dmaStatus; uint32 dma0_3FifoStatus; uint32 unused0[3]; /* 0x4c-0x57 */ /* 0x58 */ uint32 l1IrqMips1Mask; uint32 diagControl; /* 0x60 */ uint32 diagHigh; uint32 diagLow; uint32 badAddr; uint32 addr1WndwMask; /* 0x70 */ uint32 addr1WndwBaseIn; uint32 addr1WndwBaseOut; uint32 addr2WndwMask; uint32 addr2WndwBaseIn; /* 0x80 */ uint32 addr2WndwBaseOut; uint32 scratch; uint32 tm; uint32 softResets; /* 0x90 */ uint32 eb2ubusTimeout; uint32 m4keCoreStatus; uint32 gpInIrqSense; uint32 ubSlaveTimeout; /* 0xa0 */ uint32 diagEn; uint32 devTimeout; uint32 ubusErrorOutMask; uint32 diagCaptStopMask; /* 0xb0 */ uint32 revId; uint32 gpTmr2Ctl; uint32 gpTmr2Cnt; uint32 legacyMode; /* 0xc0 */ uint32 smisbMonitor; uint32 diagCtrl; uint32 diagStat; uint32 diagMask; /* 0xd0 */ uint32 diagRslt; uint32 diagCmp; uint32 diagCapt; uint32 diagCnt; /* 0xe0 */ uint32 diagEdgeCnt; uint32 unused1[4]; /* 0xe4-0xf3 */ /* 0xf4 */ uint32 iopPeriphBaseAddr; uint32 lfsr; uint32 unused2; /* 0xfc-0xff */ } PmcCtrlReg; typedef struct PmcOutFifoReg { uint32 msgCtrl; /* 0x00 */ uint32 msgSts; /* 0x04 */ uint32 unused[14]; /* 0x08-0x3f */ uint32 msgData[16]; /* 0x40-0x7c */ } PmcOutFifoReg; typedef struct PmcInFifoReg { uint32 msgCtrl; /* 0x00 */ uint32 msgSts; /* 0x04 */ uint32 unused[13]; /* 0x08-0x3b */ uint32 msgLast; /* 0x3c */ uint32 msgData[16]; /* 0x40-0x7c */ } PmcInFifoReg; typedef struct PmcDmaReg { /* 0x00 */ uint32 src; uint32 dest; uint32 cmdList; uint32 lenCtl; /* 0x10 */ uint32 rsltSrc; uint32 rsltDest; uint32 rsltHcs; uint32 rsltLenStat; } PmcDmaReg; typedef struct PmcTokenReg { /* 0x00 */ uint32 bufSize; uint32 bufBase; uint32 idx2ptrIdx; uint32 idx2ptrPtr; /* 0x10 */ uint32 unused[2]; uint32 bufSize2; } PmcTokenReg; typedef struct PmcPerfPowReg { /* 0x00 */ uint32 dcacheHit; uint32 dcacheMiss; uint32 icacheHit; uint32 icacheMiss; /* 0x10 */ uint32 instnComplete; uint32 wtbMerge; uint32 wtbNoMerge; uint32 itlbHit; /* 0x20 */ uint32 itlbMiss; uint32 dtlbHit; uint32 dtlbMiss; uint32 jtlbHit; /* 0x30 */ uint32 jtlbMiss; uint32 powerSubZone; uint32 powerMemPda; uint32 freqScalarCtrl; /* 0x40 */ uint32 freqScalarMask; } PmcPerfPowReg; typedef struct PmcDQMReg { /* 0x00 */ uint32 cfg; uint32 _4keLowWtmkIrqMask; uint32 mipsLowWtmkIrqMask; uint32 lowWtmkIrqMask; /* 0x10 */ uint32 _4keNotEmptyIrqMask; uint32 mipsNotEmptyIrqMask; uint32 notEmptyIrqSts; uint32 queueRst; /* 0x20 */ uint32 notEmptySts; uint32 nextAvailMask; uint32 nextAvailQueue; uint32 mips1LowWtmkIrqMask; /* 0x30 */ uint32 mips1NotEmptyIrqMask; uint32 autoSrcPidInsert; } PmcDQMReg; typedef struct PmcCntReg { uint32 cntr[10]; uint32 unused[6]; /* 0x28-0x3f */ uint32 cntrIrqMask; uint32 cntrIrqSts; } PmcCntReg; typedef struct PmcDqmQCtrlReg { uint32 size; uint32 cfga; uint32 cfgb; uint32 cfgc; } PmcDqmQCtrlReg; typedef struct PmcDqmQDataReg { uint32 word[4]; } PmcDqmQDataReg; typedef struct PmcDqmQMibReg { uint32 qNumFull[32]; uint32 qNumEmpty[32]; uint32 qNumPushed[32]; } PmcDqmQMibReg; typedef struct Pmc { uint32 baseReserved; /* 0x0000 */ uint32 unused0[1023]; PmcCtrlReg ctrl; /* 0x1000 */ PmcOutFifoReg outFifo; /* 0x1100 */ uint32 unused1[32]; /* 0x1180-0x11ff */ PmcInFifoReg inFifo; /* 0x1200 */ uint32 unused2[32]; /* 0x1280-0x12ff */ PmcDmaReg dma[2]; /* 0x1300 */ uint32 unused3[48]; /* 0x1340-0x13ff */ PmcTokenReg token; /* 0x1400 */ uint32 unused4[121]; /* 0x141c-0x15ff */ PmcPerfPowReg perfPower; /* 0x1600 */ uint32 unused5[47]; /* 0x1644-0x16ff */ uint32 msgId[32]; /* 0x1700 */ uint32 unused6[32]; /* 0x1780-0x17ff */ PmcDQMReg dqm; /* 0x1800 */ uint32 unused7[50]; /* 0x1838-0x18ff */ PmcCntReg hwCounter; /* 0x1900 */ uint32 unused8[46]; /* 0x1948-0x19ff */ PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ uint32 unused9[64]; /* 0x1e00-0x1eff */ uint32 qStatus[32]; /* 0x1f00 */ uint32 unused10[32]; /* 0x1f80-0x1fff */ PmcDqmQMibReg qMib; /* 0x2000 */ uint32 unused11[1952]; /* 0x2180-0x3ffff */ uint32 sharedMem[8192]; /* 0x4000-0xbffc */ } Pmc; #define PMC ((volatile Pmc * const) PMC_BASE) /* * Process Monitor Module */ typedef struct PMRingOscillatorControl { uint32 control; uint32 en_lo; uint32 en_mid; uint32 en_hi; uint32 idle_lo; uint32 idle_mid; uint32 idle_hi; } PMRingOscillatorControl; #define RCAL_0P25UM_HORZ 0 #define RCAL_0P25UM_VERT 1 #define RCAL_0P5UM_HORZ 2 #define RCAL_0P5UM_VERT 3 #define RCAL_1UM_HORZ 4 #define RCAL_1UM_VERT 5 #define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) #define PMMISC_RMON_VALID_MASK (0x1<<16) typedef struct PMMiscControl { uint32 gp_out; uint32 clock_select; uint32 unused[2]; uint32 misc[4]; } PMMiscControl; typedef struct PMSSBMasterControl { uint32 control; uint32 wr_data; uint32 rd_data; } PMSSBMasterControl; typedef struct PMEctrControl { uint32 control; uint32 interval; uint32 thresh_lo; uint32 thresh_hi; uint32 count; } PMEctrControl; typedef struct PMBMaster { uint32 ctrl; #define PMC_PMBM_START (1 << 31) #define PMC_PMBM_TIMEOUT (1 << 30) #define PMC_PMBM_SLAVE_ERR (1 << 29) #define PMC_PMBM_BUSY (1 << 28) #define PMC_PMBM_Read (0 << 20) #define PMC_PMBM_Write (1 << 20) uint32 wr_data; uint32 timeout; uint32 rd_data; uint32 unused[4]; } PMBMaster; typedef struct PMAPVTMONControl { uint32 control; uint32 reserved; uint32 cfg_lo; uint32 cfg_hi; uint32 data; uint32 vref_data; uint32 unused[2]; uint32 ascan_cfg; uint32 warn_temp; uint32 reset_temp; uint32 temp_value; uint32 data1_value; uint32 data2_value; uint32 data3_value; } PMAPVTMONControl; typedef struct PMUBUSCfg { uint32 window[8]; uint32 control; } PMUBUSCfg; typedef struct ProcessMonitorRegs { uint32 MonitorCtrl; /* 0x00 */ uint32 unused0[7]; PMRingOscillatorControl ROSC; /* 0x20 */ uint32 unused1; PMMiscControl Misc; /* 0x40 */ PMSSBMasterControl SSBMaster; /* 0x60 */ uint32 unused2[5]; PMEctrControl Ectr; /* 0x80 */ uint32 unused3[11]; PMBMaster PMBM[2]; /* 0xc0 */ PMAPVTMONControl APvtmonCtrl; /* 0x100 */ uint32 unused4[9]; PMUBUSCfg UBUSCfg; /* 0x160 */ } ProcessMonitorRegs; #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) /* * LedControl Register Set Definitions. */ typedef struct LedControl { uint32 glbCtrl; /* 0x00 */ uint32 mask; /* 0x04 */ uint32 hWLedEn; /* 0x08 */ uint32 serialLedShiftSel; /* 0x0c */ uint32 flashRateCtrl[4]; /* 0x10-0x1c */ uint32 brightCtrl[4]; /* 0x20-0x2c */ uint32 powerLedCfg; /* 0x30 */ uint32 pledLut[2][16]; /* 0x34-0x70, 0x74-0xb0 */ uint32 HwPolarity; /* 0xb4 */ /*B0 ONLY FROM HERE */ uint32 SwData; /* 0xb8 */ uint32 SwPolarity; /* 0xbc */ uint32 ParallelLedPolarity; /* 0xc0 */ uint32 SerialLedPolarity; /* 0xc4 */ uint32 HwLedStatus; /* 0xc8 */ uint32 FlashCtrlStatus; uint32 BrtCtrlStatus; uint32 ParallelOutStatus; uint32 SerialRegStatus; } LedControl; #define LED ((volatile LedControl * const) LED_BASE) #define LED_NUM_LEDS 32 #define LED_NUM_TO_MASK(X) (1 << ((X) & (LED_NUM_LEDS-1))) #define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) /* ** DDR Memory Controller Register Set Definitions. */ typedef struct UBUSInterface { uint32 CFG; /* 0x00 */ #define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT 0x0 #define UBUSIF_CFG_WRITE_REPLY_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT) #define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT 0x1 #define UBUSIF_CFG_WRITE_BURST_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT) #define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT 0x2 #define UBUSIF_CFG_INBAND_ERR_MASK_MASK (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT) #define UBUSIF_CFG_OOB_ERR_MASK_SHIFT 0x3 #define UBUSIF_CFG_OOB_ERR_MASK_MASK (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT) uint32 SRC_QUEUE_CTRL_0; /* 0x04 */ uint32 SRC_QUEUE_CTRL_1; /* 0x08 */ uint32 SRC_QUEUE_CTRL_2; /* 0x0c */ uint32 SRC_QUEUE_CTRL_3; /* 0x10 */ uint32 REP_ARB_MODE; /* 0x14 */ #define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0 #define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK (0x1<