/* <:copyright-BRCM:2015:DUAL/GPL:standard Copyright (c) 2015 Broadcom All Rights Reserved This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License, version 2, as published by the Free Software Foundation (the "GPL"). This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. :> */ #ifndef __BCM6856_MAP_PART_H #define __BCM6856_MAP_PART_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #include "bcm_io_map.h" #define CHIP_FAMILY_ID_HEX 0x6856 #ifndef __ASSEMBLER__ typedef enum { MEMC_IDX, PMC_IDX, PROC_MON_IDX, XRDP_IDX, UBUS_MAPPED_IDX, PERF_IDX, USIM_IDX, PERF1_IDX, NANDFLASH_IDX, PCM_IDX, PCMBUS_IDX, WAN_IDX, NGPON2_IDX, USBH_IDX, MST_PORT_NODE_PCIE0_IDX, MST_PORT_NODE_PCIE2_IDX, MST_PORT_NODE_B53_IDX, MST_PORT_NODE_USB_IDX, MST_PORT_NODE_PER_IDX, MST_PORT_NODE_DMA0_IDX, MST_PORT_NODE_DMA1_IDX, MST_PORT_NODE_RQ0_IDX, MST_PORT_NODE_RQ1_IDX, MST_PORT_NODE_NATC_IDX, MST_PORT_NODE_DQM_IDX, MST_PORT_NODE_QM_IDX, UBUS4_COHERENCY_PORT_IDX, BIUCFG_IDX, LAST_IDX } BCM_IO_MAP_IDX; #endif #define PCIE0_PHYS_BASE 0x80040000 #define PCIE0_SIZE 0x0000A000 #define PCIE1_PHYS_BASE 0x80050000 #define PCIE1_SIZE 0x0000A000 #define PCIE2_PHYS_BASE 0x80060000 #define PCIE2_SIZE 0x0000A000 #define PCIE0_MEM_PHYS_BASE 0x90000000 #define PCIE0_MEM_SIZE 0x10000000 #define PCIE1_MEM_PHYS_BASE 0xA0000000 #define PCIE1_MEM_SIZE 0x10000000 #define PCIE2_MEM_PHYS_BASE 0xB0000000 #define PCIE2_MEM_SIZE 0x10000000 #define MEMC_PHYS_BASE 0x80180000 #define MEMC_SIZE 0x24000 #define PMC_PHYS_BASE 0xffb00000 #define PMC_SIZE 0x6000 #define PROC_MON_PHYS_BASE 0xffb20000 #define PROC_MON_SIZE 0x1000 #define XRDP_PHYS_BASE 0x82000000 #define XRDP_SIZE 0x1000000 #define UBUS_MAPPED_PHYS_BASE 0x83000000 #define UBUS_MAPPED_SIZE 0x1000 #define PERF_PHYS_BASE 0xff800000 #define PERF_SIZE 0x3000 #define USIM_PHYS_BASE 0xff854000 #define USIM_SIZE 0x1000 #define PERF1_PHYS_BASE 0xff858000 #define PERF1_SIZE 0x4000 #define EMMCFLASH_PHYS_BASE 0xffc00000 #define EMMCFLASH_SIZE 0x100000 #define SPIFLASH_PHYS_BASE 0xffd00000 #define SPIFLASH_SIZE 0x100000 #define NANDFLASH_PHYS_BASE 0xffe00000 #define NANDFLASH_SIZE 0x100000 #define PCM_PHYS_BASE 0xff860000 #define APM_CORE_OFFSET 0x00000000 #define PCM_CORE_OFFSET 0x00000C00 #define PCM_DMA_OFFSET 0x00001800 #define PCM_SIZE 0x2000 #define PCMBUS_PHYS_BASE 0x83058600 #define PCMBUS_OFFSET 0x00000000 #define PCMBUS_SIZE 0x100 #define BIUCFG_PHYS_BASE 0x81060000 #define BIUCFG_SIZE 0x3000 #define TIMR_OFFSET 0x0400 #define WDTIMR0_OFFSET 0x0480 #define WDTIMR1_OFFSET 0x04c0 #define GPIO_OFFSET 0x0500 #define BROM_OFFSET 0x0600 #define UART_OFFSET 0x0640 #define UART1_OFFSET 0x0660 #define LED_OFFSET 0x0800 #define RNG_OFFSET 0x0b80 #define JTAG_OTP_OFFSET 0x2800 #define SOTP_OFFSET 0x0c00 #define HSSPIM_OFFSET 0x1000 #define NAND_REG_OFFSET 0x1800 #define NAND_CACHE_OFFSET 0x1c00 #define NAND_INTR_OFFSET 0x2000 #define MDIO_OFFSET 0x2060 #define I2S_OFFSET 0x2080 #define I2C_OFFSET 0x2100 #define MISC_OFFSET 0x2600 #define NANDFLASH_OFFSET 0x0000 #define SPIFLASH_OFFSET 0x0000 #define EMMCFLASH_OFFSET 0x0000 #define BIUCFG_OFFSET 0x0000 #define BIUCFG_AUX_OFFSET 0x0700 #define SYS_CLK_CTRL_OFFSET 0x80 #define SYS_ERR_PORT_CFG_OFFSET 0x100 #define UBUS_SYS_MODULE_REGISTRATION_OFFSET 0x200 #define TIMR_PHYS_BASE (PERF_PHYS_BASE + TIMR_OFFSET) #define WDTIMR0_PHYS_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) #define WDTIMR1_PHYS_BASE (PERF_PHYS_BASE + WDTIMR1_OFFSET) #define GPIO_PHYS_BASE (PERF_PHYS_BASE + GPIO_OFFSET) #define UART_PHYS_BASE (PERF_PHYS_BASE + UART_OFFSET) #define UART1_PHYS_BASE (PERF_PHYS_BASE + UART1_OFFSET) #define LED_PHYS_BASE (PERF_PHYS_BASE + LED1_OFFSET) #define JTAG_OTP_PHYS_BASE (PERF_PHYS_BASE + JTAG_OTP_OFFSET) #define HSSPIM_PHYS_BASE (PERF_PHYS_BASE + HSSPIM_OFFSET) #define NAND_REG_PHYS_BASE (PERF_PHYS_BASE + NAND_REG_OFFSET) #define NAND_CACHE_PHYS_BASE (PERF_PHYS_BASE + NAND_CACHE_OFFSET) #define NAND_INTR_PHYS_BASE (PERF_PHYS_BASE + NAND_INTR_OFFSET) #define MDIO_PHYS_BASE (PERF_PHYS_BASE + MDIO_OFFSET) #define I2S_PHYS_BASE (PERF_PHYS_BASE + I2S_OFFSET) #define I2C_PHYS_BASE (PERF_PHYS_BASE + I2C_OFFSET) #define MISC_PHYS_BASE (PERF_PHYS_BASE + MISC_OFFSET) #define EMMC_HOST_OFFSET 0x0000 #define EMMC_TOP_OFFSET 0x0100 #define EMMC_BOOT_OFFSET 0x0200 #define AHB_CONTROL_OFFSET 0x0300 #define HS_UART_OFFSET 0x0400 #define PL081_DMA_OFFSET 0x1000 #define I2C_2_OFFSET 0x2800 #define PMB_OFFSET 0x0100 #define TOP_CNTRL_OFFSET 0x2000 #define EMMC_HOST_PHYS_BASE (PERF1_PHYS_BASE + EMMC_HOST_OFFSET) #define EMMC_TOP_PHYS_BASE (PERF1_PHYS_BASE + EMMC_TOP_OFFSET) #define EMMC_BOOT_PHYS_BASE (PERF1_PHYS_BASE + EMMC_BOOT_OFFSET) #define AHB_CONTROL_PHYS_BASE (PERF1_PHYS_BASE + AHB_CONTROL_OFFSET) #define HS_UART_PHYS_BASE (PERF1_PHYS_BASE + HS_UART_OFFSET) #define PL081_DMA_PHYS_BASE (PERF1_PHYS_BASE + PL081_DMA_OFFSET) #define I2C_2_PHYS_BASE (PERF1_PHYS_BASE + I2C_2_OFFSET) #define TOP_CNTRL_BASE (PERF1_PHYS_BASE + TOP_CNTRL_OFFSET) /* chip top control registers*/ #define USBH_PHYS_BASE 0x8000c000 #define USBH_SIZE 0x3fff #define USBH_OFFSET 0x0000 #define CFG_OFFSET 0x200 #define EHCI_OFFSET 0x300 /* USB host registers */ #define OHCI_OFFSET 0x400 /* USB host registers */ #define EHCI1_OFFSET 0x500 /* EHCI1 host registers */ #define OHCI1_OFFSET 0x600 /* OHCI1 host registers */ #define XHCI_OFFSET 0x1000 /* USB host registers */ #define XHCI_EC_OFFSET 0x1900 /* USB host registers */ /* to support non-DT pltaform device add below defs */ #define USB_EHCI_PHYS_BASE (USBH_PHYS_BASE+EHCI_OFFSET) #define USB_OHCI_PHYS_BASE (USBH_PHYS_BASE+OHCI_OFFSET) #define USB_EHCI1_PHYS_BASE (USBH_PHYS_BASE+EHCI1_OFFSET) #define USB_OHCI1_PHYS_BASE (USBH_PHYS_BASE+OHCI1_OFFSET) #define USB_XHCI_PHYS_BASE (USBH_PHYS_BASE+XHCI_OFFSET) #define GIC_PHYS_BASE 0x81000000 #define GIC_SIZE 0x10000 #define GIC_OFFSET 0x0000 #define GICD_OFFSET 0x1000 #define GICC_OFFSET 0x2000 #define WAN_PHYS_BASE 0x82db2000 #define WAN_SIZE 0x1000 #define NGPON2_PHYS_BASE 0x82db4000 #define NGPON2_SIZE 0xE000 #define MST_PORT_NODE_PCIE0_PHYS_BASE 0x8300C000 #define MST_PORT_NODE_PCIE0_SIZE 0x1000 #define MST_PORT_NODE_PCIE2_PHYS_BASE 0x83028000 #define MST_PORT_NODE_PCIE2_SIZE 0x1000 #define MST_PORT_NODE_B53_PHYS_BASE 0x83020000 #define MST_PORT_NODE_B53_SIZE 0x1000 #define MST_PORT_NODE_USB_PHYS_BASE 0x83038000 #define MST_PORT_NODE_USB_SIZE 0x1000 #define MST_PORT_NODE_PER_PHYS_BASE 0x83058000 #define MST_PORT_NODE_PER_SIZE 0x1000 #define MST_PORT_NODE_DMA0_PHYS_BASE 0x83064000 #define MST_PORT_NODE_DMA1_PHYS_BASE 0x83068000 #define MST_PORT_NODE_DMA_SIZE 0x1000 #define MST_PORT_NODE_RQ0_PHYS_BASE 0x83080000 #define MST_PORT_NODE_RQ1_PHYS_BASE 0x83088000 #define MST_PORT_NODE_RQ_SIZE 0x1000 #define MST_PORT_NODE_NATC_PHYS_BASE 0x830A0000 #define MST_PORT_NODE_NATC_SIZE 0x1000 #define MST_PORT_NODE_DQM_PHYS_BASE 0x830A4000 #define MST_PORT_NODE_DQM_SIZE 0x1000 #define MST_PORT_NODE_QM_PHYS_BASE 0x830AC000 #define MST_PORT_NODE_QM_SIZE 0x1000 #define WAN_BASE BCM_IO_MAP(WAN_IDX, WAN_PHYS_BASE, 0) #define NGPON2_BASE BCM_IO_MAP(NGPON2_IDX, NGPON2_PHYS_BASE, 0) #define PMC_BASE BCM_IO_MAP(PMC_IDX, PMC_PHYS_BASE, 0) #define PROC_MON_BASE BCM_IO_MAP(PROC_MON_IDX, PROC_MON_PHYS_BASE, 0) #define PMB_BASE BCM_IO_MAP(PROC_MON_IDX, PROC_MON_PHYS_BASE, PMB_OFFSET) #define MEMC_BASE BCM_IO_MAP(MEMC_IDX, MEMC_PHYS_BASE, 0) #define UBUS_SYS_MODULE_BASE BCM_IO_MAP(UBUS_MAPPED_IDX, UBUS_MAPPED_PHYS_BASE, 0) #define UBUS_SYS_MODULE_REGISTRATION_BASE BCM_IO_MAP(UBUS_MAPPED_IDX, UBUS_MAPPED_PHYS_BASE, UBUS_SYS_MODULE_REGISTRATION_OFFSET) #define UBUS_MAPPED_BASE BCM_IO_MAP(UBUS_MAPPED_IDX, UBUS_MAPPED_PHYS_BASE, SYS_CLK_CTRL_OFFSET) #define XRDP_BASE BCM_IO_MAP(XRDP_IDX, XRDP_PHYS_BASE, 0) #define PERF_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, 0) #define TIMR_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, TIMR_OFFSET) #define WDTIMR0_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, WDTIMR0_OFFSET) #define WDTIMR1_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, WDTIMR1_OFFSET) #define GPIO_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, GPIO_OFFSET) #define UART_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, UART_OFFSET) #define UART1_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, UART1_OFFSET) #define LED_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, LED_OFFSET) #define SOTP_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, SOTP_OFFSET) #define RNG_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, RNG_OFFSET) #define JTAG_OTP_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, JTAG_OTP_OFFSET) #define HSSPIM_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, HSSPIM_OFFSET) #define NAND_REG_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_REG_OFFSET) #define NAND_CACHE_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_CACHE_OFFSET) #define NAND_INTR_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, NAND_INTR_OFFSET) #define MDIO_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, MDIO_OFFSET) #define I2S_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, I2S_OFFSET) #define I2C_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, I2C_OFFSET) #define MISC_BASE BCM_IO_MAP(PERF_IDX, PERF_PHYS_BASE, MISC_OFFSET) #define USIM_BASE BCM_IO_MAP(USIM_IDX, USIM_PHYS_BASE, 0) #define PERF1_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, 0) #define EMMC_HOST_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_HOST_OFFSET) #define EMMC_TOP_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_TOP_OFFSET) #define EMMC_BOOT_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, EMMC_BOOT_OFFSET) #define AHB_CONTROL_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, AHB_CONTROL_OFFSET) #define PL081_DMA_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, PL081_DMA_OFFSET) #define TOP_CONTROL_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, TOP_CNTRL_OFFSET) #define I2C_2_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, I2C_2_OFFSET) #define HS_UART_BASE BCM_IO_MAP(PERF1_IDX, PERF1_PHYS_BASE, HS_UART_OFFSET) #define APM_BASE BCM_IO_MAP(PCM_IDX, PCM_PHYS_BASE, APM_CORE_OFFSET) #define PCM_BASE BCM_IO_MAP(PCM_IDX, PCM_PHYS_BASE, PCM_CORE_OFFSET) #define PCM_DMA_BASE BCM_IO_MAP(PCM_IDX, PCM_PHYS_BASE, PCM_DMA_OFFSET) #define PCM_BUS_BASE BCM_IO_MAP(PCMBUS_IDX, PCMBUS_PHYS_BASE, PCMBUS_OFFSET) #define NANDFLASH_BASE BCM_IO_MAP(NANDFLASH_IDX, NANDFLASH_PHYS_BASE, NANDFLASH_OFFSET) #define USBH_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, USBH_OFFSET) #define USBH_CFG_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, CFG_OFFSET) #define USBH_EHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, EHCI_OFFSET) #define USBH_OHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, OHCI_OFFSET) #define USBH_XHCI_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, XHCI_OFFSET) #define USBH_XHCI_EC_BASE BCM_IO_MAP(USBH_IDX, USBH_PHYS_BASE, XHCI_EC_OFFSET) #define USB_XHCI_BASE USBH_XHCI_BASE #define MST_PORT_NODE_B53_PHYS_BASE 0x83020000 #define MST_PORT_NODE_B53_SIZE 0x1000 #define MST_PORT_NODE_USB_PHYS_BASE 0x83038000 #define MST_PORT_NODE_USB_SIZE 0x1000 #define MST_PORT_NODE_PER_PHYS_BASE 0x83058000 #define MST_PORT_NODE_PER_SIZE 0x1000 #define MST_PORT_NODE_DMA0_PHYS_BASE 0x83064000 #define MST_PORT_NODE_DMA0_SIZE 0x1000 #define MST_PORT_NODE_RQ0_PHYS_BASE 0x83080000 #define MST_PORT_NODE_RQ0_SIZE 0x1000 #define MST_PORT_NODE_NATC_PHYS_BASE 0x830A0000 #define MST_PORT_NODE_NATC_SIZE 0x1000 #define MST_PORT_NODE_DQM_PHYS_BASE 0x830A4000 #define MST_PORT_NODE_DQM_SIZE 0x1000 #define MST_PORT_NODE_QM_PHYS_BASE 0x830AC000 #define MST_PORT_NODE_QM_SIZE 0x1000 #define UBUS4_COHERENCY_PORT_PHYS_BASE 0x810A0000 #define UBUS4_COHERENCY_PORT_BASE_SIZE 0x1000 #define CCI400_PHYS_BASE 0x81090000 #define CCI400_OFFSET 0x0000 #define CCI400_SIZE 0xe000 #define UBUS4_COHERENCY_PORT_PHYS_BASE 0x810A0000 #define UBUS4_COHERENCY_PORT_BASE_SIZE 0x1000 #define XRDP_RCQ_COMMON_REGS_RCQ_GENERAL_CONFIG 0xd08500 #define XRDP_RCQ_GEN_CFG \ BCM_IO_MAP(XRDP_IDX, XRDP_PHYS_BASE, \ XRDP_RCQ_COMMON_REGS_RCQ_GENERAL_CONFIG) #define XRDP_RCQ_GENERAL_DDR_CONGEST_THRESHOLD_SHIFT 4 #define XRDP_RCQ_GENERAL_PSRAM_CONGEST_THRESHOLD_SHIFT 9 #define MST_PORT_NODE_PCIE0_BASE BCM_IO_MAP(MST_PORT_NODE_PCIE0_IDX, MST_PORT_NODE_PCIE0_PHYS_BASE, 0) #define MST_PORT_NODE_PCIE2_BASE BCM_IO_MAP(MST_PORT_NODE_PCIE2_IDX, MST_PORT_NODE_PCIE2_PHYS_BASE, 0) #define MST_PORT_NODE_B53_BASE BCM_IO_MAP(MST_PORT_NODE_B53_IDX, MST_PORT_NODE_B53_PHYS_BASE, 0) #define MST_PORT_NODE_SPU_BASE BCM_IO_MAP(MST_PORT_NODE_SPU_IDX, MST_PORT_NODE_SPU_PHYS_BASE, 0) #define MST_PORT_NODE_USB_BASE BCM_IO_MAP(MST_PORT_NODE_USB_IDX, MST_PORT_NODE_USB_PHYS_BASE, 0) #define MST_PORT_NODE_PER_BASE BCM_IO_MAP(MST_PORT_NODE_PER_IDX, MST_PORT_NODE_PER_PHYS_BASE, 0) #define MST_PORT_NODE_DMA0_BASE BCM_IO_MAP(MST_PORT_NODE_DMA0_IDX, MST_PORT_NODE_DMA0_PHYS_BASE, 0) #define MST_PORT_NODE_DMA1_BASE BCM_IO_MAP(MST_PORT_NODE_DMA1_IDX, MST_PORT_NODE_DMA1_PHYS_BASE, 0) #define MST_PORT_NODE_RQ0_BASE BCM_IO_MAP(MST_PORT_NODE_RQ0_IDX, MST_PORT_NODE_RQ0_PHYS_BASE, 0) #define MST_PORT_NODE_RQ1_BASE BCM_IO_MAP(MST_PORT_NODE_RQ1_IDX, MST_PORT_NODE_RQ1_PHYS_BASE, 0) #define MST_PORT_NODE_NATC_BASE BCM_IO_MAP(MST_PORT_NODE_NATC_IDX, MST_PORT_NODE_NATC_PHYS_BASE, 0) #define MST_PORT_NODE_DQM_BASE BCM_IO_MAP(MST_PORT_NODE_DQM_IDX, MST_PORT_NODE_DQM_PHYS_BASE, 0) #define MST_PORT_NODE_QM_BASE BCM_IO_MAP(MST_PORT_NODE_QM_IDX, MST_PORT_NODE_QM_PHYS_BASE, 0) #define BIUCFG_BASE BCM_IO_MAP(BIUCFG_IDX, BIUCFG_PHYS_BASE, BIUCFG_OFFSET) #define BIUCFG_AUXBASE BCM_IO_MAP(BIUCFG_IDX, BIUCFG_PHYS_BASE, BIUCFG_AUX_OFFSET) #define UBUS_RANGE_CHK_SETUP_BASE BCM_IO_MAP(UBUS4_COHERENCY_PORT_IDX,UBUS4_COHERENCY_PORT_PHYS_BASE, 0) #define UBUS_RANGE_CHK_CFG_BASE BCM_IO_MAP(UBUS4_COHERENCY_PORT_IDX,UBUS4_COHERENCY_PORT_PHYS_BASE, 0x310) #define UBUS_COHERENCY_PORT_CFG_BASE BCM_IO_MAP(UBUS4_COHERENCY_PORT_IDX,UBUS4_COHERENCY_PORT_PHYS_BASE, 0x400) #define UBUS_COHERENCY_PORT_CFG_LUT_BASE UBUS_COHERENCY_PORT_CFG_BASE + 0 #define UBUS_COHERENCY_PORT_CFG_DEPTH_BASE UBUS_COHERENCY_PORT_CFG_BASE + 0x80 #define UBUS_COHERENCY_PORT_CFG_CBS_BASE UBUS_COHERENCY_PORT_CFG_BASE + 0x90 #define UBUS_COHERENCY_PORT_CFG_CIR_INCR_BASE UBUS_COHERENCY_PORT_CFG_BASE + 0xB0 #define UBUS_COHERENCY_PORT_CFG_REF_COUNT_BASE UBUS_COHERENCY_PORT_CFG_BASE + 0xc0 /* These block uses DT or not used by linux at all, no need to map for the legacy support */ #define GIC_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GIC_OFFSET) #define GICC_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GICC_OFFSET) #define GICD_BASE BCM_IO_NOMAP(-1, GIC_PHYS_BASE, GICD_OFFSET) #define SPIFLASH_BASE BCM_IO_NOMAP(-1, SPIFLASH_PHYS_BASE, SPIFLASH_OFFSET) #define EMMCFLASH_BASE BCM_IO_NOMAP(-1, EMMCFLASH_PHYS_BASE, EMMCFLASH_OFFSET) #define CCI400_BASE BCM_IO_NOMAP(-1, CCI400_PHYS_BASE, CCI400_OFFSET) #ifndef __ASSEMBLER__ #ifdef __BOARD_DRV_AARCH64__ // add here any legacy driver's (driver that have no device tree node) IO memory to be mapped BCM_IO_BLOCKS bcm_io_blocks[] = { {MEMC_IDX, MEMC_SIZE, MEMC_PHYS_BASE}, {PMC_IDX, PMC_SIZE, PMC_PHYS_BASE}, {PROC_MON_IDX, PROC_MON_SIZE, PROC_MON_PHYS_BASE}, {XRDP_IDX, XRDP_SIZE, XRDP_PHYS_BASE}, {UBUS_MAPPED_IDX, UBUS_MAPPED_SIZE, UBUS_MAPPED_PHYS_BASE}, {PERF_IDX, PERF_SIZE, PERF_PHYS_BASE}, {USIM_IDX, USIM_SIZE, USIM_PHYS_BASE}, {PERF1_IDX, PERF1_SIZE, PERF1_PHYS_BASE}, {NANDFLASH_IDX, NANDFLASH_SIZE, NANDFLASH_PHYS_BASE}, {PCM_IDX, PCM_SIZE, PCM_PHYS_BASE}, {PCMBUS_IDX, PCMBUS_SIZE, PCMBUS_PHYS_BASE}, {WAN_IDX, WAN_SIZE, WAN_PHYS_BASE}, {NGPON2_IDX, NGPON2_SIZE, NGPON2_PHYS_BASE}, {USBH_IDX, USBH_SIZE, USBH_PHYS_BASE}, {MST_PORT_NODE_PCIE0_IDX, MST_PORT_NODE_PCIE0_SIZE, MST_PORT_NODE_PCIE0_PHYS_BASE}, {MST_PORT_NODE_PCIE2_IDX, MST_PORT_NODE_PCIE2_SIZE, MST_PORT_NODE_PCIE2_PHYS_BASE}, {MST_PORT_NODE_B53_IDX, MST_PORT_NODE_B53_SIZE, MST_PORT_NODE_B53_PHYS_BASE}, {MST_PORT_NODE_USB_IDX, MST_PORT_NODE_USB_SIZE, MST_PORT_NODE_USB_PHYS_BASE}, {MST_PORT_NODE_PER_IDX, MST_PORT_NODE_PER_SIZE, MST_PORT_NODE_PER_PHYS_BASE}, {MST_PORT_NODE_DMA0_IDX, MST_PORT_NODE_DMA_SIZE, MST_PORT_NODE_DMA0_PHYS_BASE}, {MST_PORT_NODE_DMA1_IDX, MST_PORT_NODE_DMA_SIZE, MST_PORT_NODE_DMA1_PHYS_BASE}, {MST_PORT_NODE_RQ0_IDX, MST_PORT_NODE_RQ_SIZE, MST_PORT_NODE_RQ0_PHYS_BASE}, {MST_PORT_NODE_RQ1_IDX, MST_PORT_NODE_RQ_SIZE, MST_PORT_NODE_RQ1_PHYS_BASE}, {MST_PORT_NODE_NATC_IDX, MST_PORT_NODE_NATC_SIZE, MST_PORT_NODE_NATC_PHYS_BASE}, {MST_PORT_NODE_DQM_IDX, MST_PORT_NODE_DQM_SIZE, MST_PORT_NODE_DQM_PHYS_BASE}, {MST_PORT_NODE_QM_IDX, MST_PORT_NODE_QM_SIZE, MST_PORT_NODE_QM_PHYS_BASE}, {UBUS4_COHERENCY_PORT_IDX, UBUS4_COHERENCY_PORT_BASE_SIZE, UBUS4_COHERENCY_PORT_PHYS_BASE}, {BIUCFG_IDX, BIUCFG_SIZE, BIUCFG_PHYS_BASE} }; unsigned long bcm_io_block_address[LAST_IDX]; #else extern BCM_IO_BLOCKS bcm_io_blocks[]; extern unsigned long bcm_io_block_address[]; #endif typedef struct EmmcHostCtrl{ uint32 emmc_host_sdma; uint32 emmc_host_block; /*************************************************************************** *BLOCK - Block Reset and Count Register ***************************************************************************/ /* EMMC_HOSTIF :: BLOCK :: TRANSFER_BLOCK_COUNT [31:16] */ #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_COUNT_MASK 0xffff0000 #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_COUNT_SHIFT 16 #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_COUNT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: BLOCK :: TRANSFER_BLOCK_SIZE_MSB [15:15] */ #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_MSB_MASK 0x00008000 #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_MSB_SHIFT 15 #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_MSB_DEFAULT 0x00000000 /* EMMC_HOSTIF :: BLOCK :: HOST_BUFFER_SIZE [14:12] */ #define EMMC_HOSTIF_BLOCK_HOST_BUFFER_SIZE_MASK 0x00007000 #define EMMC_HOSTIF_BLOCK_HOST_BUFFER_SIZE_SHIFT 12 #define EMMC_HOSTIF_BLOCK_HOST_BUFFER_SIZE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: BLOCK :: TRANSFER_BLOCK_SIZE [11:00] */ #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_MASK 0x00000fff #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_SHIFT 0 #define EMMC_HOSTIF_BLOCK_TRANSFER_BLOCK_SIZE_DEFAULT 0x00000000 uint32 emmc_host_argument; /* 8 */ uint32 emmc_host_cmd_mode; /*************************************************************************** *CMD_MODE - Command and Mode Register ***************************************************************************/ /* EMMC_HOSTIF :: CMD_MODE :: reserved0 [31:30] */ #define EMMC_HOSTIF_CMD_MODE_reserved0_MASK 0xc0000000 #define EMMC_HOSTIF_CMD_MODE_reserved0_SHIFT 30 /* EMMC_HOSTIF :: CMD_MODE :: CMD_INDEX [29:24] */ #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_MASK 0x3f000000 #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_SHIFT 24 #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: CMD_TYPE [23:22] */ #define EMMC_HOSTIF_CMD_MODE_CMD_TYPE_MASK 0x00c00000 #define EMMC_HOSTIF_CMD_MODE_CMD_TYPE_SHIFT 22 #define EMMC_HOSTIF_CMD_MODE_CMD_TYPE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: DATA_PRESENT [21:21] */ #define EMMC_HOSTIF_CMD_MODE_DATA_PRESENT_MASK 0x00200000 #define EMMC_HOSTIF_CMD_MODE_DATA_PRESENT_SHIFT 21 #define EMMC_HOSTIF_CMD_MODE_DATA_PRESENT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: CMD_INDEX_CHECK [20:20] */ #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_CHECK_MASK 0x00100000 #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_CHECK_SHIFT 20 #define EMMC_HOSTIF_CMD_MODE_CMD_INDEX_CHECK_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: CMD_CRC_CHECK [19:19] */ #define EMMC_HOSTIF_CMD_MODE_CMD_CRC_CHECK_MASK 0x00080000 #define EMMC_HOSTIF_CMD_MODE_CMD_CRC_CHECK_SHIFT 19 #define EMMC_HOSTIF_CMD_MODE_CMD_CRC_CHECK_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: reserved1 [18:18] */ #define EMMC_HOSTIF_CMD_MODE_reserved1_MASK 0x00040000 #define EMMC_HOSTIF_CMD_MODE_reserved1_SHIFT 18 /* EMMC_HOSTIF :: CMD_MODE :: RESPONSE_TYPE [17:16] */ #define EMMC_HOSTIF_CMD_MODE_RESPONSE_TYPE_MASK 0x00030000 #define EMMC_HOSTIF_CMD_MODE_RESPONSE_TYPE_SHIFT 16 #define EMMC_HOSTIF_CMD_MODE_RESPONSE_TYPE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: reserved2 [15:07] */ #define EMMC_HOSTIF_CMD_MODE_reserved2_MASK 0x0000ff80 #define EMMC_HOSTIF_CMD_MODE_reserved2_SHIFT 7 /* EMMC_HOSTIF :: CMD_MODE :: reserved_for_eco3 [06:06] */ #define EMMC_HOSTIF_CMD_MODE_reserved_for_eco3_MASK 0x00000040 #define EMMC_HOSTIF_CMD_MODE_reserved_for_eco3_SHIFT 6 #define EMMC_HOSTIF_CMD_MODE_reserved_for_eco3_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: MULTI_BLOCK [05:05] */ #define EMMC_HOSTIF_CMD_MODE_MULTI_BLOCK_MASK 0x00000020 #define EMMC_HOSTIF_CMD_MODE_MULTI_BLOCK_SHIFT 5 #define EMMC_HOSTIF_CMD_MODE_MULTI_BLOCK_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: TRANFER_WRITE [04:04] */ #define EMMC_HOSTIF_CMD_MODE_TRANFER_WRITE_MASK 0x00000010 #define EMMC_HOSTIF_CMD_MODE_TRANFER_WRITE_SHIFT 4 #define EMMC_HOSTIF_CMD_MODE_TRANFER_WRITE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: AUTO_CMD_ENA [03:02] */ #define EMMC_HOSTIF_CMD_MODE_AUTO_CMD_ENA_MASK 0x0000000c #define EMMC_HOSTIF_CMD_MODE_AUTO_CMD_ENA_SHIFT 2 #define EMMC_HOSTIF_CMD_MODE_AUTO_CMD_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: BLOCK_COUNT_ENABLE [01:01] */ #define EMMC_HOSTIF_CMD_MODE_BLOCK_COUNT_ENABLE_MASK 0x00000002 #define EMMC_HOSTIF_CMD_MODE_BLOCK_COUNT_ENABLE_SHIFT 1 #define EMMC_HOSTIF_CMD_MODE_BLOCK_COUNT_ENABLE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CMD_MODE :: DMA_ENABLE [00:00] */ #define EMMC_HOSTIF_CMD_MODE_DMA_ENABLE_MASK 0x00000001 #define EMMC_HOSTIF_CMD_MODE_DMA_ENABLE_SHIFT 0 #define EMMC_HOSTIF_CMD_MODE_DMA_ENABLE_DEFAULT 0x00000000 uint32 emmc_host_resp_01; /* 10 */ uint32 emmc_host_resp_23; uint32 emmc_host_resp_45; uint32 emmc_host_resp_67; uint32 emmc_host_buffdata; /* 20 */ uint32 emmc_host_state; /*************************************************************************** *STATE - Present State of Controller ***************************************************************************/ /* EMMC_HOSTIF :: STATE :: reserved0 [31:29] */ #define EMMC_HOSTIF_STATE_reserved0_MASK 0xe0000000 #define EMMC_HOSTIF_STATE_reserved0_SHIFT 29 /* EMMC_HOSTIF :: STATE :: LINE_7TO4 [28:25] */ #define EMMC_HOSTIF_STATE_LINE_7TO4_MASK 0x1e000000 #define EMMC_HOSTIF_STATE_LINE_7TO4_SHIFT 25 #define EMMC_HOSTIF_STATE_LINE_7TO4_DEFAULT 0x0000000f /* EMMC_HOSTIF :: STATE :: LINE_CMD [24:24] */ #define EMMC_HOSTIF_STATE_LINE_CMD_MASK 0x01000000 #define EMMC_HOSTIF_STATE_LINE_CMD_SHIFT 24 #define EMMC_HOSTIF_STATE_LINE_CMD_DEFAULT 0x00000001 /* EMMC_HOSTIF :: STATE :: LINE_3TO0 [23:20] */ #define EMMC_HOSTIF_STATE_LINE_3TO0_MASK 0x00f00000 #define EMMC_HOSTIF_STATE_LINE_3TO0_SHIFT 20 #define EMMC_HOSTIF_STATE_LINE_3TO0_DEFAULT 0x0000000f /* EMMC_HOSTIF :: STATE :: WP_LEVEL [19:19] */ #define EMMC_HOSTIF_STATE_WP_LEVEL_MASK 0x00080000 #define EMMC_HOSTIF_STATE_WP_LEVEL_SHIFT 19 /* EMMC_HOSTIF :: STATE :: CD_LEVEL [18:18] */ #define EMMC_HOSTIF_STATE_CD_LEVEL_MASK 0x00040000 #define EMMC_HOSTIF_STATE_CD_LEVEL_SHIFT 18 /* EMMC_HOSTIF :: STATE :: CD_STABLE [17:17] */ #define EMMC_HOSTIF_STATE_CD_STABLE_MASK 0x00020000 #define EMMC_HOSTIF_STATE_CD_STABLE_SHIFT 17 /* EMMC_HOSTIF :: STATE :: CARD_INSERTED [16:16] */ #define EMMC_HOSTIF_STATE_CARD_INSERTED_MASK 0x00010000 #define EMMC_HOSTIF_STATE_CARD_INSERTED_SHIFT 16 /* EMMC_HOSTIF :: STATE :: reserved1 [15:12] */ #define EMMC_HOSTIF_STATE_reserved1_MASK 0x0000f000 #define EMMC_HOSTIF_STATE_reserved1_SHIFT 12 /* EMMC_HOSTIF :: STATE :: BUFF_RDEN [11:11] */ #define EMMC_HOSTIF_STATE_BUFF_RDEN_MASK 0x00000800 #define EMMC_HOSTIF_STATE_BUFF_RDEN_SHIFT 11 #define EMMC_HOSTIF_STATE_BUFF_RDEN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: BUFF_WREN [10:10] */ #define EMMC_HOSTIF_STATE_BUFF_WREN_MASK 0x00000400 #define EMMC_HOSTIF_STATE_BUFF_WREN_SHIFT 10 #define EMMC_HOSTIF_STATE_BUFF_WREN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: RD_ACTIVE [09:09] */ #define EMMC_HOSTIF_STATE_RD_ACTIVE_MASK 0x00000200 #define EMMC_HOSTIF_STATE_RD_ACTIVE_SHIFT 9 #define EMMC_HOSTIF_STATE_RD_ACTIVE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: WR_ACTIVE [08:08] */ #define EMMC_HOSTIF_STATE_WR_ACTIVE_MASK 0x00000100 #define EMMC_HOSTIF_STATE_WR_ACTIVE_SHIFT 8 #define EMMC_HOSTIF_STATE_WR_ACTIVE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: reserved2 [07:04] */ #define EMMC_HOSTIF_STATE_reserved2_MASK 0x000000f0 #define EMMC_HOSTIF_STATE_reserved2_SHIFT 4 /* EMMC_HOSTIF :: STATE :: RE_TUNING_REQUEST [03:03] */ #define EMMC_HOSTIF_STATE_RE_TUNING_REQUEST_MASK 0x00000008 #define EMMC_HOSTIF_STATE_RE_TUNING_REQUEST_SHIFT 3 #define EMMC_HOSTIF_STATE_RE_TUNING_REQUEST_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: DAT_ACTIVE [02:02] */ #define EMMC_HOSTIF_STATE_DAT_ACTIVE_MASK 0x00000004 #define EMMC_HOSTIF_STATE_DAT_ACTIVE_SHIFT 2 #define EMMC_HOSTIF_STATE_DAT_ACTIVE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: CMD_INHIBIT_DAT [01:01] */ #define EMMC_HOSTIF_STATE_CMD_INHIBIT_DAT_MASK 0x00000002 #define EMMC_HOSTIF_STATE_CMD_INHIBIT_DAT_SHIFT 1 #define EMMC_HOSTIF_STATE_CMD_INHIBIT_DAT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: STATE :: CMD_INHIBIT_CMD [00:00] */ #define EMMC_HOSTIF_STATE_CMD_INHIBIT_CMD_MASK 0x00000001 #define EMMC_HOSTIF_STATE_CMD_INHIBIT_CMD_SHIFT 0 #define EMMC_HOSTIF_STATE_CMD_INHIBIT_CMD_DEFAULT 0x00000000 uint32 emmc_host_ctrl_set0; /*************************************************************************** *CTRL_SET0 - SD Standard Control Registers for Host, Power, BlockGap, WakeUp ***************************************************************************/ /* EMMC_HOSTIF :: CTRL_SET0 :: reserved0 [31:27] */ #define EMMC_HOSTIF_CTRL_SET0_reserved0_MASK 0xf8000000 #define EMMC_HOSTIF_CTRL_SET0_reserved0_SHIFT 27 /* EMMC_HOSTIF :: CTRL_SET0 :: WAKE_ON_REMOVAL [26:26] */ #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_REMOVAL_MASK 0x04000000 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_REMOVAL_SHIFT 26 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_REMOVAL_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: WAKE_ON_INSERTION [25:25] */ #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INSERTION_MASK 0x02000000 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INSERTION_SHIFT 25 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INSERTION_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: WAKE_ON_INTERRUPT [24:24] */ #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INTERRUPT_MASK 0x01000000 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INTERRUPT_SHIFT 24 #define EMMC_HOSTIF_CTRL_SET0_WAKE_ON_INTERRUPT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: BOOT_ACK [23:23] */ #define EMMC_HOSTIF_CTRL_SET0_BOOT_ACK_MASK 0x00800000 #define EMMC_HOSTIF_CTRL_SET0_BOOT_ACK_SHIFT 23 #define EMMC_HOSTIF_CTRL_SET0_BOOT_ACK_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: ALT_BOOT_EN [22:22] */ #define EMMC_HOSTIF_CTRL_SET0_ALT_BOOT_EN_MASK 0x00400000 #define EMMC_HOSTIF_CTRL_SET0_ALT_BOOT_EN_SHIFT 22 #define EMMC_HOSTIF_CTRL_SET0_ALT_BOOT_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: BOOT_EN [21:21] */ #define EMMC_HOSTIF_CTRL_SET0_BOOT_EN_MASK 0x00200000 #define EMMC_HOSTIF_CTRL_SET0_BOOT_EN_SHIFT 21 #define EMMC_HOSTIF_CTRL_SET0_BOOT_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: SPI_MODE [20:20] */ #define EMMC_HOSTIF_CTRL_SET0_SPI_MODE_MASK 0x00100000 #define EMMC_HOSTIF_CTRL_SET0_SPI_MODE_SHIFT 20 #define EMMC_HOSTIF_CTRL_SET0_SPI_MODE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: INT_AT_BLOCK_GAP [19:19] */ #define EMMC_HOSTIF_CTRL_SET0_INT_AT_BLOCK_GAP_MASK 0x00080000 #define EMMC_HOSTIF_CTRL_SET0_INT_AT_BLOCK_GAP_SHIFT 19 #define EMMC_HOSTIF_CTRL_SET0_INT_AT_BLOCK_GAP_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: READ_WAIT_CTRL [18:18] */ #define EMMC_HOSTIF_CTRL_SET0_READ_WAIT_CTRL_MASK 0x00040000 #define EMMC_HOSTIF_CTRL_SET0_READ_WAIT_CTRL_SHIFT 18 #define EMMC_HOSTIF_CTRL_SET0_READ_WAIT_CTRL_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: CONTINUE_REQUESTS [17:17] */ #define EMMC_HOSTIF_CTRL_SET0_CONTINUE_REQUESTS_MASK 0x00020000 #define EMMC_HOSTIF_CTRL_SET0_CONTINUE_REQUESTS_SHIFT 17 #define EMMC_HOSTIF_CTRL_SET0_CONTINUE_REQUESTS_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: STOP_AT_BLOCK_GAP [16:16] */ #define EMMC_HOSTIF_CTRL_SET0_STOP_AT_BLOCK_GAP_MASK 0x00010000 #define EMMC_HOSTIF_CTRL_SET0_STOP_AT_BLOCK_GAP_SHIFT 16 #define EMMC_HOSTIF_CTRL_SET0_STOP_AT_BLOCK_GAP_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: reserved1 [15:13] */ #define EMMC_HOSTIF_CTRL_SET0_reserved1_MASK 0x0000e000 #define EMMC_HOSTIF_CTRL_SET0_reserved1_SHIFT 13 /* EMMC_HOSTIF :: CTRL_SET0 :: HW_RESET [12:12] */ #define EMMC_HOSTIF_CTRL_SET0_HW_RESET_MASK 0x00001000 #define EMMC_HOSTIF_CTRL_SET0_HW_RESET_SHIFT 12 #define EMMC_HOSTIF_CTRL_SET0_HW_RESET_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: SD_BUS_VOLTAGE_SELECT [11:09] */ #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_VOLTAGE_SELECT_MASK 0x00000e00 #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_VOLTAGE_SELECT_SHIFT 9 #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_VOLTAGE_SELECT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: SD_BUS_POWER [08:08] */ #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_POWER_MASK 0x00000100 #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_POWER_SHIFT 8 #define EMMC_HOSTIF_CTRL_SET0_SD_BUS_POWER_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: CARD_DETECT_SELECT [07:07] */ #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_SELECT_MASK 0x00000080 #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_SELECT_SHIFT 7 #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_SELECT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: CARD_DETECT_TEST [06:06] */ #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_TEST_MASK 0x00000040 #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_TEST_SHIFT 6 #define EMMC_HOSTIF_CTRL_SET0_CARD_DETECT_TEST_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: SD_8BIT_MODE [05:05] */ #define EMMC_HOSTIF_CTRL_SET0_SD_8BIT_MODE_MASK 0x00000020 #define EMMC_HOSTIF_CTRL_SET0_SD_8BIT_MODE_SHIFT 5 #define EMMC_HOSTIF_CTRL_SET0_SD_8BIT_MODE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: DMA_SELECT [04:03] */ #define EMMC_HOSTIF_CTRL_SET0_DMA_SELECT_MASK 0x00000018 #define EMMC_HOSTIF_CTRL_SET0_DMA_SELECT_SHIFT 3 #define EMMC_HOSTIF_CTRL_SET0_DMA_SELECT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: HIGH_SPEED_ENABLE [02:02] */ #define EMMC_HOSTIF_CTRL_SET0_HIGH_SPEED_ENABLE_MASK 0x00000004 #define EMMC_HOSTIF_CTRL_SET0_HIGH_SPEED_ENABLE_SHIFT 2 #define EMMC_HOSTIF_CTRL_SET0_HIGH_SPEED_ENABLE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: SD_4BIT_MODE [01:01] */ #define EMMC_HOSTIF_CTRL_SET0_SD_4BIT_MODE_MASK 0x00000002 #define EMMC_HOSTIF_CTRL_SET0_SD_4BIT_MODE_SHIFT 1 #define EMMC_HOSTIF_CTRL_SET0_SD_4BIT_MODE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET0 :: LED_CONTROL [00:00] */ #define EMMC_HOSTIF_CTRL_SET0_LED_CONTROL_MASK 0x00000001 #define EMMC_HOSTIF_CTRL_SET0_LED_CONTROL_SHIFT 0 #define EMMC_HOSTIF_CTRL_SET0_LED_CONTROL_DEFAULT 0x00000000 uint32 emmc_host_ctrl_set1; /*************************************************************************** *CTRL_SET1 - SD Standard Control Registers for Clock, Timeout, Resets ***************************************************************************/ /* EMMC_HOSTIF :: CTRL_SET1 :: reserved0 [31:27] */ #define EMMC_HOSTIF_CTRL_SET1_reserved0_MASK 0xf8000000 #define EMMC_HOSTIF_CTRL_SET1_reserved0_SHIFT 27 /* EMMC_HOSTIF :: CTRL_SET1 :: SOFT_RESET_DAT [26:26] */ #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_DAT_MASK 0x04000000 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_DAT_SHIFT 26 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_DAT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: SOFT_RESET_CMD [25:25] */ #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CMD_MASK 0x02000000 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CMD_SHIFT 25 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CMD_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: SOFT_RESET_CORE [24:24] */ #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CORE_MASK 0x01000000 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CORE_SHIFT 24 #define EMMC_HOSTIF_CTRL_SET1_SOFT_RESET_CORE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: reserved1 [23:20] */ #define EMMC_HOSTIF_CTRL_SET1_reserved1_MASK 0x00f00000 #define EMMC_HOSTIF_CTRL_SET1_reserved1_SHIFT 20 /* EMMC_HOSTIF :: CTRL_SET1 :: TIMEOUT_COUNT [19:16] */ #define EMMC_HOSTIF_CTRL_SET1_TIMEOUT_COUNT_MASK 0x000f0000 #define EMMC_HOSTIF_CTRL_SET1_TIMEOUT_COUNT_SHIFT 16 #define EMMC_HOSTIF_CTRL_SET1_TIMEOUT_COUNT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: FREQ_CTRL [15:08] */ #define EMMC_HOSTIF_CTRL_SET1_FREQ_CTRL_MASK 0x0000ff00 #define EMMC_HOSTIF_CTRL_SET1_FREQ_CTRL_SHIFT 8 #define EMMC_HOSTIF_CTRL_SET1_FREQ_CTRL_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: MS_CLK_FREQ [07:06] */ #define EMMC_HOSTIF_CTRL_SET1_MS_CLK_FREQ_MASK 0x000000c0 #define EMMC_HOSTIF_CTRL_SET1_MS_CLK_FREQ_SHIFT 6 #define EMMC_HOSTIF_CTRL_SET1_MS_CLK_FREQ_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: CLK_GEN_SEL [05:05] */ #define EMMC_HOSTIF_CTRL_SET1_CLK_GEN_SEL_MASK 0x00000020 #define EMMC_HOSTIF_CTRL_SET1_CLK_GEN_SEL_SHIFT 5 #define EMMC_HOSTIF_CTRL_SET1_CLK_GEN_SEL_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: reserved2 [04:03] */ #define EMMC_HOSTIF_CTRL_SET1_reserved2_MASK 0x00000018 #define EMMC_HOSTIF_CTRL_SET1_reserved2_SHIFT 3 /* EMMC_HOSTIF :: CTRL_SET1 :: SD_CLK_ENA [02:02] */ #define EMMC_HOSTIF_CTRL_SET1_SD_CLK_ENA_MASK 0x00000004 #define EMMC_HOSTIF_CTRL_SET1_SD_CLK_ENA_SHIFT 2 #define EMMC_HOSTIF_CTRL_SET1_SD_CLK_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: INTERNAL_CLK_STABLE [01:01] */ #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_STABLE_MASK 0x00000002 #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_STABLE_SHIFT 1 #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_STABLE_DEFAULT 0x00000000 /* EMMC_HOSTIF :: CTRL_SET1 :: INTERNAL_CLK_ENA [00:00] */ #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_ENA_MASK 0x00000001 #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_ENA_SHIFT 0 #define EMMC_HOSTIF_CTRL_SET1_INTERNAL_CLK_ENA_DEFAULT 0x00000000 uint32 emmc_host_int_status; /* 30 */ /*************************************************************************** *INT_STATUS - Interrupt Status for Normal and Error conditions ***************************************************************************/ /* EMMC_HOSTIF :: INT_STATUS :: reserved0 [31:29] */ #define EMMC_HOSTIF_INT_STATUS_reserved0_MASK 0xe0000000 #define EMMC_HOSTIF_INT_STATUS_reserved0_SHIFT 29 /* EMMC_HOSTIF :: INT_STATUS :: TARGET_RESP_ERR_INT [28:28] */ #define EMMC_HOSTIF_INT_STATUS_TARGET_RESP_ERR_INT_MASK 0x10000000 #define EMMC_HOSTIF_INT_STATUS_TARGET_RESP_ERR_INT_SHIFT 28 #define EMMC_HOSTIF_INT_STATUS_TARGET_RESP_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: reserved1 [27:27] */ #define EMMC_HOSTIF_INT_STATUS_reserved1_MASK 0x08000000 #define EMMC_HOSTIF_INT_STATUS_reserved1_SHIFT 27 /* EMMC_HOSTIF :: INT_STATUS :: TUNE_ERR [26:26] */ #define EMMC_HOSTIF_INT_STATUS_TUNE_ERR_MASK 0x04000000 #define EMMC_HOSTIF_INT_STATUS_TUNE_ERR_SHIFT 26 #define EMMC_HOSTIF_INT_STATUS_TUNE_ERR_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: ADMA_ERR_INT [25:25] */ #define EMMC_HOSTIF_INT_STATUS_ADMA_ERR_INT_MASK 0x02000000 #define EMMC_HOSTIF_INT_STATUS_ADMA_ERR_INT_SHIFT 25 #define EMMC_HOSTIF_INT_STATUS_ADMA_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: AUTO_CMD_ERR_INT [24:24] */ #define EMMC_HOSTIF_INT_STATUS_AUTO_CMD_ERR_INT_MASK 0x01000000 #define EMMC_HOSTIF_INT_STATUS_AUTO_CMD_ERR_INT_SHIFT 24 #define EMMC_HOSTIF_INT_STATUS_AUTO_CMD_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CURRENT_LIMIT_ERR_INT [23:23] */ #define EMMC_HOSTIF_INT_STATUS_CURRENT_LIMIT_ERR_INT_MASK 0x00800000 #define EMMC_HOSTIF_INT_STATUS_CURRENT_LIMIT_ERR_INT_SHIFT 23 #define EMMC_HOSTIF_INT_STATUS_CURRENT_LIMIT_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: DATA_END_BIT_ERR_INT [22:22] */ #define EMMC_HOSTIF_INT_STATUS_DATA_END_BIT_ERR_INT_MASK 0x00400000 #define EMMC_HOSTIF_INT_STATUS_DATA_END_BIT_ERR_INT_SHIFT 22 #define EMMC_HOSTIF_INT_STATUS_DATA_END_BIT_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: DATA_CRC_ERR_INT [21:21] */ #define EMMC_HOSTIF_INT_STATUS_DATA_CRC_ERR_INT_MASK 0x00200000 #define EMMC_HOSTIF_INT_STATUS_DATA_CRC_ERR_INT_SHIFT 21 #define EMMC_HOSTIF_INT_STATUS_DATA_CRC_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: DATA_TIMEOUT_ERR_INT [20:20] */ #define EMMC_HOSTIF_INT_STATUS_DATA_TIMEOUT_ERR_INT_MASK 0x00100000 #define EMMC_HOSTIF_INT_STATUS_DATA_TIMEOUT_ERR_INT_SHIFT 20 #define EMMC_HOSTIF_INT_STATUS_DATA_TIMEOUT_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CMD_INDEX_ERR_INT [19:19] */ #define EMMC_HOSTIF_INT_STATUS_CMD_INDEX_ERR_INT_MASK 0x00080000 #define EMMC_HOSTIF_INT_STATUS_CMD_INDEX_ERR_INT_SHIFT 19 #define EMMC_HOSTIF_INT_STATUS_CMD_INDEX_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CMD_END_BIT_ERR_INT [18:18] */ #define EMMC_HOSTIF_INT_STATUS_CMD_END_BIT_ERR_INT_MASK 0x00040000 #define EMMC_HOSTIF_INT_STATUS_CMD_END_BIT_ERR_INT_SHIFT 18 #define EMMC_HOSTIF_INT_STATUS_CMD_END_BIT_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CMD_CRC_ERR_INT [17:17] */ #define EMMC_HOSTIF_INT_STATUS_CMD_CRC_ERR_INT_MASK 0x00020000 #define EMMC_HOSTIF_INT_STATUS_CMD_CRC_ERR_INT_SHIFT 17 #define EMMC_HOSTIF_INT_STATUS_CMD_CRC_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CMD_TIMEOUT_ERR_INT [16:16] */ #define EMMC_HOSTIF_INT_STATUS_CMD_TIMEOUT_ERR_INT_MASK 0x00010000 #define EMMC_HOSTIF_INT_STATUS_CMD_TIMEOUT_ERR_INT_SHIFT 16 #define EMMC_HOSTIF_INT_STATUS_CMD_TIMEOUT_ERR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: ERROR_INT [15:15] */ #define EMMC_HOSTIF_INT_STATUS_ERROR_INT_MASK 0x00008000 #define EMMC_HOSTIF_INT_STATUS_ERROR_INT_SHIFT 15 #define EMMC_HOSTIF_INT_STATUS_ERROR_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: BOOT_TERM_INT [14:14] */ #define EMMC_HOSTIF_INT_STATUS_BOOT_TERM_INT_MASK 0x00004000 #define EMMC_HOSTIF_INT_STATUS_BOOT_TERM_INT_SHIFT 14 #define EMMC_HOSTIF_INT_STATUS_BOOT_TERM_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: BOOT_ACK_RCV_INT [13:13] */ #define EMMC_HOSTIF_INT_STATUS_BOOT_ACK_RCV_INT_MASK 0x00002000 #define EMMC_HOSTIF_INT_STATUS_BOOT_ACK_RCV_INT_SHIFT 13 #define EMMC_HOSTIF_INT_STATUS_BOOT_ACK_RCV_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: RETUNE_EVENT [12:12] */ #define EMMC_HOSTIF_INT_STATUS_RETUNE_EVENT_MASK 0x00001000 #define EMMC_HOSTIF_INT_STATUS_RETUNE_EVENT_SHIFT 12 #define EMMC_HOSTIF_INT_STATUS_RETUNE_EVENT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: INT_C [11:11] */ #define EMMC_HOSTIF_INT_STATUS_INT_C_MASK 0x00000800 #define EMMC_HOSTIF_INT_STATUS_INT_C_SHIFT 11 #define EMMC_HOSTIF_INT_STATUS_INT_C_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: INT_B [10:10] */ #define EMMC_HOSTIF_INT_STATUS_INT_B_MASK 0x00000400 #define EMMC_HOSTIF_INT_STATUS_INT_B_SHIFT 10 #define EMMC_HOSTIF_INT_STATUS_INT_B_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: INT_A [09:09] */ #define EMMC_HOSTIF_INT_STATUS_INT_A_MASK 0x00000200 #define EMMC_HOSTIF_INT_STATUS_INT_A_SHIFT 9 #define EMMC_HOSTIF_INT_STATUS_INT_A_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CARD_INT [08:08] */ #define EMMC_HOSTIF_INT_STATUS_CARD_INT_MASK 0x00000100 #define EMMC_HOSTIF_INT_STATUS_CARD_INT_SHIFT 8 #define EMMC_HOSTIF_INT_STATUS_CARD_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CAR_REMOVAL_INT [07:07] */ #define EMMC_HOSTIF_INT_STATUS_CAR_REMOVAL_INT_MASK 0x00000080 #define EMMC_HOSTIF_INT_STATUS_CAR_REMOVAL_INT_SHIFT 7 #define EMMC_HOSTIF_INT_STATUS_CAR_REMOVAL_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: CAR_INSERT_INT [06:06] */ #define EMMC_HOSTIF_INT_STATUS_CAR_INSERT_INT_MASK 0x00000040 #define EMMC_HOSTIF_INT_STATUS_CAR_INSERT_INT_SHIFT 6 #define EMMC_HOSTIF_INT_STATUS_CAR_INSERT_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: BUFFER_READ_INT [05:05] */ #define EMMC_HOSTIF_INT_STATUS_BUFFER_READ_INT_MASK 0x00000020 #define EMMC_HOSTIF_INT_STATUS_BUFFER_READ_INT_SHIFT 5 #define EMMC_HOSTIF_INT_STATUS_BUFFER_READ_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: BUFFER_WRITE_INT [04:04] */ #define EMMC_HOSTIF_INT_STATUS_BUFFER_WRITE_INT_MASK 0x00000010 #define EMMC_HOSTIF_INT_STATUS_BUFFER_WRITE_INT_SHIFT 4 #define EMMC_HOSTIF_INT_STATUS_BUFFER_WRITE_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: DMA_INT [03:03] */ #define EMMC_HOSTIF_INT_STATUS_DMA_INT_MASK 0x00000008 #define EMMC_HOSTIF_INT_STATUS_DMA_INT_SHIFT 3 #define EMMC_HOSTIF_INT_STATUS_DMA_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: BLOCK_GAP_INT [02:02] */ #define EMMC_HOSTIF_INT_STATUS_BLOCK_GAP_INT_MASK 0x00000004 #define EMMC_HOSTIF_INT_STATUS_BLOCK_GAP_INT_SHIFT 2 #define EMMC_HOSTIF_INT_STATUS_BLOCK_GAP_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: TRANSFER_COMPLETE_INT [01:01] */ #define EMMC_HOSTIF_INT_STATUS_TRANSFER_COMPLETE_INT_MASK 0x00000002 #define EMMC_HOSTIF_INT_STATUS_TRANSFER_COMPLETE_INT_SHIFT 1 #define EMMC_HOSTIF_INT_STATUS_TRANSFER_COMPLETE_INT_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS :: COMMAND_COMPLETE_INT [00:00] */ #define EMMC_HOSTIF_INT_STATUS_COMMAND_COMPLETE_INT_MASK 0x00000001 #define EMMC_HOSTIF_INT_STATUS_COMMAND_COMPLETE_INT_SHIFT 0 #define EMMC_HOSTIF_INT_STATUS_COMMAND_COMPLETE_INT_DEFAULT 0x00000000 uint32 emmc_host_int_status_ena; /*************************************************************************** *INT_STATUS_ENA - Interrupt Enables for Normal and Error conditions ***************************************************************************/ /* EMMC_HOSTIF :: INT_STATUS_ENA :: reserved0 [31:30] */ #define EMMC_HOSTIF_INT_STATUS_ENA_reserved0_MASK 0xc0000000 #define EMMC_HOSTIF_INT_STATUS_ENA_reserved0_SHIFT 30 /* EMMC_HOSTIF :: INT_STATUS_ENA :: reserved_for_eco1 [29:29] */ #define EMMC_HOSTIF_INT_STATUS_ENA_reserved_for_eco1_MASK 0x20000000 #define EMMC_HOSTIF_INT_STATUS_ENA_reserved_for_eco1_SHIFT 29 #define EMMC_HOSTIF_INT_STATUS_ENA_reserved_for_eco1_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: TARGET_RESP_ERR_INT_ENA [28:28] */ #define EMMC_HOSTIF_INT_STATUS_ENA_TARGET_RESP_ERR_INT_ENA_MASK 0x10000000 #define EMMC_HOSTIF_INT_STATUS_ENA_TARGET_RESP_ERR_INT_ENA_SHIFT 28 #define EMMC_HOSTIF_INT_STATUS_ENA_TARGET_RESP_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: reserved2 [27:27] */ #define EMMC_HOSTIF_INT_STATUS_ENA_reserved2_MASK 0x08000000 #define EMMC_HOSTIF_INT_STATUS_ENA_reserved2_SHIFT 27 /* EMMC_HOSTIF :: INT_STATUS_ENA :: TUNE_ERR_STAT_EN [26:26] */ #define EMMC_HOSTIF_INT_STATUS_ENA_TUNE_ERR_STAT_EN_MASK 0x04000000 #define EMMC_HOSTIF_INT_STATUS_ENA_TUNE_ERR_STAT_EN_SHIFT 26 #define EMMC_HOSTIF_INT_STATUS_ENA_TUNE_ERR_STAT_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: ADMA_ERR_INT_ENA [25:25] */ #define EMMC_HOSTIF_INT_STATUS_ENA_ADMA_ERR_INT_ENA_MASK 0x02000000 #define EMMC_HOSTIF_INT_STATUS_ENA_ADMA_ERR_INT_ENA_SHIFT 25 #define EMMC_HOSTIF_INT_STATUS_ENA_ADMA_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: AUTO_CMD12_ERR_INT_ENA [24:24] */ #define EMMC_HOSTIF_INT_STATUS_ENA_AUTO_CMD12_ERR_INT_ENA_MASK 0x01000000 #define EMMC_HOSTIF_INT_STATUS_ENA_AUTO_CMD12_ERR_INT_ENA_SHIFT 24 #define EMMC_HOSTIF_INT_STATUS_ENA_AUTO_CMD12_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CURRENT_LIMIT_ERR_INT_ENA [23:23] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CURRENT_LIMIT_ERR_INT_ENA_MASK 0x00800000 #define EMMC_HOSTIF_INT_STATUS_ENA_CURRENT_LIMIT_ERR_INT_ENA_SHIFT 23 #define EMMC_HOSTIF_INT_STATUS_ENA_CURRENT_LIMIT_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: DATA_END_BIT_ERR_INT_ENA [22:22] */ #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_END_BIT_ERR_INT_ENA_MASK 0x00400000 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_END_BIT_ERR_INT_ENA_SHIFT 22 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_END_BIT_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: DATA_CRC_ERR_INT_ENA [21:21] */ #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_CRC_ERR_INT_ENA_MASK 0x00200000 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_CRC_ERR_INT_ENA_SHIFT 21 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_CRC_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: DATA_TIMEOUT_ERR_INT_ENA [20:20] */ #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_TIMEOUT_ERR_INT_ENA_MASK 0x00100000 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_TIMEOUT_ERR_INT_ENA_SHIFT 20 #define EMMC_HOSTIF_INT_STATUS_ENA_DATA_TIMEOUT_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CMD_INDEX_ERR_INT_ENA [19:19] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_INDEX_ERR_INT_ENA_MASK 0x00080000 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_INDEX_ERR_INT_ENA_SHIFT 19 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_INDEX_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CMD_END_BIT_ERR_INT_ENA [18:18] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_END_BIT_ERR_INT_ENA_MASK 0x00040000 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_END_BIT_ERR_INT_ENA_SHIFT 18 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_END_BIT_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CMD_CRC_ERR_INT_ENA [17:17] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_CRC_ERR_INT_ENA_MASK 0x00020000 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_CRC_ERR_INT_ENA_SHIFT 17 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_CRC_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CMD_TIMEOUT_ERR_INT_ENA [16:16] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_TIMEOUT_ERR_INT_ENA_MASK 0x00010000 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_TIMEOUT_ERR_INT_ENA_SHIFT 16 #define EMMC_HOSTIF_INT_STATUS_ENA_CMD_TIMEOUT_ERR_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: reserved3 [15:15] */ #define EMMC_HOSTIF_INT_STATUS_ENA_reserved3_MASK 0x00008000 #define EMMC_HOSTIF_INT_STATUS_ENA_reserved3_SHIFT 15 /* EMMC_HOSTIF :: INT_STATUS_ENA :: BOOT_TERM_EN [14:14] */ #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_TERM_EN_MASK 0x00004000 #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_TERM_EN_SHIFT 14 #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_TERM_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: BOOT_ACK_RCV_EN [13:13] */ #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_ACK_RCV_EN_MASK 0x00002000 #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_ACK_RCV_EN_SHIFT 13 #define EMMC_HOSTIF_INT_STATUS_ENA_BOOT_ACK_RCV_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: RETUNE_EVENT_EN [12:12] */ #define EMMC_HOSTIF_INT_STATUS_ENA_RETUNE_EVENT_EN_MASK 0x00001000 #define EMMC_HOSTIF_INT_STATUS_ENA_RETUNE_EVENT_EN_SHIFT 12 #define EMMC_HOSTIF_INT_STATUS_ENA_RETUNE_EVENT_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: INT_C_EN [11:11] */ #define EMMC_HOSTIF_INT_STATUS_ENA_INT_C_EN_MASK 0x00000800 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_C_EN_SHIFT 11 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_C_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: INT_B_EN [10:10] */ #define EMMC_HOSTIF_INT_STATUS_ENA_INT_B_EN_MASK 0x00000400 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_B_EN_SHIFT 10 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_B_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: INT_A_EN [09:09] */ #define EMMC_HOSTIF_INT_STATUS_ENA_INT_A_EN_MASK 0x00000200 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_A_EN_SHIFT 9 #define EMMC_HOSTIF_INT_STATUS_ENA_INT_A_EN_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CARD_INT_ENA [08:08] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CARD_INT_ENA_MASK 0x00000100 #define EMMC_HOSTIF_INT_STATUS_ENA_CARD_INT_ENA_SHIFT 8 #define EMMC_HOSTIF_INT_STATUS_ENA_CARD_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CAR_REMOVAL_INT_ENA [07:07] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_REMOVAL_INT_ENA_MASK 0x00000080 #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_REMOVAL_INT_ENA_SHIFT 7 #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_REMOVAL_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: CAR_INSERT_INT_ENA [06:06] */ #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_INSERT_INT_ENA_MASK 0x00000040 #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_INSERT_INT_ENA_SHIFT 6 #define EMMC_HOSTIF_INT_STATUS_ENA_CAR_INSERT_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: BUFFER_READ_INT_ENA [05:05] */ #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_READ_INT_ENA_MASK 0x00000020 #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_READ_INT_ENA_SHIFT 5 #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_READ_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: BUFFER_WRITE_INT_ENA [04:04] */ #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_WRITE_INT_ENA_MASK 0x00000010 #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_WRITE_INT_ENA_SHIFT 4 #define EMMC_HOSTIF_INT_STATUS_ENA_BUFFER_WRITE_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: DMA_INT_ENA [03:03] */ #define EMMC_HOSTIF_INT_STATUS_ENA_DMA_INT_ENA_MASK 0x00000008 #define EMMC_HOSTIF_INT_STATUS_ENA_DMA_INT_ENA_SHIFT 3 #define EMMC_HOSTIF_INT_STATUS_ENA_DMA_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: BLOCK_GAP_INT_ENA [02:02] */ #define EMMC_HOSTIF_INT_STATUS_ENA_BLOCK_GAP_INT_ENA_MASK 0x00000004 #define EMMC_HOSTIF_INT_STATUS_ENA_BLOCK_GAP_INT_ENA_SHIFT 2 #define EMMC_HOSTIF_INT_STATUS_ENA_BLOCK_GAP_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: TRANSFER_COMPLETE_INT_ENA [01:01] */ #define EMMC_HOSTIF_INT_STATUS_ENA_TRANSFER_COMPLETE_INT_ENA_MASK 0x00000002 #define EMMC_HOSTIF_INT_STATUS_ENA_TRANSFER_COMPLETE_INT_ENA_SHIFT 1 #define EMMC_HOSTIF_INT_STATUS_ENA_TRANSFER_COMPLETE_INT_ENA_DEFAULT 0x00000000 /* EMMC_HOSTIF :: INT_STATUS_ENA :: COMMAND_COMPLETE_INT_ENA [00:00] */ #define EMMC_HOSTIF_INT_STATUS_ENA_COMMAND_COMPLETE_INT_ENA_MASK 0x00000001 #define EMMC_HOSTIF_INT_STATUS_ENA_COMMAND_COMPLETE_INT_ENA_SHIFT 0 #define EMMC_HOSTIF_INT_STATUS_ENA_COMMAND_COMPLETE_INT_ENA_DEFAULT 0x00000000 uint32 emmc_host_int_signal_ena; uint32 emmc_host_autocmd12_stat; uint32 emmc_host_capable; /* 40 */ uint32 emmc_host_capable_1; uint32 emmc_host_pwr_capable; uint32 emmc_host_pwr_capable_rsvd; uint32 emmc_host_force_events; /* 50 */ uint32 emmc_host_adma_err_stat; uint32 emmc_host_adma_sysaddr_lo; uint32 emmc_host_adma_sysaddr_hi; uint32 emmc_host_preset_init_default; /* 60 */ uint32 emmc_host_preset_high_speed; uint32 emmc_host_preset_sdr25_50; uint32 emmc_host_preset_sdr104_ddr50; uint32 emmc_host_boot_timeout; /* 70 */ uint32 emmc_host_debug_select; uint32 emmc_host_ahb_reserved[26]; /* 78 */ uint32 emmc_host_shared_bus_ctrl; /* e0 */ uint32 emmc_host_ahb_reserved1[3]; uint32 emmc_host_spi_interrupt; /* f0 */ uint32 emmc_host_ahb_reserved2[2]; uint32 emmc_host_version_stat; /* fc */ } EmmcHostCtrl; #define EMMC_HOSTIF ((volatile EmmcHostCtrl * const) EMMC_HOST_BASE) typedef struct EmmcTopCnfg{ uint32 emmc_top_cfg_sdio_emmc_ctrl1; uint32 emmc_top_cfg_sdio_emmc_ctrl2; uint32 emmc_top_cfg_tp_out_sel; uint32 emmc_top_cfg_cap_reg_override; uint32 emmc_top_cfg_cap_reg0; /* 10 */ uint32 emmc_top_cfg_cap_reg1; uint32 emmc_top_cfg_preset1; uint32 emmc_top_cfg_preset2; uint32 emmc_top_cfg_preset3; /* 20 */ uint32 emmc_top_cfg_preset4; uint32 emmc_top_cfg_sd_clock_delay; uint32 emmc_top_cfg_sd_pad_drv; uint32 emmc_top_cfg_ip_dly; /* 30 */ /*************************************************************************** *IP_DLY - SDIO Host input delay register ***************************************************************************/ /* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */ #define EMMC_TOP_CFG_IP_DLY_IP_TAP_EN_MASK 0x80000000 #define EMMC_TOP_CFG_IP_DLY_IP_TAP_EN_SHIFT 31 #define EMMC_TOP_CFG_IP_DLY_IP_TAP_EN_DEFAULT 0x00000000 /* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */ #define EMMC_TOP_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK 0x40000000 #define EMMC_TOP_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT 30 #define EMMC_TOP_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT 0x00000000 /* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */ #define EMMC_TOP_CFG_IP_DLY_reserved0_MASK 0x3ffc0000 #define EMMC_TOP_CFG_IP_DLY_reserved0_SHIFT 18 /* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */ #define EMMC_TOP_CFG_IP_DLY_IP_DELAY_CTRL_MASK 0x00030000 #define EMMC_TOP_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT 16 #define EMMC_TOP_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT 0x00000003 /* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */ #define EMMC_TOP_CFG_IP_DLY_reserved1_MASK 0x0000ffc0 #define EMMC_TOP_CFG_IP_DLY_reserved1_SHIFT 6 /* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [05:00] */ #define EMMC_TOP_CFG_IP_DLY_IP_TAP_DELAY_MASK 0x0000003f #define EMMC_TOP_CFG_IP_DLY_IP_TAP_DELAY_SHIFT 0 #define EMMC_TOP_CFG_IP_DLY_IP_TAP_DELAY_DEFAULT 0x00000028 uint32 emmc_top_cfg_op_dly; /*************************************************************************** *OP_DLY - SDIO Host output delay register ***************************************************************************/ /* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */ #define EMMC_TOP_CFG_OP_DLY_OP_TAP_EN_MASK 0x80000000 #define EMMC_TOP_CFG_OP_DLY_OP_TAP_EN_SHIFT 31 #define EMMC_TOP_CFG_OP_DLY_OP_TAP_EN_DEFAULT 0x00000000 /* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */ #define EMMC_TOP_CFG_OP_DLY_reserved0_MASK 0x7ffc0000 #define EMMC_TOP_CFG_OP_DLY_reserved0_SHIFT 18 /* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */ #define EMMC_TOP_CFG_OP_DLY_OP_DELAY_CTRL_MASK 0x00030000 #define EMMC_TOP_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT 16 #define EMMC_TOP_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT 0x00000000 /* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */ #define EMMC_TOP_CFG_OP_DLY_reserved1_MASK 0x0000fff0 #define EMMC_TOP_CFG_OP_DLY_reserved1_SHIFT 4 /* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */ #define EMMC_TOP_CFG_OP_DLY_OP_TAP_DELAY_MASK 0x0000000f #define EMMC_TOP_CFG_OP_DLY_OP_TAP_DELAY_SHIFT 0 #define EMMC_TOP_CFG_OP_DLY_OP_TAP_DELAY_DEFAULT 0x00000000 uint32 emmc_top_cfg_tuning; uint32 emmc_top_cfg_volt_ctrl; uint32 emmc_top_cfg_debug_tap_dly; /* 40 */ uint32 emmc_top_cfg_reserved[4]; uint32 emmc_top_cfg_sd_pin_sel; /* 54 */ uint32 emmc_top_cfg_max_current; uint32 emmc_top_cfg_reserved1[37]; /* 5c */ uint32 emmc_top_cfg_version; /* f0 */ uint32 emmc_top_cfg_reserved2[2]; uint32 emmc_top_cfg_scratch; /* fc */ } EmmcTopCnfg; #define EMMC_TOP_CFG ((volatile EmmcTopCnfg * const) EMMC_TOP_BASE) typedef struct EmmcBoot{ uint32 emmc_boot_main_ctl; #define EMMC_BOOT_ENABLE (1 << 0) uint32 emmc_boot_status; #define EMMC_BOOT_MODE_MASK (1 << 0) uint32 emmc_boot_version; uint32 emmc_boot_reserved; uint32 emmc_boot_clk_div; /* 10 */ uint32 emmc_boot_reset_cnt; uint32 emmc_boot_ram_fill; uint32 emmc_boot_error_addr; uint32 emmc_boot_base_addr0; /* 20 */ uint32 emmc_boot_base_addr1; uint32 emmc_boot_ram_fill_cnt; uint32 emmc_boot_data_access_time; uint32 emmc_boot_reserved1[3]; /* 30 */ uint32 emmc_boot_debug; /* 3c */ } EmmcBoot; #define EMMC_BOOT ((volatile EmmcBoot * const) EMMC_BOOT_BASE) typedef struct AhbssCtrlRegs { uint32 ahbss_ctrl_cfg; /* 0x00 AHB Subsystem Control Register */ #define AHB_REMAP 0x00000002 #define FORCE_EMMC_BOOT_STRAP 0x00000001 } AhbssCtrlRegs; #define AHBSS_CTRL ((volatile AhbssCtrlRegs *const) AHB_CONTROL_BASE) /* * High Speed Uart Control */ typedef struct HsUartCtrlRegs { uint32 reserved[5]; uint32 ptu_hc; /* 14 */ #define HS_UART_PTU_HC_DATA (1 << 1) uint32 reserved1; uint32 uart_data; uint32 reserved2[25]; /* 20 */ uint32 uart_int_stat; /* 84 */ uint32 reserved3[8]; /* 88 */ uint32 uart_int_en; /* a8 */ #define HS_UART_TXFIFOFULL (1 << 0) /* tx full */ #define HS_UART_TXFIFOAEMPTY (1 << 1) /* tx almost empty */ #define HS_UART_RXFIFOAFULL (1 << 2) /* rx almost full */ #define HS_UART_RXFIFOEMPTY (1 << 3) /* rx empty */ #define HS_UART_RXFIFORES (1 << 4) /* rx residue */ #define HS_UART_RXPARITYERR (1 << 5) /* rx parity error */ #define HS_UART_RXBRKDET (1 << 6) /* rx uart break */ #define HS_UART_RXCTS (1 << 7) /* uart cts */ #define HS_UART_INT_MASK (0xff) #define HS_UART_INT_MASK_DISABLE (0x00000000) uint32 reserved4[53]; /* ac */ uint32 dhbr; /* 180 */ uint32 dlbr; #define HS_UART_DHBR_3000K 0x00000001 /* Target is 16 clocks/baud(bit), Based on 50Mhz Uart clk */ #define HS_UART_DLBR_3000K 0x000000ff /* Target is 16 clocks/baud(bit), Based on 50Mhz Uart clk */ #define HS_UART_DHBR_115200 0x00000011 /* Target is 16 clocks/baud(bit), Based on 50Mhz Uart clk */ #define HS_UART_DLBR_115200 0x000000e5 /* Target is 16 clocks/baud(bit), Based on 50Mhz Uart clk */ uint32 ab0; uint32 reserved5; uint32 FCR; /* 190 */ #define HS_UART_FCR_AUTOLOAD_MODE (1 << 8) #define HS_UART_FCR_AB_MODE (1 << 7) #define HS_UART_FCR_AUTO_RTS_OE (1 << 6) #define HS_UART_FCR_AUTO_TX_OE (1 << 5) #define HS_UART_FCR_AUTOBAUD (1 << 4) #define HS_UART_FCR_TX_PACKET (1 << 3) #define HS_UART_FCR_SLIP_RESYNC (1 << 2) uint32 ab1; uint32 reserved6; uint32 LCR; /* 19c */ #define HS_UART_LCR_SLIP_TX_CRC (1 << 11) #define HS_UART_LCR_SLIP_CRC_LSBFIRST (1 << 10) #define HS_UART_LCR_SLIP_CRC_INV (1 << 9) #define HS_UART_LCR_SLIP_RX_CRC (1 << 8) #define HS_UART_LCR_SLIP (1 << 7) #define HS_UART_LCR_RTSOEN (1 << 6) #define HS_UART_LCR_TXOEN (1 << 5) #define HS_UART_LCR_LBC (1 << 4) #define HS_UART_LCR_RXEN (1 << 3) #define HS_UART_LCR_EPS (1 << 2) #define HS_UART_LCR_PEN (1 << 1) #define HS_UART_LCR_STB (1 << 0) uint32 MCR; #define HS_UART_MCR_REPEAT_XON_XOFF (1 << 9) #define HS_UART_MCR_PACKET_FLOW (1 << 8) #define HS_UART_MCR_BAUD_ADJ_EN (1 << 7) #define HS_UART_MCR_AUTO_TX_DISABLE (1 << 6) #define HS_UART_MCR_AUTO_RTS (1 << 5) #define HS_UART_MCR_LOOPBACK (1 << 4) #define HS_UART_MCR_HIGH_RATE (1 << 3) #define HS_UART_MCR_XON_XOff_EN (1 << 2) #define HS_UART_MCR_PROG_RTS (1 << 1) #define HS_UART_MCR_TX_ENABLE (1 << 0) uint32 LSR; #define HS_UART_LSR_TX_HALT (1 << 5) #define HS_UART_LSR_TX_PACKET_RDY (1 << 4) #define HS_UART_LSR_TX_IDLE (1 << 3) #define HS_UART_LSR_TX_DATA_AVAIL (1 << 2) /* 1 - Data in TX FIFO, 0 - TX FIFO empty */ #define HS_UART_LSR_RX_FULL (1 << 1) /* 1 - RX FIFO full */ #define HS_UART_LSR_RX_OVERFLOW (1 << 0) /* 1 - RX FIFO Overflow */ uint32 MSR; #define HS_UART_MSR_RX_IN (1 << 2) #define HS_UART_MSR_RTS_STAT (1 << 1) #define HS_UART_MSR_CTS_STAT (1 << 0) uint32 RFL; /* 1ac */ uint32 TFL; uint32 RFC; #define HS_UART_RFC_1039BYTES_FC_DATA (1039) #define HS_UART_RFC_NO_FC_DATA (HS_UART_RFC_1039BYTES_FC_DATA) // or should be LLI_BUFF_SIZE uint32 ESC; /* 1b8 */ #define HS_UART_ESC_SLIP_DATA (0xDB) #define HS_UART_ESC_NO_SLIP_DATA (0xDA) uint32 reserved7[3]; uint32 HOPKT_LEN; /* 1c8 */ uint32 HIPKT_LEN; uint32 HO_DMA_CTL; uint32 HI_DMA_CTL; uint32 HO_BSIZE; uint32 HI_BSIZE; #define HS_UART_DMA_CTL_BURSTMODE_EN (1 << 3) #define HS_UART_DMA_CTL_AFMODE_EN (1 << 2) #define HS_UART_DMA_CTL_FASTMODE_EN (1 << 1) #define HS_UART_DMA_CTL_DMA_EN (1 << 0) #define HS_UART_HO_BSIZE_DATA (0x3) #define HS_UART_HI_BSIZE_DATA (0x3) } HsUartCtrlRegs; #define HS_UART ((volatile HsUartCtrlRegs * const) HS_UART_BASE) typedef struct PL081Dma{ uint32 dmacintstat; uint32 dmacinttcstat; uint32 dmacinttcclr; uint32 dmacinterrstat; uint32 dmacinterrclr; /* 10 */ uint32 dmacwintc; uint32 dmacwinterr; uint32 dmacenbldchns; uint32 dmacsoftbreq; /* 20 */ uint32 dmacsoftsreq; uint32 dmacsofttlbreq; uint32 dmacsofttlsreq; uint32 dmacconfig; uint32 dmacsync; /* 34 */ uint32 dmacreserved[50]; uint32 dmacc0srcaddr; /* 100 */ uint32 dmacc0destaddr; uint32 dmacc0llireg; uint32 dmacc0control; uint32 dmacc0config; uint32 unused2[3]; /* 0x114 - 0x11f */ uint32 dmacc1srcaddr; uint32 dmacc1destaddr; uint32 dmacc1llireg; uint32 dmacc1control; uint32 dmacc1config; uint32 dmacreserved1[51]; /* 134 */ #define Pl081_DMACCxControl_TCINT_EN (1 << 31) #define Pl081_DMACCxControl_PROT_PRIVILEGED (1 << 28) #define Pl081_DMACCxControl_PROT_BUFF (1 << 29) #define Pl081_DMACCxControl_PROT_CACHE (1 << 30) #define Pl081_DMACCxControl_DI (1 << 27) #define Pl081_DMACCxControl_SI (1 << 26) #define Pl081_DMACCxControl_DWIDTH_B 0 #define Pl081_DMACCxControl_DWIDTH_H 1 #define Pl081_DMACCxControl_DWIDTH_W 2 #define Pl081_DMACCxControl_DWIDTH_SHIFT 21 #define Pl081_DMACCxControl_SWIDTH_B 0 #define Pl081_DMACCxControl_SWIDTH_H 1 #define Pl081_DMACCxControl_SWIDTH_W 2 #define Pl081_DMACCxControl_SWIDTH_SHIFT 18 #define Pl081_DMACCxControl_DBSIZE_1 0 #define Pl081_DMACCxControl_DBSIZE_4 1 #define Pl081_DMACCxControl_DBSIZE_8 2 #define Pl081_DMACCxControl_DBSIZE_16 3 #define Pl081_DMACCxControl_DBSIZE_32 4 #define Pl081_DMACCxControl_DBSIZE_64 5 #define Pl081_DMACCxControl_DBSIZE_128 6 #define Pl081_DMACCxControl_DBSIZE_256 7 #define Pl081_DMACCxControl_DBSIZE_SHIFT 15 #define Pl081_DMACCxControl_SBSIZE_1 0 #define Pl081_DMACCxControl_SBSIZE_4 1 #define Pl081_DMACCxControl_SBSIZE_8 2 #define Pl081_DMACCxControl_SBSIZE_16 3 #define Pl081_DMACCxControl_SBSIZE_32 4 #define Pl081_DMACCxControl_SBSIZE_64 5 #define Pl081_DMACCxControl_SBSIZE_128 6 #define Pl081_DMACCxControl_SBSIZE_SHIFT 12 uint32 dmactcr; /* 200 */ uint32 dmactop1; uint32 dmactop2; uint32 dmactop3; uint32 dmacreserved2[52]; /* 210 */ uint32 dmacperiphid0; /* 2e0 */ uint32 dmacperiphid1; uint32 dmacperiphid2; uint32 dmacperiphid3; uint32 dmacpcellid0; uint32 dmacpcellid1; uint32 dmacpcellid2; uint32 dmacpcellid3; } PL081Dma; #define PLDMA ((volatile PL081Dma * const) PL081_DMA_BASE) typedef struct TopControl { uint32 MiiPadCtl; // 0x0 uint32 Rgmii1PadCtl; // 0x4 uint32 Rgmii2PadCtl; // 0x8 uint32 Rgmii3PadCtl; // 0xc uint32 MiiPullCtl; // 0x10 uint32 Rgmii1PullCtl; // 0x14 uint32 Rgmii2PullCtl; // 0x18 uint32 Rgmii3PullCtl; // 0x1c uint32 SgmiiFiberDetect; // 0x20 uint32 DgSensePadCtl; // 0x24 #define DG_CTRL_SHIFT 4 #define DG_EN_SHIFT 3 #define DG_TRIM_SHIFT 0 uint32 TpDirOverride0; // 0x28 uint32 TpDirOverride1; // 0x2c uint32 RescalReadData0; // 0x30 uint32 RescalReadData1; // 0x34 uint32 reserved0; // 0x38 uint32 ResetStatus; // 0x3c #define PCIE_RESET_STATUS 0x10000000 #define SW_RESET_STATUS 0x20000000 #define HW_RESET_STATUS 0x40000000 #define POR_RESET_STATUS 0x80000000 #define RESET_STATUS_MASK 0xF0000000 uint32 TodSync; // 0x40 uint32 Pm0Pm1RescalSts; // 0x44 uint32 Pm2Pm3RescalSts; // 0x48 uint32 SgbRescalSts; // 0x4c uint32 Pm0Pm1RescalCfg; // 0x50 uint32 Pm2Pm3RescalCfg; // 0x54 uint32 SgbRescalCfg; // 0x58 uint32 Pm0Pm1TmonCfg; // 0x5c uint32 Pm2Pm3TmonCfg; // 0x60 uint32 SgbTmonCfg; // 0x64 uint32 MdioMasterSelect; // 0x68 uint32 SwControlReg; // 0x6c uint32 _2P5vDetectCtl; // 0x70 uint32 OrionIntPending; // 0x74 } TopControl; #define TOPCTRL ((volatile TopControl * const) TOP_CONTROL_BASE) #define TOP ((volatile TopControl * const) TOP_CONTROL_BASE) typedef struct AHBcontrol{ uint32 ahb_control; } AHBcontrol; #define AHBC ((volatile AHBcontrol * const) AHB_CONTROL_BASE) /* ** Peripheral Controller */ #define IRQ_BITS 64 typedef struct { uint64 IrqMask; uint64 ExtIrqMask; } IrqControl_t; typedef struct PerfControl { /* GenInt */ uint32 RevID; /* (00) word 0 */ #define CHIP_ID_SHIFT 12 #define CHIP_ID_MASK (0xfffff << CHIP_ID_SHIFT) #define REV_ID_MASK 0xff uint32 Ext1IrqCtrl; /* 0x04 */ #define EI_SENSE_SHFT 8 #define EI_INSENS_SHFT 16 #define EI_LEVEL_SHFT 24 uint32 Ext1IrqStatus; /* 0x08 */ #define EI_STATUS_SHFT 0 uint32 Ext1IrqSet; /* 0x0c */ uint32 Ext1IrqClear; /* 0x10 */ uint32 Ext1IrqMaskStatus; /* 0x14 */ uint32 Ext1IrqMaskSet; /* 0x18 */ uint32 Ext1IrqMaskClear; /* 0x1c */ uint32 ExtIrqCtrl; /* 0x20 */ uint32 ExtIrqStatus; /* 0x24 */ uint32 ExtIrqSet; /* 0x28 */ uint32 ExtIrqClear; /* 0x2c */ uint32 ExtIrqMaskStatus; /* 0x30 */ uint32 ExtIrqMaskSet; /* 0x34 */ uint32 ExtIrqMaskClear; /* 0x38 */ uint32 reserved0[2]; /* 0x3c-0x43 */ uint32 ExtIrqMuxSel0; /* 0x44 */ #define EXT_IRQ_SLOT_SIZE 16 #define EXT_IRQ_MUX_SEL0_SHIFT 4 #define EXT_IRQ_MUX_SEL0_MASK 0xf uint32 ExtIrqMuxSel1; /* 0x48 */ #define EXT_IRQ_MUX_SEL1_SHIFT 4 #define EXT_IRQ_MUX_SEL1_MASK 0xf uint32 IrqPeriphStatus; /* 0x4c */ uint32 IrqPeriphMask; /* 0x50 */ uint32 reserved[8]; /* 0x54 */ uint32 DMAIrqStatus; /* 0x74 */ uint32 DMAIrqSet; /* 0x78 */ uint32 DMAIrqClear; /* 0x7c */ uint32 DMAIrqMaskStatus; /* 0x80 */ uint32 DMAIrqMaskSet; /* 0x84 */ uint32 DMAIrqMaskClear; /* 0x88 */ uint32 DMA1IrqStatus; /* 0x8c */ uint32 DMA1IrqSet; /* 0x90 */ uint32 DMA1IrqClear; /* 0x94 */ uint32 DMA1IrqMaskStatus; /* 0x98 */ uint32 DMA1IrqMaskSet; /* 0x9c */ uint32 DMA1IrqMaskClear; /* 0xa0 */ uint32 DMA2IrqStatus; /* 0xa4 */ uint32 DMA2IrqSet; /* 0xa8 */ uint32 DMA2IrqClear; /* 0xac */ uint32 DMA2IrqMaskStatus; /* 0xb0 */ uint32 DMA2IrqMaskSet; /* 0xb4 */ uint32 DMA2IrqMaskClear; /* 0xb8 */ } PerfControl; #define PERF ((volatile PerfControl * const) PERF_BASE) /* ** Timer */ #define TIMER_64BIT typedef struct Timer { uint64 TimerCtl0; uint64 TimerCtl1; uint64 TimerCtl2; uint64 TimerCtl3; #define TIMERENABLE (1ULL << 63) #define RSTCNTCLR (1ULL << 62) uint64 TimerCnt0; uint64 TimerCnt1; uint64 TimerCnt2; uint64 TimerCnt3; #define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL uint32 TimerMask; #define TIMER0EN 0x01 #define TIMER1EN 0x02 #define TIMER2EN 0x04 #define TIMER3EN 0x08 uint32 TimerInts; #define TIMER0 0x01 #define TIMER1 0x02 #define TIMER2 0x04 #define TIMER3 0x08 uint32 ResetStatus; #define PCIE_RESET_STATUS 0x10000000 #define SW_RESET_STATUS 0x20000000 #define HW_RESET_STATUS 0x40000000 #define POR_RESET_STATUS 0x80000000 #define RESET_STATUS_MASK 0xF0000000 uint32 ResetReason; #define SW_INI_RESET 0x00000001 uint32 spare[3]; } Timer; typedef struct WDTimer { uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer * Write 0xee00 0x00ee to Stop and re-load default count * * Read from this register returns current watch dog count * */ uint32 WatchDogCtl; /* Number of 50-MHz ticks for WD Reset pulse to last */ uint32 WDResetCount; uint32 SoftRst; #define SOFT_RESET 0x00000001 uint32 WDAccessCtl; } WDTimer; #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) #define WDTIMER1 ((volatile WDTimer * const) WDTIMR1_BASE) #define TIMER ((volatile Timer * const) TIMR_BASE) /* ** UART */ typedef struct UartChannel { byte fifoctl; /* 0x00 */ #define RSTTXFIFOS 0x80 #define RSTRXFIFOS 0x40 /* 5-bit TimeoutCnt is in low bits of this register. * This count represents the number of characters * idle times before setting receive Irq when below threshold */ byte config; #define XMITBREAK 0x40 #define BITS5SYM 0x00 #define BITS6SYM 0x10 #define BITS7SYM 0x20 #define BITS8SYM 0x30 #define ONESTOP 0x07 #define TWOSTOP 0x0f /* 4-LSBS represent STOP bits/char * in 1/8 bit-time intervals. Zero * represents 1/8 stop bit interval. * Fifteen represents 2 stop bits. */ byte control; #define BRGEN 0x80 /* Control register bit defs */ #define TXEN 0x40 #define RXEN 0x20 #define LOOPBK 0x10 #define TXPARITYEN 0x08 #define TXPARITYEVEN 0x04 #define RXPARITYEN 0x02 #define RXPARITYEVEN 0x01 byte unused0; uint32 baudword; /* 0x04 */ /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate */ /* 0x08 */ byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1) * if these bits are also enabled to * GPIO_o */ #define ARMUARTEN 0x04 #define RTSEN 0x02 #define DTREN 0x01 byte fifocfg; /* Upper 4-bits are TxThresh, Lower are * RxThreshold. Irq can be asserted * when rx fifo> thresh, txfifo> 5) & 0x0f) : (0)) #define GPIO_NUM_TO_MASK(X) (((X & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X & BP_GPIO_NUM_MASK) & 0x1f)) : (0)) #define GPIO_NUM_TO_ARRAY_SHIFT(X) (((X) & BP_GPIO_NUM_MASK) & 0x1f) /* ** Misc Register Set Definitions. */ typedef struct Misc { uint32 miscStrapBus; /* 0x00 */ #define MISC_STRAP_BUS_BOOT_SEL_SHIFT 5 #define MISC_STRAP_BUS_BOOT_SEL_MASK (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NOR (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_EMMC (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SPI_NAND (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_512_PAGE (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT) #define MISC_STRAP_BUS_BOOTROM_BOOT_N (0x1 << 11) uint32 miscStrapOverride; /* 0x04 */ uint32 miscMaskUBUSErr; /* 0x08 */ uint32 miscPeriphCtrl; /* 0x0c */ uint32 miscSPImasterCtrl; /* 0x10 */ uint32 miscDierevid; /* 0x14 */ uint32 miscPeriphMiscCtrl; /* 0x18 */ uint32 miscPeriphMiscStat; /* 0x1c */ uint32 miscMbox0_data; /* 0x20 */ uint32 miscMbox1_data; /* 0x24 */ uint32 miscMbox2_data; /* 0x28 */ uint32 miscMbox3_data; /* 0x2c */ uint32 miscMbox_ctrl; /* 0x30 */ uint32 miscSoftResetB; /* 0x34 */ uint32 miscSpare0; /* 0x38 */ uint32 miscSWdebugNW[2]; /* 0x3c-0x40 */ uint32 miscWDenReset; /* 0x44 */ } Misc; #define MISC ((volatile Misc * const) MISC_BASE) typedef struct Rng { uint32 ctrl0; /* 0x00 */ uint32 rngSoftReset; /* 0x04 */ uint32 rbgSoftReset; /* 0x08 */ uint32 totalBitCnt; /* 0x0c */ uint32 totalBitCntThreshold; /* 0x10 */ uint32 revId; /* 0x14 */ uint32 intStatus; /* 0x18 */ #define RNG_INT_STATUS_NIST_FAIL (0x1<<5) #define RNG_INT_STATUS_FIFO_FULL (0x1<<2) uint32 intEn; /* 0x1c */ uint32 rngFifoData; /* 0x20 */ uint32 fifoCnt; /* 0x24 */ #define RNG_PERM_ALLOW_SECURE_ACCESS 0xCC #define RNG_PERM_ALLOW_NONSEC_ACCESS 0x33 uint32 perm; /* 0x28 */ } Rng; #define RNG ((volatile Rng * const) RNG_BASE) /* ** High-Speed SPI Controller */ #define __mask(end, start) (((1 << ((end - start) + 1)) - 1) << start) typedef struct HsSpiControl { uint32 hs_spiGlobalCtrl; // 0x0000 #define HS_SPI_MOSI_IDLE (1 << 18) #define HS_SPI_CLK_POLARITY (1 << 17) #define HS_SPI_CLK_GATE_SSOFF (1 << 16) #define HS_SPI_PLL_CLK_CTRL (8) #define HS_SPI_PLL_CLK_CTRL_MASK __mask(15, HS_SPI_PLL_CLK_CTRL) #define HS_SPI_SS_POLARITY (0) #define HS_SPI_SS_POLARITY_MASK __mask(7, HS_SPI_SS_POLARITY) uint32 hs_spiExtTrigCtrl; // 0x0004 #define HS_SPI_TRIG_RAW_STATE (24) #define HS_SPI_TRIG_RAW_STATE_MASK __mask(31, HS_SPI_TRIG_RAW_STATE) #define HS_SPI_TRIG_LATCHED (16) #define HS_SPI_TRIG_LATCHED_MASK __mask(23, HS_SPI_TRIG_LATCHED) #define HS_SPI_TRIG_SENSE (8) #define HS_SPI_TRIG_SENSE_MASK __mask(15, HS_SPI_TRIG_SENSE) #define HS_SPI_TRIG_TYPE (0) #define HS_SPI_TRIG_TYPE_MASK __mask(7, HS_SPI_TRIG_TYPE) #define HS_SPI_TRIG_TYPE_EDGE (0) #define HS_SPI_TRIG_TYPE_LEVEL (1) uint32 hs_spiIntStatus; // 0x0008 #define HS_SPI_IRQ_PING1_USER (28) #define HS_SPI_IRQ_PING1_USER_MASK __mask(31, HS_SPI_IRQ_PING1_USER) #define HS_SPI_IRQ_PING0_USER (24) #define HS_SPI_IRQ_PING0_USER_MASK __mask(27, HS_SPI_IRQ_PING0_USER) #define HS_SPI_IRQ_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQ_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQ_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQ_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQ_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQ_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQ_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQ_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQ_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQ_PING0_CMD_DONE (1 << 0) uint32 hs_spiIntStatusMasked; // 0x000C #define HS_SPI_IRQSM__PING1_USER (28) #define HS_SPI_IRQSM__PING1_USER_MASK __mask(31, HS_SPI_IRQSM__PING1_USER) #define HS_SPI_IRQSM__PING0_USER (24) #define HS_SPI_IRQSM__PING0_USER_MASK __mask(27, HS_SPI_IRQSM__PING0_USER) #define HS_SPI_IRQSM__PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQSM__PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQSM__PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9) #define HS_SPI_IRQSM__PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQSM__PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQSM__PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQSM__PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQSM__PING0_RX_OVER (1 << 1) #define HS_SPI_IRQSM__PING0_CMD_DONE (1 << 0) uint32 hs_spiIntMask; // 0x0010 #define HS_SPI_IRQM_PING1_USER (28) #define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER) #define HS_SPI_IRQM_PING0_USER (24) #define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER) #define HS_SPI_IRQM_PING1_CTRL_INV (1 << 12) #define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11) #define HS_SPI_IRQM_PING1_TX_UNDER (1 << 10) #define HS_SPI_IRQM_PING1_RX_OVER (1 << 9) #define HS_SPI_IRQM_PING1_CMD_DONE (1 << 8) #define HS_SPI_IRQM_PING0_CTRL_INV (1 << 4) #define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3) #define HS_SPI_IRQM_PING0_TX_UNDER (1 << 2) #define HS_SPI_IRQM_PING0_RX_OVER (1 << 1) #define HS_SPI_IRQM_PING0_CMD_DONE (1 << 0) #define HS_SPI_INTR_CLEAR_ALL (0xFF001F1F) uint32 hs_spiFlashCtrl; // 0x0014 #define HS_SPI_FCTRL_MB_ENABLE (23) #define HS_SPI_FCTRL_SS_NUM (20) #define HS_SPI_FCTRL_SS_NUM_MASK __mask(22, HS_SPI_FCTRL_SS_NUM) #define HS_SPI_FCTRL_PROFILE_NUM (16) #define HS_SPI_FCTRL_PROFILE_NUM_MASK __mask(18, HS_SPI_FCTRL_PROFILE_NUM) #define HS_SPI_FCTRL_DUMMY_BYTES (10) #define HS_SPI_FCTRL_DUMMY_BYTES_MASK __mask(11, HS_SPI_FCTRL_DUMMY_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES (8) #define HS_SPI_FCTRL_ADDR_BYTES_MASK __mask(9, HS_SPI_FCTRL_ADDR_BYTES) #define HS_SPI_FCTRL_ADDR_BYTES_2 (0) #define HS_SPI_FCTRL_ADDR_BYTES_3 (1) #define HS_SPI_FCTRL_ADDR_BYTES_4 (2) #define HS_SPI_FCTRL_READ_OPCODE (0) #define HS_SPI_FCTRL_READ_OPCODE_MASK __mask(7, HS_SPI_FCTRL_READ_OPCODE) uint32 hs_spiFlashAddrBase; // 0x0018 } HsSpiControl; typedef struct HsSpiPingPong { uint32 command; #define HS_SPI_SS_NUM (12) #define ZSI_SPI_DEV_ID 7 // SS_N[7] connected to APM/PCM block for use by MSIF/ZDS interfaces #define HS_SPI_PROFILE_NUM (8) #define HS_SPI_TRIGGER_NUM (4) #define HS_SPI_COMMAND_VALUE (0) #define HS_SPI_COMMAND_NOOP (0) #define HS_SPI_COMMAND_START_NOW (1) #define HS_SPI_COMMAND_START_TRIGGER (2) #define HS_SPI_COMMAND_HALT (3) #define HS_SPI_COMMAND_FLUSH (4) uint32 status; #define HS_SPI_ERROR_BYTE_OFFSET (16) #define HS_SPI_WAIT_FOR_TRIGGER (2) #define HS_SPI_SOURCE_BUSY (1) #define HS_SPI_SOURCE_GNT (0) uint32 fifo_status; uint32 control; uint32 PingPongReserved[12]; } HsSpiPingPong; typedef struct HsSpiProfile { uint32 clk_ctrl; #define HS_SPI_ACCUM_RST_ON_LOOP (15) #define HS_SPI_SPI_CLK_2X_SEL (14) #define HS_SPI_FREQ_CTRL_WORD (0) uint32 signal_ctrl; #define HS_SPI_ASYNC_INPUT_PATH (1 << 16) #define HS_SPI_LAUNCH_RISING (1 << 13) #define HS_SPI_LATCH_RISING (1 << 12) uint32 mode_ctrl; #define HS_SPI_PREPENDBYTE_CNT (24) #define HS_SPI_MODE_ONE_WIRE (20) #define HS_SPI_MULTIDATA_WR_SIZE (18) #define HS_SPI_MULTIDATA_RD_SIZE (16) #define HS_SPI_MULTIDATA_WR_STRT (12) #define HS_SPI_MULTIDATA_RD_STRT (8) #define HS_SPI_FILLBYTE (0) uint32 unused[5]; } HsSpiProfile; #define HS_SPI_OP_CODE 13 #define HS_SPI_OP_SLEEP (0) #define HS_SPI_OP_READ_WRITE (1) #define HS_SPI_OP_WRITE (2) #define HS_SPI_OP_READ (3) #define HS_SPI_OP_SETIRQ (4) #define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE) #define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80)) #define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0)) #define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100)) #define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200)) #define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400)) typedef struct NandCtrlRegs { uint32 NandRevision; /* 0x00 */ uint32 NandCmdStart; /* 0x04 */ #define NCMD_MASK 0x0000001f #define NCMD_BLOCK_ERASE_MULTI 0x15 #define NCMD_PROGRAM_PAGE_MULTI 0x13 #define NCMD_STS_READ_MULTI 0x12 #define NCMD_PAGE_READ_MULTI 0x11 #define NCMD_LOW_LEVEL_OP 0x10 #define NCMD_PARAM_CHG_COL 0x0f #define NCMD_PARAM_READ 0x0e #define NCMD_BLK_LOCK_STS 0x0d #define NCMD_BLK_UNLOCK 0x0c #define NCMD_BLK_LOCK_DOWN 0x0b #define NCMD_BLK_LOCK 0x0a #define NCMD_FLASH_RESET 0x09 #define NCMD_BLOCK_ERASE 0x08 #define NCMD_DEV_ID_READ 0x07 #define NCMD_COPY_BACK 0x06 #define NCMD_PROGRAM_SPARE 0x05 #define NCMD_PROGRAM_PAGE 0x04 #define NCMD_STS_READ 0x03 #define NCMD_SPARE_READ 0x02 #define NCMD_PAGE_READ 0x01 uint32 NandCmdExtAddr; /* 0x08 */ uint32 NandCmdAddr; /* 0x0c */ uint32 NandCmdEndAddr; /* 0x10 */ uint32 NandIntfcStatus; /* 0x14 */ #define NIS_CTLR_READY (1 << 31) #define NIS_FLASH_READY (1 << 30) #define NIS_CACHE_VALID (1 << 29) #define NIS_SPARE_VALID (1 << 28) #define NIS_FLASH_STS_MASK 0x000000ff #define NIS_WRITE_PROTECT 0x00000080 #define NIS_DEV_READY 0x00000040 #define NIS_PGM_ERASE_ERROR 0x00000001 uint32 NandNandBootConfig; /* 0x18 */ #define NBC_CS_LOCK (1 << 31) #define NBC_AUTO_DEV_ID_CFG (1 << 30) #define NBC_WR_PROT_BLK0 (1 << 28) #define NBC_EBI_CS7_USES_NAND (1<<15) #define NBC_EBI_CS6_USES_NAND (1<<14) #define NBC_EBI_CS5_USES_NAND (1<<13) #define NBC_EBI_CS4_USES_NAND (1<<12) #define NBC_EBI_CS3_USES_NAND (1<<11) #define NBC_EBI_CS2_USES_NAND (1<<10) #define NBC_EBI_CS1_USES_NAND (1<< 9) #define NBC_EBI_CS0_USES_NAND (1<< 8) #define NBC_EBC_CS7_SEL (1<< 7) #define NBC_EBC_CS6_SEL (1<< 6) #define NBC_EBC_CS5_SEL (1<< 5) #define NBC_EBC_CS4_SEL (1<< 4) #define NBC_EBC_CS3_SEL (1<< 3) #define NBC_EBC_CS2_SEL (1<< 2) #define NBC_EBC_CS1_SEL (1<< 1) #define NBC_EBC_CS0_SEL (1<< 0) uint32 NandCsNandXor; /* 0x1c */ uint32 NandLlOpNand; /* 0x20 */ uint32 NandMplaneBaseExtAddr; /* 0x24 */ uint32 NandMplaneBaseAddr; /* 0x28 */ uint32 NandReserved1[9]; /* 0x2c-0x4f */ uint32 NandAccControl; /* 0x50 */ #define NAC_RD_ECC_EN (1 << 31) #define NAC_WR_ECC_EN (1 << 30) #define NAC_CE_CARE_EN (1 << 28) #define NAC_RD_ERASED_ECC_EN (1 << 27) #define NAC_PARTIAL_PAGE_EN (1 << 26) #define NAC_WR_PREEMPT_EN (1 << 25) #define NAC_PAGE_HIT_EN (1 << 24) #define NAC_PREFETCH_EN (1 << 23) #define NAC_CACHE_MODE_EN (1 << 22) #define NAC_ECC_LVL_SHIFT 16 #define NAC_ECC_LVL_MASK 0x001f0000 #define NAC_ECC_LVL_DISABLE 0 #define NAC_ECC_LVL_BCH_1 1 #define NAC_ECC_LVL_BCH_2 2 #define NAC_ECC_LVL_BCH_3 3 #define NAC_ECC_LVL_BCH_4 4 #define NAC_ECC_LVL_BCH_5 5 #define NAC_ECC_LVL_BCH_6 6 #define NAC_ECC_LVL_BCH_7 7 #define NAC_ECC_LVL_BCH_8 8 #define NAC_ECC_LVL_BCH_9 9 #define NAC_ECC_LVL_BCH_10 10 #define NAC_ECC_LVL_BCH_11 11 #define NAC_ECC_LVL_BCH_12 12 #define NAC_ECC_LVL_BCH_13 13 #define NAC_ECC_LVL_BCH_14 14 #define NAC_ECC_LVL_HAMMING 15 /* Hamming if spare are size = 16, BCH15 otherwise */ #define NAC_ECC_LVL_BCH15 15 #define NAC_ECC_LVL_BCH_16 16 #define NAC_ECC_LVL_BCH_17 17 /* BCH18 to 30 for sector size = 1K. To be added when we need it */ #define NAC_SECTOR_SIZE_1K (1 << 7) #define NAC_SPARE_SZ_SHIFT 0 #define NAC_SPARE_SZ_MASK 0x0000007f uint32 NandConfigExt; /* 0x54 */ /* Nand Flash Config Ext*/ #define NC_BLK_SIZE_MASK (0xff << 4) #define NC_BLK_SIZE_8192K (0xa << 4) #define NC_BLK_SIZE_4096K (0x9 << 4) #define NC_BLK_SIZE_2048K (0x8 << 4) #define NC_BLK_SIZE_1024K (0x7 << 4) #define NC_BLK_SIZE_512K (0x6 << 4) #define NC_BLK_SIZE_256K (0x5 << 4) #define NC_BLK_SIZE_128K (0x4 << 4) #define NC_BLK_SIZE_64K (0x3 << 4) #define NC_BLK_SIZE_32K (0x2 << 4) #define NC_BLK_SIZE_16K (0x1 << 4) #define NC_BLK_SIZE_8K (0x0 << 4) #define NC_PG_SIZE_MASK (0xf << 0) #define NC_PG_SIZE_16K (0x5 << 0) #define NC_PG_SIZE_8K (0x4 << 0) #define NC_PG_SIZE_4K (0x3 << 0) #define NC_PG_SIZE_2K (0x2 << 0) #define NC_PG_SIZE_1K (0x1 << 0) #define NC_PG_SIZE_512B (0x0 << 0) uint32 NandConfig; /* 0x58 */ /* Nand Flash Config */ #define NC_CONFIG_LOCK (1 << 31) #define NC_DEV_SIZE_SHIFT 24 #define NC_DEV_SIZE_MASK (0x0f << NC_DEV_SIZE_SHIFT) #define NC_DEV_WIDTH_MASK (1 << 23) #define NC_DEV_WIDTH_16 (1 << 23) #define NC_DEV_WIDTH_8 (0 << 23) #define NC_FUL_ADDR_SHIFT 16 #define NC_FUL_ADDR_MASK (0x7 << NC_FUL_ADDR_SHIFT) #define NC_BLK_ADDR_SHIFT 8 #define NC_BLK_ADDR_MASK (0x07 << NC_BLK_ADDR_SHIFT) uint32 NandTiming1; /* 0x5c */ /* Nand Flash Timing Parameters 1 */ #define NT_TREH_MASK 0x000f0000 #define NT_TREH_SHIFT 16 #define NT_TRP_MASK 0x00f00000 #define NT_TRP_SHIFT 20 uint32 NandTiming2; /* 0x60 */ /* Nand Flash Timing Parameters 2 */ #define NT_TREAD_MASK 0x0000000f #define NT_TREAD_SHIFT 0 /* 0x64 */ uint32 NandAccControlCs1; /* Nand Flash Access Control */ uint32 NandConfigExtCs1; /* Nand Flash Config Ext*/ uint32 NandConfigCs1; /* Nand Flash Config */ uint32 NandTiming1Cs1; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs1; /* Nand Flash Timing Parameters 2 */ /* 0x78 */ uint32 NandAccControlCs2; /* Nand Flash Access Control */ uint32 NandConfigExtCs2; /* Nand Flash Config Ext*/ uint32 NandConfigCs2; /* Nand Flash Config */ uint32 NandTiming1Cs2; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs2; /* Nand Flash Timing Parameters 2 */ /* 0x8c */ uint32 NandAccControlCs3; /* Nand Flash Access Control */ uint32 NandConfigExtCs3; /* Nand Flash Config Ext*/ uint32 NandConfigCs3; /* Nand Flash Config */ uint32 NandTiming1Cs3; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs3; /* Nand Flash Timing Parameters 2 */ /* 0xa0 */ uint32 NandAccControlCs4; /* Nand Flash Access Control */ uint32 NandConfigExtCs4; /* Nand Flash Config Ext*/ uint32 NandConfigCs4; /* Nand Flash Config */ uint32 NandTiming1Cs4; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs4; /* Nand Flash Timing Parameters 2 */ /* 0xb4 */ uint32 NandAccControlCs5; /* Nand Flash Access Control */ uint32 NandConfigExtCs5; /* Nand Flash Config Ext*/ uint32 NandConfigCs5; /* Nand Flash Config */ uint32 NandTiming1Cs5; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs5; /* Nand Flash Timing Parameters 2 */ /* 0xc8 */ uint32 NandAccControlCs6; /* Nand Flash Access Control */ uint32 NandConfigExtCs6; /* Nand Flash Config Ext*/ uint32 NandConfigCs6; /* Nand Flash Config */ uint32 NandTiming1Cs6; /* Nand Flash Timing Parameters 1 */ uint32 NandTiming2Cs6; /* Nand Flash Timing Parameters 2 */ /* 0xdc */ uint32 NandCorrStatThreshold; /* Correctable Error Reporting Threshold */ uint32 NandCorrStatThresholdExt; /* Correctable Error Reporting Threshold */ uint32 NandBlkWrProtect; /* Block Write Protect Enable and Size */ /* for EBI_CS0b */ uint32 NandMplaneOpcode1; /* 0xec */ uint32 NandMplaneOpcode2; uint32 NandMplaneCtrl; uint32 NandReserved2[2]; /* 0xf4-0xfb */ uint32 NandUncorrErrorCount; /* 0xfc */ /* 0x100 */ uint32 NandCorrErrorCount; uint32 NandReadErrorCount; /* Read Error Count */ uint32 NandBlockLockStatus; /* Nand Flash Block Lock Status */ uint32 NandEccCorrExtAddr; /* ECC Correctable Error Extended Address*/ /* 0x110 */ uint32 NandEccCorrAddr; /* ECC Correctable Error Address */ uint32 NandEccUncExtAddr; /* ECC Uncorrectable Error Extended Addr */ uint32 NandEccUncAddr; /* ECC Uncorrectable Error Address */ uint32 NandFlashReadExtAddr; /* Flash Read Data Extended Address */ /* 0x120 */ uint32 NandFlashReadAddr; /* Flash Read Data Address */ uint32 NandProgramPageExtAddr; /* Page Program Extended Address */ uint32 NandProgramPageAddr; /* Page Program Address */ uint32 NandCopyBackExtAddr; /* Copy Back Extended Address */ /* 0x130 */ uint32 NandCopyBackAddr; /* Copy Back Address */ uint32 NandBlockEraseExtAddr; /* Block Erase Extended Address */ uint32 NandBlockEraseAddr; /* Block Erase Address */ uint32 NandInvReadExtAddr; /* Flash Invalid Data Extended Address */ /* 0x140 */ uint32 NandInvReadAddr; /* Flash Invalid Data Address */ uint32 NandInitStatus; uint32 NandOnfiStatus; /* ONFI Status */ uint32 NandOnfiDebugData; /* ONFI Debug Data */ uint32 NandSemaphore; /* 0x150 */ /* Semaphore */ uint32 NandReserved3[16]; /* 0x154-0x193 */ /* 0x194 */ uint32 NandFlashDeviceId; /* Nand Flash Device ID */ uint32 NandFlashDeviceIdExt; /* Nand Flash Extended Device ID */ uint32 NandLlRdData; /* Nand Flash Low Level Read Data */ uint32 NandReserved4[24]; /* 0x1a0 - 0x1ff */ /* 0x200 */ uint32 NandSpareAreaReadOfs0; /* Nand Flash Spare Area Read Bytes 0-3 */ uint32 NandSpareAreaReadOfs4; /* Nand Flash Spare Area Read Bytes 4-7 */ uint32 NandSpareAreaReadOfs8; /* Nand Flash Spare Area Read Bytes 8-11 */ uint32 NandSpareAreaReadOfsC; /* Nand Flash Spare Area Read Bytes 12-15*/ /* 0x210 */ uint32 NandSpareAreaReadOfs10; /* Nand Flash Spare Area Read Bytes 16-19 */ uint32 NandSpareAreaReadOfs14; /* Nand Flash Spare Area Read Bytes 20-23 */ uint32 NandSpareAreaReadOfs18; /* Nand Flash Spare Area Read Bytes 24-27 */ uint32 NandSpareAreaReadOfs1C; /* Nand Flash Spare Area Read Bytes 28-31*/ /* 0x220 */ uint32 NandSpareAreaReadOfs20; /* Nand Flash Spare Area Read Bytes 32-35 */ uint32 NandSpareAreaReadOfs24; /* Nand Flash Spare Area Read Bytes 36-39 */ uint32 NandSpareAreaReadOfs28; /* Nand Flash Spare Area Read Bytes 40-43 */ uint32 NandSpareAreaReadOfs2C; /* Nand Flash Spare Area Read Bytes 44-47*/ /* 0x230 */ uint32 NandSpareAreaReadOfs30; /* Nand Flash Spare Area Read Bytes 48-51 */ uint32 NandSpareAreaReadOfs34; /* Nand Flash Spare Area Read Bytes 52-55 */ uint32 NandSpareAreaReadOfs38; /* Nand Flash Spare Area Read Bytes 56-59 */ uint32 NandSpareAreaReadOfs3C; /* Nand Flash Spare Area Read Bytes 60-63*/ uint32 NandReserved5[16]; /* 0x240-0x27f */ /* 0x280 */ uint32 NandSpareAreaWriteOfs0; /* Nand Flash Spare Area Write Bytes 0-3 */ uint32 NandSpareAreaWriteOfs4; /* Nand Flash Spare Area Write Bytes 4-7 */ uint32 NandSpareAreaWriteOfs8; /* Nand Flash Spare Area Write Bytes 8-11 */ uint32 NandSpareAreaWriteOfsC; /* Nand Flash Spare Area Write Bytes 12-15 */ /* 0x290 */ uint32 NandSpareAreaWriteOfs10; /* Nand Flash Spare Area Write Bytes 16-19 */ uint32 NandSpareAreaWriteOfs14; /* Nand Flash Spare Area Write Bytes 20-23 */ uint32 NandSpareAreaWriteOfs18; /* Nand Flash Spare Area Write Bytes 24-27 */ uint32 NandSpareAreaWriteOfs1C; /* Nand Flash Spare Area Write Bytes 28-31 */ /* 0x2a0 */ uint32 NandSpareAreaWriteOfs20; /* Nand Flash Spare Area Write Bytes 32-35 */ uint32 NandSpareAreaWriteOfs24; /* Nand Flash Spare Area Write Bytes 36-39 */ uint32 NandSpareAreaWriteOfs28; /* Nand Flash Spare Area Write Bytes 40-43 */ uint32 NandSpareAreaWriteOfs2C; /* Nand Flash Spare Area Write Bytes 44-47 */ /* 0x2b0 */ uint32 NandSpareAreaWriteOfs30; /* Nand Flash Spare Area Write Bytes 48-51 */ uint32 NandSpareAreaWriteOfs34; /* Nand Flash Spare Area Write Bytes 52-55 */ uint32 NandSpareAreaWriteOfs38; /* Nand Flash Spare Area Write Bytes 56-59 */ uint32 NandSpareAreaWriteOfs3C; /* Nand Flash Spare Area Write Bytes 60-63 */ /* 0x2c0 */ uint32 NandDdrTiming; uint32 NandDdrNcdlCalibCtl; uint32 NandDdrNcdlCalibPeriod; uint32 NandDdrNcdlCalibStat; /* 0x2d0 */ uint32 NandDdrNcdlMode; uint32 NandDdrNcdlOffset; uint32 NandDdrPhyCtl; uint32 NandDdrPhyBistCtl; /* 0x2e0 */ uint32 NandDdrPhyBistStat; uint32 NandDdrDiagStat0; uint32 NandDdrDiagStat1; uint32 NandReserved6[69]; /* 0x2ec-0x3ff */ /* 0x400 */ uint32 NandFlashCache[128]; /* 0x400-0x5ff */ } NandCtrlRegs; /* * ** NAND Interrupt Controller Registers * */ typedef struct NandIntrCtrlRegs { uint32 NandInterrupt; #define NINT_STS_MASK 0x00000fff #define NINT_ECC_ERROR_CORR_SEC 0x00000800 #define NINT_ECC_ERROR_UNC_SEC 0x00000400 #define NINT_CTRL_READY_SEC 0x00000200 #define NINT_INV_ACC_SEC 0x00000100 #define NINT_ECC_ERROR_CORR 0x00000080 #define NINT_ECC_ERROR_UNC 0x00000040 #define NINT_DEV_RBPIN 0x00000020 #define NINT_CTRL_READY 0x00000010 #define NINT_PAGE_PGM 0x00000008 #define NINT_COPY_BACK 0x00000004 #define NINT_BLOCK_ERASE 0x00000002 #define NINT_NP_READ 0x00000001 uint32 NandInterruptEn; #define NINT_ENABLE_MASK 0x0000ffff uint32 NandBaseAddr0; /* Default address when booting from NAND flash */ uint32 NandBaseAddr1; /* Secondary base address for NAND flash */ } NandIntrCtrlRegs; #define NAND_INTR ((volatile NandIntrCtrlRegs * const) NAND_INTR_BASE) #define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE) #define NAND_CACHE ((volatile uint8 * const) NAND_CACHE_BASE) typedef struct UsimBase { uint32 UsimScr; //sim Control Register uint32 UsimSsr; //sim Status Register uint32 UsimSdr; //sim Data Register uint32 UsimSier; //siM Interrupt Enable Register uint32 UsimSfcr; //siM FIFO Control Register uint32 UsimSecgtr; //SIM Extra Character Guard Time Register uint32 UsimStgtr; //sIM Turnaround Guard Time Register uint32 UsimSgccr; //sIM Generic Counter Compare Register uint32 UsimSgcvr; //sIM Generic Counter Value Register uint32 UsimScdr; //siM Clock Divide Register uint32 UsimSfdrr; //sIM F/D Ratio Register uint32 UsimSesr; //siM Extra Sample Register uint32 UsimSimdebug; //SIM Debug Register uint32 UsimSrtor; //sIM Received Time Out Register uint32 UsimReserved[4]; uint32 UsimSipver; //SIM Controller IP version - 0x4c uint32 UsimReserved1[4]; uint32 UsimSesdcr; //SIM Card Detection and Emergency Shutdown Control Register - 0x60 uint32 UsimSesdisr; //SIM Card Detection and Emergency Shutdown Interrupt Status Register uint32 UsimScardsr; //SIM Card Status Control and Status Register uint32 UsimSldocr; //SIM LDO Controler Register } UsimBase; #define USIM ((volatile UsimBase * const) USIM_BASE) typedef struct MDIOBase { uint32 MDIO_PerCmd; //MDIO Command Register uint32 MDIO_PerCfg; //MDIO Configuration Register } MDIOBase; #define MDIO ((volatile MDIOBase * const) MDIO_BASE) typedef struct I2CControl { uint32 ChipAddress; /* 0x0 */ #define I2C_CHIP_ADDRESS_MASK 0x000000f7 #define I2C_CHIP_ADDRESS_SHIFT 0x1 uint32 DataIn0; /* 0x4 */ uint32 DataIn1; /* 0x8 */ uint32 DataIn2; /* 0xc */ uint32 DataIn3; /* 0x10 */ uint32 DataIn4; /* 0x14 */ uint32 DataIn5; /* 0x18 */ uint32 DataIn6; /* 0x1c */ uint32 DataIn7; /* 0x20 */ uint32 CntReg; /* 0x24 */ #define I2C_CNT_REG1_SHIFT 0x0 #define I2C_CNT_REG2_SHIFT 0x6 uint32 CtlReg; /* 0x28 */ #define I2C_CTL_REG_DTF_MASK 0x00000003 #define I2C_CTL_REG_DTF_WRITE 0x0 #define I2C_CTL_REG_DTF_READ 0x1 #define I2C_CTL_REG_DTF_READ_AND_WRITE 0x2 #define I2C_CTL_REG_DTF_WRITE_AND_READ 0x3 #define I2C_CTL_REG_DEGLITCH_DISABLE 0x00000004 #define I2C_CTL_REG_DELAY_DISABLE 0x00000008 #define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 #define I2C_CTL_REG_SCL_CLK_375KHZ 0x00000000 #define I2C_CTL_REG_SCL_CLK_390KHZ 0x00000010 #define I2C_CTL_REG_SCL_CLK_187_5KHZ 0x00000020 #define I2C_CTL_REG_SCL_CLK_200KHZ 0x00000030 #define I2C_CTL_REG_INT_ENABLE 0x00000040 #define I2C_CTL_REG_DIV_CLK 0x00000080 uint32 IICEnable; /* 0x2c */ #define I2C_IIC_ENABLE 0x00000001 #define I2C_IIC_INTRP 0x00000002 #define I2C_IIC_NO_ACK 0x00000004 #define I2C_IIC_NO_STOP 0x00000010 #define I2C_IIC_NO_START 0x00000020 uint32 DataOut0; /* 0x30 */ uint32 DataOut1; /* 0x34 */ uint32 DataOut2; /* 0x38 */ uint32 DataOut3; /* 0x3c */ uint32 DataOut4; /* 0x40 */ uint32 DataOut5; /* 0x44 */ uint32 DataOut6; /* 0x48 */ uint32 DataOut7; /* 0x4c */ uint32 CtlHiReg; /* 0x50 */ #define I2C_CTLHI_REG_WAIT_DISABLE 0x00000001 #define I2C_CTLHI_REG_IGNORE_ACK 0x00000002 #define I2C_CTLHI_REG_DATA_REG_SIZE 0x00000040 uint32 SclParam; /* 0x54 */ } I2CControl; #define I2C ((volatile I2CControl * const) I2C_BASE) #define I2C_2 ((volatile I2CControl * const) I2C_2_BASE) /* * Power Management Control */ typedef struct PmcCtrlReg { uint32 gpTmr0Ctl; /* 0x018 */ uint32 gpTmr0Cnt; /* 0x01c */ uint32 gpTmr1Ctl; /* 0x020 */ uint32 gpTmr1Cnt; /* 0x024 */ uint32 hostMboxIn; /* 0x028 */ uint32 hostMboxOut; /* 0x02c */ uint32 reserved[4]; /* 0x030 */ uint32 dmaCtrl; /* 0x040 */ uint32 dmaStatus; /* 0x044 */ uint32 dma0_3FifoStatus; /* 0x048 */ uint32 reserved1[4]; /* 0x04c */ uint32 diagControl; /* 0x05c */ uint32 diagHigh; /* 0x060 */ uint32 diagLow; /* 0x064 */ uint32 reserved8; /* 0x068 */ uint32 addr1WndwMask; /* 0x06c */ uint32 addr1WndwBaseIn; /* 0x070 */ uint32 addr1WndwBaseOut; /* 0x074 */ uint32 addr2WndwMask; /* 0x078 */ uint32 addr2WndwBaseIn; /* 0x07c */ uint32 addr2WndwBaseOut; /* 0x080 */ uint32 scratch; /* 0x084 */ uint32 reserved9; /* 0x088 */ uint32 softResets; /* 0x08c */ uint32 reserved2; /* 0x090 */ uint32 m4keCoreStatus; /* 0x094 */ uint32 reserved3; /* 0x098 */ uint32 ubSlaveTimeout; /* 0x09c */ uint32 diagEn; /* 0x0a0 */ uint32 devTimeout; /* 0x0a4 */ uint32 ubusErrorOutMask; /* 0x0a8 */ uint32 diagCaptStopMask; /* 0x0ac */ uint32 revId; /* 0x0b0 */ uint32 gpTmr2Ctl; /* 0x0b4 */ uint32 gpTmr2Cnt; /* 0x0b8 */ uint32 reserved4[2]; /* 0x0bc */ uint32 diagCtrl; /* 0x0c4 */ uint32 diagStat; /* 0x0c8 */ uint32 diagMask; /* 0x0cc */ uint32 diagRslt; /* 0x0d0 */ uint32 diagCmp; /* 0x0d4 */ uint32 diagCapt; /* 0x0d8 */ uint32 diagCnt; /* 0x0dc */ uint32 diagEdgeCnt; /* 0x0e0 */ uint32 reserved5[4]; /* 0x0e4 */ uint32 smisc_bus_config; /* 0x0f4 */ uint32 lfsr; /* 0x0f8 */ uint32 dqm_pac_lock; /* 0x0fc */ uint32 l1_irq_4ke_mask; /* 0x100 */ uint32 l1_irq_4ke_status; /* 0x104 */ uint32 l1_irq_mips_mask; /* 0x108 */ uint32 l1_irq_mips_status; /* 0x10c */ uint32 l1_irq_mips1_mask; /* 0x110 */ uint32 reserved6[3]; /* 0x114 */ uint32 l2_irq_gp_mask; /* 0x120 */ uint32 l2_irq_gp_status; /* 0x124 */ uint32 l2_irq_gp_set; /* 0x128 */ uint32 reserved7; /* 0x12c */ uint32 gp_in_irq_mask; /* 0x130 */ uint32 gp_in_irq_status; /* 0x134 */ uint32 gp_in_irq_set; /* 0x138 */ uint32 gp_in_irq_sense; /* 0x13c */ uint32 gp_in; /* 0x140 */ uint32 gp_out; /* 0x144 */ } PmcCtrlReg; typedef struct PmcDmaReg { /* 0x00 */ uint32 src; uint32 dest; uint32 cmdList; uint32 lenCtl; /* 0x10 */ uint32 rsltSrc; uint32 rsltDest; uint32 rsltHcs; uint32 rsltLenStat; } PmcDmaReg; typedef struct PmcTokenReg { /* 0x00 */ uint32 bufSize; uint32 bufBase; uint32 idx2ptrIdx; uint32 idx2ptrPtr; /* 0x10 */ uint32 unused[2]; uint32 bufSize2; } PmcTokenReg; typedef struct PmcPerfPowReg { uint32 freqScalarCtrl; /* 0x3c */ uint32 freqScalarMask; /* 0x40 */ } PmcPerfPowReg; typedef struct PmcDQMPac { uint32 dqmPac[32]; } PmcDQMPac; typedef struct PmcDQMReg { uint32 cfg; /* 0x1c00 */ uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ uint32 lowWtmkIrqMask; /* 0x1c0c */ uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ uint32 notEmptyIrqSts; /* 0x1c18 */ uint32 queueRst; /* 0x1c1c */ uint32 notEmptySts; /* 0x1c20 */ uint32 nextAvailMask; /* 0x1c24 */ uint32 nextAvailQueue; /* 0x1c28 */ uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ uint32 autoSrcPidInsert; /* 0x1c34 */ uint32 timerIrqStatus; /* 0x1c38 */ uint32 timerStatus; /* 0x1c3c */ uint32 _4keTimerIrqMask; /* 0x1c40 */ uint32 mipsTimerIrqMask; /* 0x1c44 */ uint32 mips1TimerIrqMask; /* 0x1c48 */ } PmcDQMReg; typedef struct PmcCntReg { uint32 cntr[10]; uint32 unused[6]; /* 0x28-0x3f */ uint32 cntrIrqMask; uint32 cntrIrqSts; } PmcCntReg; typedef struct PmcDqmQCtrlReg { uint32 size; uint32 cfga; uint32 cfgb; uint32 cfgc; } PmcDqmQCtrlReg; typedef struct PmcDqmQDataReg { uint32 word[4]; } PmcDqmQDataReg; typedef struct PmcDqmQMibReg { uint32 qNumFull[32]; uint32 qNumEmpty[32]; uint32 qNumPushed[32]; } PmcDqmQMibReg; typedef struct SSBMaster { uint32 ssbmControl; /* 0x0060 */ uint32 ssbmWrData; /* 0x0064 */ uint32 ssbmRdData; /* 0x0068 */ uint32 ssbmStatus; /* 0x006c */ } SSBMaster; typedef struct PmmReg { uint32 memPowerCtrl; /* 0x0000 */ uint32 regSecurityConfig; /* 0x0004 */ } PmmReg; typedef struct keyholeReg { uint32 ctrlSts; uint32 wrData; uint32 mutex; uint32 rdData; } keyholeReg; typedef struct PmbBus { uint32 config; /* 0x0100 */ uint32 arbiter; /* 0x0104 */ uint32 timeout; /* 0x0108 */ uint32 unused1; /* 0x010c */ keyholeReg keyhole[4]; /* 0x0110-0x014f */ uint32 unused2[44]; /* 0x0150-0x01ff */ uint32 map[64]; /* 0x0200-0x02ff */ }PmbBus; typedef struct CoreCtrl { uint32 coreEnable; /* 0x0400 */ uint32 autoresetControl; /* 0x0404 */ uint32 coreIdle; /* 0x0408 */ uint32 coreResetCause; /* 0x040c */ uint32 memPwrDownCtrl0; /* 0x0410 */ uint32 memPwrDownSts0; /* 0x0414 */ uint32 memPwrDownCtrl1; /* 0x0418 */ uint32 memPwrDownSts1; /* 0x041c */ uint32 sysFlg0Status; /* 0x0420 */ uint32 sysFlg0Set; /* 0x0424 */ uint32 sysFlg0Clear; /* 0x0428 */ uint32 unused1; /* 0x042c */ uint32 usrFlg0Status; /* 0x0430 */ uint32 usrFlg0Set; /* 0x0434 */ uint32 usrFlg0Clear; /* 0x0438 */ uint32 unused2; /* 0x043c */ uint32 subsystemRev; /* 0x0440 */ uint32 resetVector; /* 0x0444 */ } CoreCtrl; typedef struct CoreState { uint32 sysMbx[8]; /* 0x0480 */ uint32 usrMbx[8]; /* 0x04a0 */ uint32 sysMtx[4]; /* 0x04c0 */ uint32 usrMtx[8]; /* 0x04d0 */ } CoreState; typedef struct CoreIntr { uint32 irqStatus; /* 0x0500 */ uint32 irqSet; /* 0x0504 */ uint32 irqClear; /* 0x0508 */ uint32 unused1; /* 0x050c */ uint32 srqStatus; /* 0x0510 */ uint32 srqSet; /* 0x0514 */ uint32 srqClear; /* 0x0518 */ uint32 unused2; /* 0x051c */ uint32 drqStatus; /* 0x0520 */ uint32 drqSet; /* 0x0524 */ uint32 drqClear; /* 0x0528 */ uint32 unused3; /* 0x052c */ uint32 frqStatus; /* 0x0530 */ uint32 frqSet; /* 0x0534 */ uint32 frqClear; /* 0x0538 */ uint32 unused4; /* 0x053c */ uint32 hostIrqLatched; /* 0x0540 */ uint32 hostIrqSet; /* 0x0544 */ uint32 hostIrqClear; /* 0x0548 */ uint32 hostIrqEnable; /* 0x054c */ uint32 obusFaultStatus; /* 0x0550 */ uint32 obusFaultClear; /* 0x0554 */ uint32 obusFaultAddr; /* 0x0558 */ } CoreIntr; typedef struct CoreProfile { uint32 mutex; /* 0x0580 */ uint32 lastConfPcLo; /* 0x0584 */ uint32 lastConfPcHi; /* 0x0588 */ uint32 lastPcLo; /* 0x058c */ uint32 lastPcHi; /* 0x0590 */ uint32 braTargetPc0Lo; /* 0x0594 */ uint32 braTargetPc0Hi; /* 0x0598 */ uint32 braTargetPc1Lo; /* 0x059c */ uint32 braTargetPc1Hi; /* 0x05a0 */ uint32 braTargetPc2Lo; /* 0x05a4 */ uint32 braTargetPc2Hi; /* 0x05a8 */ uint32 braTargetPc3Lo; /* 0x05ac */ uint32 braTargetPc3Hi; /* 0x05b0 */ uint32 unused[3]; /* 0x05b4-0x05bf */ uint32 profSampleW[4]; /* 0x05c0 */ } CoreProfile; typedef struct MaestroMisc { CoreCtrl coreCtrl; /* 0x0400 */ uint32 unused1[14]; /* 0x0448-0x047f */ CoreState coreState; /* 0x0480 */ uint32 unused2[4]; /* 0x04f0-0x04ff */ CoreIntr interrupt; /* 0x0500 */ uint32 unused3[9]; /* 0x055c-0x057f */ CoreProfile profile; /* 0x0580 */ } MaestroMisc; typedef struct Pmc { uint32 baseReserved; /* 0x0000 */ uint32 unused0[1029]; PmcCtrlReg ctrl; /* 0x1018 */ uint32 unused1[174]; /* 0x1148-0x13ff */ PmcTokenReg token; /* 0x1400 */ uint32 unused2[136]; /* 0x141c-0x163b */ PmcPerfPowReg perfPower; /* 0x163c */ uint32 unused3[175]; /* 0x1644-0x18ff */ PmcCntReg hwCounter; /* 0x1900 */ uint32 unused4[110]; /* 0x1948-0x1aff */ PmcDQMPac dqmPac; /* 0x1b00 */ uint32 unused5[32]; /* 0x1b80-0x1bff */ PmcDQMReg dqm; /* 0x1c00 */ uint32 unused6[749]; /* 0x1c4c-0x27ff */ uint32 qStatus[32]; /* 0x2800 */ uint32 unused7[480]; /* 0x2880-0x2fff */ PmcDqmQMibReg qMib; /* 0x3000 */ uint32 unused8[928]; /* 0x3180-0x3fff */ PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ uint32 unused9[992]; /* 0x4080-0x4fff */ PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ } Pmc; #define PMC ((volatile Pmc * const) PMC_BASE) typedef struct Procmon { PmmReg pmm; /* 0x20000 */ uint32 unused11[22]; /* 0x20008-0x2005f */ SSBMaster ssbMasterCtrl; /* 0x20060 */ uint32 unused12[36]; /* 0x20070-0x200ff */ PmbBus pmb; /* 0x20100 */ uint32 unused13[64]; /* 0x20300-0x203ff */ MaestroMisc maestroReg; /* 0x20400 */ } Procmon; #define PROCMON ((volatile Procmon * const) PROC_MON_BASE) typedef struct Ubus4SysModuleTop { uint32 unused0[16]; /* 0x0 */ uint32 UcbData; /* 0x40 */ uint32 UcbHdr; /* 0x44 */ uint32 UcbCntl; /* 0x48 */ uint32 unused1; /* 0x4c */ uint32 ReadUcbHdr; /* 0x50 */ uint32 ReadUcbData; /* 0x54 */ uint32 ReadUcbStatus; /* 0x58 */ uint32 ReacUcbFifoStatus; /* 0x5c */ } Ubus4SysModuleTop; typedef struct Ubus4ModuleClientRegistration { uint32 SlvStatus[16]; /* 0x0 */ uint32 MstStatus[ 8]; /* 0x240 */ uint32 RegCntl; /* 0x260 */ uint32 SlvStopProgDelay; /* 0x264 */ } Ubus4ModuleClientRegistration; #define UBUSSYSTOP ((volatile Ubus4SysModuleTop * const) UBUS_SYS_MODULE_BASE) #define UBUSSYSTOP_REGISTRATION \ ((volatile Ubus4ModuleClientRegistration * const) \ UBUS_SYS_MODULE_REGISTRATION_BASE) typedef struct Ubus4ClkCtrlCfgRegs { uint32 ClockCtrl; #define UBUS4_CLK_CTRL_EN_SHIFT (0) #define UBUS4_CLK_CTRL_EN_MASK (0x1 << UBUS4_CLK_CTRL_EN_SHIFT) #define UBUS4_CLK_BYPASS_SHIFT (2) #define UBUS4_CLK_BYPASS_MASK (0x1 << UBUS4_CLK_BYPASS_SHIFT) #define UBUS4_MIN_CLK_SEL_SHIFT (4) #define UBUS4_MIN_CLK_SEL_MASK (0x7 << UBUS4_MIN_CLK_SEL_SHIFT) #define UBUS4_MID_CLK_SEL_SHIFT (8) #define UBUS4_MID_CLK_SEL_MASK (0x7 << UBUS4_MID_CLK_SEL_SHIFT) uint32 reserved0[3]; uint32 Min2Mid_threshhold; uint32 Mid2Max_threshhold; uint32 Mid2Min_threshhold; uint32 Max2Mid_threshhold; uint32 ClkIntoMin; uint32 ClkIntoMid; uint32 ClkIntoMax; uint32 reserved1; uint32 ClkMinTime; uint32 ClkMidTime; uint32 ClkMaxTime; } Ubus4ClkCtrlCfgRegs; #define UBUS4CLK ((volatile Ubus4ClkCtrlCfgRegs * const) UBUS_MAPPED_BASE) typedef struct { uint32 control; #define PMC_PMBM_START (1 << 31) #define PMC_PMBM_TIMEOUT (1 << 30) #define PMC_PMBM_SLAVE_ERR (1 << 29) #define PMC_PMBM_BUSY (1 << 28) #define PMC_PMBM_BUS_SHIFT (20) #define PMC_PMBM_Read (0 << 24) #define PMC_PMBM_Write (1 << 24) uint32 wr_data; uint32 mutex; uint32 rd_data; } PMB_keyhole_reg; typedef struct PMBMaster { uint32 config; #define PMB_NUM_REGS_SHIFT (20) #define PMB_NUM_REGS_MASK (0x3ff) uint32 arbitger; uint32 timeout; uint32 reserved; PMB_keyhole_reg keyhole[4]; uint32 reserved1[44]; uint32 map[64]; } PMBMaster; #define PMB ((volatile PMBMaster * const) PMB_BASE) /* * LedControl Register Set Definitions. */ typedef struct LedControl { uint32 glbCtrl; /* 0x00 */ uint32 mask; /* 0x04 */ uint32 hWLedEn; /* 0x08 */ uint32 serialLedShiftSel; /* 0x0c */ uint32 flashRateCtrl[4]; /* 0x10-0x1c */ uint32 brightCtrl[4]; /* 0x20-0x2c */ uint32 powerLedCfg; /* 0x30 */ uint32 pledLut[2][16]; /* 0x34-0x70, 0x74-0xb0 */ uint32 HwPolarity; /* 0xb4 */ uint32 SwData; /* 0xb8 */ uint32 SwPolarity; /* 0xbc */ uint32 ParallelLedPolarity; /* 0xc0 */ uint32 SerialLedPolarity; /* 0xc4 */ uint32 HwLedStatus; /* 0xc8 */ uint32 FlashCtrlStatus; uint32 BrtCtrlStatus; uint32 ParallelOutStatus; uint32 SerialRegStatus; } LedControl; #define LED ((volatile LedControl * const) LED_BASE) #define LED_NUM_LEDS 32 #define LED_NUM_TO_MASK(X) (1 << ((X) & (LED_NUM_LEDS-1))) #define GPIO_NUM_TO_LED_MODE_SHIFT(X) \ ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \ ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) typedef struct AXIInterface { uint32 CFG; /* 0x00 */ #define MEMC_AXI_WRITE_ACK_MODE_SHIFT 9 #define MEMC_AXI_FAST_ACK_MODE_MASK (1 << MEMC_AXI_WRITE_ACK_MODE_SHIFT) uint32 REP_ARB_MODE; /* 0x04 */ uint32 SCRATCH; /* 0x08 */ uint32 ESRCID_CFG; /* 0x0c */ uint32 SRC_QUEUE_CTL[8]; /* 0x10 */ uint32 DEBUG; /* 0x30 */ uint32 unused[3]; /* 0x34-0x3f */ } AXIInterface; typedef struct EDISEngine { uint32 REV_ID; /* 0x00 */ uint32 CTRL_TRIG; /* 0x04 */ uint32 CTRL_MODE; /* 0x08 */ uint32 CTRL_SIZE; /* 0x0c */ uint32 CTRL_ADDR_START; /* 0x10 */ uint32 CTRL_ADDR_START_EXT;/* 0x14 */ uint32 CTRL_ADDR_END; /* 0x18 */ uint32 CTRL_ADDR_END_EXT; /* 0x1c */ uint32 CTRL_WRITE_MASKS; /* 0x20 */ uint32 CTRL_INT_ENABLES; /* 0x24 */ uint32 unused0[6]; /* 0x28-0x3f */ uint32 STAT_MAIN; /* 0x40 */ uint32 STAT_WORDS_WRITTEN; /* 0x44 */ uint32 STAT_WORDS_READ; /* 0x48 */ uint32 STAT_ERROR_COUNT; /* 0x4c */ uint32 STAT_ERROR_BITS; /* 0x50 */ uint32 STAT_ADDR_LAST; /* 0x54 */ uint32 STAT_ADDR_LAST_EXT; /* 0x58 */ uint32 STAT_CLOCK_CYCLES; /* 0x5c */ uint32 unused1[7]; /* 0x60-0x7b */ uint32 STAT_DEBUG; /* 0x7c */ uint32 STAT_DATA_PORT[8]; /* 0x80-0x9c */ uint32 GEN_LFSR_STATE[4]; /* 0xa0-0xac */ uint32 GEN_CLOCK; /* 0xb0 */ uint32 GEN_PATTERN; /* 0xb4 */ uint32 unused2[2]; /* 0xb8-0xbf */ uint32 BYTELANE_0_CTRL_LO; /* 0xc0 */ uint32 BYTELANE_0_CTRL_HI; /* 0xc4 */ uint32 BYTELANE_1_CTRL_LO; /* 0xc8 */ uint32 BYTELANE_1_CTRL_HI; /* 0xcc */ uint32 BYTELANE_2_CTRL_LO; /* 0xd0 */ uint32 BYTELANE_2_CTRL_HI; /* 0xd4 */ uint32 BYTELANE_3_CTRL_LO; /* 0xd8 */ uint32 BYTELANE_3_CTRL_HI; /* 0xdc */ uint32 BYTELANE_0_STAT_LO; /* 0xe0 */ uint32 BYTELANE_0_STAT_HI; /* 0xe4 */ uint32 BYTELANE_1_STAT_LO; /* 0xe8 */ uint32 BYTELANE_1_STAT_HI; /* 0xec */ uint32 BYTELANE_2_STAT_LO; /* 0xf0 */ uint32 BYTELANE_2_STAT_HI; /* 0xf4 */ uint32 BYTELANE_3_STAT_LO; /* 0xf8 */ uint32 BYTELANE_3_STAT_HI; /* 0xfc */ } EDISEngine; typedef struct RangeCtrl { uint32 CTRL; /* 0x00 */ uint32 UBUS0_PORT; /* 0x04 */ uint32 UBUS0_PORT_UPPER; /* 0x08 */ uint32 BASE; /* 0x0c */ uint32 BASE_UPPER; /* 0x10 */ uint32 SECLEV_EN; /* 0x14 */ } RangeCtrl; typedef struct SecureRangeCheckers { uint32 LOCK; /* 0x00 */ uint32 LOG_INFO[3]; /* 0x04 - 0x0c */ RangeCtrl RANGE_CTRL[8];/* 0x10 - 0xcc */ uint32 unused[12]; /* 0xd0 - 0xff */ } SecureRangeCheckers; typedef struct DDRPhyControl { uint32 PRIMARY_REVISION; /* 0x00 */ uint32 SECONDARY_REVISION; /* 0x04 */ uint32 FEATURE; /* 0x08 */ uint32 PLL_STATUS; /* 0x0c */ uint32 PLL_CONFIG; /* 0x10 */ uint32 PLL_CONTROL1; /* 0x14 */ uint32 PLL_CONTROL2; /* 0x18 */ uint32 PLL_CONTROL3; /* 0x1c */ uint32 PLL_DIVIDER; /* 0x20 */ uint32 PLL_PRE_DIVIDER; /* 0x24 */ uint32 PLL_SS_EN; /* 0x28 */ uint32 PLL_SS_CFG; /* 0x2c */ uint32 AUX_CONTROL; /* 0x30 */ uint32 IDLE_PAD_CONTROL; /* 0x34 */ uint32 IDLE_PAD_EN0; /* 0x38 */ uint32 IDLE_PAD_EN1; /* 0x3c */ uint32 DRIVE_PAD_CTL; /* 0x40 */ uint32 DRIVE_PAD_CTL_2T; /* 0x44 */ uint32 DRIVE_PAD_CTL_2T_A; /* 0x48 */ uint32 STATIC_PAD_CTL; /* 0x4c */ uint32 STATIC_PAD_CTL_2T; /* 0x50 */ uint32 STATIC_PAD_CTL_2T_A; /* 0x54 */ uint32 RX_TRIM; /* 0x58 */ uint32 DRAM_CFG; /* 0x5c */ uint32 DRAM_TIMING2; /* 0x60 */ uint32 DRAM_TIMING3; /* 0x64 */ uint32 VDL_REGS[45]; /* 0x68-0x11b */ uint32 UPDATE_VDL; /* 0x11c */ uint32 UPDATE_VDL_SNOOP1; /* 0x120 */ uint32 UPDATE_VDL_SNOOP2; /* 0x124 */ uint32 CMND_REG1; /* 0x128 */ uint32 CMND_AUX_REG1; /* 0x12c */ uint32 CMND_REG2; /* 0x130 */ uint32 CMND_AUX_REG2; /* 0x134 */ uint32 CMND_REG3; /* 0x138 */ uint32 CMND_AUX_REG3; /* 0x13c */ uint32 CMND_REG4; /* 0x140 */ uint32 CMND_AUX_REG4; /* 0x144 */ uint32 MODE_REG[8]; /* 0x148-167 */ uint32 ALERT_CLEAR; /* 0x168 */ uint32 ALERT_STATUS; /* 0x16c */ uint32 ALERT_DF1; /* 0x170 */ uint32 WRITE_LEVEL_CTRL; /* 0x174 */ uint32 WRITE_LEVEL_STATUS; /* 0x178 */ uint32 READ_EN_CTRL; /* 0x17c */ uint32 READ_EN_STATUS ; /* 0x180 */ uint32 VIRT_VTT_CTRL; /* 0x184 */ uint32 VIRT_VTT_STATUS; /* 0x188 */ uint32 VIRT_VTT_CONNECTION; /* 0x18c */ uint32 VIRT_VTT_OVERRIDE; /* 0x190 */ uint32 VREF_DAC_CTRL; /* 0x194 */ uint32 STANDBY_CTRL; /* 0x198 */ uint32 DEBUG_FREEZE_EN; /* 0x19c */ uint32 DEBUG_MUX_CTRL; /* 0x1a0 */ uint32 DFI_CTRL; /* 0x1a4 */ uint32 WRITE_ODT_CTRL; /* 0x1a8 */ uint32 ABI_PAR_CTRL; /* 0x1ac */ uint32 ZQ_CAL; /* 0x1b0 */ uint32 unused6[147]; /* 0x1b4-0x3ff */ } DDRPhyControl; typedef struct DDRPhyByteLaneControl { uint32 VDL_CTRL_WR[10]; /* 0x00 - 0x27 */ uint32 VDL_CTRL_RD[22]; /* 0x28 - 0x7f */ uint32 VDL_CLK_CTRL; /* 0x80 */ uint32 VDL_LDE_CTRL; /* 0x84 */ uint32 RD_EN_DLY_CYC; /* 0x88 */ #define RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0x0 #define RD_EN_DLY_CYC_CS0_CYCLES_MASK (0xf<>5) #define WLU_SRCPID_TO_REG_BIT(srcpid) ((srcpid)%32) uint32 wlu_srcpid[MAX_WLU_SRCPID_REG_NUM]; /* 0xd8 */ uint32 qos_reg[2]; /* 0xf8 */ }CoherencyPortCfgReg_t; #define CohPortCfg ((volatile CoherencyPortCfgReg_t * const) UBUS_COHERENCY_PORT_CFG_BASE) /* CCI-400 Reg Defines */ #define CCI400_CONTROL_OVERRIDE_REG_OFFSET 0 #define CCI400_CONTROL_OVERRIDE_SNOOP_ENABLE_OFFSET (1<<0) #define CCI400_SECURE_ACCESS_REG_OFFSET 8 #define CCI400_SECURE_ACCESS_UNSECURE_ENABLE (1<<0) #define CCI400_S2_SAHREABLE_OVERRIDE_REG_OFFSET 0x3004 #define CCI400_S2_SAHREABLE_OVERRIDE_AX_DOMAIN 0x3 #define CCI400_S3_SNOOP_CTRL_REG_OFFSET 0x4000 #define CCI400_S3_SNOOP_CTRL_EN_SNOOP (1<<0) typedef struct BIUCFG_Access { uint32 permission; /* 0x0 */ uint32 sbox; /* 0x4 */ uint32 cpu_defeature; /* 0x8 */ uint32 dbg_security; /* 0xc */ uint32 rsvd1[32]; /* 0x10 - 0x8f */ uint64 violation[2]; /* 0x90 - 0x9f */ uint32 ts_access[2]; /* 0xa0 - 0xa7 */ uint32 rsvd2[22]; /* 0xa8 - 0xff */ }BIUCFG_Access; typedef struct BIUCFG_Cluster { uint32 permission; /* 0x0 */ uint32 config; /* 0x4 */ uint32 status; /* 0x8 */ uint32 control; /* 0xc */ uint32 cpucfg; /* 0x10 */ uint32 dbgrom; /* 0x14 */ uint32 rsvd1[2]; /* 0x18 - 0x1f */ uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ uint32 rsvd2[48]; /* 0x40 - 0xff */ }BIUCFG_Cluster; typedef struct BIUCFG_AuxClkCtrl { uint32 clk_control; /* 0x0 */ uint32 clk_ramp; /* 0x4 */ uint32 clk_pattern; /* 0x8 */ uint32 rsvd; /* 0xC */ } BIUCFG_AuxClkCtrl; typedef struct BIUCFG_Aux { uint32 permission; /* 0 */ uint32 rsvd1[3]; /* 0x04 - 0x0c */ BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */ uint32 rsvd2[52]; /* 0x30 - 0xFF */ } BIUCFG_Aux; typedef struct BIUCFG { BIUCFG_Access access; /* 0x0 - 0xff*/ BIUCFG_Cluster cluster[1]; /* 0x100 - 0x1ff*/ uint32 rsvd1[320]; /* 0x200 - 0x6ff */ BIUCFG_Aux aux; /* 0x700 - 0x7ff */ uint32 rsvd2[2560]; /* 0x800 - 0x2fff */ }BIUCFG; #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) #endif #ifdef __cplusplus } #endif #endif