#include "inc/68552.dtsi"

/ {
	memory_controller {
		memcfg = <(BP_DDR_SPEED_1067_14_14_14 | \
					BP_DDR_TOTAL_SIZE_1024MB  | \
					BP_DDR_DEVICE_WIDTH_16    | \
					BP_DDR_TOTAL_WIDTH_32BIT  | \
					BP_DDR_SSC_CONFIG_1)>;
	};
};

/ {
	model = "968550RFDVT";

      buttons {
        compatible = "brcm,buttons";
        reset_button {
            ext_irq = <&bca_extintr 14 BCA_GPIO_ACTIVE_LOW (BCA_EXTINTR_TYPE_LOW_LEVEL | BCA_EXTINTR_TYPE_SENSE_EDGE)>;
            press {
                print = "Button Press -- Hold for 5s to do restore to default";
     };
            hold {
                rst_to_dflt = <5>;
            };
            release {
                reset = <0>;
            };
        };
        ses_button {
            ext_irq = <&bca_extintr 26 BCA_GPIO_ACTIVE_LOW (BCA_EXTINTR_TYPE_LOW_LEVEL | BCA_EXTINTR_TYPE_SENSE_EDGE)>;
            release {
                ses_short_period = <0>;
                ses_long_period = <3>;
            };
        };
    };

    xfp_sfp: xfp_sfp {
        compatible = "brcm,sfp";
        pinctrl-names = "default", "tx-sd";
        pinctrl-0 = <&pon_lbe_p_pin_100>;
        pinctrl-1 = <&pon_lbe_p_pin_100 &rogue_onu_in_pin_29>;
        i2c-bus = <&i2c0>;
        los-gpio = <&gpioc 12 GPIO_ACTIVE_HIGH>;
        mod-def0 = <&bca_extintr 16 GPIO_ACTIVE_LOW (BCA_EXTINTR_TYPE_BOTH_EDGE | BCA_EXTINTR_TYPE_SENSE_EDGE)>;
        tx-power-gpio = <&gpioc 13 GPIO_ACTIVE_HIGH>;
    };

    wan_serdes {
            compatible = "brcm,pon-drv";
            trx = <&xfp_sfp>;
            tx-polarity-invert;
    };
};

&i2c0 {
    pinctrl-0 = <&i2c_scl_pin_77 &i2c_sda_pin_78>;
    pinctrl-names = "default";
    status = "okay";
};
&nand {
	status = "okay";
};
&wdt {
	status = "okay";
};
&uart0 {
	status = "okay";
};

&usb_ctrl {
    pinctrl-names = "default";
    pinctrl-0 = <&usb0_pwr_pins &usb1_pwr_pins>;
    xhci-enable;
    status = "okay";
};
&usb0_ehci {
    status = "okay";
};
&usb0_xhci {
    status = "okay";
};
&usb0_ohci {
    status = "okay";
};
&usb1_ehci {
    status = "okay";
};
&usb1_ohci {
    status = "okay";
};

&pincontroller {
    pinctrl-names = "default";
    pinctrl-0 = <&c0_femctrl_0_pin_84 &c0_femctrl_1_pin_85 &c0_femctrl_2_pin_86 &c0_femctrl_3_pin_87 \
                 &c0_femctrl_4_pin_88 &c0_femctrl_5_pin_89 &c1_femctrl_0_pin_90 &c1_femctrl_1_pin_91 \
                 &c1_femctrl_2_pin_92 &c1_femctrl_3_pin_93 &c1_femctrl_4_pin_94 &c1_femctrl_5_pin_95 >;
};

&mdio {
        phy1:1 {
                status = "okay";
        };

        phy2:2 {
                status = "okay";
        };

        phy_serdes: serdes {
                phy-handle = <&phy_ext_serdes>;
                status = "okay";
        };

        phy_ext_serdes: ext_serdes {
                reg = <0x1e>;
                enet-phy-lane-swap;
                caps-no-10000;
                caps-no-5000;
                status = "okay";
        };
};

&switch0 {
        pinctrl-names = "default";
        pinctrl-0 = <&per_mdc_pin_68 &per_mdio_pin_69>;

        ports {
                port0@0 {
                        label = "eth0";
                        oam-idx = <0>;
                        status = "okay";
                };

                port1@1 {
                        label = "eth1";
                        oam-idx = <1>;
                        status = "okay";
                };

                port5@5 {
                        label = "eth2";
                        oam-idx = <2>;
                        status = "okay";
                };
        };
};

#if defined(CONFIG_BCM_PCIE_HCD) || defined(CONFIG_BCM_PCIE_HCD_MODULE)
&pcie0 {
    brcm,dual-lane;
    status = "okay";
};
#endif // defined(CONFIG_BCM_PCIE_HCD) || defined (CONFIG_BCM_PCIE_HCD_MODULE)