--- zzzz-none-000/linux-4.19.183/include/linux/mtd/rawnand.h	2021-03-24 10:07:39.000000000 +0000
+++ bcm63-7530ax-756/linux-4.19.183/include/linux/mtd/rawnand.h	2023-06-28 08:54:20.000000000 +0000
@@ -198,6 +198,15 @@
  */
 #define NAND_USE_BOUNCE_BUFFER	0x00100000
 
+#if defined(CONFIG_BCM_KF_MTD_BCMNAND)
+/* For Hynix MLC flashes, the BI are written to last and (last-2) pages. */
+#define NAND_SCAN_BI_3RD_PAGE   0x10000000
+
+/* NOP=1 NAND SLC device */
+#define NAND_PAGE_NOP1          0x20000000
+#endif
+
+
 /*
  * In case your controller is implementing ->cmd_ctrl() and is relying on the
  * default ->cmdfunc() implementation, you may want to let the core handle the
@@ -1331,6 +1340,13 @@
 	uint16_t ecc_strength_ds;
 	uint16_t ecc_step_ds;
 	int onfi_timing_mode_default;
+#if defined(CONFIG_BCM_KF_MTD_BCMNAND)
+	/* Before ONFI auto timing adjustment in kernel, add Broadcom specific timing
+	* parameters for better performnace.
+	*/
+	uint32_t timing_1;
+	uint32_t timing_2;
+#endif
 	int badblockpos;
 	int badblockbits;
 
@@ -1518,6 +1534,13 @@
 		uint16_t step_ds;
 	} ecc;
 	int onfi_timing_mode_default;
+#if defined(CONFIG_BCM_KF_MTD_BCMNAND)
+	/* before ONFI auto timing adjustment in kernel, add Broadcom specific timing
+	 * parameters for better performnace.
+	 */
+	uint32_t timing_1;
+	uint32_t timing_2;
+#endif
 };
 
 /**