/* Copyright (c) 2015 Broadcom Corporation All Rights Reserved <:label-BRCM:2015:DUAL/GPL:standard Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Not withstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. :> */ /* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */ #ifndef MERLIN16_SHORTFIN_FIELDS_H #define MERLIN16_SHORTFIN_FIELDS_H #define rd_ams_rx_term_lowzvdd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,0,15,__ERR) #define wr_ams_rx_term_lowzvdd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x8000,15,wr_val) #define rd_ams_rx_term_lowzgnd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,1,15,__ERR) #define wr_ams_rx_term_lowzgnd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x4000,14,wr_val) #define rd_ams_rx_term_cmult_ena() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,2,15,__ERR) #define wr_ams_rx_term_cmult_ena(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x2000,13,wr_val) #define rd_ams_rx_term_cm_ena() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,3,15,__ERR) #define wr_ams_rx_term_cm_ena(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x1000,12,wr_val) #define rd_ams_rx_en_rxck_test() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,4,14,__ERR) #define wr_ams_rx_en_rxck_test(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0c00,10,wr_val) #define rd_ams_rx_en_rxck_testport() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,6,15,__ERR) #define wr_ams_rx_en_rxck_testport(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0200,9,wr_val) #define rd_ams_rx_spare_0_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,7,14,__ERR) #define wr_ams_rx_spare_0_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0180,7,wr_val) #define rd_ams_rx_input_cm_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,9,15,__ERR) #define wr_ams_rx_input_cm_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0040,6,wr_val) #define rd_ams_rx_vga_cm_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,10,15,__ERR) #define wr_ams_rx_vga_cm_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0020,5,wr_val) #define rd_ams_rx_rcm_sum() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,11,15,__ERR) #define wr_ams_rx_rcm_sum(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0010,4,wr_val) #define rd_ams_rx_sigdet_bypass() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,12,15,__ERR) #define wr_ams_rx_sigdet_bypass(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0008,3,wr_val) #define rd_ams_rx_sigdet_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,13,15,__ERR) #define wr_ams_rx_sigdet_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0004,2,wr_val) #define rd_ams_rx_cm_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,14,15,__ERR) #define wr_ams_rx_cm_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0002,1,wr_val) #define rd_ams_rx_sum_cm_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd090,15,15,__ERR) #define wr_ams_rx_sum_cm_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd090,0x0001,0,wr_val) #define rd_ams_rx_curr_dfe_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,2,13,__ERR) #define wr_ams_rx_curr_dfe_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x3800,11,wr_val) #define rd_ams_rx_spare_1_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,5,13,__ERR) #define wr_ams_rx_spare_1_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x0700,8,wr_val) #define rd_ams_rx_curr_pi() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,8,13,__ERR) #define wr_ams_rx_curr_pi(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x00e0,5,wr_val) #define rd_ams_rx_curr_ctle() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,11,13,__ERR) #define wr_ams_rx_curr_ctle(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x001c,2,wr_val) #define rd_ams_rx_vga_en_hgain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,14,15,__ERR) #define wr_ams_rx_vga_en_hgain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x0002,1,wr_val) #define rd_ams_rx_vga_out_idle() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd091,15,15,__ERR) #define wr_ams_rx_vga_out_idle(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd091,0x0001,0,wr_val) #define rd_ams_rx_spare_2_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd092,0,14,__ERR) #define wr_ams_rx_spare_2_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd092,0xc000,14,wr_val) #define rd_ams_rx_en_dfe_tap_fb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd092,2,11,__ERR) #define wr_ams_rx_en_dfe_tap_fb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd092,0x3e00,9,wr_val) #define rd_ams_rx_curr_vga() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd092,7,13,__ERR) #define wr_ams_rx_curr_vga(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd092,0x01c0,6,wr_val) #define rd_ams_rx_spare_2_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd092,10,13,__ERR) #define wr_ams_rx_spare_2_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd092,0x0038,3,wr_val) #define rd_ams_rx_curr_dfe_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd092,13,13,__ERR) #define wr_ams_rx_curr_dfe_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd092,0x0007,0,wr_val) #define rd_ams_rx_ll_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,1,15,__ERR) #define wr_ams_rx_ll_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x4000,14,wr_val) #define rd_ams_rx_seli1p25dfe() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,2,15,__ERR) #define wr_ams_rx_seli1p25dfe(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x2000,13,wr_val) #define rd_ams_rx_i4deadzone() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,3,15,__ERR) #define wr_ams_rx_i4deadzone(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x1000,12,wr_val) #define rd_ams_rx_curr_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,4,13,__ERR) #define wr_ams_rx_curr_sigdet(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0e00,9,wr_val) #define rd_ams_rx_curr_vddr_afe() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,7,13,__ERR) #define wr_ams_rx_curr_vddr_afe(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x01c0,6,wr_val) #define rd_ams_rx_os2x_mode_even_odd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,10,15,__ERR) #define wr_ams_rx_os2x_mode_even_odd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0020,5,wr_val) #define rd_ams_rx_dfe_os2x_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,11,15,__ERR) #define wr_ams_rx_dfe_os2x_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0010,4,wr_val) #define rd_ams_rx_en_20b_demux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,12,15,__ERR) #define wr_ams_rx_en_20b_demux(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0008,3,wr_val) #define rd_ams_rx_en_clk16() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,13,15,__ERR) #define wr_ams_rx_en_clk16(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0004,2,wr_val) #define rd_ams_rx_en_clk33() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,14,15,__ERR) #define wr_ams_rx_en_clk33(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0002,1,wr_val) #define rd_ams_rx_en_vcctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd093,15,15,__ERR) #define wr_ams_rx_en_vcctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd093,0x0001,0,wr_val) #define rd_ams_rx_vga_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,0,12,__ERR) #define wr_ams_rx_vga_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0xf000,12,wr_val) #define rd_ams_rx_oc_2x() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,4,15,__ERR) #define wr_ams_rx_oc_2x(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0800,11,wr_val) #define rd_ams_rx_spare_4_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,5,15,__ERR) #define wr_ams_rx_spare_4_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0400,10,wr_val) #define rd_ams_rx_i_rx_hi_z() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,6,15,__ERR) #define wr_ams_rx_i_rx_hi_z(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0200,9,wr_val) #define rd_ams_rx_spare_4_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,7,15,__ERR) #define wr_ams_rx_spare_4_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0100,8,wr_val) #define rd_ams_rx_en_recclkdiv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,8,15,__ERR) #define wr_ams_rx_en_recclkdiv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0080,7,wr_val) #define rd_ams_rx_div3o4o5() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,9,14,__ERR) #define wr_ams_rx_div3o4o5(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x0060,5,wr_val) #define rd_ams_rx_recclkdiv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd094,11,11,__ERR) #define wr_ams_rx_recclkdiv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd094,0x001f,0,wr_val) #define rd_ams_rx_dcc2_phase_flip() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,0,15,__ERR) #define wr_ams_rx_dcc2_phase_flip(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x8000,15,wr_val) #define rd_ams_rx_slcr_calib_range_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,1,15,__ERR) #define wr_ams_rx_slcr_calib_range_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x4000,14,wr_val) #define rd_ams_rx_pi_pd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,2,15,__ERR) #define wr_ams_rx_pi_pd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x2000,13,wr_val) #define rd_ams_rx_dcc1_phase_flip() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,3,15,__ERR) #define wr_ams_rx_dcc1_phase_flip(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x1000,12,wr_val) #define rd_ams_rx_en_dfeclk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,4,15,__ERR) #define wr_ams_rx_en_dfeclk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x0800,11,wr_val) #define rd_ams_rx_ctle_gain_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,5,12,__ERR) #define wr_ams_rx_ctle_gain_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x0780,7,wr_val) #define rd_ams_rx_curr_in_offset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,9,13,__ERR) #define wr_ams_rx_curr_in_offset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x0070,4,wr_val) #define rd_ams_rx_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd095,12,12,__ERR) #define wr_ams_rx_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd095,0x000f,0,wr_val) #define rd_ams_rx_sigdet_offset_correction_pos() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,3,11,__ERR) #define wr_ams_rx_sigdet_offset_correction_pos(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x1f00,8,wr_val) #define rd_ams_rx_sigdet_calibration_select() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,8,15,__ERR) #define wr_ams_rx_sigdet_calibration_select(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x0080,7,wr_val) #define rd_ams_rx_sum_gain_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,9,12,__ERR) #define wr_ams_rx_sum_gain_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x0078,3,wr_val) #define rd_ams_rx_en_sigdet_calib() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,13,15,__ERR) #define wr_ams_rx_en_sigdet_calib(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x0004,2,wr_val) #define rd_ams_rx_hiz_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,14,15,__ERR) #define wr_ams_rx_hiz_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x0002,1,wr_val) #define rd_ams_rx_m1_sign() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd096,15,15,__ERR) #define wr_ams_rx_m1_sign(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd096,0x0001,0,wr_val) #define rd_ams_rx_spare_7_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd097,2,12,__ERR) #define wr_ams_rx_spare_7_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd097,0x3c00,10,wr_val) #define rd_ams_rx_sigdet_threshold() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd097,6,11,__ERR) #define wr_ams_rx_sigdet_threshold(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd097,0x03e0,5,wr_val) #define rd_ams_rx_sigdet_offset_correction_neg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd097,11,11,__ERR) #define wr_ams_rx_sigdet_offset_correction_neg(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd097,0x001f,0,wr_val) #define rd_ams_rx_rxpon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd098,14,15,__ERR) #define wr_ams_rx_rxpon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd098,0x0002,1,wr_val) #define rd_ams_rx_vgapon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd098,15,15,__ERR) #define wr_ams_rx_vgapon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd098,0x0001,0,wr_val) #define rd_ams_rx_vgapon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd099,8,12,__ERR) #define rd_ams_rx_rxpon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd099,12,12,__ERR) #define rd_ams_tx_lowlatency_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,0,15,__ERR) #define wr_ams_tx_lowlatency_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x8000,15,wr_val) #define rd_ams_tx_fifo_resetb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,1,15,__ERR) #define wr_ams_tx_fifo_resetb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x4000,14,wr_val) #define rd_ams_tx_ll_fifo_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,2,13,__ERR) #define wr_ams_tx_ll_fifo_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x3800,11,wr_val) #define rd_ams_tx_ll_fifo_zero_out() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,5,15,__ERR) #define wr_ams_tx_ll_fifo_zero_out(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0400,10,wr_val) #define rd_ams_tx_ll_polarity_flip() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,6,15,__ERR) #define wr_ams_tx_ll_polarity_flip(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0200,9,wr_val) #define rd_ams_tx_ll_selpath_tx() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,7,15,__ERR) #define wr_ams_tx_ll_selpath_tx(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0100,8,wr_val) #define rd_ams_tx_enable_os_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,8,15,__ERR) #define wr_ams_tx_enable_os_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0080,7,wr_val) #define rd_ams_tx_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,9,12,__ERR) #define wr_ams_tx_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0078,3,wr_val) #define rd_ams_tx_ticksel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,13,14,__ERR) #define wr_ams_tx_ticksel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0006,1,wr_val) #define rd_ams_tx_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a0,15,15,__ERR) #define wr_ams_tx_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a0,0x0001,0,wr_val) #define rd_ams_tx_en_slow() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,1,12,__ERR) #define wr_ams_tx_en_slow(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x7800,11,wr_val) #define rd_ams_tx_en_wclk33() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,5,15,__ERR) #define wr_ams_tx_en_wclk33(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0400,10,wr_val) #define rd_ams_tx_en_wclk20() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,6,15,__ERR) #define wr_ams_tx_en_wclk20(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0200,9,wr_val) #define rd_ams_tx_en_wclk16() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,7,15,__ERR) #define wr_ams_tx_en_wclk16(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0100,8,wr_val) #define rd_ams_tx_testclk_ena() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,8,15,__ERR) #define wr_ams_tx_testclk_ena(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0080,7,wr_val) #define rd_ams_tx_testsel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,9,14,__ERR) #define wr_ams_tx_testsel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0060,5,wr_val) #define rd_ams_tx_cntrl_rxdetect_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,11,15,__ERR) #define wr_ams_tx_cntrl_rxdetect_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0010,4,wr_val) #define rd_ams_tx_rxdtct_th_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,12,14,__ERR) #define wr_ams_tx_rxdtct_th_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x000c,2,wr_val) #define rd_ams_tx_en_high_current() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,14,15,__ERR) #define wr_ams_tx_en_high_current(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0002,1,wr_val) #define rd_ams_tx_enable_os_4() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a1,15,15,__ERR) #define wr_ams_tx_enable_os_4(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a1,0x0001,0,wr_val) #define rd_ams_tx_fifo_phsdetect_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,1,15,__ERR) #define wr_ams_tx_fifo_phsdetect_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x4000,14,wr_val) #define rd_ams_tx_ibias_pibuf_cntl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,2,13,__ERR) #define wr_ams_tx_ibias_pibuf_cntl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x3800,11,wr_val) #define rd_ams_tx_ibias_pi_cntl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,5,13,__ERR) #define wr_ams_tx_ibias_pi_cntl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0700,8,wr_val) #define rd_ams_tx_ibias_opamp_cntl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,8,13,__ERR) #define wr_ams_tx_ibias_opamp_cntl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x00e0,5,wr_val) #define rd_ams_tx_dcc_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,11,15,__ERR) #define wr_ams_tx_dcc_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x0010,4,wr_val) #define rd_ams_tx_en_hpf() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a2,12,12,__ERR) #define wr_ams_tx_en_hpf(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a2,0x000f,0,wr_val) #define rd_ams_tx_refcalm() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a3,2,12,__ERR) #define wr_ams_tx_refcalm(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a3,0x3c00,10,wr_val) #define rd_ams_tx_refcalp() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a3,6,12,__ERR) #define wr_ams_tx_refcalp(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a3,0x03c0,6,wr_val) #define rd_ams_tx_refcalshunt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a3,10,12,__ERR) #define wr_ams_tx_refcalshunt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a3,0x003c,2,wr_val) #define rd_ams_tx_spare_3_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a3,14,14,__ERR) #define wr_ams_tx_spare_3_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a3,0x0003,0,wr_val) #define rd_ams_tx_shntpost2_post2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a4,0,12,__ERR) #define wr_ams_tx_shntpost2_post2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a4,0xf000,12,wr_val) #define rd_ams_tx_shntpost1_post1pre() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a4,4,10,__ERR) #define wr_ams_tx_shntpost1_post1pre(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a4,0x0fc0,6,wr_val) #define rd_ams_tx_shntpre_post1pre() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a4,10,10,__ERR) #define wr_ams_tx_shntpre_post1pre(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a4,0x003f,0,wr_val) #define rd_ams_tx_post2to1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,2,15,__ERR) #define wr_ams_tx_post2to1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x2000,13,wr_val) #define rd_ams_tx_en_pre() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,3,15,__ERR) #define wr_ams_tx_en_pre(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x1000,12,wr_val) #define rd_ams_tx_en_post1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,4,15,__ERR) #define wr_ams_tx_en_post1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0800,11,wr_val) #define rd_ams_tx_en_post2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,5,15,__ERR) #define wr_ams_tx_en_post2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x0400,10,wr_val) #define rd_ams_tx_shntmain_post2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,6,12,__ERR) #define wr_ams_tx_shntmain_post2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x03c0,6,wr_val) #define rd_ams_tx_shntmain_post1pre() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a5,10,10,__ERR) #define wr_ams_tx_shntmain_post1pre(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a5,0x003f,0,wr_val) #define rd_ams_tx_shntpost1_post1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a6,0,11,__ERR) #define wr_ams_tx_shntpost1_post1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a6,0xf800,11,wr_val) #define rd_ams_tx_dis_cal() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a6,5,11,__ERR) #define wr_ams_tx_dis_cal(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a6,0x07c0,6,wr_val) #define rd_ams_tx_spare_6_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a6,10,12,__ERR) #define wr_ams_tx_spare_6_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a6,0x003c,2,wr_val) #define rd_ams_tx_pd_phasedet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a6,14,15,__ERR) #define wr_ams_tx_pd_phasedet(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0002,1,wr_val) #define rd_ams_tx_en_shuntmode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a6,15,15,__ERR) #define wr_ams_tx_en_shuntmode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a6,0x0001,0,wr_val) #define rd_ams_tx_refcalpcs() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a7,3,12,__ERR) #define wr_ams_tx_refcalpcs(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a7,0x1e00,9,wr_val) #define rd_ams_tx_refcalmcs() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a7,7,12,__ERR) #define wr_ams_tx_refcalmcs(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a7,0x01e0,5,wr_val) #define rd_ams_tx_shntmain_post1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a7,11,11,__ERR) #define wr_ams_tx_shntmain_post1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a7,0x001f,0,wr_val) #define rd_ams_tx_spare_8_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a8,7,8,__ERR) #define wr_ams_tx_spare_8_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a8,0x01fe,1,wr_val) #define rd_ams_tx_shnten_main() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a8,15,15,__ERR) #define wr_ams_tx_shnten_main(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a8,0x0001,0,wr_val) #define rd_ams_tx_sel_txmaster() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a9,12,15,__ERR) #define wr_ams_tx_sel_txmaster(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0008,3,wr_val) #define rd_ams_tx_auto_ll_selpath_tx_dis() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a9,13,15,__ERR) #define wr_ams_tx_auto_ll_selpath_tx_dis(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0004,2,wr_val) #define rd_ams_tx_txpon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0a9,14,15,__ERR) #define wr_ams_tx_txpon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0a9,0x0002,1,wr_val) #define rd_ams_tx_rescal() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0aa,8,12,__ERR) #define rd_ams_tx_txpon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0aa,12,12,__ERR) #define rdc_ams_pll_cpar() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,0,14,__ERR) #define wrc_ams_pll_cpar(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0xc000,14,wr_val) #define rdc_ams_pll_term_cm_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,2,15,__ERR) #define wrc_ams_pll_term_cm_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0x2000,13,wr_val) #define rdc_ams_pll_spare_0_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,3,15,__ERR) #define wrc_ams_pll_spare_0_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0x1000,12,wr_val) #define rdc_ams_pll_rpar() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,4,13,__ERR) #define wrc_ams_pll_rpar(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0e00,9,wr_val) #define rdc_ams_pll_lc_refclk_adj_1_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,7,14,__ERR) #define wrc_ams_pll_lc_refclk_adj_1_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0x0180,7,wr_val) #define rdc_ams_pll_spare_0_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b0,9,9,__ERR) #define wrc_ams_pll_spare_0_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b0,0x007f,0,wr_val) #define rdc_ams_pll_en_hcur_vco() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,0,15,__ERR) #define wrc_ams_pll_en_hcur_vco(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x8000,15,wr_val) #define rdc_ams_pll_enb_10t() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,1,15,__ERR) #define wrc_ams_pll_enb_10t(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x4000,14,wr_val) #define rdc_ams_pll_enb_8t() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,2,15,__ERR) #define wrc_ams_pll_enb_8t(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x2000,13,wr_val) #define rdc_ams_pll_vco_range() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,3,9,__ERR) #define wrc_ams_pll_vco_range(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x1fc0,6,wr_val) #define rdc_ams_pll_en_8p5g_vco() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,10,15,__ERR) #define wrc_ams_pll_en_8p5g_vco(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0020,5,wr_val) #define rdc_ams_pll_spare_1_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,11,15,__ERR) #define wrc_ams_pll_spare_1_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x0010,4,wr_val) #define rdc_ams_pll_curr_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b1,12,12,__ERR) #define wrc_ams_pll_curr_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b1,0x000f,0,wr_val) #define rdc_ams_pll_en_i4iqbuf() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,0,14,__ERR) #define wrc_ams_pll_en_i4iqbuf(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0xc000,14,wr_val) #define rdc_ams_pll_vco_buf_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,2,12,__ERR) #define wrc_ams_pll_vco_buf_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x3c00,10,wr_val) #define rdc_ams_pll_clkvco_cal_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,6,15,__ERR) #define wrc_ams_pll_clkvco_cal_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0200,9,wr_val) #define rdc_ams_pll_en_cmos_refclk_ch_hiz() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,7,15,__ERR) #define wrc_ams_pll_en_cmos_refclk_ch_hiz(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0100,8,wr_val) #define rdc_ams_pll_calib_adj() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,8,13,__ERR) #define wrc_ams_pll_calib_adj(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x00e0,5,wr_val) #define rdc_ams_pll_en_8p5g() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,11,15,__ERR) #define wrc_ams_pll_en_8p5g(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x0010,4,wr_val) #define rdc_ams_pll_vco_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b2,12,12,__ERR) #define wrc_ams_pll_vco_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b2,0x000f,0,wr_val) #define rdc_ams_pll_en_mmd_halfrate() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,0,15,__ERR) #define wrc_ams_pll_en_mmd_halfrate(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x8000,15,wr_val) #define rdc_ams_pll_cp_bias() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,1,13,__ERR) #define wrc_ams_pll_cp_bias(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x7000,12,wr_val) #define rdc_ams_pll_spare3_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,4,15,__ERR) #define wrc_ams_pll_spare3_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0800,11,wr_val) #define rdc_ams_pll_ref_cmos_hz() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,5,15,__ERR) #define wrc_ams_pll_ref_cmos_hz(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0400,10,wr_val) #define rdc_ams_pll_ref_cml_pd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,6,15,__ERR) #define wrc_ams_pll_ref_cml_pd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0200,9,wr_val) #define rdc_ams_pll_clksel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,7,15,__ERR) #define wrc_ams_pll_clksel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0100,8,wr_val) #define rdc_ams_pll_en_rclk_refout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,8,15,__ERR) #define wrc_ams_pll_en_rclk_refout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0080,7,wr_val) #define rdc_ams_pll_en_cmos_refout_overwr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,9,15,__ERR) #define wrc_ams_pll_en_cmos_refout_overwr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0040,6,wr_val) #define rdc_ams_pll_en_cml_refout_overwr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,10,15,__ERR) #define wrc_ams_pll_en_cml_refout_overwr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0020,5,wr_val) #define rdc_ams_pll_en_test_frac_clk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,11,15,__ERR) #define wrc_ams_pll_en_test_frac_clk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0010,4,wr_val) #define rdc_ams_pll_enb_16t() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,12,15,__ERR) #define wrc_ams_pll_enb_16t(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0008,3,wr_val) #define rdc_ams_pll_band_iqbuf_ctr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b3,13,13,__ERR) #define wrc_ams_pll_band_iqbuf_ctr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b3,0x0007,0,wr_val) #define rdc_ams_pll_test_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,1,13,__ERR) #define wrc_ams_pll_test_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x7000,12,wr_val) #define rdc_ams_pll_test_amp() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,4,14,__ERR) #define wrc_ams_pll_test_amp(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0c00,10,wr_val) #define rdc_ams_pll_vco_test_clk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,6,15,__ERR) #define wrc_ams_pll_vco_test_clk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0200,9,wr_val) #define rdc_ams_pll_bias_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,7,15,__ERR) #define wrc_ams_pll_bias_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0100,8,wr_val) #define rdc_ams_pll_vco_hkvco() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,8,15,__ERR) #define wrc_ams_pll_vco_hkvco(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0080,7,wr_val) #define rdc_ams_pll_bias_vdd_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,9,14,__ERR) #define wrc_ams_pll_bias_vdd_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0060,5,wr_val) #define rdc_ams_pll_cmos_tport_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,11,15,__ERR) #define wrc_ams_pll_cmos_tport_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0010,4,wr_val) #define rdc_ams_pll_cp_opamp_bias() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,12,14,__ERR) #define wrc_ams_pll_cp_opamp_bias(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x000c,2,wr_val) #define rdc_ams_pll_lc_refclk_adj_3_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b4,14,14,__ERR) #define wrc_ams_pll_lc_refclk_adj_3_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b4,0x0003,0,wr_val) #define rdc_ams_pll_refdiv_test_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,3,13,__ERR) #define wrc_ams_pll_refdiv_test_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x1c00,10,wr_val) #define rdc_ams_pll_pwdb_extr_d2c() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,6,15,__ERR) #define wrc_ams_pll_pwdb_extr_d2c(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0200,9,wr_val) #define rdc_ams_pll_en_refout_div() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,7,15,__ERR) #define wrc_ams_pll_en_refout_div(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0100,8,wr_val) #define rdc_ams_pll_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,8,15,__ERR) #define wrc_ams_pll_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0080,7,wr_val) #define rdc_ams_pll_term_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,9,14,__ERR) #define wrc_ams_pll_term_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0060,5,wr_val) #define rdc_ams_pll_test_sel_overwrite() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,11,15,__ERR) #define wrc_ams_pll_test_sel_overwrite(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0010,4,wr_val) #define rdc_ams_pll_test_vc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,12,15,__ERR) #define wrc_ams_pll_test_vc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0008,3,wr_val) #define rdc_ams_pll_refout_div_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b5,13,13,__ERR) #define wrc_ams_pll_refout_div_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b5,0x0007,0,wr_val) #define rdc_ams_pll_i_ndiv_frac_l() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,0,12,__ERR) #define wrc_ams_pll_i_ndiv_frac_l(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0xf000,12,wr_val) #define rdc_ams_pll_i_pfd_offset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,4,14,__ERR) #define wrc_ams_pll_i_pfd_offset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0c00,10,wr_val) #define rdc_ams_pll_spare6_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,6,15,__ERR) #define wrc_ams_pll_spare6_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0200,9,wr_val) #define rdc_ams_pll_i_pfd_offset_enlarge() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,7,15,__ERR) #define wrc_ams_pll_i_pfd_offset_enlarge(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0100,8,wr_val) #define rdc_ams_pll_vco_i_boost() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,8,14,__ERR) #define wrc_ams_pll_vco_i_boost(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x00c0,6,wr_val) #define rdc_ams_pll_vco_gm_boost() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,10,14,__ERR) #define wrc_ams_pll_vco_gm_boost(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x0030,4,wr_val) #define rdc_ams_pll_pon() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b6,12,12,__ERR) #define wrc_ams_pll_pon(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b6,0x000f,0,wr_val) #define rdc_ams_pll_i_ndiv_frac_h() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0b7,2,2,__ERR) #define wrc_ams_pll_i_ndiv_frac_h(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd0b7,0x3fff,0,wr_val) #define rdc_ams_pll_i_ndiv_dither_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b8,0,15,__ERR) #define wrc_ams_pll_i_ndiv_dither_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b8,0x8000,15,wr_val) #define rdc_ams_pll_i_pll_sdm_pwrdnb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b8,1,15,__ERR) #define wrc_ams_pll_i_pll_sdm_pwrdnb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b8,0x4000,14,wr_val) #define rdc_ams_pll_vcofb_div() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b8,2,14,__ERR) #define wrc_ams_pll_vcofb_div(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b8,0x3000,12,wr_val) #define rdc_ams_pll_cml_refclk_bias() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b8,4,14,__ERR) #define wrc_ams_pll_cml_refclk_bias(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b8,0x0c00,10,wr_val) #define rdc_ams_pll_i_ndiv_int() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0b8,6,6,__ERR) #define wrc_ams_pll_i_ndiv_int(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd0b8,0x03ff,0,wr_val) #define rdc_ams_pll_cml_refclk_adj() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,0,14,__ERR) #define wrc_ams_pll_cml_refclk_adj(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0xc000,14,wr_val) #define rdc_ams_pll_bias_iq_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,2,13,__ERR) #define wrc_ams_pll_bias_iq_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x3800,11,wr_val) #define rdc_ams_pll_bias_div_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,5,13,__ERR) #define wrc_ams_pll_bias_div_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0700,8,wr_val) #define rdc_ams_pll_vco_supply_adj() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,8,15,__ERR) #define wrc_ams_pll_vco_supply_adj(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0080,7,wr_val) #define rdc_ams_pll_sel_fp3cap() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,9,12,__ERR) #define wrc_ams_pll_sel_fp3cap(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0078,3,wr_val) #define rdc_ams_pll_i_pll_frac_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,13,14,__ERR) #define wrc_ams_pll_i_pll_frac_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0006,1,wr_val) #define rdc_ams_pll_mmd_resetb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0b9,15,15,__ERR) #define wrc_ams_pll_mmd_resetb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0b9,0x0001,0,wr_val) #define rdc_ams_pll_refclk_in_bias() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0ba,10,10,__ERR) #define wrc_ams_pll_refclk_in_bias(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0ba,0x003f,0,wr_val) #define rdc_ams_pll_refclk_term_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0be,12,15,__ERR) #define wrc_ams_pll_refclk_term_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0be,0x0008,3,wr_val) #define rdc_ams_pll_refclk_div_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0be,13,15,__ERR) #define wrc_ams_pll_refclk_div_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0be,0x0004,2,wr_val) #define rdc_ams_pll_refclk_div2_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0be,14,15,__ERR) #define wrc_ams_pll_refclk_div2_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0be,0x0002,1,wr_val) #define rdc_ams_pll_refclk_div4_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0be,15,15,__ERR) #define wrc_ams_pll_refclk_div4_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0be,0x0001,0,wr_val) #define rdc_ams_pll_afe_rev_id() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0bf,12,12,__ERR) #define rd_cl72_ieee_lp_coeff_update() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0098,__ERR) #define rd_cl72_ieee_lp_status_report() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0099,__ERR) #define rd_cl72_ieee_training_enable() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0096,14,15,__ERR) #define wr_cl72_ieee_training_enable(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0x0096,0x0002,1,wr_val) #define rd_cl72_ieee_restart_training() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0096,15,15,__ERR) #define wr_cl72_ieee_restart_training(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0x0096,0x0001,0,wr_val) #define rd_cl72_ieee_training_failure() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0097,12,15,__ERR) #define rd_cl72_ieee_training_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0097,13,15,__ERR) #define rd_cl72_ieee_frame_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0097,14,15,__ERR) #define rd_cl72_ieee_receiver_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x0097,15,15,__ERR) #define rd_cl72_ieee_ld_coeff_update() _merlin16_shortfin_pmd_rde_reg(sa__, 0x009a,__ERR) #define rd_cl72_ieee_ld_status_report() _merlin16_shortfin_pmd_rde_reg(sa__, 0x009b,__ERR) #define rd_cl72_rx_signal_ok() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd050,13,15,__ERR) #define wr_cl72_rx_signal_ok(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd050,0x0004,2,wr_val) #define rd_cl72_tr_coarse_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd050,14,15,__ERR) #define wr_cl72_tr_coarse_lock(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd050,0x0002,1,wr_val) #define rd_cl72_rx_training_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd050,15,15,__ERR) #define wr_cl72_rx_training_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd050,0x0001,0,wr_val) #define rd_cl72_bad_marker_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd051,9,13,__ERR) #define wr_cl72_bad_marker_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd051,0x0070,4,wr_val) #define rd_cl72_good_marker_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd051,14,14,__ERR) #define wr_cl72_good_marker_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd051,0x0003,0,wr_val) #define rd_cl72_frame_consistency_chk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,6,15,__ERR) #define wr_cl72_frame_consistency_chk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0200,9,wr_val) #define rd_cl72_rx_dp_ln_clk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,7,15,__ERR) #define wr_cl72_rx_dp_ln_clk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0100,8,wr_val) #define rd_cl72_ppm_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,8,15,__ERR) #define wr_cl72_ppm_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0080,7,wr_val) #define rd_cl72_strict_marker_chk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,9,15,__ERR) #define wr_cl72_strict_marker_chk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0040,6,wr_val) #define rd_cl72_strict_dme_chk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,10,15,__ERR) #define wr_cl72_strict_dme_chk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0020,5,wr_val) #define rd_cl72_dme_cell_boundary_chk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,11,15,__ERR) #define wr_cl72_dme_cell_boundary_chk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x0010,4,wr_val) #define rd_cl72_ctrl_frame_dly() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd052,12,12,__ERR) #define wr_cl72_ctrl_frame_dly(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd052,0x000f,0,wr_val) #define rd_cl72_remote_rx_ready() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd053,14,15,__ERR) #define rd_cl72_frame_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd053,15,15,__ERR) #define rd_cl72_micro_status_resp_int_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,4,15,__ERR) #define wr_cl72_micro_status_resp_int_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0800,11,wr_val) #define rd_cl72_micro_status_resp_int_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,5,15,__ERR) #define wr_cl72_micro_status_resp_int_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0400,10,wr_val) #define rd_cl72_micro_update_req_int_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,6,15,__ERR) #define wr_cl72_micro_update_req_int_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0200,9,wr_val) #define rd_cl72_micro_update_req_int_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,7,15,__ERR) #define wr_cl72_micro_update_req_int_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0100,8,wr_val) #define rd_cl72_micro_frame_lock_int_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,13,15,__ERR) #define wr_cl72_micro_frame_lock_int_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0004,2,wr_val) #define rd_cl72_micro_status_chg_int_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,14,15,__ERR) #define wr_cl72_micro_status_chg_int_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0002,1,wr_val) #define rd_cl72_micro_update_chg_int_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd054,15,15,__ERR) #define wr_cl72_micro_update_chg_int_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd054,0x0001,0,wr_val) #define rd_cl72_micro_update_chg_lstatus() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd055,15,15,__ERR) #define rd_cl72_micro_frame_lock_lstatus() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd056,14,15,__ERR) #define rd_cl72_micro_status_chg_lstatus() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd056,15,15,__ERR) #define rd_cl72_xmt_update_page() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd060,__ERR) #define wr_cl72_xmt_update_page(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd060,wr_val) #define rd_cl72_ld_xmt_status_page() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd061,__ERR) #define wr_cl72_ld_xmt_status_page(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd061,wr_val) #define rd_cl72_sw_remote_rx_ready() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd062,13,15,__ERR) #define wr_cl72_sw_remote_rx_ready(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd062,0x0004,2,wr_val) #define rd_cl72_sw_rx_trained() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd062,15,15,__ERR) #define wr_cl72_sw_rx_trained(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd062,0x0001,0,wr_val) #define rd_cl72_sw_frame_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd062,14,15,__ERR) #define wr_cl72_sw_frame_lock(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd062,0x0002,1,wr_val) #define rd_cl72_tx_dp_ln_clk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd063,13,15,__ERR) #define wr_cl72_tx_dp_ln_clk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd063,0x0004,2,wr_val) #define rd_cl72_dis_max_wait_timer() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd063,14,15,__ERR) #define wr_cl72_dis_max_wait_timer(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd063,0x0002,1,wr_val) #define rd_cl72_brk_ring_osc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd063,15,15,__ERR) #define wr_cl72_brk_ring_osc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd063,0x0001,0,wr_val) #define rd_cl72_txfir_post() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd064,3,11,__ERR) #define wr_cl72_txfir_post(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd064,0x1f00,8,wr_val) #define rd_cl72_txfir_pre() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd064,12,12,__ERR) #define wr_cl72_txfir_pre(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd064,0x000f,0,wr_val) #define rd_cl72_txfir_main() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd065,10,10,__ERR) #define wr_cl72_txfir_main(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd065,0x003f,0,wr_val) #define rd_cl72_training_fsm_signal_detect() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd066,14,15,__ERR) #define rd_cl72_local_rx_ready() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd066,15,15,__ERR) #define rd_cl72_prbs_seed_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd067,0,14,__ERR) #define wr_cl72_prbs_seed_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd067,0xc000,14,wr_val) #define rd_cl72_prbs_mode_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd067,2,15,__ERR) #define wr_cl72_prbs_mode_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd067,0x2000,13,wr_val) #define rd_cl72_cl93prbs_poly_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd067,3,14,__ERR) #define wr_cl72_cl93prbs_poly_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd067,0x1800,11,wr_val) #define rd_cl72_prbs_seed_val() _merlin16_shortfin_pmd_rde_field(sa__, 0xd067,5,5,__ERR) #define wr_cl72_prbs_seed_val(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd067,0x07ff,0,wr_val) #define rdc_revid_rev_letter() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f0,0,14,__ERR) #define rdc_revid_rev_number() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f0,2,13,__ERR) #define rdc_revid_bonding() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f0,5,14,__ERR) #define rdc_revid_process() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f0,7,13,__ERR) #define rdc_revid_model() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f0,10,10,__ERR) #define rdc_revid_multiplicity() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,0,12,__ERR) #define rdc_revid_mdio() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,10,15,__ERR) #define rdc_revid_micro() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,11,15,__ERR) #define rdc_revid_cl72() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,12,15,__ERR) #define rdc_revid_pir() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,13,15,__ERR) #define rdc_revid_llp() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,14,15,__ERR) #define rdc_revid_eee() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fa,15,15,__ERR) #define rdc_revid2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0fe,12,12,__ERR) #define rdc_core_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f1,15,15,__ERR) #define wrc_core_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f1,0x0001,0,wr_val) #define rdc_disable_ack_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,0,15,__ERR) #define wrc_disable_ack_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x8000,15,wr_val) #define rdc_pmd_vcoclk16_vld_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,5,15,__ERR) #define wrc_pmd_vcoclk16_vld_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0400,10,wr_val) #define rdc_pmd_vcoclk16_vld_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,6,15,__ERR) #define wrc_pmd_vcoclk16_vld_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0200,9,wr_val) #define rdc_vcoclk16_s_comclk_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,7,15,__ERR) #define wrc_vcoclk16_s_comclk_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0100,8,wr_val) #define rdc_vcoclk16_s_comclk_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,8,15,__ERR) #define wrc_vcoclk16_s_comclk_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0080,7,wr_val) #define rdc_pmd_mdio_trans_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,10,15,__ERR) #define wrc_pmd_mdio_trans_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0020,5,wr_val) #define rdc_sup_rst_seq_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,11,15,__ERR) #define wrc_sup_rst_seq_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0010,4,wr_val) #define rdc_sup_rst_seq_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,12,15,__ERR) #define wrc_sup_rst_seq_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0008,3,wr_val) #define rdc_pmd_core_dp_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f2,14,15,__ERR) #define wrc_pmd_core_dp_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f2,0x0002,1,wr_val) #define rdc_maskdata() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f3,__ERR) #define wrc_maskdata(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f3,wr_val) #define rdc_uc_active() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f4,0,15,__ERR) #define wrc_uc_active(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f4,0x8000,15,wr_val) #define rdc_afe_s_pll_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f4,1,15,__ERR) #define wrc_afe_s_pll_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f4,0x4000,14,wr_val) #define rdc_core_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f4,2,15,__ERR) #define wrc_core_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f4,0x2000,13,wr_val) #define rdc_maskdata_bus_assign() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f4,4,14,__ERR) #define wrc_maskdata_bus_assign(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f4,0x0c00,10,wr_val) #define rdc_heartbeat_count_1us() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0f4,6,6,__ERR) #define wrc_heartbeat_count_1us(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd0f4,0x03ff,0,wr_val) #define rdc_uc_ack_core_dp_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f5,14,15,__ERR) #define wrc_uc_ack_core_dp_reset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0002,1,wr_val) #define rdc_uc_ack_core_cfg_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f5,15,15,__ERR) #define wrc_uc_ack_core_cfg_done(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f5,0x0001,0,wr_val) #define rdc_lane_reset_released() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f8,1,15,__ERR) #define rdc_lane_reset_released_index() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f8,3,11,__ERR) #define rdc_tx_lane_reset_released() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f8,0,15,__ERR) #define rdc_tx_lane_reset_released_index() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f8,8,11,__ERR) #define rdc_core_dp_reset_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f8,13,13,__ERR) #define rdc_core_reg_reset_occurred() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f6,15,15,__ERR) #define wrc_core_reg_reset_occurred(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f6,0x0001,0,wr_val) #define rdc_rst_seq_dis_flt_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f7,0,14,__ERR) #define wrc_rst_seq_dis_flt_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f7,0xc000,14,wr_val) #define rdc_pwrdn_seq_timer() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f7,4,13,__ERR) #define wrc_pwrdn_seq_timer(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0e00,9,wr_val) #define rdc_rst_seq_timer() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0f7,13,13,__ERR) #define wrc_rst_seq_timer(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0f7,0x0007,0,wr_val) #define rdc_pmd_core_mode() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f9,__ERR) #define rd_cdr_integ_reg() _merlin16_shortfin_pmd_rde_field_signed(sa__, 0xd005,0,0,__ERR) #define rd_cdr_lm_outoflock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd006,7,15,__ERR) #define rd_cdr_phase_err() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd006,11,11,__ERR) #define rd_cnt_bin_p1_dreg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd007,1,9,__ERR) #define rd_cnt_bin_d_dreg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd007,9,9,__ERR) #define rd_cnt_bin_m1_preg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd008,1,9,__ERR) #define rd_cnt_bin_p1_preg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd008,9,9,__ERR) #define rd_cnt_bin_d_mreg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd009,1,9,__ERR) #define rd_cnt_bin_m1_mreg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd009,9,9,__ERR) #define rd_cnt_d_minus_p1() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd00a,0,8,__ERR) #define rd_cnt_d_minus_m1() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd00a,8,8,__ERR) #define rd_cdr_lm_thr_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,5,13,__ERR) #define wr_cdr_lm_thr_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0700,8,wr_val) #define rd_cdr_freq_override_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,8,15,__ERR) #define wr_cdr_freq_override_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0080,7,wr_val) #define rd_cdr_integ_sat_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,9,15,__ERR) #define wr_cdr_integ_sat_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0040,6,wr_val) #define rd_cdr_phase_err_frz() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,10,15,__ERR) #define wr_cdr_phase_err_frz(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0020,5,wr_val) #define rd_cdr_integ_reg_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,11,15,__ERR) #define wr_cdr_integ_reg_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0010,4,wr_val) #define rd_cdr_freq_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,13,15,__ERR) #define wr_cdr_freq_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0004,2,wr_val) #define rd_br_pd_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,14,15,__ERR) #define wr_br_pd_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0002,1,wr_val) #define rd_cdr_phase_sat_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd001,15,15,__ERR) #define wr_cdr_phase_sat_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd001,0x0001,0,wr_val) #define rd_cdr_freq_override_val() _merlin16_shortfin_pmd_rde_field_signed(sa__, 0xd002,0,1,__ERR) #define wr_cdr_freq_override_val(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd002,0xfffe,1,wr_val) #define rd_dfe_vga_unfreeze() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd002,15,15,__ERR) #define wr_dfe_vga_unfreeze(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd002,0x0001,0,wr_val) #define rd_osx2p_pherr_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd003,6,14,__ERR) #define wr_osx2p_pherr_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd003,0x0300,8,wr_val) #define rd_pattern_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd003,8,12,__ERR) #define wr_pattern_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd003,0x00f0,4,wr_val) #define rd_phase_err_offset_mult_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd003,14,15,__ERR) #define wr_phase_err_offset_mult_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd003,0x0002,1,wr_val) #define rd_cdr_zero_polarity() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd003,15,15,__ERR) #define wr_cdr_zero_polarity(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd003,0x0001,0,wr_val) #define rd_rx_pi_manual_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,0,15,__ERR) #define wr_rx_pi_manual_reset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x8000,15,wr_val) #define rd_rx_pi_slicers_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,1,13,__ERR) #define wr_rx_pi_slicers_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x7000,12,wr_val) #define rd_rx_pi_manual_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,4,15,__ERR) #define wr_rx_pi_manual_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x0800,11,wr_val) #define rd_rx_pi_phase_step_dir() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,5,15,__ERR) #define wr_rx_pi_phase_step_dir(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x0400,10,wr_val) #define rd_rx_pi_manual_strobe() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,6,15,__ERR) #define wr_rx_pi_manual_strobe(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x0200,9,wr_val) #define rd_rx_pi_phase_step_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd004,9,9,__ERR) #define wr_rx_pi_phase_step_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd004,0x007f,0,wr_val) #define rd_uc_dsc_supp_info() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd00d,0,8,__ERR) #define wr_uc_dsc_supp_info(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd00d,0xff00,8,wr_val) #define rd_uc_dsc_ready_for_cmd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd00d,8,15,__ERR) #define wr_uc_dsc_ready_for_cmd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd00d,0x0080,7,wr_val) #define rd_uc_dsc_error_found() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd00d,9,15,__ERR) #define wr_uc_dsc_error_found(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd00d,0x0040,6,wr_val) #define rd_uc_dsc_gp_uc_req() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd00d,10,10,__ERR) #define wr_uc_dsc_gp_uc_req(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd00d,0x003f,0,wr_val) #define rd_uc_dsc_data() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd00e,__ERR) #define wr_uc_dsc_data(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd00e,wr_val) #define rd_eee_mode_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,14,15,__ERR) #define wr_eee_mode_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0002,1,wr_val) #define rd_eee_quiet_rx_afe_pwrdwn_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,13,15,__ERR) #define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0004,2,wr_val) #define rd_ignore_rx_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,12,15,__ERR) #define wr_ignore_rx_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0008,3,wr_val) #define rd_cl72_timer_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,11,15,__ERR) #define wr_cl72_timer_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0010,4,wr_val) #define rd_uc_tune_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,10,15,__ERR) #define wr_uc_tune_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0020,5,wr_val) #define rd_hw_tune_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,9,15,__ERR) #define wr_hw_tune_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0040,6,wr_val) #define rd_uc_trnsum_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,8,15,__ERR) #define wr_uc_trnsum_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0080,7,wr_val) #define rd_eee_measure_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,7,15,__ERR) #define wr_eee_measure_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0100,8,wr_val) #define rd_slicer_cal_done_clear() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,6,15,__ERR) #define wr_slicer_cal_done_clear(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0200,9,wr_val) #define rd_slicer_cal_bypass() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,5,15,__ERR) #define wr_slicer_cal_bypass(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0400,10,wr_val) #define rd_uc_ack_dsc_eee_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,4,15,__ERR) #define wr_uc_ack_dsc_eee_done(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x0800,11,wr_val) #define rd_uc_ack_dsc_restart() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,2,15,__ERR) #define wr_uc_ack_dsc_restart(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x2000,13,wr_val) #define rd_uc_ack_dsc_config() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,1,15,__ERR) #define wr_uc_ack_dsc_config(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x4000,14,wr_val) #define rd_set_meas_incomplete() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd010,0,15,__ERR) #define wr_set_meas_incomplete(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd010,0x8000,15,wr_val) #define rd_rx_dsc_lock_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,15,15,__ERR) #define wr_rx_dsc_lock_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0001,0,wr_val) #define rd_rx_dsc_lock_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,14,15,__ERR) #define wr_rx_dsc_lock_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0002,1,wr_val) #define rd_dsc_clr_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,13,15,__ERR) #define wr_dsc_clr_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0004,2,wr_val) #define rd_dsc_clr_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,12,15,__ERR) #define wr_dsc_clr_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0008,3,wr_val) #define rd_trnsum_frz_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,11,15,__ERR) #define wr_trnsum_frz_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0010,4,wr_val) #define rd_trnsum_frz_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,10,15,__ERR) #define wr_trnsum_frz_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0020,5,wr_val) #define rd_timer_done_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,9,15,__ERR) #define wr_timer_done_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0040,6,wr_val) #define rd_timer_done_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,8,15,__ERR) #define wr_timer_done_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0080,7,wr_val) #define rd_freq_upd_en_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,7,15,__ERR) #define wr_freq_upd_en_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0100,8,wr_val) #define rd_freq_upd_en_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,6,15,__ERR) #define wr_freq_upd_en_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0200,9,wr_val) #define rd_cdr_frz_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,5,15,__ERR) #define wr_cdr_frz_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0400,10,wr_val) #define rd_cdr_frz_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,4,15,__ERR) #define wr_cdr_frz_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x0800,11,wr_val) #define rd_trnsum_clr_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,3,15,__ERR) #define wr_trnsum_clr_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x1000,12,wr_val) #define rd_trnsum_clr_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd011,2,15,__ERR) #define wr_trnsum_clr_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd011,0x2000,13,wr_val) #define rd_eee_lfsr_cnt() _merlin16_shortfin_pmd_rde_field(sa__, 0xd012,3,3,__ERR) #define wr_eee_lfsr_cnt(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd012,0x1fff,0,wr_val) #define rd_measure_lfsr_cnt() _merlin16_shortfin_pmd_rde_field(sa__, 0xd013,3,3,__ERR) #define wr_measure_lfsr_cnt(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd013,0x1fff,0,wr_val) #define rd_acq_cdr_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd014,11,11,__ERR) #define wr_acq_cdr_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd014,0x001f,0,wr_val) #define rd_cdr_settle_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd014,6,11,__ERR) #define wr_cdr_settle_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd014,0x03e0,5,wr_val) #define rd_hw_tune_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd014,1,11,__ERR) #define wr_hw_tune_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd014,0x7c00,10,wr_val) #define rd_measure_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd015,11,11,__ERR) #define wr_measure_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd015,0x001f,0,wr_val) #define rd_eee_acq_cdr_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd015,6,11,__ERR) #define wr_eee_acq_cdr_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd015,0x03e0,5,wr_val) #define rd_eee_cdr_settle_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd015,1,11,__ERR) #define wr_eee_cdr_settle_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd015,0x7c00,10,wr_val) #define rd_eee_hw_tune_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd016,11,11,__ERR) #define wr_eee_hw_tune_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd016,0x001f,0,wr_val) #define rd_eee_ana_pwr_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd016,1,11,__ERR) #define wr_eee_ana_pwr_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd016,0x7c00,10,wr_val) #define rd_slicer_cal_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd016,6,11,__ERR) #define wr_slicer_cal_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd016,0x03e0,5,wr_val) #define rd_cdr_bwsel_integ_acqcdr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd017,12,12,__ERR) #define wr_cdr_bwsel_integ_acqcdr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd017,0x000f,0,wr_val) #define rd_cdr_bwsel_integ_eee_acqcdr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd017,8,12,__ERR) #define wr_cdr_bwsel_integ_eee_acqcdr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd017,0x00f0,4,wr_val) #define rd_cdr_bwsel_integ_norm() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd017,4,12,__ERR) #define wr_cdr_bwsel_integ_norm(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd017,0x0f00,8,wr_val) #define rd_cdr_bwsel_prop_acqcdr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd017,2,14,__ERR) #define wr_cdr_bwsel_prop_acqcdr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd017,0x3000,12,wr_val) #define rd_cdr_bwsel_prop_norm() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd017,0,14,__ERR) #define wr_cdr_bwsel_prop_norm(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd017,0xc000,14,wr_val) #define rd_phase_err_offset() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd018,12,12,__ERR) #define wr_phase_err_offset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd018,0x000f,0,wr_val) #define rd_eee_phase_err_offset() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd018,8,12,__ERR) #define wr_eee_phase_err_offset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd018,0x00f0,4,wr_val) #define rd_phase_err_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd018,6,14,__ERR) #define wr_phase_err_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd018,0x0300,8,wr_val) #define rd_eee_phase_err_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd018,4,14,__ERR) #define wr_eee_phase_err_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd018,0x0c00,10,wr_val) #define rd_cdr_bwsel_prop_eee_acqcdr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd018,0,14,__ERR) #define wr_cdr_bwsel_prop_eee_acqcdr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd018,0xc000,14,wr_val) #define rd_dcoff_cal_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd019,1,11,__ERR) #define wr_dcoff_cal_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd019,0x7c00,10,wr_val) #define rd_rx_restart_pmd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd019,15,15,__ERR) #define wr_rx_restart_pmd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd019,0x0001,0,wr_val) #define rd_rx_restart_pmd_hold() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd019,14,15,__ERR) #define wr_rx_restart_pmd_hold(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd019,0x0002,1,wr_val) #define rd_dsc_state_one_hot() _merlin16_shortfin_pmd_rde_field(sa__, 0xd01b,4,4,__ERR) #define rd_dsc_state_eee_one_hot() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01c,9,9,__ERR) #define rd_restart_pi_ext_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01d,15,15,__ERR) #define rd_restart_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01d,14,15,__ERR) #define rd_restart_pmd_restart() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01d,13,15,__ERR) #define rd_eee_quiet_from_eee_states() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01d,12,15,__ERR) #define rd_dsc_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01e,0,11,__ERR) #define rd_dsc_sm_ready_for_cmd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01e,8,15,__ERR) #define rd_dsc_sm_scratch() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01e,5,13,__ERR) #define rd_dsc_sm_gp_uc_req() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01e,10,10,__ERR) #define rd_eee_measure_cnt() _merlin16_shortfin_pmd_rde_field(sa__, 0xd01a,0,7,__ERR) #define rd_slicer_cal_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01a,13,15,__ERR) #define rd_meas_incomplete() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01a,14,15,__ERR) #define rd_rx_dsc_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd01a,15,15,__ERR) #define rd_dfe_1_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,0,15,__ERR) #define wr_dfe_1_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x8000,15,wr_val) #define rd_dfe_1_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,1,14,__ERR) #define wr_dfe_1_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x6000,13,wr_val) #define rd_dfe_1_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,3,15,__ERR) #define wr_dfe_1_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x1000,12,wr_val) #define rd_dfe_1_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,4,14,__ERR) #define wr_dfe_1_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x0c00,10,wr_val) #define rd_dfe_1_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,6,15,__ERR) #define wr_dfe_1_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x0200,9,wr_val) #define rd_dfe_1_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,7,15,__ERR) #define wr_dfe_1_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x0100,8,wr_val) #define rd_dfe_1_cmn_only() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,14,15,__ERR) #define wr_dfe_1_cmn_only(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x0002,1,wr_val) #define rd_dfe_1_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd021,15,15,__ERR) #define wr_dfe_1_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd021,0x0001,0,wr_val) #define rd_dfe_2_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,0,15,__ERR) #define wr_dfe_2_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x8000,15,wr_val) #define rd_dfe_2_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,1,14,__ERR) #define wr_dfe_2_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x6000,13,wr_val) #define rd_dfe_2_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,3,15,__ERR) #define wr_dfe_2_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x1000,12,wr_val) #define rd_dfe_2_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,4,14,__ERR) #define wr_dfe_2_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x0c00,10,wr_val) #define rd_dfe_2_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,6,15,__ERR) #define wr_dfe_2_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x0200,9,wr_val) #define rd_dfe_2_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,7,15,__ERR) #define wr_dfe_2_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x0100,8,wr_val) #define rd_dfe_2_cmn_only() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,14,15,__ERR) #define wr_dfe_2_cmn_only(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x0002,1,wr_val) #define rd_dfe_2_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd022,15,15,__ERR) #define wr_dfe_2_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd022,0x0001,0,wr_val) #define rd_dfe_3_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,0,15,__ERR) #define wr_dfe_3_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x8000,15,wr_val) #define rd_dfe_3_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,1,14,__ERR) #define wr_dfe_3_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x6000,13,wr_val) #define rd_dfe_3_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,3,15,__ERR) #define wr_dfe_3_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x1000,12,wr_val) #define rd_dfe_3_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,4,14,__ERR) #define wr_dfe_3_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x0c00,10,wr_val) #define rd_dfe_3_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,6,15,__ERR) #define wr_dfe_3_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x0200,9,wr_val) #define rd_dfe_3_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,7,15,__ERR) #define wr_dfe_3_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x0100,8,wr_val) #define rd_dfe_3_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd023,15,15,__ERR) #define wr_dfe_3_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd023,0x0001,0,wr_val) #define rd_dfe_4_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,0,15,__ERR) #define wr_dfe_4_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x8000,15,wr_val) #define rd_dfe_4_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,1,14,__ERR) #define wr_dfe_4_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x6000,13,wr_val) #define rd_dfe_4_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,3,15,__ERR) #define wr_dfe_4_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x1000,12,wr_val) #define rd_dfe_4_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,4,14,__ERR) #define wr_dfe_4_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x0c00,10,wr_val) #define rd_dfe_4_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,6,15,__ERR) #define wr_dfe_4_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x0200,9,wr_val) #define rd_dfe_4_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,7,15,__ERR) #define wr_dfe_4_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x0100,8,wr_val) #define rd_dfe_4_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd024,15,15,__ERR) #define wr_dfe_4_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd024,0x0001,0,wr_val) #define rd_dfe_5_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,0,15,__ERR) #define wr_dfe_5_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x8000,15,wr_val) #define rd_dfe_5_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,1,14,__ERR) #define wr_dfe_5_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x6000,13,wr_val) #define rd_dfe_5_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,3,15,__ERR) #define wr_dfe_5_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x1000,12,wr_val) #define rd_dfe_5_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,4,14,__ERR) #define wr_dfe_5_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x0c00,10,wr_val) #define rd_dfe_5_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,6,15,__ERR) #define wr_dfe_5_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x0200,9,wr_val) #define rd_dfe_5_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,7,15,__ERR) #define wr_dfe_5_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x0100,8,wr_val) #define rd_dfe_5_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd025,15,15,__ERR) #define wr_dfe_5_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd025,0x0001,0,wr_val) #define rd_dfe_pattern_bit_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd026,2,10,__ERR) #define wr_dfe_pattern_bit_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd026,0x3f00,8,wr_val) #define rd_dfe_pattern() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd026,10,10,__ERR) #define wr_dfe_pattern(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd026,0x003f,0,wr_val) #define rd_dfe_acc_hys_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,0,15,__ERR) #define wr_dfe_acc_hys_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x8000,15,wr_val) #define rd_dfe_allow_simult() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,1,15,__ERR) #define wr_dfe_allow_simult(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x4000,14,wr_val) #define rd_dfe_update_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,2,15,__ERR) #define wr_dfe_update_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x2000,13,wr_val) #define rd_dfe_eye_closure_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,8,14,__ERR) #define wr_dfe_eye_closure_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x00c0,6,wr_val) #define rd_dfe_hw_eye_closure_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,10,15,__ERR) #define wr_dfe_hw_eye_closure_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x0020,5,wr_val) #define rd_dfe_leaky_lms_upd_dur() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,11,12,__ERR) #define wr_dfe_leaky_lms_upd_dur(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x001e,1,wr_val) #define rd_dfe_leaky_lms_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd020,15,15,__ERR) #define wr_dfe_leaky_lms_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd020,0x0001,0,wr_val) #define rd_hwtune_ovr_write_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02b,0,15,__ERR) #define wr_hwtune_ovr_write_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02b,0x8000,15,wr_val) #define rd_hwtune_ovr_write_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02b,2,11,__ERR) #define wr_hwtune_ovr_write_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02b,0x3e00,9,wr_val) #define rd_hwtune_ovr_write_val() _merlin16_shortfin_pmd_rde_field(sa__, 0xd02b,7,7,__ERR) #define wr_hwtune_ovr_write_val(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd02b,0x01ff,0,wr_val) #define rd_vga_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,0,15,__ERR) #define wr_vga_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x8000,15,wr_val) #define rd_vga_err_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,1,14,__ERR) #define wr_vga_err_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x6000,13,wr_val) #define rd_vga_p1_gradient_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,3,15,__ERR) #define wr_vga_p1_gradient_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x1000,12,wr_val) #define rd_vga_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,4,14,__ERR) #define wr_vga_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0c00,10,wr_val) #define rd_vga_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,6,15,__ERR) #define wr_vga_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0200,9,wr_val) #define rd_vga_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,7,15,__ERR) #define wr_vga_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0100,8,wr_val) #define rd_vga_update_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,8,14,__ERR) #define wr_vga_update_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x00c0,6,wr_val) #define rd_vga_affected_by_dfe1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,11,15,__ERR) #define wr_vga_affected_by_dfe1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0010,4,wr_val) #define rd_vga_update_style() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,12,14,__ERR) #define wr_vga_update_style(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x000c,2,wr_val) #define rd_vga_acc_hys_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,14,15,__ERR) #define wr_vga_acc_hys_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0002,1,wr_val) #define rd_vga_p1_acc_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02c,15,15,__ERR) #define wr_vga_p1_acc_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02c,0x0001,0,wr_val) #define rd_p1_eyediag_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02d,0,15,__ERR) #define wr_p1_eyediag_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02d,0x8000,15,wr_val) #define rd_vga_pattern_bit_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02d,8,12,__ERR) #define wr_vga_pattern_bit_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02d,0x00f0,4,wr_val) #define rd_vga_pattern() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02d,12,12,__ERR) #define wr_vga_pattern(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02d,0x000f,0,wr_val) #define rd_p1_hwtune_max() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd02e,0,10,__ERR) #define wr_p1_hwtune_max(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02e,0xfc00,10,wr_val) #define rd_p1_off_3levelq_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02e,7,15,__ERR) #define wr_p1_off_3levelq_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02e,0x0100,8,wr_val) #define rd_p1_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02e,8,15,__ERR) #define wr_p1_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02e,0x0080,7,wr_val) #define rd_p1_offset() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd02e,9,9,__ERR) #define wr_p1_offset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02e,0x007f,0,wr_val) #define rd_p1_hwtune_min() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd027,0,10,__ERR) #define wr_p1_hwtune_min(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd027,0xfc00,10,wr_val) #define rd_vga_op_short_norm() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd027,8,15,__ERR) #define wr_vga_op_short_norm(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd027,0x0080,7,wr_val) #define rd_vga_op_short_offcal() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd027,9,15,__ERR) #define wr_vga_op_short_offcal(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd027,0x0040,6,wr_val) #define rd_vga_hwtune_min() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd027,10,10,__ERR) #define wr_vga_hwtune_min(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd027,0x003f,0,wr_val) #define rd_hw_slicer_offset_grad_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,8,15,__ERR) #define wr_hw_slicer_offset_grad_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0080,7,wr_val) #define rd_hw_slicer_offset_inv_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,9,15,__ERR) #define wr_hw_slicer_offset_inv_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0040,6,wr_val) #define rd_hw_slicer_offset_inv_m1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,10,15,__ERR) #define wr_hw_slicer_offset_inv_m1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0020,5,wr_val) #define rd_hw_slicer_offset_inv_data() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,11,15,__ERR) #define wr_hw_slicer_offset_inv_data(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0010,4,wr_val) #define rd_hw_slicer_offset_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,12,14,__ERR) #define wr_hw_slicer_offset_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x000c,2,wr_val) #define rd_hw_slicer_offset_hys_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,14,15,__ERR) #define wr_hw_slicer_offset_hys_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0002,1,wr_val) #define rd_hw_slicer_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd02a,15,15,__ERR) #define wr_hw_slicer_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd02a,0x0001,0,wr_val) #define rd_dc_offset_pattern_bit_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,0,12,__ERR) #define wr_dc_offset_pattern_bit_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0xf000,12,wr_val) #define rd_dc_offset_pattern() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,4,12,__ERR) #define wr_dc_offset_pattern(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0f00,8,wr_val) #define rd_hw_dc_offset_grad_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,9,15,__ERR) #define wr_hw_dc_offset_grad_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0040,6,wr_val) #define rd_dc_offset_pattern_inv_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,10,15,__ERR) #define wr_dc_offset_pattern_inv_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0020,5,wr_val) #define rd_dc_offset_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,11,15,__ERR) #define wr_dc_offset_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0010,4,wr_val) #define rd_hw_dc_offset_err_gain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,12,14,__ERR) #define wr_hw_dc_offset_err_gain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x000c,2,wr_val) #define rd_hw_dc_offset_hys_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,14,15,__ERR) #define wr_hw_dc_offset_hys_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0002,1,wr_val) #define rd_dc_offset_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd029,15,15,__ERR) #define wr_dc_offset_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd029,0x0001,0,wr_val) #define rd_p1_wants_to_go_high() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03a,0,15,__ERR) #define rd_p1_wants_to_go_low() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03a,1,15,__ERR) #define rd_p1_eyediag_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd03a,2,10,__ERR) #define rd_vga_wants_to_go_low() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03a,9,15,__ERR) #define rd_vga_bin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03a,10,10,__ERR) #define rd_dfe_1_wants_negative() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03b,0,15,__ERR) #define rd_dfe_1_e() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03b,2,13,__ERR) #define rd_dfe_1_o() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03b,5,13,__ERR) #define rd_dfe_1_cmn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03b,10,10,__ERR) #define rd_dfe_2_e() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03c,2,13,__ERR) #define rd_dfe_2_o() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03c,5,13,__ERR) #define rd_dfe_2_se() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03c,9,15,__ERR) #define rd_dfe_2_so() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03c,10,15,__ERR) #define rd_dfe_2_cmn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03c,11,11,__ERR) #define rd_dfe_5_cmn() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd03d,0,11,__ERR) #define rd_dfe_4_cmn() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd03d,5,11,__ERR) #define rd_dfe_3_cmn() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd03d,10,10,__ERR) #define rd_vga3_ctrl_bin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03e,4,12,__ERR) #define rd_vga2_ctrl_bin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03e,8,12,__ERR) #define rd_vga1_ctrl_bin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd03e,12,12,__ERR) #define rd_pf_hiz() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,8,15,__ERR) #define wr_pf_hiz(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0080,7,wr_val) #define rd_m1_thresh_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,9,14,__ERR) #define wr_m1_thresh_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0060,5,wr_val) #define rd_m1_thresh_zero() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,11,15,__ERR) #define wr_m1_thresh_zero(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0010,4,wr_val) #define rd_p1_thresh_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,12,15,__ERR) #define wr_p1_thresh_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0008,3,wr_val) #define rd_en_hgain() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,13,15,__ERR) #define wr_en_hgain(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0004,2,wr_val) #define rd_offset_pd() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,14,15,__ERR) #define wr_offset_pd(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0002,1,wr_val) #define rd_pd_ch_p1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd040,15,15,__ERR) #define wr_pd_ch_p1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd040,0x0001,0,wr_val) #define rd_pf_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd041,12,12,__ERR) #define wr_pf_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd041,0x000f,0,wr_val) #define rd_pf2_lowp_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd042,13,13,__ERR) #define wr_pf2_lowp_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd042,0x0007,0,wr_val) #define rd_data_offset_odd_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd141,10,10,__ERR) #define rd_data_offset_evn_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd142,10,10,__ERR) #define rd_p1_offset_odd_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd143,10,10,__ERR) #define rd_p1_offset_evn_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd144,10,10,__ERR) #define rd_m1_offset_odd_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd145,10,10,__ERR) #define rd_m1_offset_evn_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd146,10,10,__ERR) #define rd_dc_offset_bin() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd147,9,9,__ERR) #define rdc_mdio_blk_addr() _merlin16_shortfin_pmd_rde_field(sa__, 0xffdf,1,5,__ERR) #define wrc_mdio_blk_addr(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xffdf,0x7ff0,4,wr_val) #define rdc_mdio_function() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x000d,0,14,__ERR) #define wrc_mdio_function(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0x000d,0xc000,14,wr_val) #define rdc_mdio_devad() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0x000d,11,11,__ERR) #define wrc_mdio_devad(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0x000d,0x001f,0,wr_val) #define rdc_mdio_addr_data() _merlin16_shortfin_pmd_rde_reg(sa__, 0x000e,__ERR) #define wrc_mdio_addr_data(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x000e,wr_val) #define rdc_mdio_drv_comclk() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdc,0,15,__ERR) #define wrc_mdio_drv_comclk(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdc,0x8000,15,wr_val) #define rdc_mdio_brcst_port_addr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdc,11,11,__ERR) #define wrc_mdio_brcst_port_addr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdc,0x001f,0,wr_val) #define rdc_mdio_multi_prts_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,0,15,__ERR) #define wrc_mdio_multi_prts_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x8000,15,wr_val) #define rdc_mdio_multi_mmds_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,1,15,__ERR) #define wrc_mdio_multi_mmds_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x4000,14,wr_val) #define rdc_mdio_dev_pcs_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,9,15,__ERR) #define wrc_mdio_dev_pcs_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0040,6,wr_val) #define rdc_mdio_dev_dte_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,10,15,__ERR) #define wrc_mdio_dev_dte_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0020,5,wr_val) #define rdc_mdio_dev_phy_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,11,15,__ERR) #define wrc_mdio_dev_phy_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0010,4,wr_val) #define rdc_mdio_dev_an_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,12,15,__ERR) #define wrc_mdio_dev_an_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0008,3,wr_val) #define rdc_mdio_dev_pmd_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,13,15,__ERR) #define wrc_mdio_dev_pmd_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0004,2,wr_val) #define rdc_mdio_dev_id0_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xffdd,15,15,__ERR) #define wrc_mdio_dev_id0_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xffdd,0x0001,0,wr_val) #define rdc_mdio_aer() _merlin16_shortfin_pmd_rde_reg(sa__, 0xffde,__ERR) #define wrc_mdio_aer(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xffde,wr_val) #define rdc_micro_core_clk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd200,14,15,__ERR) #define wrc_micro_core_clk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd200,0x0002,1,wr_val) #define rdc_micro_master_clk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd200,15,15,__ERR) #define wrc_micro_master_clk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd200,0x0001,0,wr_val) #define rdc_micro_pram_if_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd201,12,15,__ERR) #define wrc_micro_pram_if_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd201,0x0008,3,wr_val) #define rdc_micro_core_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd201,14,15,__ERR) #define wrc_micro_core_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd201,0x0002,1,wr_val) #define rdc_micro_master_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd201,15,15,__ERR) #define wrc_micro_master_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd201,0x0001,0,wr_val) #define rdc_micro_autoinc_rdaddr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd202,2,15,__ERR) #define wrc_micro_autoinc_rdaddr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd202,0x2000,13,wr_val) #define rdc_micro_autoinc_wraddr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd202,3,15,__ERR) #define wrc_micro_autoinc_wraddr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd202,0x1000,12,wr_val) #define rdc_micro_ra_init() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd202,6,14,__ERR) #define wrc_micro_ra_init(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd202,0x0300,8,wr_val) #define rdc_micro_ra_rddatasize() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd202,10,14,__ERR) #define wrc_micro_ra_rddatasize(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd202,0x0030,4,wr_val) #define rdc_micro_ra_wrdatasize() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd202,14,14,__ERR) #define wrc_micro_ra_wrdatasize(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd202,0x0003,0,wr_val) #define rdc_micro_ra_initdone() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd203,15,15,__ERR) #define rdc_micro_ra_wraddr_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd204,__ERR) #define wrc_micro_ra_wraddr_lsw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd204,wr_val) #define rdc_micro_ra_wraddr_msw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd205,__ERR) #define wrc_micro_ra_wraddr_msw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd205,wr_val) #define rdc_micro_ra_wrdata_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd206,__ERR) #define wrc_micro_ra_wrdata_lsw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd206,wr_val) #define rdc_micro_ra_wrdata_msw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd207,__ERR) #define wrc_micro_ra_wrdata_msw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd207,wr_val) #define rdc_micro_ra_rdaddr_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd208,__ERR) #define wrc_micro_ra_rdaddr_lsw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd208,wr_val) #define rdc_micro_ra_rdaddr_msw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd209,__ERR) #define wrc_micro_ra_rdaddr_msw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd209,wr_val) #define rdc_micro_ra_rddata_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20a,__ERR) #define rdc_micro_ra_rddata_msw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20b,__ERR) #define rdc_micro_pramif_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd20c,15,15,__ERR) #define wrc_micro_pramif_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd20c,0x0001,0,wr_val) #define rdc_micro_pramif_ahb_wraddr_lsw() _merlin16_shortfin_pmd_rde_field(sa__, 0xd20d,0,2,__ERR) #define wrc_micro_pramif_ahb_wraddr_lsw(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd20d,0xfffc,2,wr_val) #define rdc_micro_pramif_ahb_wraddr_msw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20e,__ERR) #define wrc_micro_pramif_ahb_wraddr_msw(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20e,wr_val) #define rdc_micro_pvt_tempdata_rmi() _merlin16_shortfin_pmd_rde_field(sa__, 0xd210,6,6,__ERR) #define rdc_micro_rmi_to_micro_mbox0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd211,__ERR) #define wrc_micro_rmi_to_micro_mbox0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd211,wr_val) #define rdc_micro_rmi_to_micro_mbox1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd212,__ERR) #define wrc_micro_rmi_to_micro_mbox1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd212,wr_val) #define rdc_micro_to_rmi_mbox0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd213,__ERR) #define rdc_micro_to_rmi_mbox1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd214,__ERR) #define rdc_micro_gen_intr_rmi_mbox1wr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd215,13,15,__ERR) #define wrc_micro_gen_intr_rmi_mbox1wr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd215,0x0004,2,wr_val) #define rdc_micro_gen_intr_rmi_mbox0wr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd215,14,15,__ERR) #define wrc_micro_gen_intr_rmi_mbox0wr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd215,0x0002,1,wr_val) #define rdc_micro_rmi_mbox_send_msgin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd215,15,15,__ERR) #define wrc_micro_rmi_mbox_send_msgin(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd215,0x0001,0,wr_val) #define rdc_micro_pmi_hp_ext_ack_timeout_dis() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd216,11,15,__ERR) #define wrc_micro_pmi_hp_ext_ack_timeout_dis(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd216,0x0010,4,wr_val) #define rdc_micro_pmi_hp_ack_timeout_dis() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd216,12,15,__ERR) #define wrc_micro_pmi_hp_ack_timeout_dis(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd216,0x0008,3,wr_val) #define rdc_micro_sw_pmi_hp_ext_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd216,13,15,__ERR) #define wrc_micro_sw_pmi_hp_ext_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd216,0x0004,2,wr_val) #define rdc_micro_sw_pmi_hp_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd216,14,15,__ERR) #define wrc_micro_sw_pmi_hp_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd216,0x0002,1,wr_val) #define rdc_micro_m0_hresp_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd216,15,15,__ERR) #define wrc_micro_m0_hresp_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd216,0x0001,0,wr_val) #define rdc_micro_pr_default_slave_error() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd217,13,15,__ERR) #define rdc_micro_rmi_default_slave_error() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd217,14,15,__ERR) #define rdc_micro_m0_default_slave_error() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd217,15,15,__ERR) #define rdc_micro_ra_autoinc_nxt_wraddr_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd218,__ERR) #define rdc_micro_ra_autoinc_nxt_rdaddr_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd219,__ERR) #define rdc_micro_pr_autoinc_nxt_wraddr_lsw() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd21a,__ERR) #define rdc_micro_pvt_tempdata_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd21b,3,15,__ERR) #define wrc_micro_pvt_tempdata_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd21b,0x1000,12,wr_val) #define rdc_micro_pvt_tempdata_frcval() _merlin16_shortfin_pmd_rde_field(sa__, 0xd21b,6,6,__ERR) #define wrc_micro_pvt_tempdata_frcval(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd21b,0x03ff,0,wr_val) #define rdc_micro_ecc_corrupt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd220,10,14,__ERR) #define wrc_micro_ecc_corrupt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd220,0x0030,4,wr_val) #define rdc_micro_ecc_frc_disable() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd220,14,15,__ERR) #define wrc_micro_ecc_frc_disable(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd220,0x0002,1,wr_val) #define rdc_micro_eccg_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd220,15,15,__ERR) #define wrc_micro_eccg_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd220,0x0001,0,wr_val) #define rdc_micro_ra_ecc_wrdata() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd221,9,9,__ERR) #define wrc_micro_ra_ecc_wrdata(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd221,0x007f,0,wr_val) #define rdc_micro_code_ram_ecc_address() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd222,__ERR) #define rdc_micro_ra_ecc_rddata() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd223,9,9,__ERR) #define rdc_micro_code_ram_tm() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd224,9,9,__ERR) #define wrc_micro_code_ram_tm(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd224,0x007f,0,wr_val) #define rdc_micro_ignore_m0_code_writes() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd225,0,15,__ERR) #define wrc_micro_ignore_m0_code_writes(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd225,0x8000,15,wr_val) #define rdc_micro_ramclk_noninv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd225,1,15,__ERR) #define wrc_micro_ramclk_noninv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd225,0x4000,14,wr_val) #define rdc_micro_dr_size() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd225,2,10,__ERR) #define wrc_micro_dr_size(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd225,0x3f00,8,wr_val) #define rdc_micro_protect_fwcode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd225,14,15,__ERR) #define wrc_micro_protect_fwcode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd225,0x0002,1,wr_val) #define rdc_micro_dr_looktab_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd225,15,15,__ERR) #define wrc_micro_dr_looktab_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd225,0x0001,0,wr_val) #define rdc_micro_rmi_m0_systemresetreq_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,6,15,__ERR) #define rdc_micro_rmi_m0_lockup_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,7,15,__ERR) #define rdc_micro_rmi_ecc_multirow_err_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,9,15,__ERR) #define rdc_micro_rmi_ecc_uncorr_err_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,10,15,__ERR) #define rdc_micro_rmi_ecc_corr_err_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,11,15,__ERR) #define rdc_micro_rmi_mbox_msgout_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd227,15,15,__ERR) #define rdc_micro_rmi_m0_systemresetreq_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,6,15,__ERR) #define wrc_micro_rmi_m0_systemresetreq_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0200,9,wr_val) #define rdc_micro_rmi_m0_lockup_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,7,15,__ERR) #define wrc_micro_rmi_m0_lockup_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0100,8,wr_val) #define rdc_micro_rmi_ecc_multirow_err_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,9,15,__ERR) #define wrc_micro_rmi_ecc_multirow_err_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0040,6,wr_val) #define rdc_micro_rmi_ecc_uncorr_err_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,10,15,__ERR) #define wrc_micro_rmi_ecc_uncorr_err_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0020,5,wr_val) #define rdc_micro_rmi_ecc_corr_err_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,11,15,__ERR) #define wrc_micro_rmi_ecc_corr_err_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0010,4,wr_val) #define rdc_micro_rmi_mbox_msgout_intr_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd226,15,15,__ERR) #define wrc_micro_rmi_mbox_msgout_intr_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd226,0x0001,0,wr_val) #define rdc_micro_pmi_hp_ext_fast_bktobk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,5,15,__ERR) #define wrc_micro_pmi_hp_ext_fast_bktobk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0400,10,wr_val) #define rdc_micro_pmi_hp_ext_fast_dual_meta_ff_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,6,15,__ERR) #define wrc_micro_pmi_hp_ext_fast_dual_meta_ff_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0200,9,wr_val) #define rdc_micro_pmi_hp_ext_fast_read_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,7,15,__ERR) #define wrc_micro_pmi_hp_ext_fast_read_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0100,8,wr_val) #define rdc_micro_pmi_hp_fast_bktobk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,13,15,__ERR) #define wrc_micro_pmi_hp_fast_bktobk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0004,2,wr_val) #define rdc_micro_pmi_hp_fast_dual_meta_ff_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,14,15,__ERR) #define wrc_micro_pmi_hp_fast_dual_meta_ff_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0002,1,wr_val) #define rdc_micro_pmi_hp_fast_read_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd228,15,15,__ERR) #define wrc_micro_pmi_hp_fast_read_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd228,0x0001,0,wr_val) #define rdc_micro_silicon_debug_status_mux_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd229,14,14,__ERR) #define wrc_micro_silicon_debug_status_mux_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd229,0x0003,0,wr_val) #define rdc_micro_silicon_debug_status_muxed_data() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd22a,__ERR) #define rdc_patt_gen_seq_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd100,__ERR) #define wrc_patt_gen_seq_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd100,wr_val) #define rdc_patt_gen_seq_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd101,__ERR) #define wrc_patt_gen_seq_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd101,wr_val) #define rdc_patt_gen_seq_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd102,__ERR) #define wrc_patt_gen_seq_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd102,wr_val) #define rdc_patt_gen_seq_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd103,__ERR) #define wrc_patt_gen_seq_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd103,wr_val) #define rdc_patt_gen_seq_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd104,__ERR) #define wrc_patt_gen_seq_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd104,wr_val) #define rdc_patt_gen_seq_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd105,__ERR) #define wrc_patt_gen_seq_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd105,wr_val) #define rdc_patt_gen_seq_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd106,__ERR) #define wrc_patt_gen_seq_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd106,wr_val) #define rdc_patt_gen_seq_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd107,__ERR) #define wrc_patt_gen_seq_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd107,wr_val) #define rdc_patt_gen_seq_8() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd108,__ERR) #define wrc_patt_gen_seq_8(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd108,wr_val) #define rdc_patt_gen_seq_9() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd109,__ERR) #define wrc_patt_gen_seq_9(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd109,wr_val) #define rdc_patt_gen_seq_10() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10a,__ERR) #define wrc_patt_gen_seq_10(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10a,wr_val) #define rdc_patt_gen_seq_11() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10b,__ERR) #define wrc_patt_gen_seq_11(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10b,wr_val) #define rdc_patt_gen_seq_12() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10c,__ERR) #define wrc_patt_gen_seq_12(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10c,wr_val) #define rdc_patt_gen_seq_13() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10d,__ERR) #define wrc_patt_gen_seq_13(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10d,wr_val) #define rdc_patt_gen_seq_14() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10e,__ERR) #define wrc_patt_gen_seq_14(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10e,wr_val) #define rdc_cal_th() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd120,0,14,__ERR) #define wrc_cal_th(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd120,0xc000,14,wr_val) #define rdc_calib_step_time() _merlin16_shortfin_pmd_rde_field(sa__, 0xd120,3,3,__ERR) #define wrc_calib_step_time(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd120,0x1fff,0,wr_val) #define rdc_freqdet_time() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd121,__ERR) #define wrc_freqdet_time(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd121,wr_val) #define rdc_calib_cap_charge_time() _merlin16_shortfin_pmd_rde_field(sa__, 0xd122,4,4,__ERR) #define wrc_calib_cap_charge_time(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd122,0x0fff,0,wr_val) #define rdc_ext_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd123,0,12,__ERR) #define wrc_ext_state(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd123,0xf000,12,wr_val) #define rdc_accel_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd123,4,15,__ERR) #define wrc_accel_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd123,0x0800,11,wr_val) #define rdc_debug_clr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd123,5,15,__ERR) #define wrc_debug_clr(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd123,0x0400,10,wr_val) #define rdc_freqdet_time_msb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd123,6,15,__ERR) #define wrc_freqdet_time_msb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd123,0x0200,9,wr_val) #define rdc_freqdet_win() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd123,8,8,__ERR) #define wrc_freqdet_win(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd123,0x00ff,0,wr_val) #define rdc_halfstep_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,0,15,__ERR) #define wrc_halfstep_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x8000,15,wr_val) #define rdc_pll_force_cap_pass_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,1,15,__ERR) #define wrc_pll_force_cap_pass_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x4000,14,wr_val) #define rdc_pll_force_cap_pass() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,2,15,__ERR) #define wrc_pll_force_cap_pass(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x2000,13,wr_val) #define rdc_cal_pause_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,3,15,__ERR) #define wrc_cal_pause_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x1000,12,wr_val) #define rdc_cal_pause_rel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,4,15,__ERR) #define wrc_cal_pause_rel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x0800,11,wr_val) #define rdc_cap_delay() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,5,15,__ERR) #define wrc_cap_delay(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x0400,10,wr_val) #define rdc_calib_start() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,6,15,__ERR) #define wrc_calib_start(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x0200,9,wr_val) #define rdc_en_calib_n() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,7,15,__ERR) #define wrc_en_calib_n(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x0100,8,wr_val) #define rdc_ext_range() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd124,9,9,__ERR) #define wrc_ext_range(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd124,0x007f,0,wr_val) #define rdc_pll_seq_start() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,0,15,__ERR) #define wrc_pll_seq_start(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x8000,15,wr_val) #define rdc_lkdt_pause_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,1,15,__ERR) #define wrc_lkdt_pause_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x4000,14,wr_val) #define rdc_lkdt_pause_rel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,2,15,__ERR) #define wrc_lkdt_pause_rel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x2000,13,wr_val) #define rdc_vco_rst_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,3,15,__ERR) #define wrc_vco_rst_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x1000,12,wr_val) #define rdc_ext_range_force() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,6,15,__ERR) #define wrc_ext_range_force(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0200,9,wr_val) #define rdc_autocal_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,7,15,__ERR) #define wrc_autocal_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0100,8,wr_val) #define rdc_autocal_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,8,13,__ERR) #define wrc_autocal_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x00e0,5,wr_val) #define rdc_lkdt_byp() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,11,15,__ERR) #define wrc_lkdt_byp(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0010,4,wr_val) #define rdc_pll_lock_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,12,15,__ERR) #define wrc_pll_lock_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0008,3,wr_val) #define rdc_pll_lock_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,13,15,__ERR) #define wrc_pll_lock_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0004,2,wr_val) #define rdc_pllforce_fdone() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,14,15,__ERR) #define wrc_pllforce_fdone(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0002,1,wr_val) #define rdc_pllforce_fdone_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd125,15,15,__ERR) #define wrc_pllforce_fdone_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd125,0x0001,0,wr_val) #define rdc_band_iqbuf_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd126,8,15,__ERR) #define wrc_band_iqbuf_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd126,0x0080,7,wr_val) #define rdc_vcorange_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd126,9,15,__ERR) #define wrc_vcorange_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd126,0x0040,6,wr_val) #define rdc_vcobufpon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd126,10,15,__ERR) #define wrc_vcobufpon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd126,0x0020,5,wr_val) #define rdc_vcopon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd126,12,15,__ERR) #define wrc_vcopon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd126,0x0008,3,wr_val) #define rdc_pllpon_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd126,14,15,__ERR) #define wrc_pllpon_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd126,0x0002,1,wr_val) #define rdc_pll_fail_stky() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,0,15,__ERR) #define rdc_cal_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,1,12,__ERR) #define rdc_cal_valid() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,5,15,__ERR) #define rdc_pll_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,6,15,__ERR) #define rdc_pll_lock_bar_stky() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,7,15,__ERR) #define rdc_pll_range() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd128,9,9,__ERR) #define rdc_lkdtref_counter_msb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd129,0,15,__ERR) #define rdc_lkdtvco_counter_msb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd129,1,15,__ERR) #define rdc_calref_counter() _merlin16_shortfin_pmd_rde_field(sa__, 0xd129,3,3,__ERR) #define rdc_band_iqbuf_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12a,0,13,__ERR) #define rdc_calvco_counter() _merlin16_shortfin_pmd_rde_field(sa__, 0xd12a,3,3,__ERR) #define rdc_lkdtref_counter() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12b,__ERR) #define rdc_lkdtvco_counter() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12c,__ERR) #define rdc_vcobufpon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12d,2,12,__ERR) #define rdc_calstate_onehot() _merlin16_shortfin_pmd_rde_field(sa__, 0xd12d,6,6,__ERR) #define rdc_pll_pwrdn_or() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12e,0,15,__ERR) #define rdc_vco_range_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12e,1,9,__ERR) #define rdc_vcopon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12e,8,12,__ERR) #define rdc_pllpon_mux() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd12e,12,12,__ERR) #define rd_afe_sigdet_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd161,14,15,__ERR) #define wr_afe_sigdet_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd161,0x0002,1,wr_val) #define rd_ln_rx_s_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd161,15,15,__ERR) #define wr_ln_rx_s_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd161,0x0001,0,wr_val) #define rd_pmd_rx_clk_vld_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd167,11,15,__ERR) #define wr_pmd_rx_clk_vld_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd167,0x0010,4,wr_val) #define rd_pmd_rx_clk_vld_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd167,12,15,__ERR) #define wr_pmd_rx_clk_vld_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd167,0x0008,3,wr_val) #define rd_ln_rx_s_comclk_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd167,13,15,__ERR) #define wr_ln_rx_s_comclk_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd167,0x0004,2,wr_val) #define rd_ln_rx_s_comclk_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd167,14,15,__ERR) #define wr_ln_rx_s_comclk_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd167,0x0002,1,wr_val) #define rd_ln_rx_s_clkgate_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd167,15,15,__ERR) #define wr_ln_rx_s_clkgate_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd167,0x0001,0,wr_val) #define rd_sigdet_dp_rstb_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd164,13,15,__ERR) #define wr_sigdet_dp_rstb_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd164,0x0004,2,wr_val) #define rd_ln_rx_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd164,14,15,__ERR) #define wr_ln_rx_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd164,0x0002,1,wr_val) #define rd_ln_rx_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd164,15,15,__ERR) #define wr_ln_rx_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd164,0x0001,0,wr_val) #define rd_afe_rx_reset_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd162,12,15,__ERR) #define wr_afe_rx_reset_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd162,0x0008,3,wr_val) #define rd_afe_rx_reset_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd162,13,15,__ERR) #define wr_afe_rx_reset_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd162,0x0004,2,wr_val) #define rd_afe_rx_pwrdn_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd162,14,15,__ERR) #define wr_afe_rx_pwrdn_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd162,0x0002,1,wr_val) #define rd_afe_rx_pwrdn_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd162,15,15,__ERR) #define wr_afe_rx_pwrdn_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd162,0x0001,0,wr_val) #define rd_pmd_ln_rx_h_pwrdn_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd163,15,15,__ERR) #define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd163,0x0001,0,wr_val) #define rd_pmd_lane_mode() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd168,__ERR) #define rd_afe_rx_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd16c,14,15,__ERR) #define rd_afe_rx_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd16c,15,15,__ERR) #define rd_rx_osr_mode_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd180,0,15,__ERR) #define wr_rx_osr_mode_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd180,0x8000,15,wr_val) #define rd_rx_osr_mode_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd180,12,12,__ERR) #define wr_rx_osr_mode_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd180,0x000f,0,wr_val) #define rd_rx_ln_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd181,15,15,__ERR) #define wr_rx_ln_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd181,0x0001,0,wr_val) #define rd_rx_ln_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd18e,15,15,__ERR) #define wr_rx_ln_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd18e,0x0001,0,wr_val) #define rd_pmd_ln_rx_dp_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd183,14,15,__ERR) #define wr_pmd_ln_rx_dp_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd183,0x0002,1,wr_val) #define rd_pmd_ln_rx_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd183,15,15,__ERR) #define wr_pmd_ln_rx_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd183,0x0001,0,wr_val) #define rd_rx_uc_ack_lane_dp_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd185,14,15,__ERR) #define wr_rx_uc_ack_lane_dp_reset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd185,0x0002,1,wr_val) #define rd_rx_uc_ack_lane_cfg_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd185,15,15,__ERR) #define wr_rx_uc_ack_lane_cfg_done(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd185,0x0001,0,wr_val) #define rd_rx_lane_dp_reset_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd189,13,13,__ERR) #define rd_rx_lane_reg_reset_occurred() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd186,15,15,__ERR) #define wr_rx_lane_reg_reset_occurred(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd186,0x0001,0,wr_val) #define rd_rx_osr_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd18b,12,12,__ERR) #define rd_rx_osr_mode_pin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd18c,12,12,__ERR) #define rd_osr_mode_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd080,0,15,__ERR) #define wr_osr_mode_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd080,0x8000,15,wr_val) #define rd_osr_mode_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd080,12,12,__ERR) #define wr_osr_mode_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd080,0x000f,0,wr_val) #define rd_ln_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd081,15,15,__ERR) #define wr_ln_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd081,0x0001,0,wr_val) #define rd_ln_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd08e,15,15,__ERR) #define wr_ln_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd08e,0x0001,0,wr_val) #define rd_pmd_ln_dp_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd083,14,15,__ERR) #define wr_pmd_ln_dp_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd083,0x0002,1,wr_val) #define rd_pmd_ln_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd083,15,15,__ERR) #define wr_pmd_ln_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd083,0x0001,0,wr_val) #define rd_uc_ack_lane_dp_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd085,14,15,__ERR) #define wr_uc_ack_lane_dp_reset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd085,0x0002,1,wr_val) #define rd_uc_ack_lane_cfg_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd085,15,15,__ERR) #define wr_uc_ack_lane_cfg_done(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd085,0x0001,0,wr_val) #define rd_lane_dp_reset_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd089,13,13,__ERR) #define rd_lane_reg_reset_occurred() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd086,15,15,__ERR) #define wr_lane_reg_reset_occurred(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd086,0x0001,0,wr_val) #define rd_osr_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd08b,12,12,__ERR) #define rd_osr_mode_pin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd08c,12,12,__ERR) #define rd_signal_detect_filter_count() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c0,11,11,__ERR) #define wr_signal_detect_filter_count(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c0,0x001f,0,wr_val) #define rd_los_filter_count() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c0,6,11,__ERR) #define wr_los_filter_count(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c0,0x03e0,5,wr_val) #define rd_energy_detect_mask_count() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c0,1,11,__ERR) #define wr_energy_detect_mask_count(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c0,0x7c00,10,wr_val) #define rd_afe_signal_detect_dis() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,15,15,__ERR) #define wr_afe_signal_detect_dis(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0001,0,wr_val) #define rd_ext_los_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,14,15,__ERR) #define wr_ext_los_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0002,1,wr_val) #define rd_ext_los_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,13,15,__ERR) #define wr_ext_los_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0004,2,wr_val) #define rd_ignore_lp_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,12,15,__ERR) #define wr_ignore_lp_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0008,3,wr_val) #define rd_signal_detect_filter_1us() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,11,15,__ERR) #define wr_signal_detect_filter_1us(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0010,4,wr_val) #define rd_energy_detect_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,10,15,__ERR) #define wr_energy_detect_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0020,5,wr_val) #define rd_energy_detect_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,9,15,__ERR) #define wr_energy_detect_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0040,6,wr_val) #define rd_signal_detect_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,8,15,__ERR) #define wr_signal_detect_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0080,7,wr_val) #define rd_signal_detect_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c1,7,15,__ERR) #define wr_signal_detect_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c1,0x0100,8,wr_val) #define rd_los_thresh() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c2,11,11,__ERR) #define wr_los_thresh(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c2,0x001f,0,wr_val) #define rd_signal_detect_thresh() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c2,6,11,__ERR) #define wr_signal_detect_thresh(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c2,0x03e0,5,wr_val) #define rd_hold_los_count() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c2,3,13,__ERR) #define wr_hold_los_count(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c2,0x1c00,10,wr_val) #define rd_hold_sd_count() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c2,0,13,__ERR) #define wr_hold_sd_count(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0c2,0xe000,13,wr_val) #define rd_signal_detect() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,15,15,__ERR) #define rd_signal_detect_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,14,15,__ERR) #define rd_signal_detect_raw() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,11,15,__ERR) #define rd_signal_detect_raw_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,10,15,__ERR) #define rd_ext_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,9,15,__ERR) #define rd_ext_sigdet_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,8,15,__ERR) #define rd_afe_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,7,15,__ERR) #define rd_afe_sigdet_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c8,6,15,__ERR) #define rd_uc_signal_detect() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,15,15,__ERR) #define rd_uc_signal_detect_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,14,15,__ERR) #define rd_uc_ext_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,9,15,__ERR) #define rd_uc_ext_sigdet_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,8,15,__ERR) #define rd_uc_afe_sigdet() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,7,15,__ERR) #define rd_uc_afe_sigdet_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0c9,6,15,__ERR) #define rd_energy_detect() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0ca,15,15,__ERR) #define rd_energy_detect_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0ca,14,15,__ERR) #define rd_pmd_signal_detect() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0cb,15,15,__ERR) #define rd_afe_sigdet_thresh() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0cc,11,11,__ERR) #define rd_prbs_chk_burst_err_cnt_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,0,15,__ERR) #define wr_prbs_chk_burst_err_cnt_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x8000,15,wr_val) #define rd_prbs_chk_clk_en_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,4,15,__ERR) #define wr_prbs_chk_clk_en_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0800,11,wr_val) #define rd_trnsum_error_count_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,5,15,__ERR) #define wr_trnsum_error_count_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0400,10,wr_val) #define rd_prbs_chk_err_cnt_burst_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,6,15,__ERR) #define wr_prbs_chk_err_cnt_burst_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0200,9,wr_val) #define rd_prbs_chk_en_auto_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,8,15,__ERR) #define wr_prbs_chk_en_auto_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0080,7,wr_val) #define rd_prbs_chk_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,9,14,__ERR) #define wr_prbs_chk_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0060,5,wr_val) #define rd_prbs_chk_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,11,15,__ERR) #define wr_prbs_chk_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0010,4,wr_val) #define rd_prbs_chk_mode_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,12,13,__ERR) #define wr_prbs_chk_mode_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x000e,1,wr_val) #define rd_prbs_chk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d1,15,15,__ERR) #define wr_prbs_chk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d1,0x0001,0,wr_val) #define rd_prbs_chk_lock_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d0,11,11,__ERR) #define wr_prbs_chk_lock_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d0,0x001f,0,wr_val) #define rd_prbs_chk_ool_cnt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d0,3,11,__ERR) #define wr_prbs_chk_ool_cnt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d0,0x1f00,8,wr_val) #define rd_dig_lpbk_pd_bias_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d2,12,15,__ERR) #define wr_dig_lpbk_pd_bias_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0008,3,wr_val) #define rd_dig_lpbk_pd_flt_bypass() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d2,13,15,__ERR) #define wr_dig_lpbk_pd_flt_bypass(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0004,2,wr_val) #define rd_dig_lpbk_pd_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d2,14,15,__ERR) #define wr_dig_lpbk_pd_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0002,1,wr_val) #define rd_dig_lpbk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d2,15,15,__ERR) #define wr_dig_lpbk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d2,0x0001,0,wr_val) #define rd_dbg_mask_dig_lpbk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d3,13,15,__ERR) #define wr_dbg_mask_dig_lpbk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0004,2,wr_val) #define rd_rx_aggregator_bypass_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d3,14,15,__ERR) #define wr_rx_aggregator_bypass_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0002,1,wr_val) #define rd_rx_pmd_dp_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d3,15,15,__ERR) #define wr_rx_pmd_dp_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d3,0x0001,0,wr_val) #define rd_prbs_chk_en_timeout() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d4,3,11,__ERR) #define wr_prbs_chk_en_timeout(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d4,0x1f00,8,wr_val) #define rd_prbs_chk_en_timer_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d4,14,14,__ERR) #define wr_prbs_chk_en_timer_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0d4,0x0003,0,wr_val) #define rd_dig_lpbk_pd_early_ind() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d8,14,15,__ERR) #define rd_dig_lpbk_pd_late_ind() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d8,15,15,__ERR) #define rd_prbs_chk_err_cnt_no_clr() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0d9,0,1,__ERR) #define rd_prbs_chk_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d9,15,15,__ERR) #define rd_prbs_chk_lock_lost_lh() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0da,0,15,__ERR) #define rd_prbs_chk_err_cnt_msb() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0da,1,1,__ERR) #define rd_prbs_chk_err_cnt_lsb() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0db,__ERR) #define rd_pmd_rx_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0dc,15,15,__ERR) #define rd_pmd_rx_lock_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0dc,14,15,__ERR) #define rd_dbg_pmd_rx_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d6,15,15,__ERR) #define rd_dbg_pmd_rx_lock_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d6,14,15,__ERR) #define rd_uc_pmd_rx_lock() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d7,15,15,__ERR) #define rd_uc_pmd_rx_lock_change() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0d7,14,15,__ERR) #define rd_prbs_chk_burst_err_cnt() _merlin16_shortfin_pmd_rde_field(sa__, 0xd0d5,6,6,__ERR) #define rd_patt_gen_start_pos() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e0,0,12,__ERR) #define wr_patt_gen_start_pos(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e0,0xf000,12,wr_val) #define rd_patt_gen_stop_pos() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e0,4,12,__ERR) #define wr_patt_gen_stop_pos(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0f00,8,wr_val) #define rd_patt_gen_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e0,15,15,__ERR) #define wr_patt_gen_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e0,0x0001,0,wr_val) #define rd_prbs_gen_err_ins() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e1,10,15,__ERR) #define wr_prbs_gen_err_ins(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0020,5,wr_val) #define rd_prbs_gen_inv() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e1,11,15,__ERR) #define wr_prbs_gen_inv(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0010,4,wr_val) #define rd_prbs_gen_mode_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e1,12,13,__ERR) #define wr_prbs_gen_mode_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e1,0x000e,1,wr_val) #define rd_prbs_gen_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e1,15,15,__ERR) #define wr_prbs_gen_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e1,0x0001,0,wr_val) #define rd_rmt_lpbk_pd_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e2,13,15,__ERR) #define wr_rmt_lpbk_pd_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0004,2,wr_val) #define rd_rmt_lpbk_pd_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e2,14,15,__ERR) #define wr_rmt_lpbk_pd_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0002,1,wr_val) #define rd_rmt_lpbk_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e2,15,15,__ERR) #define wr_rmt_lpbk_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e2,0x0001,0,wr_val) #define rd_tx_mux_sel_order() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e3,13,15,__ERR) #define wr_tx_mux_sel_order(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0004,2,wr_val) #define rd_tx_pcs_native_ana_frmt_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e3,14,15,__ERR) #define wr_tx_pcs_native_ana_frmt_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0002,1,wr_val) #define rd_tx_pmd_dp_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e3,15,15,__ERR) #define wr_tx_pmd_dp_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd0e3,0x0001,0,wr_val) #define rd_rmt_lpbk_pd_early_ind() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e8,14,15,__ERR) #define rd_rmt_lpbk_pd_late_ind() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd0e8,15,15,__ERR) #define rd_afe_tx_reset_deassert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd171,0,15,__ERR) #define wr_afe_tx_reset_deassert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd171,0x8000,15,wr_val) #define rd_ln_tx_s_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd171,15,15,__ERR) #define wr_ln_tx_s_pwrdn(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd171,0x0001,0,wr_val) #define rd_pmd_tx_clk_vld_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd177,11,15,__ERR) #define wr_pmd_tx_clk_vld_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd177,0x0010,4,wr_val) #define rd_pmd_tx_clk_vld_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd177,12,15,__ERR) #define wr_pmd_tx_clk_vld_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd177,0x0008,3,wr_val) #define rd_ln_tx_s_comclk_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd177,13,15,__ERR) #define wr_ln_tx_s_comclk_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd177,0x0004,2,wr_val) #define rd_ln_tx_s_comclk_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd177,14,15,__ERR) #define wr_ln_tx_s_comclk_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd177,0x0002,1,wr_val) #define rd_ln_tx_s_clkgate_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd177,15,15,__ERR) #define wr_ln_tx_s_clkgate_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd177,0x0001,0,wr_val) #define rd_ln_tx_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd174,14,15,__ERR) #define wr_ln_tx_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd174,0x0002,1,wr_val) #define rd_ln_tx_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd174,15,15,__ERR) #define wr_ln_tx_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd174,0x0001,0,wr_val) #define rd_afe_txclk_reset_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,10,15,__ERR) #define wr_afe_txclk_reset_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0020,5,wr_val) #define rd_afe_txclk_reset_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,11,15,__ERR) #define wr_afe_txclk_reset_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0010,4,wr_val) #define rd_afe_tx_reset_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,12,15,__ERR) #define wr_afe_tx_reset_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0008,3,wr_val) #define rd_afe_tx_reset_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,13,15,__ERR) #define wr_afe_tx_reset_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0004,2,wr_val) #define rd_afe_tx_pwrdn_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,14,15,__ERR) #define wr_afe_tx_pwrdn_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0002,1,wr_val) #define rd_afe_tx_pwrdn_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd172,15,15,__ERR) #define wr_afe_tx_pwrdn_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd172,0x0001,0,wr_val) #define rd_pmd_ln_tx_h_pwrdn_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd173,15,15,__ERR) #define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd173,0x0001,0,wr_val) #define rd_afe_txclk_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd17c,13,15,__ERR) #define rd_afe_tx_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd17c,14,15,__ERR) #define rd_afe_tx_pwrdn() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd17c,15,15,__ERR) #define rd_tx_pi_loop_filter_stable() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd17d,15,15,__ERR) #define wr_tx_pi_loop_filter_stable(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd17d,0x0001,0,wr_val) #define rd_txfir_post2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd110,12,12,__ERR) #define wr_txfir_post2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd110,0x000f,0,wr_val) #define rd_convert_taps_to_afe_error() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd111,9,15,__ERR) #define wr_convert_taps_to_afe_error(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd111,0x0040,6,wr_val) #define rd_convert_taps_to_afe_int_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd111,10,15,__ERR) #define wr_convert_taps_to_afe_int_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd111,0x0020,5,wr_val) #define rd_convert_taps_to_afe() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd111,11,15,__ERR) #define wr_convert_taps_to_afe(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd111,0x0010,4,wr_val) #define rd_tx_disable_output_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd111,12,14,__ERR) #define wr_tx_disable_output_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd111,0x000c,2,wr_val) #define rd_sdk_tx_disable() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd111,15,15,__ERR) #define wr_sdk_tx_disable(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd111,0x0001,0,wr_val) #define rd_tx_elec_idle_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd112,14,15,__ERR) #define rd_tx_disable_status() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd112,15,15,__ERR) #define rd_tx_eee_alert_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,0,15,__ERR) #define wr_tx_eee_alert_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x8000,15,wr_val) #define rd_tx_eee_quiet_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,1,15,__ERR) #define wr_tx_eee_quiet_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x4000,14,wr_val) #define rd_tx_disable_timer_ctrl() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,6,10,__ERR) #define wr_tx_disable_timer_ctrl(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x03f0,4,wr_val) #define rd_pmd_tx_disable_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,12,15,__ERR) #define wr_pmd_tx_disable_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x0008,3,wr_val) #define rd_dp_reset_tx_disable_dis() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,13,15,__ERR) #define wr_dp_reset_tx_disable_dis(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x0004,2,wr_val) #define rd_tx_disable_trigger() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,14,15,__ERR) #define wr_tx_disable_trigger(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x0002,1,wr_val) #define rd_micro_tx_disable() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd113,15,15,__ERR) #define wr_micro_tx_disable(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd113,0x0001,0,wr_val) #define rd_txfir_dc_level_post2_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,8,15,__ERR) #define wr_txfir_dc_level_post2_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0080,7,wr_val) #define rd_txfir_post2_post2_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,9,15,__ERR) #define wr_txfir_post2_post2_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0040,6,wr_val) #define rd_txfir_dc_level_post2_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,10,15,__ERR) #define wr_txfir_dc_level_post2_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0020,5,wr_val) #define rd_txfir_post2_post2_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,11,15,__ERR) #define wr_txfir_post2_post2_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0010,4,wr_val) #define rd_txfir_dc_level_post2_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,12,15,__ERR) #define wr_txfir_dc_level_post2_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0008,3,wr_val) #define rd_txfir_post2_post2_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,13,15,__ERR) #define wr_txfir_post2_post2_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0004,2,wr_val) #define rd_txfir_dc_level_post2_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,14,15,__ERR) #define wr_txfir_dc_level_post2_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0002,1,wr_val) #define rd_txfir_post2_post2_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11b,15,15,__ERR) #define wr_txfir_post2_post2_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11b,0x0001,0,wr_val) #define rd_txfir_dc_level_post1pre_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,1,15,__ERR) #define wr_txfir_dc_level_post1pre_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x4000,14,wr_val) #define rd_txfir_post1_post1pre_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,2,15,__ERR) #define wr_txfir_post1_post1pre_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x2000,13,wr_val) #define rd_txfir_pre_post1pre_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,3,15,__ERR) #define wr_txfir_pre_post1pre_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x1000,12,wr_val) #define rd_txfir_dc_level_post1_2x_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,6,15,__ERR) #define wr_txfir_dc_level_post1_2x_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0200,9,wr_val) #define rd_txfir_post1_post1_2x_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,7,15,__ERR) #define wr_txfir_post1_post1_2x_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0100,8,wr_val) #define rd_txfir_dc_level_post1_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,8,15,__ERR) #define wr_txfir_dc_level_post1_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0080,7,wr_val) #define rd_txfir_post1_post1_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,9,15,__ERR) #define wr_txfir_post1_post1_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0040,6,wr_val) #define rd_txfir_dc_level_post1_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,10,15,__ERR) #define wr_txfir_dc_level_post1_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0020,5,wr_val) #define rd_txfir_post1_post1_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,11,15,__ERR) #define wr_txfir_post1_post1_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0010,4,wr_val) #define rd_txfir_dc_level_post1_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,12,15,__ERR) #define wr_txfir_dc_level_post1_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0008,3,wr_val) #define rd_txfir_post1_post1_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,13,15,__ERR) #define wr_txfir_post1_post1_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0004,2,wr_val) #define rd_txfir_dc_level_post1_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,14,15,__ERR) #define wr_txfir_dc_level_post1_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0002,1,wr_val) #define rd_txfir_post1_post1_1x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11c,15,15,__ERR) #define wr_txfir_post1_post1_1x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11c,0x0001,0,wr_val) #define rd_txfir_dc_level_post1pre_2x_3() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,1,15,__ERR) #define wr_txfir_dc_level_post1pre_2x_3(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x4000,14,wr_val) #define rd_txfir_post1_post1pre_2x_3() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,2,15,__ERR) #define wr_txfir_post1_post1pre_2x_3(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x2000,13,wr_val) #define rd_txfir_pre_post1pre_2x_3() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,3,15,__ERR) #define wr_txfir_pre_post1pre_2x_3(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x1000,12,wr_val) #define rd_txfir_dc_level_post1pre_2x_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,4,15,__ERR) #define wr_txfir_dc_level_post1pre_2x_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0800,11,wr_val) #define rd_txfir_post1_post1pre_2x_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,5,15,__ERR) #define wr_txfir_post1_post1pre_2x_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0400,10,wr_val) #define rd_txfir_pre_post1pre_2x_2() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,6,15,__ERR) #define wr_txfir_pre_post1pre_2x_2(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0200,9,wr_val) #define rd_txfir_dc_level_post1pre_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,7,15,__ERR) #define wr_txfir_dc_level_post1pre_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0100,8,wr_val) #define rd_txfir_post1_post1pre_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,8,15,__ERR) #define wr_txfir_post1_post1pre_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0080,7,wr_val) #define rd_txfir_pre_post1pre_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,9,15,__ERR) #define wr_txfir_pre_post1pre_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0040,6,wr_val) #define rd_txfir_dc_level_post1pre_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,10,15,__ERR) #define wr_txfir_dc_level_post1pre_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0020,5,wr_val) #define rd_txfir_post1_post1pre_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,11,15,__ERR) #define wr_txfir_post1_post1pre_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0010,4,wr_val) #define rd_txfir_pre_post1pre_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,12,15,__ERR) #define wr_txfir_pre_post1pre_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0008,3,wr_val) #define rd_txfir_dc_level_post1pre_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,13,15,__ERR) #define wr_txfir_dc_level_post1pre_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0004,2,wr_val) #define rd_txfir_post1_post1pre_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,14,15,__ERR) #define wr_txfir_post1_post1pre_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0002,1,wr_val) #define rd_txfir_pre_post1pre_1x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11d,15,15,__ERR) #define wr_txfir_pre_post1pre_1x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11d,0x0001,0,wr_val) #define rd_txfir_dc_level_2x_1() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11e,12,15,__ERR) #define wr_txfir_dc_level_2x_1(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11e,0x0008,3,wr_val) #define rd_txfir_dc_level_2x_0() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11e,13,15,__ERR) #define wr_txfir_dc_level_2x_0(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11e,0x0004,2,wr_val) #define rd_txfir_dc_level_1x() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11e,14,15,__ERR) #define wr_txfir_dc_level_1x(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11e,0x0002,1,wr_val) #define rd_txfir_dc_level_0p5x() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd11e,15,15,__ERR) #define wr_txfir_dc_level_0p5x(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd11e,0x0001,0,wr_val) #define rd_tx_pi_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,15,15,__ERR) #define wr_tx_pi_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0001,0,wr_val) #define rd_tx_pi_jitter_filter_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,14,15,__ERR) #define wr_tx_pi_jitter_filter_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0002,1,wr_val) #define rd_tx_pi_ext_ctrl_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,13,15,__ERR) #define wr_tx_pi_ext_ctrl_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0004,2,wr_val) #define rd_tx_pi_freq_override_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,12,15,__ERR) #define wr_tx_pi_freq_override_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0008,3,wr_val) #define rd_tx_pi_sj_gen_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,11,15,__ERR) #define wr_tx_pi_sj_gen_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0010,4,wr_val) #define rd_tx_pi_ssc_gen_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,10,15,__ERR) #define wr_tx_pi_ssc_gen_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0020,5,wr_val) #define rd_tx_pi_jit_ssc_freq_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,9,15,__ERR) #define wr_tx_pi_jit_ssc_freq_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0040,6,wr_val) #define rd_tx_pi_reset_code_dbg() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,8,15,__ERR) #define wr_tx_pi_reset_code_dbg(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0080,7,wr_val) #define rd_tx_pi_second_order_loop_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,7,15,__ERR) #define wr_tx_pi_second_order_loop_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0100,8,wr_val) #define rd_tx_pi_first_order_bwsel_integ() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,4,14,__ERR) #define wr_tx_pi_first_order_bwsel_integ(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x0c00,10,wr_val) #define rd_tx_pi_second_order_bwsel_integ() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,2,14,__ERR) #define wr_tx_pi_second_order_bwsel_integ(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x3000,12,wr_val) #define rd_tx_pi_frc_phase_step_mux_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd070,0,15,__ERR) #define wr_tx_pi_frc_phase_step_mux_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd070,0x8000,15,wr_val) #define rd_tx_pi_freq_override_val() _merlin16_shortfin_pmd_rde_field_signed(sa__, 0xd071,1,1,__ERR) #define wr_tx_pi_freq_override_val(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd071,0x7fff,0,wr_val) #define rd_tx_pi_jit_freq_idx() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd072,10,10,__ERR) #define wr_tx_pi_jit_freq_idx(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd072,0x003f,0,wr_val) #define rd_tx_pi_jit_amp() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd072,2,10,__ERR) #define wr_tx_pi_jit_amp(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd072,0x3f00,8,wr_val) #define rd_tx_pi_phase_override() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,15,15,__ERR) #define wr_tx_pi_phase_override(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x0001,0,wr_val) #define rd_tx_pi_phase_strobe() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,14,15,__ERR) #define wr_tx_pi_phase_strobe(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x0002,1,wr_val) #define rd_tx_pi_phase_step_dir() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,13,15,__ERR) #define wr_tx_pi_phase_step_dir(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x0004,2,wr_val) #define rd_tx_pi_phase_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,11,15,__ERR) #define wr_tx_pi_phase_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x0010,4,wr_val) #define rd_tx_pi_phase_step_num() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,4,12,__ERR) #define wr_tx_pi_phase_step_num(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x0f00,8,wr_val) #define rd_tx_pi_ext_phase_bwsel_integ() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd073,1,13,__ERR) #define wr_tx_pi_ext_phase_bwsel_integ(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd073,0x7000,12,wr_val) #define rd_tx_pi_frz_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd074,15,15,__ERR) #define wr_tx_pi_frz_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd074,0x0001,0,wr_val) #define rd_tx_pi_frz_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd074,14,15,__ERR) #define wr_tx_pi_frz_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd074,0x0002,1,wr_val) #define rd_tx_pi_frz_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd074,13,15,__ERR) #define wr_tx_pi_frz_mode(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd074,0x0004,2,wr_val) #define rd_tx_pi_hs_fifo_phserr_invert() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,14,15,__ERR) #define wr_tx_pi_hs_fifo_phserr_invert(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0002,1,wr_val) #define rd_tx_pi_repeater_mode_en() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,13,15,__ERR) #define wr_tx_pi_repeater_mode_en(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0004,2,wr_val) #define rd_tx_pi_ext_pd_sel() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,12,15,__ERR) #define wr_tx_pi_ext_pd_sel(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0008,3,wr_val) #define rd_afe_tx_fifo_resetb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,7,15,__ERR) #define wr_afe_tx_fifo_resetb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0100,8,wr_val) #define rd_afe_tx_fifo_resetb_frc_on() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,6,15,__ERR) #define wr_afe_tx_fifo_resetb_frc_on(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0200,9,wr_val) #define rd_tx_pi_pd_bypass_flt() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,5,15,__ERR) #define wr_tx_pi_pd_bypass_flt(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0400,10,wr_val) #define rd_tx_pi_pd_bypass_vco() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd075,4,15,__ERR) #define wr_tx_pi_pd_bypass_vco(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd075,0x0800,11,wr_val) #define rd_tx_pi_phase_cntr() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd078,9,9,__ERR) #define rd_tx_pi_integ1_reg() _merlin16_shortfin_pmd_rde_field_signed(sa__, 0xd079,2,2,__ERR) #define rd_tx_pi_integ2_reg() _merlin16_shortfin_pmd_rde_field_signed(sa__, 0xd07a,1,1,__ERR) #define rd_tx_pi_phase_err() _merlin16_shortfin_pmd_rde_field_signed_byte(sa__, 0xd07b,10,10,__ERR) #define rd_st_afe_tx_fifo_resetb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd07c,14,15,__ERR) #define rd_tx_pi_hs_fifo_phserr() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd07c,15,15,__ERR) #define rd_tx_fifo_ovfb_fall_edge_lh() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd07d,14,15,__ERR) #define rd_tx_fifo_ovfb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd07d,15,15,__ERR) #define rd_tx_osr_mode_frc() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd190,0,15,__ERR) #define wr_tx_osr_mode_frc(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd190,0x8000,15,wr_val) #define rd_tx_osr_mode_frc_val() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd190,12,12,__ERR) #define wr_tx_osr_mode_frc_val(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd190,0x000f,0,wr_val) #define rd_tx_ln_dp_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd191,15,15,__ERR) #define wr_tx_ln_dp_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd191,0x0001,0,wr_val) #define rd_tx_ln_s_rstb() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd19e,15,15,__ERR) #define wr_tx_ln_s_rstb(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd19e,0x0001,0,wr_val) #define rd_pmd_ln_tx_dp_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd193,14,15,__ERR) #define wr_pmd_ln_tx_dp_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd193,0x0002,1,wr_val) #define rd_pmd_ln_tx_h_rstb_pkill() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd193,15,15,__ERR) #define wr_pmd_ln_tx_h_rstb_pkill(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd193,0x0001,0,wr_val) #define rd_tx_uc_ack_lane_dp_reset() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd195,14,15,__ERR) #define wr_tx_uc_ack_lane_dp_reset(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd195,0x0002,1,wr_val) #define rd_tx_uc_ack_lane_cfg_done() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd195,15,15,__ERR) #define wr_tx_uc_ack_lane_cfg_done(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd195,0x0001,0,wr_val) #define rd_tx_lane_dp_reset_state() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd199,13,13,__ERR) #define rd_tx_lane_reg_reset_occurred() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd196,15,15,__ERR) #define wr_tx_lane_reg_reset_occurred(wr_val) _merlin16_shortfin_pmd_mwr_reg_byte(sa__, 0xd196,0x0001,0,wr_val) #define rd_tx_osr_mode() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd19b,12,12,__ERR) #define rd_tx_osr_mode_pin() _merlin16_shortfin_pmd_rde_field_byte(sa__, 0xd19c,12,12,__ERR) #define rdc_txcom_cl72_max_wait_timer_period() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd130,__ERR) #define wrc_txcom_cl72_max_wait_timer_period(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd130,wr_val) #define rdc_txcom_cl72_wait_cntr_limit() _merlin16_shortfin_pmd_rde_field(sa__, 0xd131,7,7,__ERR) #define wrc_txcom_cl72_wait_cntr_limit(wr_val) merlin16_shortfin_pmd_mwr_reg(sa__, 0xd131,0x01ff,0,wr_val) #define reg_rd_AMS_RX_RXCONTROL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd090,__ERR) #define reg_wr_AMS_RX_RXCONTROL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd090,wr_val) #define reg_rd_AMS_RX_RXCONTROL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd091,__ERR) #define reg_wr_AMS_RX_RXCONTROL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd091,wr_val) #define reg_rd_AMS_RX_RXCONTROL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd092,__ERR) #define reg_wr_AMS_RX_RXCONTROL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd092,wr_val) #define reg_rd_AMS_RX_RXCONTROL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd093,__ERR) #define reg_wr_AMS_RX_RXCONTROL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd093,wr_val) #define reg_rd_AMS_RX_RXCONTROL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd094,__ERR) #define reg_wr_AMS_RX_RXCONTROL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd094,wr_val) #define reg_rd_AMS_RX_RXCONTROL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd095,__ERR) #define reg_wr_AMS_RX_RXCONTROL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd095,wr_val) #define reg_rd_AMS_RX_RXCONTROL_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd096,__ERR) #define reg_wr_AMS_RX_RXCONTROL_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd096,wr_val) #define reg_rd_AMS_RX_RXCONTROL_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd097,__ERR) #define reg_wr_AMS_RX_RXCONTROL_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd097,wr_val) #define reg_rd_AMS_RX_INTCTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd098,__ERR) #define reg_wr_AMS_RX_INTCTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd098,wr_val) #define reg_rd_AMS_RX_RXSTATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd099,__ERR) #define reg_wr_AMS_RX_RXSTATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd099,wr_val) #define reg_rd_AMS_TX_TXCONTROL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a0,__ERR) #define reg_wr_AMS_TX_TXCONTROL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a0,wr_val) #define reg_rd_AMS_TX_TXCONTROL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a1,__ERR) #define reg_wr_AMS_TX_TXCONTROL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a1,wr_val) #define reg_rd_AMS_TX_TXCONTROL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a2,__ERR) #define reg_wr_AMS_TX_TXCONTROL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a2,wr_val) #define reg_rd_AMS_TX_TXCONTROL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a3,__ERR) #define reg_wr_AMS_TX_TXCONTROL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a3,wr_val) #define reg_rd_AMS_TX_TXCONTROL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a4,__ERR) #define reg_wr_AMS_TX_TXCONTROL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a4,wr_val) #define reg_rd_AMS_TX_TXCONTROL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a5,__ERR) #define reg_wr_AMS_TX_TXCONTROL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a5,wr_val) #define reg_rd_AMS_TX_TXCONTROL_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a6,__ERR) #define reg_wr_AMS_TX_TXCONTROL_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a6,wr_val) #define reg_rd_AMS_TX_TXCONTROL_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a7,__ERR) #define reg_wr_AMS_TX_TXCONTROL_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a7,wr_val) #define reg_rd_AMS_TX_TXCONTROL_8() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a8,__ERR) #define reg_wr_AMS_TX_TXCONTROL_8(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a8,wr_val) #define reg_rd_AMS_TX_TXINTCTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0a9,__ERR) #define reg_wr_AMS_TX_TXINTCTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0a9,wr_val) #define reg_rd_AMS_TX_TXSTATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0aa,__ERR) #define reg_wr_AMS_TX_TXSTATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0aa,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b0,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b0,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b1,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b1,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b2,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b2,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b3,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b3,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b4,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b4,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b5,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b5,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b6,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b6,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b7,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b7,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_8() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b8,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_8(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b8,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_9() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0b9,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_9(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0b9,wr_val) #define reg_rdc_AMS_COM_PLL_CTRL_10() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0ba,__ERR) #define reg_wrc_AMS_COM_PLL_CTRL_10(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0ba,wr_val) #define reg_rdc_AMS_COM_PLL_INT() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0be,__ERR) #define reg_wrc_AMS_COM_PLL_INT(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0be,wr_val) #define reg_rdc_AMS_COM_PLL_STS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0bf,__ERR) #define reg_wrc_AMS_COM_PLL_STS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0bf,wr_val) #define reg_rd_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0098,__ERR) #define reg_wr_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x0098,wr_val) #define reg_rd_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0099,__ERR) #define reg_wr_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x0099,wr_val) #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0096,__ERR) #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x0096,wr_val) #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151() _merlin16_shortfin_pmd_rde_reg(sa__, 0x0097,__ERR) #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x0097,wr_val) #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154() _merlin16_shortfin_pmd_rde_reg(sa__, 0x009a,__ERR) #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x009a,wr_val) #define reg_rd_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155() _merlin16_shortfin_pmd_rde_reg(sa__, 0x009b,__ERR) #define reg_wr_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x009b,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_CONTROL0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd050,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_CONTROL0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd050,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_CONTROL1_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd051,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_CONTROL1_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd051,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_CONTROL2_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd052,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_CONTROL2_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd052,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_STATUS0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd053,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_STATUS0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd053,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd054,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd054,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd055,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd055,wr_val) #define reg_rd_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd056,__ERR) #define reg_wr_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd056,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd060,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd060,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd061,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd061,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_CONTROL0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd062,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_CONTROL0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd062,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_CONTROL1_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd063,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_CONTROL1_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd063,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_CONTROL2_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd064,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_CONTROL2_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd064,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_CONTROL3_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd065,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_CONTROL3_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd065,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_STATUS0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd066,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_STATUS0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd066,wr_val) #define reg_rd_CL72_USER_TX_CL72UT_CONTROL4_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd067,__ERR) #define reg_wr_CL72_USER_TX_CL72UT_CONTROL4_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd067,wr_val) #define reg_rdc_DIG_COM_REVID0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f0,__ERR) #define reg_wrc_DIG_COM_REVID0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f0,wr_val) #define reg_rdc_DIG_COM_REVID1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0fa,__ERR) #define reg_wrc_DIG_COM_REVID1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0fa,wr_val) #define reg_rdc_DIG_COM_REVID2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0fe,__ERR) #define reg_wrc_DIG_COM_REVID2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0fe,wr_val) #define reg_rdc_DIG_COM_RESET_CONTROL_PMD() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f1,__ERR) #define reg_wrc_DIG_COM_RESET_CONTROL_PMD(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f1,wr_val) #define reg_rdc_DIG_COM_RESET_CONTROL_CORE_DP() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f2,__ERR) #define reg_wrc_DIG_COM_RESET_CONTROL_CORE_DP(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f2,wr_val) #define reg_rdc_DIG_COM_MASKDATA_REG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f3,__ERR) #define reg_wrc_DIG_COM_MASKDATA_REG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f3,wr_val) #define reg_rdc_DIG_COM_TOP_USER_CONTROL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f4,__ERR) #define reg_wrc_DIG_COM_TOP_USER_CONTROL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f4,wr_val) #define reg_rdc_DIG_COM_UC_ACK_CORE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f5,__ERR) #define reg_wrc_DIG_COM_UC_ACK_CORE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f5,wr_val) #define reg_rdc_DIG_COM_CORE_DP_RESET_STATE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f8,__ERR) #define reg_wrc_DIG_COM_CORE_DP_RESET_STATE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f8,wr_val) #define reg_rdc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f6,__ERR) #define reg_wrc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f6,wr_val) #define reg_rdc_DIG_COM_RST_SEQ_TIMER_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f7,__ERR) #define reg_wrc_DIG_COM_RST_SEQ_TIMER_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f7,wr_val) #define reg_rdc_DIG_COM_PMD_CORE_MODE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0f9,__ERR) #define reg_wrc_DIG_COM_PMD_CORE_MODE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0f9,wr_val) #define reg_rd_DSC_A_CDR_STATUS_INTEG_REG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd005,__ERR) #define reg_wr_DSC_A_CDR_STATUS_INTEG_REG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd005,wr_val) #define reg_rd_DSC_A_CDR_STATUS_PHASE_ERROR() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd006,__ERR) #define reg_wr_DSC_A_CDR_STATUS_PHASE_ERROR(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd006,wr_val) #define reg_rd_DSC_A_RX_PI_CNT_BIN_D() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd007,__ERR) #define reg_wr_DSC_A_RX_PI_CNT_BIN_D(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd007,wr_val) #define reg_rd_DSC_A_RX_PI_CNT_BIN_P() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd008,__ERR) #define reg_wr_DSC_A_RX_PI_CNT_BIN_P(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd008,wr_val) #define reg_rd_DSC_A_RX_PI_CNT_BIN_M() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd009,__ERR) #define reg_wr_DSC_A_RX_PI_CNT_BIN_M(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd009,wr_val) #define reg_rd_DSC_A_RX_PI_DIFF_BIN() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd00a,__ERR) #define reg_wr_DSC_A_RX_PI_DIFF_BIN(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd00a,wr_val) #define reg_rd_DSC_A_CDR_CONTROL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd001,__ERR) #define reg_wr_DSC_A_CDR_CONTROL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd001,wr_val) #define reg_rd_DSC_A_CDR_CONTROL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd002,__ERR) #define reg_wr_DSC_A_CDR_CONTROL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd002,wr_val) #define reg_rd_DSC_A_CDR_CONTROL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd003,__ERR) #define reg_wr_DSC_A_CDR_CONTROL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd003,wr_val) #define reg_rd_DSC_A_RX_PI_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd004,__ERR) #define reg_wr_DSC_A_RX_PI_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd004,wr_val) #define reg_rd_DSC_A_DSC_UC_CTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd00d,__ERR) #define reg_wr_DSC_A_DSC_UC_CTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd00d,wr_val) #define reg_rd_DSC_A_DSC_SCRATCH() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd00e,__ERR) #define reg_wr_DSC_A_DSC_SCRATCH(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd00e,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd010,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd010,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd011,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd011,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd012,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd012,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd013,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd013,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd014,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd014,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd015,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd015,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd016,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd016,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd017,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd017,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_8() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd018,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_8(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd018,wr_val) #define reg_rd_DSC_B_DSC_SM_CTRL_9() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd019,__ERR) #define reg_wr_DSC_B_DSC_SM_CTRL_9(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd019,wr_val) #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd01b,__ERR) #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd01b,wr_val) #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd01c,__ERR) #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd01c,wr_val) #define reg_rd_DSC_B_DSC_SM_STATUS_RESTART() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd01d,__ERR) #define reg_wr_DSC_B_DSC_SM_STATUS_RESTART(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd01d,wr_val) #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_STATE() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd01e,__ERR) #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_STATE(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd01e,wr_val) #define reg_rd_DSC_B_DSC_SM_STATUS_DSC_LOCK() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd01a,__ERR) #define reg_wr_DSC_B_DSC_SM_STATUS_DSC_LOCK(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd01a,wr_val) #define reg_rd_DSC_C_DFE_1_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd021,__ERR) #define reg_wr_DSC_C_DFE_1_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd021,wr_val) #define reg_rd_DSC_C_DFE_2_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd022,__ERR) #define reg_wr_DSC_C_DFE_2_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd022,wr_val) #define reg_rd_DSC_C_DFE_3_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd023,__ERR) #define reg_wr_DSC_C_DFE_3_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd023,wr_val) #define reg_rd_DSC_C_DFE_4_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd024,__ERR) #define reg_wr_DSC_C_DFE_4_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd024,wr_val) #define reg_rd_DSC_C_DFE_5_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd025,__ERR) #define reg_wr_DSC_C_DFE_5_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd025,wr_val) #define reg_rd_DSC_C_DFE_PAT_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd026,__ERR) #define reg_wr_DSC_C_DFE_PAT_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd026,wr_val) #define reg_rd_DSC_C_DFE_COMMON_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd020,__ERR) #define reg_wr_DSC_C_DFE_COMMON_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd020,wr_val) #define reg_rd_DSC_C_HWTUNE_OVR_OVERRIDE() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd02b,__ERR) #define reg_wr_DSC_C_HWTUNE_OVR_OVERRIDE(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd02b,wr_val) #define reg_rd_DSC_C_VGA_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd02c,__ERR) #define reg_wr_DSC_C_VGA_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd02c,wr_val) #define reg_rd_DSC_C_VGA_PAT_EYEDIAG_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd02d,__ERR) #define reg_wr_DSC_C_VGA_PAT_EYEDIAG_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd02d,wr_val) #define reg_rd_DSC_C_P1_FRAC_OFFS_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd02e,__ERR) #define reg_wr_DSC_C_P1_FRAC_OFFS_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd02e,wr_val) #define reg_rd_DSC_C_VGA_P1_MISC_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd027,__ERR) #define reg_wr_DSC_C_VGA_P1_MISC_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd027,wr_val) #define reg_rd_DSC_C_SLICER_OFFSET_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd02a,__ERR) #define reg_wr_DSC_C_SLICER_OFFSET_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd02a,wr_val) #define reg_rd_DSC_C_DC_SLICER_OFFSET_CTL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd029,__ERR) #define reg_wr_DSC_C_DC_SLICER_OFFSET_CTL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd029,wr_val) #define reg_rd_DSC_D_VGA_P1EYEDIAG_STS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd03a,__ERR) #define reg_wr_DSC_D_VGA_P1EYEDIAG_STS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd03a,wr_val) #define reg_rd_DSC_D_DFE_1_STS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd03b,__ERR) #define reg_wr_DSC_D_DFE_1_STS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd03b,wr_val) #define reg_rd_DSC_D_DFE_2_STS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd03c,__ERR) #define reg_wr_DSC_D_DFE_2_STS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd03c,wr_val) #define reg_rd_DSC_D_DFE_3_4_5_STS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd03d,__ERR) #define reg_wr_DSC_D_DFE_3_4_5_STS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd03d,wr_val) #define reg_rd_DSC_D_VGA_TAP_BIN() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd03e,__ERR) #define reg_wr_DSC_D_VGA_TAP_BIN(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd03e,wr_val) #define reg_rd_DSC_E_CTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd040,__ERR) #define reg_wr_DSC_E_CTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd040,wr_val) #define reg_rd_DSC_E_PF_CTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd041,__ERR) #define reg_wr_DSC_E_PF_CTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd041,wr_val) #define reg_rd_DSC_E_PF2_LOWP_CTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd042,__ERR) #define reg_wr_DSC_E_PF2_LOWP_CTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd042,wr_val) #define reg_rd_DSC_F_DATA_ODD_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd141,__ERR) #define reg_wr_DSC_F_DATA_ODD_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd141,wr_val) #define reg_rd_DSC_F_DATA_EVEN_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd142,__ERR) #define reg_wr_DSC_F_DATA_EVEN_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd142,wr_val) #define reg_rd_DSC_F_P1_ODD_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd143,__ERR) #define reg_wr_DSC_F_P1_ODD_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd143,wr_val) #define reg_rd_DSC_F_P1_EVEN_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd144,__ERR) #define reg_wr_DSC_F_P1_EVEN_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd144,wr_val) #define reg_rd_DSC_F_M1_ODD_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd145,__ERR) #define reg_wr_DSC_F_M1_ODD_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd145,wr_val) #define reg_rd_DSC_F_M1_EVEN_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd146,__ERR) #define reg_wr_DSC_F_M1_EVEN_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd146,wr_val) #define reg_rd_DSC_F_DC_OFFSET() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd147,__ERR) #define reg_wr_DSC_F_DC_OFFSET(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd147,wr_val) #define reg_rdc_MDIO_BLK_ADDR_BLK_ADDR() _merlin16_shortfin_pmd_rde_reg(sa__, 0xffdf,__ERR) #define reg_wrc_MDIO_BLK_ADDR_BLK_ADDR(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xffdf,wr_val) #define reg_rdc_MDIO_CL22_IEEE_ACC_CTRL() _merlin16_shortfin_pmd_rde_reg(sa__, 0x000d,__ERR) #define reg_wrc_MDIO_CL22_IEEE_ACC_CTRL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x000d,wr_val) #define reg_rdc_MDIO_CL22_IEEE_ACC_ADDR_DATA() _merlin16_shortfin_pmd_rde_reg(sa__, 0x000e,__ERR) #define reg_wrc_MDIO_CL22_IEEE_ACC_ADDR_DATA(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0x000e,wr_val) #define reg_rdc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR() _merlin16_shortfin_pmd_rde_reg(sa__, 0xffdc,__ERR) #define reg_wrc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xffdc,wr_val) #define reg_rdc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT() _merlin16_shortfin_pmd_rde_reg(sa__, 0xffdd,__ERR) #define reg_wrc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xffdd,wr_val) #define reg_rdc_MDIO_MMDSEL_AER_MDIO_AER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xffde,__ERR) #define reg_wrc_MDIO_MMDSEL_AER_MDIO_AER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xffde,wr_val) #define reg_rdc_MICRO_A_COM_CLOCK_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd200,__ERR) #define reg_wrc_MICRO_A_COM_CLOCK_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd200,wr_val) #define reg_rdc_MICRO_A_COM_RESET_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd201,__ERR) #define reg_wrc_MICRO_A_COM_RESET_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd201,wr_val) #define reg_rdc_MICRO_A_COM_AHB_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd202,__ERR) #define reg_wrc_MICRO_A_COM_AHB_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd202,wr_val) #define reg_rdc_MICRO_A_COM_AHB_STATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd203,__ERR) #define reg_wrc_MICRO_A_COM_AHB_STATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd203,wr_val) #define reg_rdc_MICRO_A_COM_AHB_WRADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd204,__ERR) #define reg_wrc_MICRO_A_COM_AHB_WRADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd204,wr_val) #define reg_rdc_MICRO_A_COM_AHB_WRADDR_MSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd205,__ERR) #define reg_wrc_MICRO_A_COM_AHB_WRADDR_MSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd205,wr_val) #define reg_rdc_MICRO_A_COM_AHB_WRDATA_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd206,__ERR) #define reg_wrc_MICRO_A_COM_AHB_WRDATA_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd206,wr_val) #define reg_rdc_MICRO_A_COM_AHB_WRDATA_MSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd207,__ERR) #define reg_wrc_MICRO_A_COM_AHB_WRDATA_MSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd207,wr_val) #define reg_rdc_MICRO_A_COM_AHB_RDADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd208,__ERR) #define reg_wrc_MICRO_A_COM_AHB_RDADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd208,wr_val) #define reg_rdc_MICRO_A_COM_AHB_RDADDR_MSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd209,__ERR) #define reg_wrc_MICRO_A_COM_AHB_RDADDR_MSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd209,wr_val) #define reg_rdc_MICRO_A_COM_AHB_RDDATA_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20a,__ERR) #define reg_wrc_MICRO_A_COM_AHB_RDDATA_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20a,wr_val) #define reg_rdc_MICRO_A_COM_AHB_RDDATA_MSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20b,__ERR) #define reg_wrc_MICRO_A_COM_AHB_RDDATA_MSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20b,wr_val) #define reg_rdc_MICRO_A_COM_PRAMIF_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20c,__ERR) #define reg_wrc_MICRO_A_COM_PRAMIF_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20c,wr_val) #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20d,__ERR) #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20d,wr_val) #define reg_rdc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd20e,__ERR) #define reg_wrc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd20e,wr_val) #define reg_rdc_MICRO_B_COM_PVT_STATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd210,__ERR) #define reg_wrc_MICRO_B_COM_PVT_STATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd210,wr_val) #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd211,__ERR) #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd211,wr_val) #define reg_rdc_MICRO_B_COM_RMI_TO_MICRO_MBOX1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd212,__ERR) #define reg_wrc_MICRO_B_COM_RMI_TO_MICRO_MBOX1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd212,wr_val) #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd213,__ERR) #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd213,wr_val) #define reg_rdc_MICRO_B_COM_MICRO_TO_RMI_MBOX1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd214,__ERR) #define reg_wrc_MICRO_B_COM_MICRO_TO_RMI_MBOX1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd214,wr_val) #define reg_rdc_MICRO_B_COM_RMI_MBOX_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd215,__ERR) #define reg_wrc_MICRO_B_COM_RMI_MBOX_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd215,wr_val) #define reg_rdc_MICRO_B_COM_RMI_AHB_CONTROL1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd216,__ERR) #define reg_wrc_MICRO_B_COM_RMI_AHB_CONTROL1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd216,wr_val) #define reg_rdc_MICRO_B_COM_RMI_AHB_STATUS1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd217,__ERR) #define reg_wrc_MICRO_B_COM_RMI_AHB_STATUS1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd217,wr_val) #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd218,__ERR) #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd218,wr_val) #define reg_rdc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd219,__ERR) #define reg_wrc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd219,wr_val) #define reg_rdc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd21a,__ERR) #define reg_wrc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd21a,wr_val) #define reg_rdc_MICRO_B_COM_RMI_PVT_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd21b,__ERR) #define reg_wrc_MICRO_B_COM_RMI_PVT_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd21b,wr_val) #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd220,__ERR) #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd220,wr_val) #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCCONTRO1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd221,__ERR) #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCCONTRO1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd221,wr_val) #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd222,__ERR) #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd222,wr_val) #define reg_rdc_MICRO_C_COM_CODE_RAM_ECCSTATUS1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd223,__ERR) #define reg_wrc_MICRO_C_COM_CODE_RAM_ECCSTATUS1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd223,wr_val) #define reg_rdc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd224,__ERR) #define reg_wrc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd224,wr_val) #define reg_rdc_MICRO_C_COM_RAM_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd225,__ERR) #define reg_wrc_MICRO_C_COM_RAM_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd225,wr_val) #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_STATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd227,__ERR) #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_STATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd227,wr_val) #define reg_rdc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd226,__ERR) #define reg_wrc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd226,wr_val) #define reg_rdc_MICRO_C_COM_RMI_PMI_IF_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd228,__ERR) #define reg_wrc_MICRO_C_COM_RMI_PMI_IF_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd228,wr_val) #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd229,__ERR) #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd229,wr_val) #define reg_rdc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd22a,__ERR) #define reg_wrc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd22a,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd100,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd100,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd101,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd101,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd102,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd102,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd103,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd103,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd104,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd104,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd105,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd105,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd106,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd106,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_7() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd107,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_7(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd107,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_8() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd108,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_8(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd108,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_9() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd109,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_9(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd109,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_10() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10a,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_10(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10a,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_11() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10b,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_11(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10b,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_12() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10c,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_12(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10c,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_13() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10d,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_13(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10d,wr_val) #define reg_rdc_PATT_GEN_COM_SEQ_14() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd10e,__ERR) #define reg_wrc_PATT_GEN_COM_SEQ_14(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd10e,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd120,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd120,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd121,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd121,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd122,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd122,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd123,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd123,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd124,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd124,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd125,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd125,wr_val) #define reg_rdc_PLL_CAL_COM_CTL_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd126,__ERR) #define reg_wrc_PLL_CAL_COM_CTL_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd126,wr_val) #define reg_rdc_PLL_CAL_COM_STS_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd128,__ERR) #define reg_wrc_PLL_CAL_COM_STS_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd128,wr_val) #define reg_rdc_PLL_CAL_COM_STS_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd129,__ERR) #define reg_wrc_PLL_CAL_COM_STS_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd129,wr_val) #define reg_rdc_PLL_CAL_COM_STS_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12a,__ERR) #define reg_wrc_PLL_CAL_COM_STS_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd12a,wr_val) #define reg_rdc_PLL_CAL_COM_STS_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12b,__ERR) #define reg_wrc_PLL_CAL_COM_STS_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd12b,wr_val) #define reg_rdc_PLL_CAL_COM_STS_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12c,__ERR) #define reg_wrc_PLL_CAL_COM_STS_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd12c,wr_val) #define reg_rdc_PLL_CAL_COM_STS_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12d,__ERR) #define reg_wrc_PLL_CAL_COM_STS_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd12d,wr_val) #define reg_rdc_PLL_CAL_COM_STS_6() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd12e,__ERR) #define reg_wrc_PLL_CAL_COM_STS_6(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd12e,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd161,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd161,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd167,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd167,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd164,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd164,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd162,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd162,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd163,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd163,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd168,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd168,wr_val) #define reg_rd_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd16c,__ERR) #define reg_wr_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd16c,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd180,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd180,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd181,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd181,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd18e,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd18e,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd183,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd183,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd185,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd185,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd189,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd189,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd186,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd186,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd18b,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd18b,wr_val) #define reg_rd_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd18c,__ERR) #define reg_wr_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd18c,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd080,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd080,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd081,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd081,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd08e,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd08e,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd083,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd083,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd085,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd085,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd089,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd089,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd086,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd086,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd08b,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd08b,wr_val) #define reg_rd_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd08c,__ERR) #define reg_wr_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd08c,wr_val) #define reg_rd_SIGDET_SDCTRL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0c0,__ERR) #define reg_wr_SIGDET_SDCTRL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0c0,wr_val) #define reg_rd_SIGDET_SDCTRL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0c1,__ERR) #define reg_wr_SIGDET_SDCTRL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0c1,wr_val) #define reg_rd_SIGDET_SDCTRL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0c2,__ERR) #define reg_wr_SIGDET_SDCTRL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0c2,wr_val) #define reg_rd_SIGDET_SDSTATUS_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0c8,__ERR) #define reg_wr_SIGDET_SDSTATUS_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0c8,wr_val) #define reg_rd_SIGDET_SDSTATUS_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0c9,__ERR) #define reg_wr_SIGDET_SDSTATUS_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0c9,wr_val) #define reg_rd_SIGDET_SDSTATUS_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0ca,__ERR) #define reg_wr_SIGDET_SDSTATUS_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0ca,wr_val) #define reg_rd_SIGDET_SDSTATUS_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0cb,__ERR) #define reg_wr_SIGDET_SDSTATUS_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0cb,wr_val) #define reg_rd_SIGDET_SDSTATUS_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0cc,__ERR) #define reg_wr_SIGDET_SDSTATUS_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0cc,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d1,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d1,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_CNT_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d0,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_CNT_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d0,wr_val) #define reg_rd_TLB_RX_DIG_LPBK_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d2,__ERR) #define reg_wr_TLB_RX_DIG_LPBK_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d2,wr_val) #define reg_rd_TLB_RX_RXMISC_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d3,__ERR) #define reg_wr_TLB_RX_RXMISC_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d3,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d4,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d4,wr_val) #define reg_rd_TLB_RX_DIG_LPBK_PD_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d8,__ERR) #define reg_wr_TLB_RX_DIG_LPBK_PD_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d8,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_LOCK_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d9,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_LOCK_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d9,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0da,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0da,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0db,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0db,wr_val) #define reg_rd_TLB_RX_PMD_RX_LOCK_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0dc,__ERR) #define reg_wr_TLB_RX_PMD_RX_LOCK_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0dc,wr_val) #define reg_rd_TLB_RX_DBG_PMD_RX_LOCK_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d6,__ERR) #define reg_wr_TLB_RX_DBG_PMD_RX_LOCK_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d6,wr_val) #define reg_rd_TLB_RX_UC_PMD_RX_LOCK_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d7,__ERR) #define reg_wr_TLB_RX_UC_PMD_RX_LOCK_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d7,wr_val) #define reg_rd_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0d5,__ERR) #define reg_wr_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0d5,wr_val) #define reg_rd_TLB_TX_PATT_GEN_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0e0,__ERR) #define reg_wr_TLB_TX_PATT_GEN_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0e0,wr_val) #define reg_rd_TLB_TX_PRBS_GEN_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0e1,__ERR) #define reg_wr_TLB_TX_PRBS_GEN_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0e1,wr_val) #define reg_rd_TLB_TX_RMT_LPBK_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0e2,__ERR) #define reg_wr_TLB_TX_RMT_LPBK_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0e2,wr_val) #define reg_rd_TLB_TX_TXMISC_CONFIG() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0e3,__ERR) #define reg_wr_TLB_TX_TXMISC_CONFIG(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0e3,wr_val) #define reg_rd_TLB_TX_RMT_LPBK_PD_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd0e8,__ERR) #define reg_wr_TLB_TX_RMT_LPBK_PD_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd0e8,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd171,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd171,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd177,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd177,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd174,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd174,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd172,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd172,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd173,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd173,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd17c,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd17c,wr_val) #define reg_rd_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd17d,__ERR) #define reg_wr_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd17d,wr_val) #define reg_rd_TX_FED_TXFIR_TAP_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd110,__ERR) #define reg_wr_TX_FED_TXFIR_TAP_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd110,wr_val) #define reg_rd_TX_FED_MISC_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd111,__ERR) #define reg_wr_TX_FED_MISC_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd111,wr_val) #define reg_rd_TX_FED_MISC_STATUS0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd112,__ERR) #define reg_wr_TX_FED_MISC_STATUS0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd112,wr_val) #define reg_rd_TX_FED_MICRO_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd113,__ERR) #define reg_wr_TX_FED_MICRO_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd113,wr_val) #define reg_rd_TX_FED_POST2_AFE_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd11b,__ERR) #define reg_wr_TX_FED_POST2_AFE_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd11b,wr_val) #define reg_rd_TX_FED_POST1_AFE_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd11c,__ERR) #define reg_wr_TX_FED_POST1_AFE_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd11c,wr_val) #define reg_rd_TX_FED_POST1PRE_AFE_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd11d,__ERR) #define reg_wr_TX_FED_POST1PRE_AFE_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd11d,wr_val) #define reg_rd_TX_FED_DC_LEVEL_AFE_CONTROL0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd11e,__ERR) #define reg_wr_TX_FED_DC_LEVEL_AFE_CONTROL0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd11e,wr_val) #define reg_rd_TX_PI_TXPICONTROL_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd070,__ERR) #define reg_wr_TX_PI_TXPICONTROL_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd070,wr_val) #define reg_rd_TX_PI_TXPICONTROL_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd071,__ERR) #define reg_wr_TX_PI_TXPICONTROL_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd071,wr_val) #define reg_rd_TX_PI_TXPICONTROL_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd072,__ERR) #define reg_wr_TX_PI_TXPICONTROL_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd072,wr_val) #define reg_rd_TX_PI_TXPICONTROL_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd073,__ERR) #define reg_wr_TX_PI_TXPICONTROL_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd073,wr_val) #define reg_rd_TX_PI_TXPICONTROL_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd074,__ERR) #define reg_wr_TX_PI_TXPICONTROL_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd074,wr_val) #define reg_rd_TX_PI_TXPICONTROL_5() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd075,__ERR) #define reg_wr_TX_PI_TXPICONTROL_5(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd075,wr_val) #define reg_rd_TX_PI_TXPISTATUS_0() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd078,__ERR) #define reg_wr_TX_PI_TXPISTATUS_0(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd078,wr_val) #define reg_rd_TX_PI_TXPISTATUS_1() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd079,__ERR) #define reg_wr_TX_PI_TXPISTATUS_1(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd079,wr_val) #define reg_rd_TX_PI_TXPISTATUS_2() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd07a,__ERR) #define reg_wr_TX_PI_TXPISTATUS_2(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd07a,wr_val) #define reg_rd_TX_PI_TXPISTATUS_3() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd07b,__ERR) #define reg_wr_TX_PI_TXPISTATUS_3(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd07b,wr_val) #define reg_rd_TX_PI_TXPISTATUS_4() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd07c,__ERR) #define reg_wr_TX_PI_TXPISTATUS_4(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd07c,wr_val) #define reg_rd_TX_PI_TX_FIFO_OVFB_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd07d,__ERR) #define reg_wr_TX_PI_TX_FIFO_OVFB_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd07d,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd190,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd190,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd191,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd191,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd19e,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd19e,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd193,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd193,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd195,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd195,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd199,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd199,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd196,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd196,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd19b,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd19b,wr_val) #define reg_rd_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd19c,__ERR) #define reg_wr_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd19c,wr_val) #define reg_rdc_TX_COM_CONTROL0_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd130,__ERR) #define reg_wrc_TX_COM_CONTROL0_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd130,wr_val) #define reg_rdc_TX_COM_CONTROL1_REGISTER() _merlin16_shortfin_pmd_rde_reg(sa__, 0xd131,__ERR) #define reg_wrc_TX_COM_CONTROL1_REGISTER(wr_val) merlin16_shortfin_pmd_wr_reg(sa__, 0xd131,wr_val) #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_lowzvdd(reg_value) extract_field((reg_value),15,15) #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_lowzgnd(reg_value) extract_field((reg_value),14,14) #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_cmult_ena(reg_value) extract_field((reg_value),13,13) #define ex_AMS_RX_RXCONTROL_0__ams_rx_term_cm_ena(reg_value) extract_field((reg_value),12,12) #define ex_AMS_RX_RXCONTROL_0__ams_rx_en_rxck_test(reg_value) extract_field((reg_value),11,10) #define ex_AMS_RX_RXCONTROL_0__ams_rx_en_rxck_testport(reg_value) extract_field((reg_value),9,9) #define ex_AMS_RX_RXCONTROL_0__ams_rx_spare_0_1(reg_value) extract_field((reg_value),8,7) #define ex_AMS_RX_RXCONTROL_0__ams_rx_input_cm_sel(reg_value) extract_field((reg_value),6,6) #define ex_AMS_RX_RXCONTROL_0__ams_rx_vga_cm_sel(reg_value) extract_field((reg_value),5,5) #define ex_AMS_RX_RXCONTROL_0__ams_rx_rcm_sum(reg_value) extract_field((reg_value),4,4) #define ex_AMS_RX_RXCONTROL_0__ams_rx_sigdet_bypass(reg_value) extract_field((reg_value),3,3) #define ex_AMS_RX_RXCONTROL_0__ams_rx_sigdet_pwrdn(reg_value) extract_field((reg_value),2,2) #define ex_AMS_RX_RXCONTROL_0__ams_rx_cm_sel(reg_value) extract_field((reg_value),1,1) #define ex_AMS_RX_RXCONTROL_0__ams_rx_sum_cm_sel(reg_value) extract_field((reg_value),0,0) #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_dfe_2(reg_value) extract_field((reg_value),13,11) #define ex_AMS_RX_RXCONTROL_1__ams_rx_spare_1_0(reg_value) extract_field((reg_value),10,8) #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_pi(reg_value) extract_field((reg_value),7,5) #define ex_AMS_RX_RXCONTROL_1__ams_rx_curr_ctle(reg_value) extract_field((reg_value),4,2) #define ex_AMS_RX_RXCONTROL_1__ams_rx_vga_en_hgain(reg_value) extract_field((reg_value),1,1) #define ex_AMS_RX_RXCONTROL_1__ams_rx_vga_out_idle(reg_value) extract_field((reg_value),0,0) #define ex_AMS_RX_RXCONTROL_2__ams_rx_spare_2_0(reg_value) extract_field((reg_value),15,14) #define ex_AMS_RX_RXCONTROL_2__ams_rx_en_dfe_tap_fb(reg_value) extract_field((reg_value),13,9) #define ex_AMS_RX_RXCONTROL_2__ams_rx_curr_vga(reg_value) extract_field((reg_value),8,6) #define ex_AMS_RX_RXCONTROL_2__ams_rx_spare_2_1(reg_value) extract_field((reg_value),5,3) #define ex_AMS_RX_RXCONTROL_2__ams_rx_curr_dfe_1(reg_value) extract_field((reg_value),2,0) #define ex_AMS_RX_RXCONTROL_3__ams_rx_ll_en(reg_value) extract_field((reg_value),14,14) #define ex_AMS_RX_RXCONTROL_3__ams_rx_seli1p25dfe(reg_value) extract_field((reg_value),13,13) #define ex_AMS_RX_RXCONTROL_3__ams_rx_i4deadzone(reg_value) extract_field((reg_value),12,12) #define ex_AMS_RX_RXCONTROL_3__ams_rx_curr_sigdet(reg_value) extract_field((reg_value),11,9) #define ex_AMS_RX_RXCONTROL_3__ams_rx_curr_vddr_afe(reg_value) extract_field((reg_value),8,6) #define ex_AMS_RX_RXCONTROL_3__ams_rx_os2x_mode_even_odd(reg_value) extract_field((reg_value),5,5) #define ex_AMS_RX_RXCONTROL_3__ams_rx_dfe_os2x_mode(reg_value) extract_field((reg_value),4,4) #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_20b_demux(reg_value) extract_field((reg_value),3,3) #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_clk16(reg_value) extract_field((reg_value),2,2) #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_clk33(reg_value) extract_field((reg_value),1,1) #define ex_AMS_RX_RXCONTROL_3__ams_rx_en_vcctrl(reg_value) extract_field((reg_value),0,0) #define ex_AMS_RX_RXCONTROL_4__ams_rx_vga_pon(reg_value) extract_field((reg_value),15,12) #define ex_AMS_RX_RXCONTROL_4__ams_rx_oc_2x(reg_value) extract_field((reg_value),11,11) #define ex_AMS_RX_RXCONTROL_4__ams_rx_spare_4_1(reg_value) extract_field((reg_value),10,10) #define ex_AMS_RX_RXCONTROL_4__ams_rx_i_rx_hi_z(reg_value) extract_field((reg_value),9,9) #define ex_AMS_RX_RXCONTROL_4__ams_rx_spare_4_0(reg_value) extract_field((reg_value),8,8) #define ex_AMS_RX_RXCONTROL_4__ams_rx_en_recclkdiv(reg_value) extract_field((reg_value),7,7) #define ex_AMS_RX_RXCONTROL_4__ams_rx_div3o4o5(reg_value) extract_field((reg_value),6,5) #define ex_AMS_RX_RXCONTROL_4__ams_rx_recclkdiv(reg_value) extract_field((reg_value),4,0) #define ex_AMS_RX_RXCONTROL_5__ams_rx_dcc2_phase_flip(reg_value) extract_field((reg_value),15,15) #define ex_AMS_RX_RXCONTROL_5__ams_rx_slcr_calib_range_sel(reg_value) extract_field((reg_value),14,14) #define ex_AMS_RX_RXCONTROL_5__ams_rx_pi_pd(reg_value) extract_field((reg_value),13,13) #define ex_AMS_RX_RXCONTROL_5__ams_rx_dcc1_phase_flip(reg_value) extract_field((reg_value),12,12) #define ex_AMS_RX_RXCONTROL_5__ams_rx_en_dfeclk(reg_value) extract_field((reg_value),11,11) #define ex_AMS_RX_RXCONTROL_5__ams_rx_ctle_gain_ctrl(reg_value) extract_field((reg_value),10,7) #define ex_AMS_RX_RXCONTROL_5__ams_rx_curr_in_offset(reg_value) extract_field((reg_value),6,4) #define ex_AMS_RX_RXCONTROL_5__ams_rx_pon(reg_value) extract_field((reg_value),3,0) #define ex_AMS_RX_RXCONTROL_6__ams_rx_sigdet_offset_correction_pos(reg_value) extract_field((reg_value),12,8) #define ex_AMS_RX_RXCONTROL_6__ams_rx_sigdet_calibration_select(reg_value) extract_field((reg_value),7,7) #define ex_AMS_RX_RXCONTROL_6__ams_rx_sum_gain_ctrl(reg_value) extract_field((reg_value),6,3) #define ex_AMS_RX_RXCONTROL_6__ams_rx_en_sigdet_calib(reg_value) extract_field((reg_value),2,2) #define ex_AMS_RX_RXCONTROL_6__ams_rx_hiz_1(reg_value) extract_field((reg_value),1,1) #define ex_AMS_RX_RXCONTROL_6__ams_rx_m1_sign(reg_value) extract_field((reg_value),0,0) #define ex_AMS_RX_RXCONTROL_7__ams_rx_spare_7_0(reg_value) extract_field((reg_value),13,10) #define ex_AMS_RX_RXCONTROL_7__ams_rx_sigdet_threshold(reg_value) extract_field((reg_value),9,5) #define ex_AMS_RX_RXCONTROL_7__ams_rx_sigdet_offset_correction_neg(reg_value) extract_field((reg_value),4,0) #define ex_AMS_RX_INTCTRL__ams_rx_rxpon_sel(reg_value) extract_field((reg_value),1,1) #define ex_AMS_RX_INTCTRL__ams_rx_vgapon_sel(reg_value) extract_field((reg_value),0,0) #define ex_AMS_RX_RXSTATUS__ams_rx_vgapon_mux(reg_value) extract_field((reg_value),7,4) #define ex_AMS_RX_RXSTATUS__ams_rx_rxpon_mux(reg_value) extract_field((reg_value),3,0) #define ex_AMS_TX_TXCONTROL_0__ams_tx_lowlatency_en(reg_value) extract_field((reg_value),15,15) #define ex_AMS_TX_TXCONTROL_0__ams_tx_fifo_resetb(reg_value) extract_field((reg_value),14,14) #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_fifo_ctrl(reg_value) extract_field((reg_value),13,11) #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_fifo_zero_out(reg_value) extract_field((reg_value),10,10) #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_polarity_flip(reg_value) extract_field((reg_value),9,9) #define ex_AMS_TX_TXCONTROL_0__ams_tx_ll_selpath_tx(reg_value) extract_field((reg_value),8,8) #define ex_AMS_TX_TXCONTROL_0__ams_tx_enable_os_2(reg_value) extract_field((reg_value),7,7) #define ex_AMS_TX_TXCONTROL_0__ams_tx_pon(reg_value) extract_field((reg_value),6,3) #define ex_AMS_TX_TXCONTROL_0__ams_tx_ticksel(reg_value) extract_field((reg_value),2,1) #define ex_AMS_TX_TXCONTROL_0__ams_tx_pwrdn(reg_value) extract_field((reg_value),0,0) #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_slow(reg_value) extract_field((reg_value),14,11) #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk33(reg_value) extract_field((reg_value),10,10) #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk20(reg_value) extract_field((reg_value),9,9) #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_wclk16(reg_value) extract_field((reg_value),8,8) #define ex_AMS_TX_TXCONTROL_1__ams_tx_testclk_ena(reg_value) extract_field((reg_value),7,7) #define ex_AMS_TX_TXCONTROL_1__ams_tx_testsel(reg_value) extract_field((reg_value),6,5) #define ex_AMS_TX_TXCONTROL_1__ams_tx_cntrl_rxdetect_en(reg_value) extract_field((reg_value),4,4) #define ex_AMS_TX_TXCONTROL_1__ams_tx_rxdtct_th_sel(reg_value) extract_field((reg_value),3,2) #define ex_AMS_TX_TXCONTROL_1__ams_tx_en_high_current(reg_value) extract_field((reg_value),1,1) #define ex_AMS_TX_TXCONTROL_1__ams_tx_enable_os_4(reg_value) extract_field((reg_value),0,0) #define ex_AMS_TX_TXCONTROL_2__ams_tx_fifo_phsdetect_mode(reg_value) extract_field((reg_value),14,14) #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_pibuf_cntl(reg_value) extract_field((reg_value),13,11) #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_pi_cntl(reg_value) extract_field((reg_value),10,8) #define ex_AMS_TX_TXCONTROL_2__ams_tx_ibias_opamp_cntl(reg_value) extract_field((reg_value),7,5) #define ex_AMS_TX_TXCONTROL_2__ams_tx_dcc_en(reg_value) extract_field((reg_value),4,4) #define ex_AMS_TX_TXCONTROL_2__ams_tx_en_hpf(reg_value) extract_field((reg_value),3,0) #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalm(reg_value) extract_field((reg_value),13,10) #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalp(reg_value) extract_field((reg_value),9,6) #define ex_AMS_TX_TXCONTROL_3__ams_tx_refcalshunt(reg_value) extract_field((reg_value),5,2) #define ex_AMS_TX_TXCONTROL_3__ams_tx_spare_3_0(reg_value) extract_field((reg_value),1,0) #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpost2_post2(reg_value) extract_field((reg_value),15,12) #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpost1_post1pre(reg_value) extract_field((reg_value),11,6) #define ex_AMS_TX_TXCONTROL_4__ams_tx_shntpre_post1pre(reg_value) extract_field((reg_value),5,0) #define ex_AMS_TX_TXCONTROL_5__ams_tx_post2to1(reg_value) extract_field((reg_value),13,13) #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_pre(reg_value) extract_field((reg_value),12,12) #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_post1(reg_value) extract_field((reg_value),11,11) #define ex_AMS_TX_TXCONTROL_5__ams_tx_en_post2(reg_value) extract_field((reg_value),10,10) #define ex_AMS_TX_TXCONTROL_5__ams_tx_shntmain_post2(reg_value) extract_field((reg_value),9,6) #define ex_AMS_TX_TXCONTROL_5__ams_tx_shntmain_post1pre(reg_value) extract_field((reg_value),5,0) #define ex_AMS_TX_TXCONTROL_6__ams_tx_shntpost1_post1(reg_value) extract_field((reg_value),15,11) #define ex_AMS_TX_TXCONTROL_6__ams_tx_dis_cal(reg_value) extract_field((reg_value),10,6) #define ex_AMS_TX_TXCONTROL_6__ams_tx_spare_6_0(reg_value) extract_field((reg_value),5,2) #define ex_AMS_TX_TXCONTROL_6__ams_tx_pd_phasedet(reg_value) extract_field((reg_value),1,1) #define ex_AMS_TX_TXCONTROL_6__ams_tx_en_shuntmode(reg_value) extract_field((reg_value),0,0) #define ex_AMS_TX_TXCONTROL_7__ams_tx_refcalpcs(reg_value) extract_field((reg_value),12,9) #define ex_AMS_TX_TXCONTROL_7__ams_tx_refcalmcs(reg_value) extract_field((reg_value),8,5) #define ex_AMS_TX_TXCONTROL_7__ams_tx_shntmain_post1(reg_value) extract_field((reg_value),4,0) #define ex_AMS_TX_TXCONTROL_8__ams_tx_spare_8_0(reg_value) extract_field((reg_value),8,1) #define ex_AMS_TX_TXCONTROL_8__ams_tx_shnten_main(reg_value) extract_field((reg_value),0,0) #define ex_AMS_TX_TXINTCTRL__ams_tx_sel_txmaster(reg_value) extract_field((reg_value),3,3) #define ex_AMS_TX_TXINTCTRL__ams_tx_auto_ll_selpath_tx_dis(reg_value) extract_field((reg_value),2,2) #define ex_AMS_TX_TXINTCTRL__ams_tx_txpon_sel(reg_value) extract_field((reg_value),1,1) #define ex_AMS_TX_TXSTATUS__ams_tx_rescal(reg_value) extract_field((reg_value),7,4) #define ex_AMS_TX_TXSTATUS__ams_tx_txpon_mux(reg_value) extract_field((reg_value),3,0) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_cpar(reg_value) extract_field((reg_value),15,14) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_term_cm_en(reg_value) extract_field((reg_value),13,13) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_1(reg_value) extract_field((reg_value),12,12) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_rpar(reg_value) extract_field((reg_value),11,9) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_lc_refclk_adj_1_0(reg_value) extract_field((reg_value),8,7) #define exc_AMS_COM_PLL_CTRL_0__ams_pll_spare_0_0(reg_value) extract_field((reg_value),6,0) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_hcur_vco(reg_value) extract_field((reg_value),15,15) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_10t(reg_value) extract_field((reg_value),14,14) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_enb_8t(reg_value) extract_field((reg_value),13,13) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_vco_range(reg_value) extract_field((reg_value),12,6) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_en_8p5g_vco(reg_value) extract_field((reg_value),5,5) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_spare_1_0(reg_value) extract_field((reg_value),4,4) #define exc_AMS_COM_PLL_CTRL_1__ams_pll_curr_sel(reg_value) extract_field((reg_value),3,0) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_i4iqbuf(reg_value) extract_field((reg_value),15,14) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vco_buf_pon(reg_value) extract_field((reg_value),13,10) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_clkvco_cal_invert(reg_value) extract_field((reg_value),9,9) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_cmos_refclk_ch_hiz(reg_value) extract_field((reg_value),8,8) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_calib_adj(reg_value) extract_field((reg_value),7,5) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_en_8p5g(reg_value) extract_field((reg_value),4,4) #define exc_AMS_COM_PLL_CTRL_2__ams_pll_vco_pon(reg_value) extract_field((reg_value),3,0) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_mmd_halfrate(reg_value) extract_field((reg_value),15,15) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_cp_bias(reg_value) extract_field((reg_value),14,12) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_spare3_1(reg_value) extract_field((reg_value),11,11) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cmos_hz(reg_value) extract_field((reg_value),10,10) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_ref_cml_pd(reg_value) extract_field((reg_value),9,9) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_clksel(reg_value) extract_field((reg_value),8,8) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_rclk_refout(reg_value) extract_field((reg_value),7,7) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cmos_refout_overwr(reg_value) extract_field((reg_value),6,6) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_cml_refout_overwr(reg_value) extract_field((reg_value),5,5) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_en_test_frac_clk(reg_value) extract_field((reg_value),4,4) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_enb_16t(reg_value) extract_field((reg_value),3,3) #define exc_AMS_COM_PLL_CTRL_3__ams_pll_band_iqbuf_ctr(reg_value) extract_field((reg_value),2,0) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_sel(reg_value) extract_field((reg_value),14,12) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_test_amp(reg_value) extract_field((reg_value),11,10) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_vco_test_clk_en(reg_value) extract_field((reg_value),9,9) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_en(reg_value) extract_field((reg_value),8,8) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_vco_hkvco(reg_value) extract_field((reg_value),7,7) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_bias_vdd_sel(reg_value) extract_field((reg_value),6,5) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_cmos_tport_en(reg_value) extract_field((reg_value),4,4) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_cp_opamp_bias(reg_value) extract_field((reg_value),3,2) #define exc_AMS_COM_PLL_CTRL_4__ams_pll_lc_refclk_adj_3_2(reg_value) extract_field((reg_value),1,0) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refdiv_test_sel(reg_value) extract_field((reg_value),12,10) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwdb_extr_d2c(reg_value) extract_field((reg_value),9,9) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_en_refout_div(reg_value) extract_field((reg_value),8,8) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_pwrdn(reg_value) extract_field((reg_value),7,7) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_term_sel(reg_value) extract_field((reg_value),6,5) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_sel_overwrite(reg_value) extract_field((reg_value),4,4) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_test_vc(reg_value) extract_field((reg_value),3,3) #define exc_AMS_COM_PLL_CTRL_5__ams_pll_refout_div_sel(reg_value) extract_field((reg_value),2,0) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_ndiv_frac_l(reg_value) extract_field((reg_value),15,12) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_pfd_offset(reg_value) extract_field((reg_value),11,10) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_spare6_1(reg_value) extract_field((reg_value),9,9) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_i_pfd_offset_enlarge(reg_value) extract_field((reg_value),8,8) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_i_boost(reg_value) extract_field((reg_value),7,6) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_vco_gm_boost(reg_value) extract_field((reg_value),5,4) #define exc_AMS_COM_PLL_CTRL_6__ams_pll_pon(reg_value) extract_field((reg_value),3,0) #define exc_AMS_COM_PLL_CTRL_7__ams_pll_i_ndiv_frac_h(reg_value) extract_field((reg_value),13,0) #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_dither_en(reg_value) extract_field((reg_value),15,15) #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_pll_sdm_pwrdnb(reg_value) extract_field((reg_value),14,14) #define exc_AMS_COM_PLL_CTRL_8__ams_pll_vcofb_div(reg_value) extract_field((reg_value),13,12) #define exc_AMS_COM_PLL_CTRL_8__ams_pll_cml_refclk_bias(reg_value) extract_field((reg_value),11,10) #define exc_AMS_COM_PLL_CTRL_8__ams_pll_i_ndiv_int(reg_value) extract_field((reg_value),9,0) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_cml_refclk_adj(reg_value) extract_field((reg_value),15,14) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_iq_ctrl(reg_value) extract_field((reg_value),13,11) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_bias_div_ctrl(reg_value) extract_field((reg_value),10,8) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_vco_supply_adj(reg_value) extract_field((reg_value),7,7) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_sel_fp3cap(reg_value) extract_field((reg_value),6,3) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_i_pll_frac_mode(reg_value) extract_field((reg_value),2,1) #define exc_AMS_COM_PLL_CTRL_9__ams_pll_mmd_resetb(reg_value) extract_field((reg_value),0,0) #define exc_AMS_COM_PLL_CTRL_10__ams_pll_refclk_in_bias(reg_value) extract_field((reg_value),5,0) #define exc_AMS_COM_PLL_INT__ams_pll_refclk_term_frc(reg_value) extract_field((reg_value),3,3) #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div_frc(reg_value) extract_field((reg_value),2,2) #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div2_frc_val(reg_value) extract_field((reg_value),1,1) #define exc_AMS_COM_PLL_INT__ams_pll_refclk_div4_frc_val(reg_value) extract_field((reg_value),0,0) #define exc_AMS_COM_PLL_STS__ams_pll_afe_rev_id(reg_value) extract_field((reg_value),3,0) #define ex_CL72_IEEE_RX_CL72IR_BASE_R_LP_COEFF_UPDATE_REGISTER_152__cl72_ieee_lp_coeff_update(reg_value) extract_field((reg_value),15,0) #define ex_CL72_IEEE_RX_CL72IR_BASE_R_LP_STATUS_REPORT_REGISTER_153__cl72_ieee_lp_status_report(reg_value) extract_field((reg_value),15,0) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150__cl72_ieee_training_enable(reg_value) extract_field((reg_value),1,1) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_CONTROL_REGISTER_150__cl72_ieee_restart_training(reg_value) extract_field((reg_value),0,0) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_training_failure(reg_value) extract_field((reg_value),3,3) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_training_status(reg_value) extract_field((reg_value),2,2) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_frame_lock(reg_value) extract_field((reg_value),1,1) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_PMD_STATUS_REGISTER_151__cl72_ieee_receiver_status(reg_value) extract_field((reg_value),0,0) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_LD_COEFF_UPDATE_REGISTER_154__cl72_ieee_ld_coeff_update(reg_value) extract_field((reg_value),15,0) #define ex_CL72_IEEE_TX_CL72IT_BASE_R_LD_STATUS_REPORT_REGISTER_155__cl72_ieee_ld_status_report(reg_value) extract_field((reg_value),15,0) #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_rx_signal_ok(reg_value) extract_field((reg_value),2,2) #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_tr_coarse_lock(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_RX_CL72UR_CONTROL0_REGISTER__cl72_rx_training_en(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_RX_CL72UR_CONTROL1_REGISTER__cl72_bad_marker_cnt(reg_value) extract_field((reg_value),6,4) #define ex_CL72_USER_RX_CL72UR_CONTROL1_REGISTER__cl72_good_marker_cnt(reg_value) extract_field((reg_value),1,0) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_frame_consistency_chk_en(reg_value) extract_field((reg_value),9,9) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_rx_dp_ln_clk_en(reg_value) extract_field((reg_value),8,8) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_ppm_offset_en(reg_value) extract_field((reg_value),7,7) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_strict_marker_chk(reg_value) extract_field((reg_value),6,6) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_strict_dme_chk(reg_value) extract_field((reg_value),5,5) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_dme_cell_boundary_chk(reg_value) extract_field((reg_value),4,4) #define ex_CL72_USER_RX_CL72UR_CONTROL2_REGISTER__cl72_ctrl_frame_dly(reg_value) extract_field((reg_value),3,0) #define ex_CL72_USER_RX_CL72UR_STATUS0_REGISTER__cl72_remote_rx_ready(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_RX_CL72UR_STATUS0_REGISTER__cl72_frame_lock(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_resp_int_frc_val(reg_value) extract_field((reg_value),11,11) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_resp_int_frc(reg_value) extract_field((reg_value),10,10) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_req_int_frc_val(reg_value) extract_field((reg_value),9,9) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_req_int_frc(reg_value) extract_field((reg_value),8,8) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_frame_lock_int_en(reg_value) extract_field((reg_value),2,2) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_status_chg_int_en(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_RX_CL72UR_MICRO_INTERRUPT_CONTROL0_REGISTER__cl72_micro_update_chg_int_en(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS0_REGISTER__cl72_micro_update_chg_lstatus(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER__cl72_micro_frame_lock_lstatus(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_RX_CL72UR_MICRO_STATUS1_REGISTER__cl72_micro_status_chg_lstatus(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_TX_CL72UT_XMT_UPDATE_PAGE_REGISTER__cl72_xmt_update_page(reg_value) extract_field((reg_value),15,0) #define ex_CL72_USER_TX_CL72UT_LD_XMT_STATUS_PAGE__cl72_ld_xmt_status_page(reg_value) extract_field((reg_value),15,0) #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_remote_rx_ready(reg_value) extract_field((reg_value),2,2) #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_rx_trained(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_TX_CL72UT_CONTROL0_REGISTER__cl72_sw_frame_lock(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_tx_dp_ln_clk_en(reg_value) extract_field((reg_value),2,2) #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_dis_max_wait_timer(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_TX_CL72UT_CONTROL1_REGISTER__cl72_brk_ring_osc(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_TX_CL72UT_CONTROL2_REGISTER__cl72_txfir_post(reg_value) extract_field((reg_value),12,8) #define ex_CL72_USER_TX_CL72UT_CONTROL2_REGISTER__cl72_txfir_pre(reg_value) extract_field((reg_value),3,0) #define ex_CL72_USER_TX_CL72UT_CONTROL3_REGISTER__cl72_txfir_main(reg_value) extract_field((reg_value),5,0) #define ex_CL72_USER_TX_CL72UT_STATUS0_REGISTER__cl72_training_fsm_signal_detect(reg_value) extract_field((reg_value),1,1) #define ex_CL72_USER_TX_CL72UT_STATUS0_REGISTER__cl72_local_rx_ready(reg_value) extract_field((reg_value),0,0) #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_seed_sel(reg_value) extract_field((reg_value),15,14) #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_mode_sel(reg_value) extract_field((reg_value),13,13) #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_cl93prbs_poly_sel(reg_value) extract_field((reg_value),12,11) #define ex_CL72_USER_TX_CL72UT_CONTROL4_REGISTER__cl72_prbs_seed_val(reg_value) extract_field((reg_value),10,0) #define exc_DIG_COM_REVID0__revid_rev_letter(reg_value) extract_field((reg_value),15,14) #define exc_DIG_COM_REVID0__revid_rev_number(reg_value) extract_field((reg_value),13,11) #define exc_DIG_COM_REVID0__revid_bonding(reg_value) extract_field((reg_value),10,9) #define exc_DIG_COM_REVID0__revid_process(reg_value) extract_field((reg_value),8,6) #define exc_DIG_COM_REVID0__revid_model(reg_value) extract_field((reg_value),5,0) #define exc_DIG_COM_REVID1__revid_multiplicity(reg_value) extract_field((reg_value),15,12) #define exc_DIG_COM_REVID1__revid_mdio(reg_value) extract_field((reg_value),5,5) #define exc_DIG_COM_REVID1__revid_micro(reg_value) extract_field((reg_value),4,4) #define exc_DIG_COM_REVID1__revid_cl72(reg_value) extract_field((reg_value),3,3) #define exc_DIG_COM_REVID1__revid_pir(reg_value) extract_field((reg_value),2,2) #define exc_DIG_COM_REVID1__revid_llp(reg_value) extract_field((reg_value),1,1) #define exc_DIG_COM_REVID1__revid_eee(reg_value) extract_field((reg_value),0,0) #define exc_DIG_COM_REVID2__revid2(reg_value) extract_field((reg_value),3,0) #define exc_DIG_COM_RESET_CONTROL_PMD__core_s_rstb(reg_value) extract_field((reg_value),0,0) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__disable_ack_timeout(reg_value) extract_field((reg_value),15,15) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc_val(reg_value) extract_field((reg_value),10,10) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_vcoclk16_vld_frc(reg_value) extract_field((reg_value),9,9) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_frc_on(reg_value) extract_field((reg_value),8,8) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__vcoclk16_s_comclk_sel(reg_value) extract_field((reg_value),7,7) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_mdio_trans_pkill(reg_value) extract_field((reg_value),5,5) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc(reg_value) extract_field((reg_value),4,4) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__sup_rst_seq_frc_val(reg_value) extract_field((reg_value),3,3) #define exc_DIG_COM_RESET_CONTROL_CORE_DP__pmd_core_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) #define exc_DIG_COM_MASKDATA_REG__maskdata(reg_value) extract_field((reg_value),15,0) #define exc_DIG_COM_TOP_USER_CONTROL_0__uc_active(reg_value) extract_field((reg_value),15,15) #define exc_DIG_COM_TOP_USER_CONTROL_0__afe_s_pll_pwrdn(reg_value) extract_field((reg_value),14,14) #define exc_DIG_COM_TOP_USER_CONTROL_0__core_dp_s_rstb(reg_value) extract_field((reg_value),13,13) #define exc_DIG_COM_TOP_USER_CONTROL_0__maskdata_bus_assign(reg_value) extract_field((reg_value),11,10) #define exc_DIG_COM_TOP_USER_CONTROL_0__heartbeat_count_1us(reg_value) extract_field((reg_value),9,0) #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_dp_reset(reg_value) extract_field((reg_value),1,1) #define exc_DIG_COM_UC_ACK_CORE_CONTROL__uc_ack_core_cfg_done(reg_value) extract_field((reg_value),0,0) #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released(reg_value) extract_field((reg_value),14,14) #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__lane_reset_released_index(reg_value) extract_field((reg_value),12,8) #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released(reg_value) extract_field((reg_value),15,15) #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__tx_lane_reset_released_index(reg_value) extract_field((reg_value),7,3) #define exc_DIG_COM_CORE_DP_RESET_STATE_STATUS__core_dp_reset_state(reg_value) extract_field((reg_value),2,0) #define exc_DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL__core_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_dis_flt_mode(reg_value) extract_field((reg_value),15,14) #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__pwrdn_seq_timer(reg_value) extract_field((reg_value),11,9) #define exc_DIG_COM_RST_SEQ_TIMER_CONTROL__rst_seq_timer(reg_value) extract_field((reg_value),2,0) #define exc_DIG_COM_PMD_CORE_MODE_STATUS__pmd_core_mode(reg_value) extract_field((reg_value),15,0) #define ex_DSC_A_CDR_STATUS_INTEG_REG__cdr_integ_reg(reg_value) extract_field_signed((reg_value),15,0) #define ex_DSC_A_CDR_STATUS_PHASE_ERROR__cdr_lm_outoflock(reg_value) extract_field((reg_value),8,8) #define ex_DSC_A_CDR_STATUS_PHASE_ERROR__cdr_phase_err(reg_value) extract_field_signed((reg_value),4,0) #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_p1_dreg(reg_value) extract_field((reg_value),14,8) #define ex_DSC_A_RX_PI_CNT_BIN_D__cnt_bin_d_dreg(reg_value) extract_field((reg_value),6,0) #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_m1_preg(reg_value) extract_field((reg_value),14,8) #define ex_DSC_A_RX_PI_CNT_BIN_P__cnt_bin_p1_preg(reg_value) extract_field((reg_value),6,0) #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_d_mreg(reg_value) extract_field((reg_value),14,8) #define ex_DSC_A_RX_PI_CNT_BIN_M__cnt_bin_m1_mreg(reg_value) extract_field((reg_value),6,0) #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_p1(reg_value) extract_field_signed((reg_value),15,8) #define ex_DSC_A_RX_PI_DIFF_BIN__cnt_d_minus_m1(reg_value) extract_field_signed((reg_value),7,0) #define ex_DSC_A_CDR_CONTROL_0__cdr_lm_thr_sel(reg_value) extract_field((reg_value),10,8) #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_override_en(reg_value) extract_field((reg_value),7,7) #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_sat_sel(reg_value) extract_field((reg_value),6,6) #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_err_frz(reg_value) extract_field((reg_value),5,5) #define ex_DSC_A_CDR_CONTROL_0__cdr_integ_reg_clr(reg_value) extract_field((reg_value),4,4) #define ex_DSC_A_CDR_CONTROL_0__cdr_freq_en(reg_value) extract_field((reg_value),2,2) #define ex_DSC_A_CDR_CONTROL_0__br_pd_en(reg_value) extract_field((reg_value),1,1) #define ex_DSC_A_CDR_CONTROL_0__cdr_phase_sat_ctrl(reg_value) extract_field((reg_value),0,0) #define ex_DSC_A_CDR_CONTROL_1__cdr_freq_override_val(reg_value) extract_field_signed((reg_value),15,1) #define ex_DSC_A_CDR_CONTROL_1__dfe_vga_unfreeze(reg_value) extract_field((reg_value),0,0) #define ex_DSC_A_CDR_CONTROL_2__osx2p_pherr_gain(reg_value) extract_field((reg_value),9,8) #define ex_DSC_A_CDR_CONTROL_2__pattern_sel(reg_value) extract_field((reg_value),7,4) #define ex_DSC_A_CDR_CONTROL_2__phase_err_offset_mult_2(reg_value) extract_field((reg_value),1,1) #define ex_DSC_A_CDR_CONTROL_2__cdr_zero_polarity(reg_value) extract_field((reg_value),0,0) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_reset(reg_value) extract_field((reg_value),15,15) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_slicers_en(reg_value) extract_field((reg_value),14,12) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_mode(reg_value) extract_field((reg_value),11,11) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_dir(reg_value) extract_field((reg_value),10,10) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_manual_strobe(reg_value) extract_field((reg_value),9,9) #define ex_DSC_A_RX_PI_CONTROL__rx_pi_phase_step_cnt(reg_value) extract_field((reg_value),6,0) #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_supp_info(reg_value) extract_field((reg_value),15,8) #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_ready_for_cmd(reg_value) extract_field((reg_value),7,7) #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_error_found(reg_value) extract_field((reg_value),6,6) #define ex_DSC_A_DSC_UC_CTRL__uc_dsc_gp_uc_req(reg_value) extract_field((reg_value),5,0) #define ex_DSC_A_DSC_SCRATCH__uc_dsc_data(reg_value) extract_field((reg_value),15,0) #define ex_DSC_B_DSC_SM_CTRL_0__eee_mode_en(reg_value) extract_field((reg_value),1,1) #define ex_DSC_B_DSC_SM_CTRL_0__eee_quiet_rx_afe_pwrdwn_val(reg_value) extract_field((reg_value),2,2) #define ex_DSC_B_DSC_SM_CTRL_0__ignore_rx_mode(reg_value) extract_field((reg_value),3,3) #define ex_DSC_B_DSC_SM_CTRL_0__cl72_timer_en(reg_value) extract_field((reg_value),4,4) #define ex_DSC_B_DSC_SM_CTRL_0__uc_tune_en(reg_value) extract_field((reg_value),5,5) #define ex_DSC_B_DSC_SM_CTRL_0__hw_tune_en(reg_value) extract_field((reg_value),6,6) #define ex_DSC_B_DSC_SM_CTRL_0__uc_trnsum_en(reg_value) extract_field((reg_value),7,7) #define ex_DSC_B_DSC_SM_CTRL_0__eee_measure_en(reg_value) extract_field((reg_value),8,8) #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_done_clear(reg_value) extract_field((reg_value),9,9) #define ex_DSC_B_DSC_SM_CTRL_0__slicer_cal_bypass(reg_value) extract_field((reg_value),10,10) #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_eee_done(reg_value) extract_field((reg_value),11,11) #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_restart(reg_value) extract_field((reg_value),13,13) #define ex_DSC_B_DSC_SM_CTRL_0__uc_ack_dsc_config(reg_value) extract_field((reg_value),14,14) #define ex_DSC_B_DSC_SM_CTRL_0__set_meas_incomplete(reg_value) extract_field((reg_value),15,15) #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc(reg_value) extract_field((reg_value),0,0) #define ex_DSC_B_DSC_SM_CTRL_1__rx_dsc_lock_frc_val(reg_value) extract_field((reg_value),1,1) #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc(reg_value) extract_field((reg_value),2,2) #define ex_DSC_B_DSC_SM_CTRL_1__dsc_clr_frc_val(reg_value) extract_field((reg_value),3,3) #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc(reg_value) extract_field((reg_value),4,4) #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_frz_frc_val(reg_value) extract_field((reg_value),5,5) #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc(reg_value) extract_field((reg_value),6,6) #define ex_DSC_B_DSC_SM_CTRL_1__timer_done_frc_val(reg_value) extract_field((reg_value),7,7) #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc(reg_value) extract_field((reg_value),8,8) #define ex_DSC_B_DSC_SM_CTRL_1__freq_upd_en_frc_val(reg_value) extract_field((reg_value),9,9) #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc(reg_value) extract_field((reg_value),10,10) #define ex_DSC_B_DSC_SM_CTRL_1__cdr_frz_frc_val(reg_value) extract_field((reg_value),11,11) #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc(reg_value) extract_field((reg_value),12,12) #define ex_DSC_B_DSC_SM_CTRL_1__trnsum_clr_frc_val(reg_value) extract_field((reg_value),13,13) #define ex_DSC_B_DSC_SM_CTRL_2__eee_lfsr_cnt(reg_value) extract_field((reg_value),12,0) #define ex_DSC_B_DSC_SM_CTRL_3__measure_lfsr_cnt(reg_value) extract_field((reg_value),12,0) #define ex_DSC_B_DSC_SM_CTRL_4__acq_cdr_timeout(reg_value) extract_field((reg_value),4,0) #define ex_DSC_B_DSC_SM_CTRL_4__cdr_settle_timeout(reg_value) extract_field((reg_value),9,5) #define ex_DSC_B_DSC_SM_CTRL_4__hw_tune_timeout(reg_value) extract_field((reg_value),14,10) #define ex_DSC_B_DSC_SM_CTRL_5__measure_timeout(reg_value) extract_field((reg_value),4,0) #define ex_DSC_B_DSC_SM_CTRL_5__eee_acq_cdr_timeout(reg_value) extract_field((reg_value),9,5) #define ex_DSC_B_DSC_SM_CTRL_5__eee_cdr_settle_timeout(reg_value) extract_field((reg_value),14,10) #define ex_DSC_B_DSC_SM_CTRL_6__eee_hw_tune_timeout(reg_value) extract_field((reg_value),4,0) #define ex_DSC_B_DSC_SM_CTRL_6__eee_ana_pwr_timeout(reg_value) extract_field((reg_value),14,10) #define ex_DSC_B_DSC_SM_CTRL_6__slicer_cal_timeout(reg_value) extract_field((reg_value),9,5) #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_acqcdr(reg_value) extract_field((reg_value),3,0) #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_eee_acqcdr(reg_value) extract_field((reg_value),7,4) #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_integ_norm(reg_value) extract_field((reg_value),11,8) #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_acqcdr(reg_value) extract_field((reg_value),13,12) #define ex_DSC_B_DSC_SM_CTRL_7__cdr_bwsel_prop_norm(reg_value) extract_field((reg_value),15,14) #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset(reg_value) extract_field_signed((reg_value),3,0) #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset(reg_value) extract_field_signed((reg_value),7,4) #define ex_DSC_B_DSC_SM_CTRL_8__phase_err_offset_en(reg_value) extract_field((reg_value),9,8) #define ex_DSC_B_DSC_SM_CTRL_8__eee_phase_err_offset_en(reg_value) extract_field((reg_value),11,10) #define ex_DSC_B_DSC_SM_CTRL_8__cdr_bwsel_prop_eee_acqcdr(reg_value) extract_field((reg_value),15,14) #define ex_DSC_B_DSC_SM_CTRL_9__dcoff_cal_timeout(reg_value) extract_field((reg_value),14,10) #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd(reg_value) extract_field((reg_value),0,0) #define ex_DSC_B_DSC_SM_CTRL_9__rx_restart_pmd_hold(reg_value) extract_field((reg_value),1,1) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_ONE_HOT__dsc_state_one_hot(reg_value) extract_field((reg_value),11,0) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE_EEE_ONE_HOT__dsc_state_eee_one_hot(reg_value) extract_field((reg_value),6,0) #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pi_ext_mode(reg_value) extract_field((reg_value),0,0) #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_sigdet(reg_value) extract_field((reg_value),1,1) #define ex_DSC_B_DSC_SM_STATUS_RESTART__restart_pmd_restart(reg_value) extract_field((reg_value),2,2) #define ex_DSC_B_DSC_SM_STATUS_RESTART__eee_quiet_from_eee_states(reg_value) extract_field((reg_value),3,3) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_state(reg_value) extract_field((reg_value),15,11) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_ready_for_cmd(reg_value) extract_field((reg_value),7,7) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_scratch(reg_value) extract_field((reg_value),10,8) #define ex_DSC_B_DSC_SM_STATUS_DSC_STATE__dsc_sm_gp_uc_req(reg_value) extract_field((reg_value),5,0) #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__eee_measure_cnt(reg_value) extract_field((reg_value),15,7) #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__slicer_cal_done(reg_value) extract_field((reg_value),2,2) #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__meas_incomplete(reg_value) extract_field((reg_value),1,1) #define ex_DSC_B_DSC_SM_STATUS_DSC_LOCK__rx_dsc_lock(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_1_CTL__dfe_1_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_1_CTL__dfe_1_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_DFE_1_CTL__dfe_1_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_DFE_1_CTL__dfe_1_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_DFE_1_CTL__dfe_1_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_DFE_1_CTL__dfe_1_cmn_only(reg_value) extract_field((reg_value),1,1) #define ex_DSC_C_DFE_1_CTL__dfe_1_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_2_CTL__dfe_2_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_2_CTL__dfe_2_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_DFE_2_CTL__dfe_2_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_DFE_2_CTL__dfe_2_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_DFE_2_CTL__dfe_2_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_DFE_2_CTL__dfe_2_cmn_only(reg_value) extract_field((reg_value),1,1) #define ex_DSC_C_DFE_2_CTL__dfe_2_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_3_CTL__dfe_3_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_3_CTL__dfe_3_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_DFE_3_CTL__dfe_3_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_DFE_3_CTL__dfe_3_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_DFE_3_CTL__dfe_3_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_DFE_3_CTL__dfe_3_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_4_CTL__dfe_4_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_4_CTL__dfe_4_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_DFE_4_CTL__dfe_4_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_DFE_4_CTL__dfe_4_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_DFE_4_CTL__dfe_4_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_DFE_4_CTL__dfe_4_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_5_CTL__dfe_5_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_5_CTL__dfe_5_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_DFE_5_CTL__dfe_5_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_DFE_5_CTL__dfe_5_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_DFE_5_CTL__dfe_5_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_DFE_5_CTL__dfe_5_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern_bit_en(reg_value) extract_field((reg_value),13,8) #define ex_DSC_C_DFE_PAT_CTL__dfe_pattern(reg_value) extract_field((reg_value),5,0) #define ex_DSC_C_DFE_COMMON_CTL__dfe_acc_hys_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_DFE_COMMON_CTL__dfe_allow_simult(reg_value) extract_field((reg_value),14,14) #define ex_DSC_C_DFE_COMMON_CTL__dfe_update_gain(reg_value) extract_field((reg_value),13,13) #define ex_DSC_C_DFE_COMMON_CTL__dfe_eye_closure_err_sel(reg_value) extract_field((reg_value),7,6) #define ex_DSC_C_DFE_COMMON_CTL__dfe_hw_eye_closure_en(reg_value) extract_field((reg_value),5,5) #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_upd_dur(reg_value) extract_field((reg_value),4,1) #define ex_DSC_C_DFE_COMMON_CTL__dfe_leaky_lms_en(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_sel(reg_value) extract_field((reg_value),13,9) #define ex_DSC_C_HWTUNE_OVR_OVERRIDE__hwtune_ovr_write_val(reg_value) extract_field((reg_value),8,0) #define ex_DSC_C_VGA_CTL__vga_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_VGA_CTL__vga_err_sel(reg_value) extract_field((reg_value),14,13) #define ex_DSC_C_VGA_CTL__vga_p1_gradient_invert(reg_value) extract_field((reg_value),12,12) #define ex_DSC_C_VGA_CTL__vga_err_gain(reg_value) extract_field((reg_value),11,10) #define ex_DSC_C_VGA_CTL__vga_inv_m1(reg_value) extract_field((reg_value),9,9) #define ex_DSC_C_VGA_CTL__vga_inv_p1(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_VGA_CTL__vga_update_gain(reg_value) extract_field((reg_value),7,6) #define ex_DSC_C_VGA_CTL__vga_affected_by_dfe1(reg_value) extract_field((reg_value),4,4) #define ex_DSC_C_VGA_CTL__vga_update_style(reg_value) extract_field((reg_value),3,2) #define ex_DSC_C_VGA_CTL__vga_acc_hys_en(reg_value) extract_field((reg_value),1,1) #define ex_DSC_C_VGA_CTL__vga_p1_acc_clr(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__p1_eyediag_en(reg_value) extract_field((reg_value),15,15) #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern_bit_en(reg_value) extract_field((reg_value),7,4) #define ex_DSC_C_VGA_PAT_EYEDIAG_CTL__vga_pattern(reg_value) extract_field((reg_value),3,0) #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_hwtune_max(reg_value) extract_field_signed((reg_value),15,10) #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_off_3levelq_en(reg_value) extract_field((reg_value),8,8) #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset_en(reg_value) extract_field((reg_value),7,7) #define ex_DSC_C_P1_FRAC_OFFS_CTL__p1_offset(reg_value) extract_field_signed((reg_value),6,0) #define ex_DSC_C_VGA_P1_MISC_CONTROL__p1_hwtune_min(reg_value) extract_field_signed((reg_value),15,10) #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_norm(reg_value) extract_field((reg_value),7,7) #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_op_short_offcal(reg_value) extract_field((reg_value),6,6) #define ex_DSC_C_VGA_P1_MISC_CONTROL__vga_hwtune_min(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_grad_inv(reg_value) extract_field((reg_value),7,7) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_p1(reg_value) extract_field((reg_value),6,6) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_m1(reg_value) extract_field((reg_value),5,5) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_inv_data(reg_value) extract_field((reg_value),4,4) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_err_gain(reg_value) extract_field((reg_value),3,2) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_hys_en(reg_value) extract_field((reg_value),1,1) #define ex_DSC_C_SLICER_OFFSET_CONTROL__hw_slicer_offset_en(reg_value) extract_field((reg_value),0,0) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_bit_en(reg_value) extract_field((reg_value),15,12) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern(reg_value) extract_field((reg_value),11,8) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_grad_inv(reg_value) extract_field((reg_value),6,6) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_pattern_inv_en(reg_value) extract_field((reg_value),5,5) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_inv(reg_value) extract_field((reg_value),4,4) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_err_gain(reg_value) extract_field((reg_value),3,2) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__hw_dc_offset_hys_en(reg_value) extract_field((reg_value),1,1) #define ex_DSC_C_DC_SLICER_OFFSET_CTL__dc_offset_en(reg_value) extract_field((reg_value),0,0) #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_high(reg_value) extract_field((reg_value),15,15) #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_wants_to_go_low(reg_value) extract_field((reg_value),14,14) #define ex_DSC_D_VGA_P1EYEDIAG_STS__p1_eyediag_bin(reg_value) extract_field_signed((reg_value),13,8) #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_wants_to_go_low(reg_value) extract_field((reg_value),6,6) #define ex_DSC_D_VGA_P1EYEDIAG_STS__vga_bin(reg_value) extract_field((reg_value),5,0) #define ex_DSC_D_DFE_1_STS__dfe_1_wants_negative(reg_value) extract_field((reg_value),15,15) #define ex_DSC_D_DFE_1_STS__dfe_1_e(reg_value) extract_field((reg_value),13,11) #define ex_DSC_D_DFE_1_STS__dfe_1_o(reg_value) extract_field((reg_value),10,8) #define ex_DSC_D_DFE_1_STS__dfe_1_cmn(reg_value) extract_field((reg_value),5,0) #define ex_DSC_D_DFE_2_STS__dfe_2_e(reg_value) extract_field((reg_value),13,11) #define ex_DSC_D_DFE_2_STS__dfe_2_o(reg_value) extract_field((reg_value),10,8) #define ex_DSC_D_DFE_2_STS__dfe_2_se(reg_value) extract_field((reg_value),6,6) #define ex_DSC_D_DFE_2_STS__dfe_2_so(reg_value) extract_field((reg_value),5,5) #define ex_DSC_D_DFE_2_STS__dfe_2_cmn(reg_value) extract_field((reg_value),4,0) #define ex_DSC_D_DFE_3_4_5_STS__dfe_5_cmn(reg_value) extract_field_signed((reg_value),15,11) #define ex_DSC_D_DFE_3_4_5_STS__dfe_4_cmn(reg_value) extract_field_signed((reg_value),10,6) #define ex_DSC_D_DFE_3_4_5_STS__dfe_3_cmn(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_D_VGA_TAP_BIN__vga3_ctrl_bin(reg_value) extract_field((reg_value),11,8) #define ex_DSC_D_VGA_TAP_BIN__vga2_ctrl_bin(reg_value) extract_field((reg_value),7,4) #define ex_DSC_D_VGA_TAP_BIN__vga1_ctrl_bin(reg_value) extract_field((reg_value),3,0) #define ex_DSC_E_CTRL__pf_hiz(reg_value) extract_field((reg_value),7,7) #define ex_DSC_E_CTRL__m1_thresh_sel(reg_value) extract_field((reg_value),6,5) #define ex_DSC_E_CTRL__m1_thresh_zero(reg_value) extract_field((reg_value),4,4) #define ex_DSC_E_CTRL__p1_thresh_sel(reg_value) extract_field((reg_value),3,3) #define ex_DSC_E_CTRL__en_hgain(reg_value) extract_field((reg_value),2,2) #define ex_DSC_E_CTRL__offset_pd(reg_value) extract_field((reg_value),1,1) #define ex_DSC_E_CTRL__pd_ch_p1(reg_value) extract_field((reg_value),0,0) #define ex_DSC_E_PF_CTRL__pf_ctrl(reg_value) extract_field((reg_value),3,0) #define ex_DSC_E_PF2_LOWP_CTRL__pf2_lowp_ctrl(reg_value) extract_field((reg_value),2,0) #define ex_DSC_F_DATA_ODD_OFFSET__data_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_DATA_EVEN_OFFSET__data_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_P1_ODD_OFFSET__p1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_P1_EVEN_OFFSET__p1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_M1_ODD_OFFSET__m1_offset_odd_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_M1_EVEN_OFFSET__m1_offset_evn_bin(reg_value) extract_field_signed((reg_value),5,0) #define ex_DSC_F_DC_OFFSET__dc_offset_bin(reg_value) extract_field_signed((reg_value),6,0) #define exc_MDIO_BLK_ADDR_BLK_ADDR__mdio_blk_addr(reg_value) extract_field((reg_value),14,4) #define exc_MDIO_CL22_IEEE_ACC_CTRL__mdio_function(reg_value) extract_field((reg_value),15,14) #define exc_MDIO_CL22_IEEE_ACC_CTRL__mdio_devad(reg_value) extract_field((reg_value),4,0) #define exc_MDIO_CL22_IEEE_ACC_ADDR_DATA__mdio_addr_data(reg_value) extract_field((reg_value),15,0) #define exc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR__mdio_drv_comclk(reg_value) extract_field((reg_value),15,15) #define exc_MDIO_MMDSEL_AER_MDIO_BRCST_PORT_ADDR__mdio_brcst_port_addr(reg_value) extract_field((reg_value),4,0) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_multi_prts_en(reg_value) extract_field((reg_value),15,15) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_multi_mmds_en(reg_value) extract_field((reg_value),14,14) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_pcs_en(reg_value) extract_field((reg_value),6,6) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_dte_en(reg_value) extract_field((reg_value),5,5) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_phy_en(reg_value) extract_field((reg_value),4,4) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_an_en(reg_value) extract_field((reg_value),3,3) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_pmd_en(reg_value) extract_field((reg_value),2,2) #define exc_MDIO_MMDSEL_AER_MDIO_MMD_SELECT__mdio_dev_id0_en(reg_value) extract_field((reg_value),0,0) #define exc_MDIO_MMDSEL_AER_MDIO_AER__mdio_aer(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_core_clk_en(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_A_COM_CLOCK_CONTROL0__micro_master_clk_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_A_COM_RESET_CONTROL0__micro_pram_if_rstb(reg_value) extract_field((reg_value),3,3) #define exc_MICRO_A_COM_RESET_CONTROL0__micro_core_rstb(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_A_COM_RESET_CONTROL0__micro_master_rstb(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_rdaddr_en(reg_value) extract_field((reg_value),13,13) #define exc_MICRO_A_COM_AHB_CONTROL0__micro_autoinc_wraddr_en(reg_value) extract_field((reg_value),12,12) #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_init(reg_value) extract_field((reg_value),9,8) #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_rddatasize(reg_value) extract_field((reg_value),5,4) #define exc_MICRO_A_COM_AHB_CONTROL0__micro_ra_wrdatasize(reg_value) extract_field((reg_value),1,0) #define exc_MICRO_A_COM_AHB_STATUS0__micro_ra_initdone(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_A_COM_AHB_WRADDR_LSW__micro_ra_wraddr_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_WRADDR_MSW__micro_ra_wraddr_msw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_WRDATA_LSW__micro_ra_wrdata_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_WRDATA_MSW__micro_ra_wrdata_msw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_RDADDR_LSW__micro_ra_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_RDADDR_MSW__micro_ra_rdaddr_msw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_RDDATA_LSW__micro_ra_rddata_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_AHB_RDDATA_MSW__micro_ra_rddata_msw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_A_COM_PRAMIF_CONTROL0__micro_pramif_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW__micro_pramif_ahb_wraddr_lsw(reg_value) extract_field((reg_value),15,2) #define exc_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW__micro_pramif_ahb_wraddr_msw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_PVT_STATUS0__micro_pvt_tempdata_rmi(reg_value) extract_field((reg_value),9,0) #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX0__micro_rmi_to_micro_mbox0(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_RMI_TO_MICRO_MBOX1__micro_rmi_to_micro_mbox1(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX0__micro_to_rmi_mbox0(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_MICRO_TO_RMI_MBOX1__micro_to_rmi_mbox1(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox1wr(reg_value) extract_field((reg_value),2,2) #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_gen_intr_rmi_mbox0wr(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_B_COM_RMI_MBOX_CONTROL0__micro_rmi_mbox_send_msgin(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ext_ack_timeout_dis(reg_value) extract_field((reg_value),4,4) #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_pmi_hp_ack_timeout_dis(reg_value) extract_field((reg_value),3,3) #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_ext_rstb(reg_value) extract_field((reg_value),2,2) #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_sw_pmi_hp_rstb(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_B_COM_RMI_AHB_CONTROL1__micro_m0_hresp_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_pr_default_slave_error(reg_value) extract_field((reg_value),2,2) #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_rmi_default_slave_error(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_B_COM_RMI_AHB_STATUS1__micro_m0_default_slave_error(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_WRADDR_LSW__micro_ra_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_RMI_RA_AUTOINC_NXT_RDADDR_LSW__micro_ra_autoinc_nxt_rdaddr_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_RMI_PR_AUTOINC_NXT_WRADDR_LSW__micro_pr_autoinc_nxt_wraddr_lsw(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frc(reg_value) extract_field((reg_value),12,12) #define exc_MICRO_B_COM_RMI_PVT_CONTROL0__micro_pvt_tempdata_frcval(reg_value) extract_field((reg_value),9,0) #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_corrupt(reg_value) extract_field((reg_value),5,4) #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_ecc_frc_disable(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_C_COM_CODE_RAM_ECCCONTROL0__micro_eccg_mode(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_C_COM_CODE_RAM_ECCCONTRO1__micro_ra_ecc_wrdata(reg_value) extract_field((reg_value),6,0) #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS0__micro_code_ram_ecc_address(reg_value) extract_field((reg_value),15,0) #define exc_MICRO_C_COM_CODE_RAM_ECCSTATUS1__micro_ra_ecc_rddata(reg_value) extract_field((reg_value),6,0) #define exc_MICRO_C_COM_CODE_RAM_TESTIFCONTROL0__micro_code_ram_tm(reg_value) extract_field((reg_value),6,0) #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ignore_m0_code_writes(reg_value) extract_field((reg_value),15,15) #define exc_MICRO_C_COM_RAM_CONTROL0__micro_ramclk_noninv(reg_value) extract_field((reg_value),14,14) #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_size(reg_value) extract_field((reg_value),13,8) #define exc_MICRO_C_COM_RAM_CONTROL0__micro_protect_fwcode(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_C_COM_RAM_CONTROL0__micro_dr_looktab_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_systemresetreq_status(reg_value) extract_field((reg_value),9,9) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_m0_lockup_status(reg_value) extract_field((reg_value),8,8) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_multirow_err_status(reg_value) extract_field((reg_value),6,6) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_uncorr_err_status(reg_value) extract_field((reg_value),5,5) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_ecc_corr_err_status(reg_value) extract_field((reg_value),4,4) #define exc_MICRO_C_COM_RMI_EXT_INTR_STATUS0__micro_rmi_mbox_msgout_status(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_systemresetreq_intr_en(reg_value) extract_field((reg_value),9,9) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_m0_lockup_intr_en(reg_value) extract_field((reg_value),8,8) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_multirow_err_intr_en(reg_value) extract_field((reg_value),6,6) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_uncorr_err_intr_en(reg_value) extract_field((reg_value),5,5) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_ecc_corr_err_intr_en(reg_value) extract_field((reg_value),4,4) #define exc_MICRO_C_COM_RMI_EXT_INTR_CONTROL0__micro_rmi_mbox_msgout_intr_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_bktobk_en(reg_value) extract_field((reg_value),10,10) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),9,9) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_ext_fast_read_en(reg_value) extract_field((reg_value),8,8) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_bktobk_en(reg_value) extract_field((reg_value),2,2) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_dual_meta_ff_en(reg_value) extract_field((reg_value),1,1) #define exc_MICRO_C_COM_RMI_PMI_IF_CONTROL0__micro_pmi_hp_fast_read_en(reg_value) extract_field((reg_value),0,0) #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_CONTROL0__micro_silicon_debug_status_mux_sel(reg_value) extract_field((reg_value),1,0) #define exc_MICRO_C_COM_RMI_SILICON_DEBUG_STATUS0__micro_silicon_debug_status_muxed_data(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_0__patt_gen_seq_0(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_1__patt_gen_seq_1(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_2__patt_gen_seq_2(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_3__patt_gen_seq_3(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_4__patt_gen_seq_4(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_5__patt_gen_seq_5(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_6__patt_gen_seq_6(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_7__patt_gen_seq_7(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_8__patt_gen_seq_8(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_9__patt_gen_seq_9(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_10__patt_gen_seq_10(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_11__patt_gen_seq_11(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_12__patt_gen_seq_12(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_13__patt_gen_seq_13(reg_value) extract_field((reg_value),15,0) #define exc_PATT_GEN_COM_SEQ_14__patt_gen_seq_14(reg_value) extract_field((reg_value),15,0) #define exc_PLL_CAL_COM_CTL_0__cal_th(reg_value) extract_field((reg_value),15,14) #define exc_PLL_CAL_COM_CTL_0__calib_step_time(reg_value) extract_field((reg_value),12,0) #define exc_PLL_CAL_COM_CTL_1__freqdet_time(reg_value) extract_field((reg_value),15,0) #define exc_PLL_CAL_COM_CTL_2__calib_cap_charge_time(reg_value) extract_field((reg_value),11,0) #define exc_PLL_CAL_COM_CTL_3__ext_state(reg_value) extract_field((reg_value),15,12) #define exc_PLL_CAL_COM_CTL_3__accel_en(reg_value) extract_field((reg_value),11,11) #define exc_PLL_CAL_COM_CTL_3__debug_clr(reg_value) extract_field((reg_value),10,10) #define exc_PLL_CAL_COM_CTL_3__freqdet_time_msb(reg_value) extract_field((reg_value),9,9) #define exc_PLL_CAL_COM_CTL_3__freqdet_win(reg_value) extract_field((reg_value),7,0) #define exc_PLL_CAL_COM_CTL_4__halfstep_en(reg_value) extract_field((reg_value),15,15) #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass_en(reg_value) extract_field((reg_value),14,14) #define exc_PLL_CAL_COM_CTL_4__pll_force_cap_pass(reg_value) extract_field((reg_value),13,13) #define exc_PLL_CAL_COM_CTL_4__cal_pause_en(reg_value) extract_field((reg_value),12,12) #define exc_PLL_CAL_COM_CTL_4__cal_pause_rel(reg_value) extract_field((reg_value),11,11) #define exc_PLL_CAL_COM_CTL_4__cap_delay(reg_value) extract_field((reg_value),10,10) #define exc_PLL_CAL_COM_CTL_4__calib_start(reg_value) extract_field((reg_value),9,9) #define exc_PLL_CAL_COM_CTL_4__en_calib_n(reg_value) extract_field((reg_value),8,8) #define exc_PLL_CAL_COM_CTL_4__ext_range(reg_value) extract_field((reg_value),6,0) #define exc_PLL_CAL_COM_CTL_5__pll_seq_start(reg_value) extract_field((reg_value),15,15) #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_en(reg_value) extract_field((reg_value),14,14) #define exc_PLL_CAL_COM_CTL_5__lkdt_pause_rel(reg_value) extract_field((reg_value),13,13) #define exc_PLL_CAL_COM_CTL_5__vco_rst_en(reg_value) extract_field((reg_value),12,12) #define exc_PLL_CAL_COM_CTL_5__ext_range_force(reg_value) extract_field((reg_value),9,9) #define exc_PLL_CAL_COM_CTL_5__autocal_en(reg_value) extract_field((reg_value),8,8) #define exc_PLL_CAL_COM_CTL_5__autocal_cnt(reg_value) extract_field((reg_value),7,5) #define exc_PLL_CAL_COM_CTL_5__lkdt_byp(reg_value) extract_field((reg_value),4,4) #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc_val(reg_value) extract_field((reg_value),3,3) #define exc_PLL_CAL_COM_CTL_5__pll_lock_frc(reg_value) extract_field((reg_value),2,2) #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone(reg_value) extract_field((reg_value),1,1) #define exc_PLL_CAL_COM_CTL_5__pllforce_fdone_en(reg_value) extract_field((reg_value),0,0) #define exc_PLL_CAL_COM_CTL_6__band_iqbuf_sel(reg_value) extract_field((reg_value),7,7) #define exc_PLL_CAL_COM_CTL_6__vcorange_sel(reg_value) extract_field((reg_value),6,6) #define exc_PLL_CAL_COM_CTL_6__vcobufpon_sel(reg_value) extract_field((reg_value),5,5) #define exc_PLL_CAL_COM_CTL_6__vcopon_sel(reg_value) extract_field((reg_value),3,3) #define exc_PLL_CAL_COM_CTL_6__pllpon_sel(reg_value) extract_field((reg_value),1,1) #define exc_PLL_CAL_COM_STS_0__pll_fail_stky(reg_value) extract_field((reg_value),15,15) #define exc_PLL_CAL_COM_STS_0__cal_state(reg_value) extract_field((reg_value),14,11) #define exc_PLL_CAL_COM_STS_0__cal_valid(reg_value) extract_field((reg_value),10,10) #define exc_PLL_CAL_COM_STS_0__pll_lock(reg_value) extract_field((reg_value),9,9) #define exc_PLL_CAL_COM_STS_0__pll_lock_bar_stky(reg_value) extract_field((reg_value),8,8) #define exc_PLL_CAL_COM_STS_0__pll_range(reg_value) extract_field((reg_value),6,0) #define exc_PLL_CAL_COM_STS_1__lkdtref_counter_msb(reg_value) extract_field((reg_value),15,15) #define exc_PLL_CAL_COM_STS_1__lkdtvco_counter_msb(reg_value) extract_field((reg_value),14,14) #define exc_PLL_CAL_COM_STS_1__calref_counter(reg_value) extract_field((reg_value),12,0) #define exc_PLL_CAL_COM_STS_2__band_iqbuf_mux(reg_value) extract_field((reg_value),15,13) #define exc_PLL_CAL_COM_STS_2__calvco_counter(reg_value) extract_field((reg_value),12,0) #define exc_PLL_CAL_COM_STS_3__lkdtref_counter(reg_value) extract_field((reg_value),15,0) #define exc_PLL_CAL_COM_STS_4__lkdtvco_counter(reg_value) extract_field((reg_value),15,0) #define exc_PLL_CAL_COM_STS_5__vcobufpon_mux(reg_value) extract_field((reg_value),13,10) #define exc_PLL_CAL_COM_STS_5__calstate_onehot(reg_value) extract_field((reg_value),9,0) #define exc_PLL_CAL_COM_STS_6__pll_pwrdn_or(reg_value) extract_field((reg_value),15,15) #define exc_PLL_CAL_COM_STS_6__vco_range_mux(reg_value) extract_field((reg_value),14,8) #define exc_PLL_CAL_COM_STS_6__vcopon_mux(reg_value) extract_field((reg_value),7,4) #define exc_PLL_CAL_COM_STS_6__pllpon_mux(reg_value) extract_field((reg_value),3,0) #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_sigdet_pwrdn(reg_value) extract_field((reg_value),1,1) #define ex_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_rx_s_pwrdn(reg_value) extract_field((reg_value),0,0) #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_rx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) #define ex_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL__ln_rx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__sigdet_dp_rstb_en(reg_value) extract_field((reg_value),2,2) #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) #define ex_RX_CKRST_CTRL_RX_LANE_DEBUG_RESET_CONTROL__ln_rx_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc_val(reg_value) extract_field((reg_value),3,3) #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_reset_frc(reg_value) extract_field((reg_value),2,2) #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) #define ex_RX_CKRST_CTRL_RX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_rx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) #define ex_RX_CKRST_CTRL_RX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) #define ex_RX_CKRST_CTRL_RX_PMD_LANE_MODE_STATUS__pmd_lane_mode(reg_value) extract_field((reg_value),15,0) #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_reset(reg_value) extract_field((reg_value),1,1) #define ex_RX_CKRST_CTRL_RX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_rx_pwrdn(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_CONTROL__rx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__rx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL__rx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_rx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) #define ex_RXCOM_CKRST_CTRL_RXCOM_UC_ACK_LANE_CONTROL__rx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_DP_RESET_STATE_STATUS__rx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_LANE_REG_RESET_OCCURRED_CONTROL__rx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_OSR_MODE_STATUS_MC_MASK__rx_osr_mode(reg_value) extract_field((reg_value),3,0) #define ex_RXCOM_CKRST_CTRL_RXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__rx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc(reg_value) extract_field((reg_value),15,15) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_CONTROL__osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LN_S_RSTB_CONTROL__ln_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_UC_ACK_LANE_CONTROL__uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_DP_RESET_STATE_STATUS__lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_REG_RESET_OCCURRED_CONTROL__lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_OSR_MODE_STATUS_MC_MASK__osr_mode(reg_value) extract_field((reg_value),3,0) #define ex_RXTXCOM_CKRST_CTRL_RXTXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__osr_mode_pin(reg_value) extract_field((reg_value),3,0) #define ex_SIGDET_SDCTRL_0__signal_detect_filter_count(reg_value) extract_field((reg_value),4,0) #define ex_SIGDET_SDCTRL_0__los_filter_count(reg_value) extract_field((reg_value),9,5) #define ex_SIGDET_SDCTRL_0__energy_detect_mask_count(reg_value) extract_field((reg_value),14,10) #define ex_SIGDET_SDCTRL_1__afe_signal_detect_dis(reg_value) extract_field((reg_value),0,0) #define ex_SIGDET_SDCTRL_1__ext_los_en(reg_value) extract_field((reg_value),1,1) #define ex_SIGDET_SDCTRL_1__ext_los_inv(reg_value) extract_field((reg_value),2,2) #define ex_SIGDET_SDCTRL_1__ignore_lp_mode(reg_value) extract_field((reg_value),3,3) #define ex_SIGDET_SDCTRL_1__signal_detect_filter_1us(reg_value) extract_field((reg_value),4,4) #define ex_SIGDET_SDCTRL_1__energy_detect_frc(reg_value) extract_field((reg_value),5,5) #define ex_SIGDET_SDCTRL_1__energy_detect_frc_val(reg_value) extract_field((reg_value),6,6) #define ex_SIGDET_SDCTRL_1__signal_detect_frc(reg_value) extract_field((reg_value),7,7) #define ex_SIGDET_SDCTRL_1__signal_detect_frc_val(reg_value) extract_field((reg_value),8,8) #define ex_SIGDET_SDCTRL_2__los_thresh(reg_value) extract_field((reg_value),4,0) #define ex_SIGDET_SDCTRL_2__signal_detect_thresh(reg_value) extract_field((reg_value),9,5) #define ex_SIGDET_SDCTRL_2__hold_los_count(reg_value) extract_field((reg_value),12,10) #define ex_SIGDET_SDCTRL_2__hold_sd_count(reg_value) extract_field((reg_value),15,13) #define ex_SIGDET_SDSTATUS_0__signal_detect(reg_value) extract_field((reg_value),0,0) #define ex_SIGDET_SDSTATUS_0__signal_detect_change(reg_value) extract_field((reg_value),1,1) #define ex_SIGDET_SDSTATUS_0__signal_detect_raw(reg_value) extract_field((reg_value),4,4) #define ex_SIGDET_SDSTATUS_0__signal_detect_raw_change(reg_value) extract_field((reg_value),5,5) #define ex_SIGDET_SDSTATUS_0__ext_sigdet(reg_value) extract_field((reg_value),6,6) #define ex_SIGDET_SDSTATUS_0__ext_sigdet_change(reg_value) extract_field((reg_value),7,7) #define ex_SIGDET_SDSTATUS_0__afe_sigdet(reg_value) extract_field((reg_value),8,8) #define ex_SIGDET_SDSTATUS_0__afe_sigdet_change(reg_value) extract_field((reg_value),9,9) #define ex_SIGDET_SDSTATUS_1__uc_signal_detect(reg_value) extract_field((reg_value),0,0) #define ex_SIGDET_SDSTATUS_1__uc_signal_detect_change(reg_value) extract_field((reg_value),1,1) #define ex_SIGDET_SDSTATUS_1__uc_ext_sigdet(reg_value) extract_field((reg_value),6,6) #define ex_SIGDET_SDSTATUS_1__uc_ext_sigdet_change(reg_value) extract_field((reg_value),7,7) #define ex_SIGDET_SDSTATUS_1__uc_afe_sigdet(reg_value) extract_field((reg_value),8,8) #define ex_SIGDET_SDSTATUS_1__uc_afe_sigdet_change(reg_value) extract_field((reg_value),9,9) #define ex_SIGDET_SDSTATUS_2__energy_detect(reg_value) extract_field((reg_value),0,0) #define ex_SIGDET_SDSTATUS_2__energy_detect_change(reg_value) extract_field((reg_value),1,1) #define ex_SIGDET_SDSTATUS_3__pmd_signal_detect(reg_value) extract_field((reg_value),0,0) #define ex_SIGDET_SDSTATUS_4__afe_sigdet_thresh(reg_value) extract_field((reg_value),4,0) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_burst_err_cnt_en(reg_value) extract_field((reg_value),15,15) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_clk_en_frc_on(reg_value) extract_field((reg_value),11,11) #define ex_TLB_RX_PRBS_CHK_CONFIG__trnsum_error_count_en(reg_value) extract_field((reg_value),10,10) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_err_cnt_burst_mode(reg_value) extract_field((reg_value),9,9) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en_auto_mode(reg_value) extract_field((reg_value),7,7) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode(reg_value) extract_field((reg_value),6,5) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_inv(reg_value) extract_field((reg_value),4,4) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_mode_sel(reg_value) extract_field((reg_value),3,1) #define ex_TLB_RX_PRBS_CHK_CONFIG__prbs_chk_en(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_lock_cnt(reg_value) extract_field((reg_value),4,0) #define ex_TLB_RX_PRBS_CHK_CNT_CONFIG__prbs_chk_ool_cnt(reg_value) extract_field((reg_value),12,8) #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_bias_en(reg_value) extract_field((reg_value),3,3) #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_flt_bypass(reg_value) extract_field((reg_value),2,2) #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_DIG_LPBK_CONFIG__dig_lpbk_en(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_RXMISC_CONFIG__dbg_mask_dig_lpbk_en(reg_value) extract_field((reg_value),2,2) #define ex_TLB_RX_RXMISC_CONFIG__rx_aggregator_bypass_en(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_RXMISC_CONFIG__rx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timeout(reg_value) extract_field((reg_value),12,8) #define ex_TLB_RX_PRBS_CHK_EN_TIMER_CONTROL__prbs_chk_en_timer_mode(reg_value) extract_field((reg_value),1,0) #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_DIG_LPBK_PD_STATUS__dig_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_err_cnt_no_clr(reg_value) extract_field((reg_value),15,1) #define ex_TLB_RX_PRBS_CHK_LOCK_STATUS__prbs_chk_lock(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_lock_lost_lh(reg_value) extract_field((reg_value),15,15) #define ex_TLB_RX_PRBS_CHK_ERR_CNT_MSB_STATUS__prbs_chk_err_cnt_msb(reg_value) extract_field((reg_value),14,0) #define ex_TLB_RX_PRBS_CHK_ERR_CNT_LSB_STATUS__prbs_chk_err_cnt_lsb(reg_value) extract_field((reg_value),15,0) #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_PMD_RX_LOCK_STATUS__pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_DBG_PMD_RX_LOCK_STATUS__dbg_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock(reg_value) extract_field((reg_value),0,0) #define ex_TLB_RX_UC_PMD_RX_LOCK_STATUS__uc_pmd_rx_lock_change(reg_value) extract_field((reg_value),1,1) #define ex_TLB_RX_PRBS_CHK_BURST_ERR_CNT_STATUS__prbs_chk_burst_err_cnt(reg_value) extract_field((reg_value),9,0) #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_start_pos(reg_value) extract_field((reg_value),15,12) #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_stop_pos(reg_value) extract_field((reg_value),11,8) #define ex_TLB_TX_PATT_GEN_CONFIG__patt_gen_en(reg_value) extract_field((reg_value),0,0) #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_err_ins(reg_value) extract_field((reg_value),5,5) #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_inv(reg_value) extract_field((reg_value),4,4) #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_mode_sel(reg_value) extract_field((reg_value),3,1) #define ex_TLB_TX_PRBS_GEN_CONFIG__prbs_gen_en(reg_value) extract_field((reg_value),0,0) #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_frc_on(reg_value) extract_field((reg_value),2,2) #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_pd_mode(reg_value) extract_field((reg_value),1,1) #define ex_TLB_TX_RMT_LPBK_CONFIG__rmt_lpbk_en(reg_value) extract_field((reg_value),0,0) #define ex_TLB_TX_TXMISC_CONFIG__tx_mux_sel_order(reg_value) extract_field((reg_value),2,2) #define ex_TLB_TX_TXMISC_CONFIG__tx_pcs_native_ana_frmt_en(reg_value) extract_field((reg_value),1,1) #define ex_TLB_TX_TXMISC_CONFIG__tx_pmd_dp_invert(reg_value) extract_field((reg_value),0,0) #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_early_ind(reg_value) extract_field((reg_value),1,1) #define ex_TLB_TX_RMT_LPBK_PD_STATUS__rmt_lpbk_pd_late_ind(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__afe_tx_reset_deassert(reg_value) extract_field((reg_value),15,15) #define ex_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL__ln_tx_s_pwrdn(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc_val(reg_value) extract_field((reg_value),4,4) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__pmd_tx_clk_vld_frc(reg_value) extract_field((reg_value),3,3) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_frc_on(reg_value) extract_field((reg_value),2,2) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_comclk_sel(reg_value) extract_field((reg_value),1,1) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL__ln_tx_s_clkgate_frc_on(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_dp_s_rstb(reg_value) extract_field((reg_value),1,1) #define ex_TX_CKRST_CTRL_TX_LANE_DEBUG_RESET_CONTROL__ln_tx_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc_val(reg_value) extract_field((reg_value),5,5) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_txclk_reset_frc(reg_value) extract_field((reg_value),4,4) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc_val(reg_value) extract_field((reg_value),3,3) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_reset_frc(reg_value) extract_field((reg_value),2,2) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc_val(reg_value) extract_field((reg_value),1,1) #define ex_TX_CKRST_CTRL_TX_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL__afe_tx_pwrdn_frc(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_pwrdn_pkill(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_txclk_reset(reg_value) extract_field((reg_value),2,2) #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_reset(reg_value) extract_field((reg_value),1,1) #define ex_TX_CKRST_CTRL_TX_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__afe_tx_pwrdn(reg_value) extract_field((reg_value),0,0) #define ex_TX_CKRST_CTRL_TX_CLOCK_N_RESET_MISC_CONTROL__tx_pi_loop_filter_stable(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_TXFIR_TAP_CONTROL0__txfir_post2(reg_value) extract_field((reg_value),3,0) #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_error(reg_value) extract_field((reg_value),6,6) #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe_int_en(reg_value) extract_field((reg_value),5,5) #define ex_TX_FED_MISC_CONTROL0__convert_taps_to_afe(reg_value) extract_field((reg_value),4,4) #define ex_TX_FED_MISC_CONTROL0__tx_disable_output_sel(reg_value) extract_field((reg_value),3,2) #define ex_TX_FED_MISC_CONTROL0__sdk_tx_disable(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_MISC_STATUS0__tx_elec_idle_status(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_MISC_STATUS0__tx_disable_status(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_MICRO_CONTROL0__tx_eee_alert_en(reg_value) extract_field((reg_value),15,15) #define ex_TX_FED_MICRO_CONTROL0__tx_eee_quiet_en(reg_value) extract_field((reg_value),14,14) #define ex_TX_FED_MICRO_CONTROL0__tx_disable_timer_ctrl(reg_value) extract_field((reg_value),9,4) #define ex_TX_FED_MICRO_CONTROL0__pmd_tx_disable_pkill(reg_value) extract_field((reg_value),3,3) #define ex_TX_FED_MICRO_CONTROL0__dp_reset_tx_disable_dis(reg_value) extract_field((reg_value),2,2) #define ex_TX_FED_MICRO_CONTROL0__tx_disable_trigger(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_MICRO_CONTROL0__micro_tx_disable(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_1(reg_value) extract_field((reg_value),7,7) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_1(reg_value) extract_field((reg_value),6,6) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_2x_0(reg_value) extract_field((reg_value),5,5) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_2x_0(reg_value) extract_field((reg_value),4,4) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_1(reg_value) extract_field((reg_value),3,3) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_1(reg_value) extract_field((reg_value),2,2) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_dc_level_post2_1x_0(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_POST2_AFE_CONTROL0__txfir_post2_post2_1x_0(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1pre_1x_0(reg_value) extract_field((reg_value),14,14) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1pre_1x_0(reg_value) extract_field((reg_value),13,13) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_pre_post1pre_1x_0(reg_value) extract_field((reg_value),12,12) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_2(reg_value) extract_field((reg_value),9,9) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_2(reg_value) extract_field((reg_value),8,8) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_1(reg_value) extract_field((reg_value),7,7) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_1(reg_value) extract_field((reg_value),6,6) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_2x_0(reg_value) extract_field((reg_value),5,5) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_2x_0(reg_value) extract_field((reg_value),4,4) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_1(reg_value) extract_field((reg_value),3,3) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_1(reg_value) extract_field((reg_value),2,2) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_dc_level_post1_1x_0(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_POST1_AFE_CONTROL0__txfir_post1_post1_1x_0(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_3(reg_value) extract_field((reg_value),14,14) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_3(reg_value) extract_field((reg_value),13,13) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_3(reg_value) extract_field((reg_value),12,12) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_2(reg_value) extract_field((reg_value),11,11) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_2(reg_value) extract_field((reg_value),10,10) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_2(reg_value) extract_field((reg_value),9,9) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_1(reg_value) extract_field((reg_value),8,8) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_1(reg_value) extract_field((reg_value),7,7) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_1(reg_value) extract_field((reg_value),6,6) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_2x_0(reg_value) extract_field((reg_value),5,5) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_2x_0(reg_value) extract_field((reg_value),4,4) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_2x_0(reg_value) extract_field((reg_value),3,3) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_dc_level_post1pre_1x_1(reg_value) extract_field((reg_value),2,2) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_post1_post1pre_1x_1(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_POST1PRE_AFE_CONTROL0__txfir_pre_post1pre_1x_1(reg_value) extract_field((reg_value),0,0) #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_1(reg_value) extract_field((reg_value),3,3) #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_2x_0(reg_value) extract_field((reg_value),2,2) #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_1x(reg_value) extract_field((reg_value),1,1) #define ex_TX_FED_DC_LEVEL_AFE_CONTROL0__txfir_dc_level_0p5x(reg_value) extract_field((reg_value),0,0) #define ex_TX_PI_TXPICONTROL_0__tx_pi_en(reg_value) extract_field((reg_value),0,0) #define ex_TX_PI_TXPICONTROL_0__tx_pi_jitter_filter_en(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TXPICONTROL_0__tx_pi_ext_ctrl_en(reg_value) extract_field((reg_value),2,2) #define ex_TX_PI_TXPICONTROL_0__tx_pi_freq_override_en(reg_value) extract_field((reg_value),3,3) #define ex_TX_PI_TXPICONTROL_0__tx_pi_sj_gen_en(reg_value) extract_field((reg_value),4,4) #define ex_TX_PI_TXPICONTROL_0__tx_pi_ssc_gen_en(reg_value) extract_field((reg_value),5,5) #define ex_TX_PI_TXPICONTROL_0__tx_pi_jit_ssc_freq_mode(reg_value) extract_field((reg_value),6,6) #define ex_TX_PI_TXPICONTROL_0__tx_pi_reset_code_dbg(reg_value) extract_field((reg_value),7,7) #define ex_TX_PI_TXPICONTROL_0__tx_pi_second_order_loop_en(reg_value) extract_field((reg_value),8,8) #define ex_TX_PI_TXPICONTROL_0__tx_pi_first_order_bwsel_integ(reg_value) extract_field((reg_value),11,10) #define ex_TX_PI_TXPICONTROL_0__tx_pi_second_order_bwsel_integ(reg_value) extract_field((reg_value),13,12) #define ex_TX_PI_TXPICONTROL_0__tx_pi_frc_phase_step_mux_sel(reg_value) extract_field((reg_value),15,15) #define ex_TX_PI_TXPICONTROL_1__tx_pi_freq_override_val(reg_value) extract_field_signed((reg_value),14,0) #define ex_TX_PI_TXPICONTROL_2__tx_pi_jit_freq_idx(reg_value) extract_field((reg_value),5,0) #define ex_TX_PI_TXPICONTROL_2__tx_pi_jit_amp(reg_value) extract_field((reg_value),13,8) #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_override(reg_value) extract_field((reg_value),0,0) #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_strobe(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_step_dir(reg_value) extract_field((reg_value),2,2) #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_invert(reg_value) extract_field((reg_value),4,4) #define ex_TX_PI_TXPICONTROL_3__tx_pi_phase_step_num(reg_value) extract_field((reg_value),11,8) #define ex_TX_PI_TXPICONTROL_3__tx_pi_ext_phase_bwsel_integ(reg_value) extract_field((reg_value),14,12) #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_frc(reg_value) extract_field((reg_value),0,0) #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_frc_val(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TXPICONTROL_4__tx_pi_frz_mode(reg_value) extract_field((reg_value),2,2) #define ex_TX_PI_TXPICONTROL_5__tx_pi_hs_fifo_phserr_invert(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TXPICONTROL_5__tx_pi_repeater_mode_en(reg_value) extract_field((reg_value),2,2) #define ex_TX_PI_TXPICONTROL_5__tx_pi_ext_pd_sel(reg_value) extract_field((reg_value),3,3) #define ex_TX_PI_TXPICONTROL_5__afe_tx_fifo_resetb(reg_value) extract_field((reg_value),8,8) #define ex_TX_PI_TXPICONTROL_5__afe_tx_fifo_resetb_frc_on(reg_value) extract_field((reg_value),9,9) #define ex_TX_PI_TXPICONTROL_5__tx_pi_pd_bypass_flt(reg_value) extract_field((reg_value),10,10) #define ex_TX_PI_TXPICONTROL_5__tx_pi_pd_bypass_vco(reg_value) extract_field((reg_value),11,11) #define ex_TX_PI_TXPISTATUS_0__tx_pi_phase_cntr(reg_value) extract_field_signed((reg_value),6,0) #define ex_TX_PI_TXPISTATUS_1__tx_pi_integ1_reg(reg_value) extract_field_signed((reg_value),13,0) #define ex_TX_PI_TXPISTATUS_2__tx_pi_integ2_reg(reg_value) extract_field_signed((reg_value),14,0) #define ex_TX_PI_TXPISTATUS_3__tx_pi_phase_err(reg_value) extract_field_signed((reg_value),5,0) #define ex_TX_PI_TXPISTATUS_4__st_afe_tx_fifo_resetb(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TXPISTATUS_4__tx_pi_hs_fifo_phserr(reg_value) extract_field((reg_value),0,0) #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb_fall_edge_lh(reg_value) extract_field((reg_value),1,1) #define ex_TX_PI_TX_FIFO_OVFB_STATUS__tx_fifo_ovfb(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc(reg_value) extract_field((reg_value),15,15) #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_CONTROL__tx_osr_mode_frc_val(reg_value) extract_field((reg_value),3,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL__tx_ln_dp_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL__tx_ln_s_rstb(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_dp_h_rstb_pkill(reg_value) extract_field((reg_value),1,1) #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL__pmd_ln_tx_h_rstb_pkill(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_dp_reset(reg_value) extract_field((reg_value),1,1) #define ex_TXCOM_CKRST_CTRL_TXCOM_UC_ACK_LANE_CONTROL__tx_uc_ack_lane_cfg_done(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_DP_RESET_STATE_STATUS__tx_lane_dp_reset_state(reg_value) extract_field((reg_value),2,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_LANE_REG_RESET_OCCURRED_CONTROL__tx_lane_reg_reset_occurred(reg_value) extract_field((reg_value),0,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_OSR_MODE_STATUS_MC_MASK__tx_osr_mode(reg_value) extract_field((reg_value),3,0) #define ex_TXCOM_CKRST_CTRL_TXCOM_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS__tx_osr_mode_pin(reg_value) extract_field((reg_value),3,0) #define exc_TX_COM_CONTROL0_REGISTER__txcom_cl72_max_wait_timer_period(reg_value) extract_field((reg_value),15,0) #define exc_TX_COM_CONTROL1_REGISTER__txcom_cl72_wait_cntr_limit(reg_value) extract_field((reg_value),8,0) #endif