/* Copyright (c) 2015 Broadcom All Rights Reserved <:label-BRCM:2015:DUAL/GPL:standard Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Not withstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. :> */ #ifndef __AG_H_ #define __AG_H_ #include "ru.h" /****************************************************************************** * Fields ******************************************************************************/ extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_CTRL_RESERVED0_FIELD_MASK 0xffffffffffff8000ULL #define XPORT_XLMAC_CORE_CTRL_RESERVED0_FIELD_WIDTH 49 #define XPORT_XLMAC_CORE_CTRL_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_EXTENDED_HIG2_EN_FIELD; #define XPORT_XLMAC_CORE_CTRL_EXTENDED_HIG2_EN_FIELD_MASK 0x0000000000004000ULL #define XPORT_XLMAC_CORE_CTRL_EXTENDED_HIG2_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_EXTENDED_HIG2_EN_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_LINK_STATUS_SELECT_FIELD; #define XPORT_XLMAC_CORE_CTRL_LINK_STATUS_SELECT_FIELD_MASK 0x0000000000002000ULL #define XPORT_XLMAC_CORE_CTRL_LINK_STATUS_SELECT_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_LINK_STATUS_SELECT_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_SW_LINK_STATUS_FIELD; #define XPORT_XLMAC_CORE_CTRL_SW_LINK_STATUS_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_CORE_CTRL_SW_LINK_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_SW_LINK_STATUS_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD; #define XPORT_XLMAC_CORE_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_CORE_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_XGMII_IPG_CHECK_DISABLE_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RS_SOFT_RESET_FIELD; #define XPORT_XLMAC_CORE_CTRL_RS_SOFT_RESET_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_CORE_CTRL_RS_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_RS_SOFT_RESET_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RSVD_5_FIELD; #define XPORT_XLMAC_CORE_CTRL_RSVD_5_FIELD_MASK 0x0000000000000200ULL #define XPORT_XLMAC_CORE_CTRL_RSVD_5_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_RSVD_5_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD; #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_MASK 0x0000000000000100ULL #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_LEAK_ENB_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RSVD_4_FIELD; #define XPORT_XLMAC_CORE_CTRL_RSVD_4_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_CTRL_RSVD_4_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_RSVD_4_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_SOFT_RESET_FIELD; #define XPORT_XLMAC_CORE_CTRL_SOFT_RESET_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_CTRL_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_LAG_FAILOVER_EN_FIELD; #define XPORT_XLMAC_CORE_CTRL_LAG_FAILOVER_EN_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_CTRL_LAG_FAILOVER_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_LAG_FAILOVER_EN_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_REMOVE_FAILOVER_LPBK_FIELD; #define XPORT_XLMAC_CORE_CTRL_REMOVE_FAILOVER_LPBK_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_CTRL_REMOVE_FAILOVER_LPBK_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_REMOVE_FAILOVER_LPBK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RSVD_1_FIELD; #define XPORT_XLMAC_CORE_CTRL_RSVD_1_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_CTRL_RSVD_1_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_RSVD_1_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_FIELD; #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_LOCAL_LPBK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_RX_EN_FIELD; #define XPORT_XLMAC_CORE_CTRL_RX_EN_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_CTRL_RX_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_RX_EN_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_CTRL_TX_EN_FIELD; #define XPORT_XLMAC_CORE_CTRL_TX_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_CTRL_TX_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CTRL_TX_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_MODE_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_MODE_RESERVED0_FIELD_MASK 0xffffffffffffff80ULL #define XPORT_XLMAC_CORE_MODE_RESERVED0_FIELD_WIDTH 57 #define XPORT_XLMAC_CORE_MODE_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_MODE_SPEED_MODE_FIELD; #define XPORT_XLMAC_CORE_MODE_SPEED_MODE_FIELD_MASK 0x0000000000000070ULL #define XPORT_XLMAC_CORE_MODE_SPEED_MODE_FIELD_WIDTH 3 #define XPORT_XLMAC_CORE_MODE_SPEED_MODE_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_MODE_NO_SOP_FOR_CRC_HG_FIELD; #define XPORT_XLMAC_CORE_MODE_NO_SOP_FOR_CRC_HG_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_MODE_NO_SOP_FOR_CRC_HG_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_MODE_NO_SOP_FOR_CRC_HG_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_MODE_HDR_MODE_FIELD; #define XPORT_XLMAC_CORE_MODE_HDR_MODE_FIELD_MASK 0x0000000000000007ULL #define XPORT_XLMAC_CORE_MODE_HDR_MODE_FIELD_WIDTH 3 #define XPORT_XLMAC_CORE_MODE_HDR_MODE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_SPARE0_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_SPARE0_RESERVED0_FIELD_MASK 0xffffffff00000000ULL #define XPORT_XLMAC_CORE_SPARE0_RESERVED0_FIELD_WIDTH 32 #define XPORT_XLMAC_CORE_SPARE0_RESERVED0_FIELD_SHIFT 32 extern const ru_field_rec XPORT_XLMAC_CORE_SPARE0_RSVD_FIELD; #define XPORT_XLMAC_CORE_SPARE0_RSVD_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_CORE_SPARE0_RSVD_FIELD_WIDTH 32 #define XPORT_XLMAC_CORE_SPARE0_RSVD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_SPARE1_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_SPARE1_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_SPARE1_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_SPARE1_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_SPARE1_RSVD_FIELD; #define XPORT_XLMAC_CORE_SPARE1_RSVD_FIELD_MASK 0x0000000000000003ULL #define XPORT_XLMAC_CORE_SPARE1_RSVD_FIELD_WIDTH 2 #define XPORT_XLMAC_CORE_SPARE1_RSVD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_RESERVED0_FIELD_MASK 0xfffffc0000000000ULL #define XPORT_XLMAC_CORE_TX_CTRL_RESERVED0_FIELD_WIDTH 22 #define XPORT_XLMAC_CORE_TX_CTRL_RESERVED0_FIELD_SHIFT 42 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_TX_THRESHOLD_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_TX_THRESHOLD_FIELD_MASK 0x000003c000000000ULL #define XPORT_XLMAC_CORE_TX_CTRL_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_XLMAC_CORE_TX_CTRL_TX_THRESHOLD_FIELD_SHIFT 38 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_EP_DISCARD_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_EP_DISCARD_FIELD_MASK 0x0000002000000000ULL #define XPORT_XLMAC_CORE_TX_CTRL_EP_DISCARD_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CTRL_EP_DISCARD_FIELD_SHIFT 37 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_MASK 0x0000001e00000000ULL #define XPORT_XLMAC_CORE_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_WIDTH 4 #define XPORT_XLMAC_CORE_TX_CTRL_TX_PREAMBLE_LENGTH_FIELD_SHIFT 33 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_THROT_DENOM_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_THROT_DENOM_FIELD_MASK 0x00000001fe000000ULL #define XPORT_XLMAC_CORE_TX_CTRL_THROT_DENOM_FIELD_WIDTH 8 #define XPORT_XLMAC_CORE_TX_CTRL_THROT_DENOM_FIELD_SHIFT 25 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_THROT_NUM_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_THROT_NUM_FIELD_MASK 0x0000000001f80000ULL #define XPORT_XLMAC_CORE_TX_CTRL_THROT_NUM_FIELD_WIDTH 6 #define XPORT_XLMAC_CORE_TX_CTRL_THROT_NUM_FIELD_SHIFT 19 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_AVERAGE_IPG_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_AVERAGE_IPG_FIELD_MASK 0x000000000007f000ULL #define XPORT_XLMAC_CORE_TX_CTRL_AVERAGE_IPG_FIELD_WIDTH 7 #define XPORT_XLMAC_CORE_TX_CTRL_AVERAGE_IPG_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_PAD_THRESHOLD_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_PAD_THRESHOLD_FIELD_MASK 0x0000000000000fe0ULL #define XPORT_XLMAC_CORE_TX_CTRL_PAD_THRESHOLD_FIELD_WIDTH 7 #define XPORT_XLMAC_CORE_TX_CTRL_PAD_THRESHOLD_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_PAD_EN_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_PAD_EN_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_TX_CTRL_PAD_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CTRL_PAD_EN_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_TX_ANY_START_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_TX_ANY_START_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_TX_CTRL_TX_ANY_START_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CTRL_TX_ANY_START_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_DISCARD_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_DISCARD_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_TX_CTRL_DISCARD_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CTRL_DISCARD_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CTRL_CRC_MODE_FIELD; #define XPORT_XLMAC_CORE_TX_CTRL_CRC_MODE_FIELD_MASK 0x0000000000000003ULL #define XPORT_XLMAC_CORE_TX_CTRL_CRC_MODE_FIELD_WIDTH 2 #define XPORT_XLMAC_CORE_TX_CTRL_CRC_MODE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_MAC_SA_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_MAC_SA_RESERVED0_FIELD_MASK 0xffff000000000000ULL #define XPORT_XLMAC_CORE_TX_MAC_SA_RESERVED0_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_TX_MAC_SA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec XPORT_XLMAC_CORE_TX_MAC_SA_CTRL_SA_FIELD; #define XPORT_XLMAC_CORE_TX_MAC_SA_CTRL_SA_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_XLMAC_CORE_TX_MAC_SA_CTRL_SA_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_TX_MAC_SA_CTRL_SA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RESERVED0_FIELD_MASK 0xffffffffffff0000ULL #define XPORT_XLMAC_CORE_RX_CTRL_RESERVED0_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_RX_CTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PFC_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PFC_FIELD_MASK 0x0000000000008000ULL #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PFC_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PFC_FIELD_SHIFT 15 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PAUSE_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PAUSE_FIELD_MASK 0x0000000000004000ULL #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PAUSE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_PAUSE_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_CTRL_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_CTRL_FIELD_MASK 0x0000000000002000ULL #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_CTRL_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RX_PASS_CTRL_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RSVD_3_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_3_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_3_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_3_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RSVD_2_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_2_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_2_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_2_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RUNT_THRESHOLD_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RUNT_THRESHOLD_FIELD_MASK 0x00000000000007f0ULL #define XPORT_XLMAC_CORE_RX_CTRL_RUNT_THRESHOLD_FIELD_WIDTH 7 #define XPORT_XLMAC_CORE_RX_CTRL_RUNT_THRESHOLD_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_STRICT_PREAMBLE_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_STRICT_PREAMBLE_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_RX_CTRL_STRICT_PREAMBLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_STRICT_PREAMBLE_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_STRIP_CRC_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_STRIP_CRC_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_RX_CTRL_STRIP_CRC_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_STRIP_CRC_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RX_ANY_START_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RX_ANY_START_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_RX_CTRL_RX_ANY_START_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RX_ANY_START_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CTRL_RSVD_1_FIELD; #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_1_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_1_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CTRL_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_MAC_SA_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_MAC_SA_RESERVED0_FIELD_MASK 0xffff000000000000ULL #define XPORT_XLMAC_CORE_RX_MAC_SA_RESERVED0_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_RX_MAC_SA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec XPORT_XLMAC_CORE_RX_MAC_SA_RX_SA_FIELD; #define XPORT_XLMAC_CORE_RX_MAC_SA_RX_SA_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_XLMAC_CORE_RX_MAC_SA_RX_SA_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_RX_MAC_SA_RX_SA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_MAX_SIZE_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RESERVED0_FIELD_MASK 0xffffffffffffc000ULL #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RESERVED0_FIELD_WIDTH 50 #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_RX_MAX_SIZE_RX_MAX_SIZE_FIELD; #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_MASK 0x0000000000003fffULL #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_WIDTH 14 #define XPORT_XLMAC_CORE_RX_MAX_SIZE_RX_MAX_SIZE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_RESERVED0_FIELD_MASK 0xfffffffc00000000ULL #define XPORT_XLMAC_CORE_RX_VLAN_TAG_RESERVED0_FIELD_WIDTH 30 #define XPORT_XLMAC_CORE_RX_VLAN_TAG_RESERVED0_FIELD_SHIFT 34 extern const ru_field_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_MASK 0x0000000200000000ULL #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_FIELD_SHIFT 33 extern const ru_field_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_MASK 0x0000000100000000ULL #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_FIELD_SHIFT 32 extern const ru_field_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_RX_VLAN_TAG_OUTER_VLAN_TAG_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_RX_VLAN_TAG_INNER_VLAN_TAG_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffff00ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESERVED0_FIELD_WIDTH 56 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8ULL #define XPORT_XLMAC_CORE_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61 #define XPORT_XLMAC_CORE_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_STATUS_REMOTE_FAULT_STATUS_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_LSS_STATUS_LOCAL_FAULT_STATUS_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8ULL #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_WIDTH 61 #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD; #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_RESERVED0_FIELD_MASK 0xffffffe000000000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_RESERVED0_FIELD_WIDTH 27 #define XPORT_XLMAC_CORE_PAUSE_CTRL_RESERVED0_FIELD_SHIFT 37 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_MASK 0x0000001fffe00000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_XOFF_TIMER_FIELD_SHIFT 21 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_2_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_2_FIELD_MASK 0x0000000000100000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_2_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_2_FIELD_SHIFT 20 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_1_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_1_FIELD_MASK 0x0000000000080000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_1_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PAUSE_CTRL_RSVD_1_FIELD_SHIFT 19 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_RX_PAUSE_EN_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_RX_PAUSE_EN_FIELD_MASK 0x0000000000040000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_RX_PAUSE_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PAUSE_CTRL_RX_PAUSE_EN_FIELD_SHIFT 18 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_TX_PAUSE_EN_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_TX_PAUSE_EN_FIELD_MASK 0x0000000000020000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_TX_PAUSE_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PAUSE_CTRL_TX_PAUSE_EN_FIELD_SHIFT 17 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_MASK 0x0000000000010000ULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_EN_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD; #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PAUSE_CTRL_PAUSE_REFRESH_TIMER_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_RESERVED0_FIELD_MASK 0xffffffc000000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_RESERVED0_FIELD_WIDTH 26 #define XPORT_XLMAC_CORE_PFC_CTRL_RESERVED0_FIELD_SHIFT 38 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_TX_PFC_EN_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_TX_PFC_EN_FIELD_MASK 0x0000002000000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_TX_PFC_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_TX_PFC_EN_FIELD_SHIFT 37 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_RX_PFC_EN_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_RX_PFC_EN_FIELD_MASK 0x0000001000000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_RX_PFC_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_RX_PFC_EN_FIELD_SHIFT 36 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_PFC_STATS_EN_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_STATS_EN_FIELD_MASK 0x0000000800000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_STATS_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_STATS_EN_FIELD_SHIFT 35 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_RSVD_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_RSVD_FIELD_MASK 0x0000000400000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_RSVD_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_RSVD_FIELD_SHIFT 34 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_FORCE_PFC_XON_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_FORCE_PFC_XON_FIELD_MASK 0x0000000200000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_FORCE_PFC_XON_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_FORCE_PFC_XON_FIELD_SHIFT 33 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_EN_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_EN_FIELD_MASK 0x0000000100000000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_EN_FIELD_SHIFT 32 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_PFC_XOFF_TIMER_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_XOFF_TIMER_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_XOFF_TIMER_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_XOFF_TIMER_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_TIMER_FIELD; #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PFC_CTRL_PFC_REFRESH_TIMER_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_TYPE_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_PFC_TYPE_RESERVED0_FIELD_MASK 0xffffffffffff0000ULL #define XPORT_XLMAC_CORE_PFC_TYPE_RESERVED0_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_PFC_TYPE_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_TYPE_PFC_ETH_TYPE_FIELD; #define XPORT_XLMAC_CORE_PFC_TYPE_PFC_ETH_TYPE_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_PFC_TYPE_PFC_ETH_TYPE_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PFC_TYPE_PFC_ETH_TYPE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_OPCODE_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_PFC_OPCODE_RESERVED0_FIELD_MASK 0xffffffffffff0000ULL #define XPORT_XLMAC_CORE_PFC_OPCODE_RESERVED0_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_PFC_OPCODE_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_OPCODE_PFC_OPCODE_FIELD; #define XPORT_XLMAC_CORE_PFC_OPCODE_PFC_OPCODE_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_PFC_OPCODE_PFC_OPCODE_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PFC_OPCODE_PFC_OPCODE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_DA_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_PFC_DA_RESERVED0_FIELD_MASK 0xffff000000000000ULL #define XPORT_XLMAC_CORE_PFC_DA_RESERVED0_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_PFC_DA_RESERVED0_FIELD_SHIFT 48 extern const ru_field_rec XPORT_XLMAC_CORE_PFC_DA_PFC_MACDA_FIELD; #define XPORT_XLMAC_CORE_PFC_DA_PFC_MACDA_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_XLMAC_CORE_PFC_DA_PFC_MACDA_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_PFC_DA_PFC_MACDA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffc000ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_RESERVED0_FIELD_WIDTH 50 #define XPORT_XLMAC_CORE_LLFC_CTRL_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IMG_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IMG_FIELD_MASK 0x0000000000003fc0ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IMG_FIELD_WIDTH 8 #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IMG_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CRC_IGNORE_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_LLFC_IN_IPG_ONLY_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_RX_LLFC_EN_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_RX_LLFC_EN_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_RX_LLFC_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_RX_LLFC_EN_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_LLFC_CTRL_TX_LLFC_EN_FIELD; #define XPORT_XLMAC_CORE_LLFC_CTRL_TX_LLFC_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_LLFC_CTRL_TX_LLFC_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LLFC_CTRL_TX_LLFC_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK 0xfffffffff0000000ULL #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 36 #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD; #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_MASK 0x000000000ffff000ULL #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD; #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK 0x0000000000000f00ULL #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4 #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD; #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK 0x00000000000000ffULL #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8 #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_MASK 0xffffffffff000000ULL #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_WIDTH 40 #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_MASK 0x0000000000f00000ULL #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_WIDTH 4 #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_FIELD_SHIFT 20 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_MASK 0x00000000000ff000ULL #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_WIDTH 8 #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_MASK 0x0000000000000f00ULL #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_WIDTH 4 #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_MASK 0x00000000000000ffULL #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_WIDTH 8 #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_MASK 0xfffe000000000000ULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_WIDTH 15 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_RESERVED0_FIELD_SHIFT 49 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_MASK 0x0001000000000000ULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_FIELD_SHIFT 48 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_MASK 0x0000ffff00000000ULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_FIELD_SHIFT 32 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_WIDTH 32 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff8ULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_WIDTH 61 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_MASK 0x0000000000000007ULL #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_WIDTH 3 #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffe00ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_RESERVED0_FIELD_WIDTH 55 #define XPORT_XLMAC_CORE_FIFO_STATUS_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_LINK_STATUS_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_LINK_STATUS_FIELD_MASK 0x0000000000000100ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_LINK_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_LINK_STATUS_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_PKT_OVERFLOW_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_2_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_2_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_TX_PKT_UNDERFLOW_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_RX_MSG_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_1_FIELD; #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_1_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RESERVED0_FIELD_MASK 0xffffffffffffff00ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 56 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_2_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_2_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_2_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_2_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_1_FIELD; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_1_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_1_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_RSVD_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RSVD_FIELD; #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RSVD_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RSVD_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_RSVD_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD; #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_EEE_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_EEE_CTRL_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_EEE_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_CTRL_RSVD_FIELD; #define XPORT_XLMAC_CORE_EEE_CTRL_RSVD_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_EEE_CTRL_RSVD_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_EEE_CTRL_RSVD_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_CTRL_EEE_EN_FIELD; #define XPORT_XLMAC_CORE_EEE_CTRL_EEE_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_EEE_CTRL_EEE_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_EEE_CTRL_EEE_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_TIMERS_EEE_REF_COUNT_FIELD; #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_REF_COUNT_FIELD_MASK 0xffff000000000000ULL #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_REF_COUNT_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_REF_COUNT_FIELD_SHIFT 48 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_TIMERS_EEE_WAKE_TIMER_FIELD; #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_MASK 0x0000ffff00000000ULL #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_WAKE_TIMER_FIELD_SHIFT 32 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD; #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_WIDTH 32 #define XPORT_XLMAC_CORE_EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_MASK 0xffffffffff000000ULL #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_WIDTH 40 #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD; #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_MASK 0x0000000000ffffffULL #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_WIDTH 24 #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_HIGIG_HDR_0_HIGIG_HDR_0_FIELD; #define XPORT_XLMAC_CORE_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_HIGIG_HDR_0_HIGIG_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_HIGIG_HDR_1_HIGIG_HDR_1_FIELD; #define XPORT_XLMAC_CORE_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_HIGIG_HDR_1_HIGIG_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_GMII_EEE_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffe0000ULL #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_RESERVED0_FIELD_WIDTH 47 #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD; #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_MASK 0x0000000000010000ULL #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD; #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_RESERVED0_FIELD_MASK 0xffffffffffff0000ULL #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_RESERVED0_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_MASK 0x0000000000008000ULL #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_FIELD_SHIFT 15 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_MASK 0x0000000000007e00ULL #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_WIDTH 6 #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_TSTS_ADJUST_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_MASK 0x00000000000001ffULL #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_WIDTH 9 #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_TS_OSTS_ADJUST_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_MASK 0xffffffffffc00000ULL #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_WIDTH 42 #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_MASK 0x0000000000200000ULL #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 21 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_MASK 0x00000000001ff800ULL #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10 #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_MASK 0x00000000000003ffULL #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_WIDTH 10 #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_MASK 0xfffffff800000000ULL #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_WIDTH 29 #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_RESERVED0_FIELD_SHIFT 35 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_MASK 0x00000007fffffff8ULL #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_WIDTH 32 #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_RESERVED0_FIELD_MASK 0xffffffffffffffe0ULL #define XPORT_XLMAC_CORE_E2E_CTRL_RESERVED0_FIELD_WIDTH 59 #define XPORT_XLMAC_CORE_E2E_CTRL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_E2E_CTRL_E2EFC_DUAL_MODID_EN_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_LEGACY_IMP_EN_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_E2E_CTRL_E2ECC_DUAL_MODID_EN_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_E2E_CTRL_HONOR_PAUSE_FOR_E2E_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_E2E_CTRL_E2E_ENABLE_FIELD; #define XPORT_XLMAC_CORE_E2E_CTRL_E2E_ENABLE_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_E2E_CTRL_E2E_ENABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_E2E_CTRL_E2E_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD; #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD; #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD; #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD; #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD; #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD; #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD; #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD; #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_MASK 0xffffffffffffffffULL #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_WIDTH 64 #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_RESERVED0_FIELD_MASK 0xffffffffffffffc0ULL #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_RESERVED0_FIELD_WIDTH 58 #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_CELL_CNT_FIELD; #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_CELL_CNT_FIELD_MASK 0x000000000000003fULL #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_CELL_CNT_FIELD_WIDTH 6 #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_CELL_CNT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_MASK 0xffffffffffffffc0ULL #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_WIDTH 58 #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD; #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_MASK 0x000000000000003fULL #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_WIDTH 6 #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_MEM_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_MEM_CTRL_RESERVED0_FIELD_MASK 0xffffffffff000000ULL #define XPORT_XLMAC_CORE_MEM_CTRL_RESERVED0_FIELD_WIDTH 40 #define XPORT_XLMAC_CORE_MEM_CTRL_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec XPORT_XLMAC_CORE_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD; #define XPORT_XLMAC_CORE_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_MASK 0x0000000000fff000ULL #define XPORT_XLMAC_CORE_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12 #define XPORT_XLMAC_CORE_MEM_CTRL_TX_CDC_MEM_CTRL_TM_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD; #define XPORT_XLMAC_CORE_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_MASK 0x0000000000000fffULL #define XPORT_XLMAC_CORE_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_WIDTH 12 #define XPORT_XLMAC_CORE_MEM_CTRL_RX_CDC_MEM_CTRL_TM_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_CTRL_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_ECC_CTRL_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_ECC_CTRL_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_ECC_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD; #define XPORT_XLMAC_CORE_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_CTRL_TX_CDC_ECC_CTRL_EN_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD; #define XPORT_XLMAC_CORE_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_CTRL_RX_CDC_ECC_CTRL_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffffcULL #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_RESERVED0_FIELD_WIDTH 62 #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_RESERVED0_FIELD_MASK 0xfffffffffffffff0ULL #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_RESERVED0_FIELD_WIDTH 60 #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_RESERVED0_FIELD_MASK 0xffffffffffffc000ULL #define XPORT_XLMAC_CORE_INTR_STATUS_RESERVED0_FIELD_WIDTH 50 #define XPORT_XLMAC_CORE_INTR_STATUS_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_MASK 0x0000000000002000ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TS_ENTRY_VALID_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_REMOTE_FAULT_STATUS_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_LOCAL_FAULT_STATUS_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000200ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000100ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_RX_PKT_OVERFLOW_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_STATUS_SUM_TX_PKT_UNDERFLOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_RESERVED0_FIELD_MASK 0xffffffffffffc000ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_RESERVED0_FIELD_WIDTH 50 #define XPORT_XLMAC_CORE_INTR_ENABLE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_MASK 0x0000000000002000ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TS_ENTRY_VALID_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_REMOTE_FAULT_STATUS_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_LOCAL_FAULT_STATUS_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000200ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000100ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_MSG_OVERFLOW_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_RX_PKT_OVERFLOW_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD; #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_WIDTH 1 #define XPORT_XLMAC_CORE_INTR_ENABLE_EN_TX_PKT_UNDERFLOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_CORE_VERSION_ID_RESERVED0_FIELD; #define XPORT_XLMAC_CORE_VERSION_ID_RESERVED0_FIELD_MASK 0xffffffffffff0000ULL #define XPORT_XLMAC_CORE_VERSION_ID_RESERVED0_FIELD_WIDTH 48 #define XPORT_XLMAC_CORE_VERSION_ID_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_XLMAC_CORE_VERSION_ID_XLMAC_VERSION_FIELD; #define XPORT_XLMAC_CORE_VERSION_ID_XLMAC_VERSION_FIELD_MASK 0x000000000000ffffULL #define XPORT_XLMAC_CORE_VERSION_ID_XLMAC_VERSION_FIELD_WIDTH 16 #define XPORT_XLMAC_CORE_VERSION_ID_XLMAC_VERSION_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX64_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX64_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX64_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX64_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX127_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX127_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX127_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX127_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX255_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX255_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX255_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX255_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX511_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX511_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX511_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX511_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX1023_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX1023_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX1023_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX1023_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX1518_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX1518_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX1518_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX1518_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX1522_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX1522_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX1522_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX1522_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX2047_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX2047_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX2047_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX2047_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX4095_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX4095_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX4095_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX4095_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX9216_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX9216_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX9216_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX9216_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRX16383_COUNT40_FIELD; #define XPORT_MIB_CORE_GRX16383_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRX16383_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRX16383_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPKT_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPKT_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPKT_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXUCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXUCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXUCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXUCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXMCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXMCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXMCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXMCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXBCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXBCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXBCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXBCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXFCS_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXFCS_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXFCS_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXCF_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXCF_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXCF_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXCF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPF_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPF_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPF_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPP_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPP_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPP_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPP_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXUO_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXUO_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXUO_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXUO_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXUDA_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXUDA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXUDA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXUDA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXWSA_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXWSA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXWSA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXWSA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXALN_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXALN_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXALN_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXALN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXFLR_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXFLR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXFLR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXFLR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXFRERR_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXFRERR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXFRERR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXFRERR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXFCR_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXFCR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXFCR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXFCR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXOVR_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXOVR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXOVR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXOVR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXJBR_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXJBR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXJBR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXJBR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXMTUE_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXMTUE_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXMTUE_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXMTUE_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXMCRC_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXMCRC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXMCRC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXMCRC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPRM_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPRM_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPRM_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPRM_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXVLN_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXVLN_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXVLN_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXDVLN_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXDVLN_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXDVLN_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXDVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXTRFU_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXTRFU_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXTRFU_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXTRFU_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPOK_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPOK_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPOK_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPOK_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF0_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF0_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF0_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF1_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF1_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF1_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF2_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF2_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF2_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF3_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF3_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF3_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF4_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF4_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF4_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF5_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF5_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF5_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF6_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF6_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF6_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCOFF7_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCOFF7_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCOFF7_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCOFF7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP0_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP0_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP0_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP1_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP1_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP1_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP2_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP2_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP2_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP3_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP3_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP3_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP4_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP4_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP4_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP5_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP5_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP5_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP6_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP6_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP6_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPFCP7_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPFCP7_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPFCP7_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPFCP7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXSCHCRC_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXSCHCRC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXSCHCRC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXSCHCRC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXBYT_COUNT48_FIELD; #define XPORT_MIB_CORE_GRXBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_MIB_CORE_GRXBYT_COUNT48_FIELD_WIDTH 48 #define XPORT_MIB_CORE_GRXBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXRPKT_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXRPKT_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXRPKT_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXRPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXUND_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXUND_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXUND_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXUND_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXFRG_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXFRG_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXFRG_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXFRG_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXRBYT_COUNT48_FIELD; #define XPORT_MIB_CORE_GRXRBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_MIB_CORE_GRXRBYT_COUNT48_FIELD_WIDTH 48 #define XPORT_MIB_CORE_GRXRBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX64_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX64_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX64_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX64_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX127_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX127_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX127_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX127_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX255_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX255_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX255_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX255_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX511_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX511_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX511_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX511_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX1023_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX1023_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX1023_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX1023_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX1518_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX1518_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX1518_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX1518_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX1522_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX1522_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX1522_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX1522_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX2047_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX2047_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX2047_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX2047_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX4095_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX4095_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX4095_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX4095_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX9216_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX9216_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX9216_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX9216_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTX16383_COUNT40_FIELD; #define XPORT_MIB_CORE_GTX16383_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTX16383_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTX16383_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPOK_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPOK_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPOK_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPOK_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPKT_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPKT_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPKT_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXUCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXUCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXUCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXUCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXMCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXMCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXMCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXMCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXBCA_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXBCA_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXBCA_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXBCA_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPF_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPF_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPF_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFC_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXJBR_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXJBR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXJBR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXJBR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXFCS_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXFCS_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXFCS_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXCF_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXCF_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXCF_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXCF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXOVR_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXOVR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXOVR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXOVR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXDFR_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXDFR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXDFR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXDFR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXEDF_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXEDF_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXEDF_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXEDF_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXSCL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXSCL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXSCL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXSCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXMCL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXMCL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXMCL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXMCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXLCL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXLCL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXLCL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXLCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXXCL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXXCL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXXCL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXXCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXFRG_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXFRG_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXFRG_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXFRG_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXERR_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXERR_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXERR_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXERR_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXVLN_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXVLN_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXVLN_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXDVLN_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXDVLN_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXDVLN_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXDVLN_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXRPKT_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXRPKT_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXRPKT_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXRPKT_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXUFL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXUFL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXUFL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXUFL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP0_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP0_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP0_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP0_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP1_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP1_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP1_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP1_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP2_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP2_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP2_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP2_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP3_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP3_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP3_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP3_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP4_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP4_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP4_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP4_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP5_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP5_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP5_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP5_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP6_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP6_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP6_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP6_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXPFCP7_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXPFCP7_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXPFCP7_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXPFCP7_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXNCL_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXNCL_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXNCL_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXNCL_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXBYT_COUNT48_FIELD; #define XPORT_MIB_CORE_GTXBYT_COUNT48_FIELD_MASK 0x0000ffffffffffffULL #define XPORT_MIB_CORE_GTXBYT_COUNT48_FIELD_WIDTH 48 #define XPORT_MIB_CORE_GTXBYT_COUNT48_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXLPI_COUNT32_FIELD; #define XPORT_MIB_CORE_GRXLPI_COUNT32_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_CORE_GRXLPI_COUNT32_FIELD_WIDTH 32 #define XPORT_MIB_CORE_GRXLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXDLPI_COUNT32_FIELD; #define XPORT_MIB_CORE_GRXDLPI_COUNT32_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_CORE_GRXDLPI_COUNT32_FIELD_WIDTH 32 #define XPORT_MIB_CORE_GRXDLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXLPI_COUNT32_FIELD; #define XPORT_MIB_CORE_GTXLPI_COUNT32_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_CORE_GTXLPI_COUNT32_FIELD_WIDTH 32 #define XPORT_MIB_CORE_GTXLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXDLPI_COUNT32_FIELD; #define XPORT_MIB_CORE_GTXDLPI_COUNT32_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_CORE_GTXDLPI_COUNT32_FIELD_WIDTH 32 #define XPORT_MIB_CORE_GTXDLPI_COUNT32_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXPTLLFC_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXPTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXPTLLFC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXPTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXLTLLFC_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXLTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXLTLLFC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXLTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GRXLLFCFCS_COUNT40_FIELD; #define XPORT_MIB_CORE_GRXLLFCFCS_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GRXLLFCFCS_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GRXLLFCFCS_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_CORE_GTXLTLLFC_COUNT40_FIELD; #define XPORT_MIB_CORE_GTXLTLLFC_COUNT40_FIELD_MASK 0x000000ffffffffffULL #define XPORT_MIB_CORE_GTXLTLLFC_COUNT40_FIELD_WIDTH 40 #define XPORT_MIB_CORE_GTXLTLLFC_COUNT40_FIELD_SHIFT 0 extern const ru_field_rec XPORT_TOP_CONTROL_RESERVED0_FIELD; #define XPORT_TOP_CONTROL_RESERVED0_FIELD_MASK 0x00000000fffffff0ULL #define XPORT_TOP_CONTROL_RESERVED0_FIELD_WIDTH 28 #define XPORT_TOP_CONTROL_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec XPORT_TOP_CONTROL_P3_MODE_FIELD; #define XPORT_TOP_CONTROL_P3_MODE_FIELD_MASK 0x0000000000000008ULL #define XPORT_TOP_CONTROL_P3_MODE_FIELD_WIDTH 1 #define XPORT_TOP_CONTROL_P3_MODE_FIELD_SHIFT 3 extern const ru_field_rec XPORT_TOP_CONTROL_P2_MODE_FIELD; #define XPORT_TOP_CONTROL_P2_MODE_FIELD_MASK 0x0000000000000004ULL #define XPORT_TOP_CONTROL_P2_MODE_FIELD_WIDTH 1 #define XPORT_TOP_CONTROL_P2_MODE_FIELD_SHIFT 2 extern const ru_field_rec XPORT_TOP_CONTROL_P1_MODE_FIELD; #define XPORT_TOP_CONTROL_P1_MODE_FIELD_MASK 0x0000000000000002ULL #define XPORT_TOP_CONTROL_P1_MODE_FIELD_WIDTH 1 #define XPORT_TOP_CONTROL_P1_MODE_FIELD_SHIFT 1 extern const ru_field_rec XPORT_TOP_CONTROL_P0_MODE_FIELD; #define XPORT_TOP_CONTROL_P0_MODE_FIELD_MASK 0x0000000000000001ULL #define XPORT_TOP_CONTROL_P0_MODE_FIELD_WIDTH 1 #define XPORT_TOP_CONTROL_P0_MODE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_TOP_STATUS_RESERVED0_FIELD; #define XPORT_TOP_STATUS_RESERVED0_FIELD_MASK 0x00000000fffffff0ULL #define XPORT_TOP_STATUS_RESERVED0_FIELD_WIDTH 28 #define XPORT_TOP_STATUS_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec XPORT_TOP_STATUS_LINK_STATUS_FIELD; #define XPORT_TOP_STATUS_LINK_STATUS_FIELD_MASK 0x000000000000000fULL #define XPORT_TOP_STATUS_LINK_STATUS_FIELD_WIDTH 4 #define XPORT_TOP_STATUS_LINK_STATUS_FIELD_SHIFT 0 extern const ru_field_rec XPORT_TOP_REVISION_RESERVED0_FIELD; #define XPORT_TOP_REVISION_RESERVED0_FIELD_MASK 0x00000000ff000000ULL #define XPORT_TOP_REVISION_RESERVED0_FIELD_WIDTH 8 #define XPORT_TOP_REVISION_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec XPORT_TOP_REVISION_XPORT_REV_FIELD; #define XPORT_TOP_REVISION_XPORT_REV_FIELD_MASK 0x0000000000ffffffULL #define XPORT_TOP_REVISION_XPORT_REV_FIELD_WIDTH 24 #define XPORT_TOP_REVISION_XPORT_REV_FIELD_SHIFT 0 extern const ru_field_rec XPORT_TOP_SPARE_CNTRL_SPARE_REG_FIELD; #define XPORT_TOP_SPARE_CNTRL_SPARE_REG_FIELD_MASK 0x00000000ffffffffULL #define XPORT_TOP_SPARE_CNTRL_SPARE_REG_FIELD_WIDTH 32 #define XPORT_TOP_SPARE_CNTRL_SPARE_REG_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD; #define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD; #define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK 0x00000000ffffe000ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_ERR_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_ERR_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_R_W_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_R_W_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK 0x0000000000000300ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK 0x00000000000000ffULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK 0x00000000ffffe000ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_ERR_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_ERR_FIELD_MASK 0x0000000000001000ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK 0x0000000000000800ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_R_W_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_R_W_FIELD_MASK 0x0000000000000400ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK 0x0000000000000300ULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK 0x00000000000000ffULL #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8 #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK 0x00000000ffffffffULL #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32 #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_RESERVED0_FIELD; #define XPORT_XLMAC_REG_CONFIG_RESERVED0_FIELD_MASK 0x00000000fffffc00ULL #define XPORT_XLMAC_REG_CONFIG_RESERVED0_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_CONFIG_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_XLMAC_RESET_FIELD; #define XPORT_XLMAC_REG_CONFIG_XLMAC_RESET_FIELD_MASK 0x0000000000000200ULL #define XPORT_XLMAC_REG_CONFIG_XLMAC_RESET_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_XLMAC_RESET_FIELD_SHIFT 9 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD; #define XPORT_XLMAC_REG_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_MASK 0x0000000000000100ULL #define XPORT_XLMAC_REG_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_RX_DUAL_CYCLE_TDM_EN_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD; #define XPORT_XLMAC_REG_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_MASK 0x0000000000000080ULL #define XPORT_XLMAC_REG_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_RX_NON_LINEAR_QUAD_TDM_EN_FIELD_SHIFT 7 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_RX_FLEX_TDM_ENABLE_FIELD; #define XPORT_XLMAC_REG_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_MASK 0x0000000000000040ULL #define XPORT_XLMAC_REG_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_RX_FLEX_TDM_ENABLE_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_MAC_MODE_FIELD; #define XPORT_XLMAC_REG_CONFIG_MAC_MODE_FIELD_MASK 0x0000000000000038ULL #define XPORT_XLMAC_REG_CONFIG_MAC_MODE_FIELD_WIDTH 3 #define XPORT_XLMAC_REG_CONFIG_MAC_MODE_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_OSTS_TIMER_DISABLE_FIELD; #define XPORT_XLMAC_REG_CONFIG_OSTS_TIMER_DISABLE_FIELD_MASK 0x0000000000000004ULL #define XPORT_XLMAC_REG_CONFIG_OSTS_TIMER_DISABLE_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_OSTS_TIMER_DISABLE_FIELD_SHIFT 2 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_BYPASS_OSTS_FIELD; #define XPORT_XLMAC_REG_CONFIG_BYPASS_OSTS_FIELD_MASK 0x0000000000000002ULL #define XPORT_XLMAC_REG_CONFIG_BYPASS_OSTS_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_BYPASS_OSTS_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_REG_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD; #define XPORT_XLMAC_REG_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_REG_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_CONFIG_EGR_1588_TIMESTAMPING_MODE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_INTERRUPT_CHECK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_INTERRUPT_CHECK_RESERVED0_FIELD_MASK 0x00000000fffffff0ULL #define XPORT_XLMAC_REG_INTERRUPT_CHECK_RESERVED0_FIELD_WIDTH 28 #define XPORT_XLMAC_REG_INTERRUPT_CHECK_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_REG_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD; #define XPORT_XLMAC_REG_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_MASK 0x000000000000000fULL #define XPORT_XLMAC_REG_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_WIDTH 4 #define XPORT_XLMAC_REG_INTERRUPT_CHECK_XLMAC_INTR_CHECK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_RSV_ERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RESERVED0_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffff800ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RESERVED0_FIELD_WIDTH 21 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_READ_THRESHOLD_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_READ_THRESHOLD_FIELD_MASK 0x0000000000000700ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_READ_THRESHOLD_FIELD_WIDTH 3 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_READ_THRESHOLD_FIELD_SHIFT 8 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_ID_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_ID_FIELD_MASK 0x00000000000000c0ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_ID_FIELD_WIDTH 2 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_ID_FIELD_SHIFT 6 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_SEL_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_SEL_FIELD_MASK 0x0000000000000020ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_SEL_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_PORT_SEL_FIELD_SHIFT 5 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RXERR_EN_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RXERR_EN_FIELD_MASK 0x0000000000000010ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RXERR_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RXERR_EN_FIELD_SHIFT 4 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_ERR_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_ERR_FIELD_MASK 0x0000000000000008ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_ERR_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_ERR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_MODE_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_MODE_FIELD_MASK 0x0000000000000006ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_MODE_FIELD_WIDTH 2 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_TX_CRC_MODE_FIELD_SHIFT 1 extern const ru_field_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RMT_LOOPBACK_EN_FIELD; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RMT_LOOPBACK_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RMT_LOOPBACK_EN_FIELD_WIDTH 1 #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_RMT_LOOPBACK_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_MIB_RSV_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_MIB_RSV_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_MIB_RSV_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_RESERVED0_FIELD; #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_RESERVED0_FIELD_MASK 0x00000000ffc00000ULL #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_RESERVED0_FIELD_WIDTH 10 #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_MIB_RSV_MASK_FIELD; #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_MASK 0x00000000003fffffULL #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_WIDTH 22 #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_MIB_RSV_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD; #define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_WIDTH 32 #define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_WRITE_DATA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD; #define XPORT_MIB_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_WIDTH 32 #define XPORT_MIB_REG_DIR_ACC_DATA_READ_READ_DATA_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_MASK 0x00000000ffffe000ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_WIDTH 19 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_ERR_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_ERR_FIELD_MASK 0x0000000000001000ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_ERR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_MASK 0x0000000000000800ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_R_W_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_R_W_FIELD_MASK 0x0000000000000400ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_R_W_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_R_W_FIELD_SHIFT 10 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_MASK 0x0000000000000300ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_WIDTH 2 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_MASK 0x00000000000000ffULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_WIDTH 8 #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD; #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_WIDTH 32 #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD; #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_WIDTH 32 #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_MASK 0x00000000ffffe000ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_WIDTH 19 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_ERR_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_ERR_FIELD_MASK 0x0000000000001000ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_ERR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_MASK 0x0000000000000800ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_START_BUSY_FIELD_SHIFT 11 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_R_W_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_R_W_FIELD_MASK 0x0000000000000400ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_R_W_FIELD_WIDTH 1 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_R_W_FIELD_SHIFT 10 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_MASK 0x0000000000000300ULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_WIDTH 2 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_PORT_ID_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_MASK 0x00000000000000ffULL #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_WIDTH 8 #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_OFFSET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD; #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_WIDTH 32 #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_DATA_LOW_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD; #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_MASK 0x00000000ffffffffULL #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_WIDTH 32 #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_DATA_HIGH_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_CONTROL_RESERVED0_FIELD; #define XPORT_MIB_REG_CONTROL_RESERVED0_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_MIB_REG_CONTROL_RESERVED0_FIELD_WIDTH 16 #define XPORT_MIB_REG_CONTROL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_MIB_REG_CONTROL_EEE_CNT_MODE_FIELD; #define XPORT_MIB_REG_CONTROL_EEE_CNT_MODE_FIELD_MASK 0x000000000000f000ULL #define XPORT_MIB_REG_CONTROL_EEE_CNT_MODE_FIELD_WIDTH 4 #define XPORT_MIB_REG_CONTROL_EEE_CNT_MODE_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MIB_REG_CONTROL_SATURATE_EN_FIELD; #define XPORT_MIB_REG_CONTROL_SATURATE_EN_FIELD_MASK 0x0000000000000f00ULL #define XPORT_MIB_REG_CONTROL_SATURATE_EN_FIELD_WIDTH 4 #define XPORT_MIB_REG_CONTROL_SATURATE_EN_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_CONTROL_COR_EN_FIELD; #define XPORT_MIB_REG_CONTROL_COR_EN_FIELD_MASK 0x00000000000000f0ULL #define XPORT_MIB_REG_CONTROL_COR_EN_FIELD_WIDTH 4 #define XPORT_MIB_REG_CONTROL_COR_EN_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MIB_REG_CONTROL_CNT_RST_FIELD; #define XPORT_MIB_REG_CONTROL_CNT_RST_FIELD_MASK 0x000000000000000fULL #define XPORT_MIB_REG_CONTROL_CNT_RST_FIELD_WIDTH 4 #define XPORT_MIB_REG_CONTROL_CNT_RST_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD; #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_MASK 0x00000000ffffff00ULL #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_WIDTH 24 #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_CNT_FIELD; #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_MASK 0x00000000000000ffULL #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_WIDTH 8 #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_CNT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD; #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000ULL #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffULL #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD; #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000ULL #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffULL #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD; #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000ULL #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffULL #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD; #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0x00000000ffffc000ULL #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x0000000000003fffULL #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_ECC_CNTRL_RESERVED0_FIELD; #define XPORT_MIB_REG_ECC_CNTRL_RESERVED0_FIELD_MASK 0x00000000fffffffcULL #define XPORT_MIB_REG_ECC_CNTRL_RESERVED0_FIELD_WIDTH 30 #define XPORT_MIB_REG_ECC_CNTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_ECC_CNTRL_TX_MIB_ECC_EN_FIELD; #define XPORT_MIB_REG_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_WIDTH 1 #define XPORT_MIB_REG_ECC_CNTRL_TX_MIB_ECC_EN_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_ECC_CNTRL_RX_MIB_ECC_EN_FIELD; #define XPORT_MIB_REG_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_WIDTH 1 #define XPORT_MIB_REG_ECC_CNTRL_RX_MIB_ECC_EN_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_RESERVED0_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_RESERVED0_FIELD_MASK 0x00000000fffffe00ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_RESERVED0_FIELD_WIDTH 23 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_MASK 0x0000000000000100ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM3_SERR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_MASK 0x0000000000000080ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM2_SERR_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_MASK 0x0000000000000040ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM1_SERR_FIELD_SHIFT 6 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_MASK 0x0000000000000020ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_TX_MEM0_SERR_FIELD_SHIFT 5 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_MASK 0x0000000000000010ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM4_SERR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_MASK 0x0000000000000008ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM3_SERR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM2_SERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM1_SERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_FORCE_RX_MEM0_SERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_RESERVED0_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_RESERVED0_FIELD_MASK 0x00000000fffffe00ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_RESERVED0_FIELD_WIDTH 23 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_MASK 0x0000000000000100ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM3_DERR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_MASK 0x0000000000000080ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM2_DERR_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_MASK 0x0000000000000040ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM1_DERR_FIELD_SHIFT 6 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_MASK 0x0000000000000020ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_TX_MEM0_DERR_FIELD_SHIFT 5 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_MASK 0x0000000000000010ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM4_DERR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_MASK 0x0000000000000008ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM3_DERR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM2_DERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM1_DERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_FORCE_RX_MEM0_DERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_RESERVED0_FIELD; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_MASK 0x00000000ffffff80ULL #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_WIDTH 25 #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_MASK 0x0000000000000078ULL #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_WIDTH 4 #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MEM_ADDR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_MASK 0x0000000000000004ULL #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_DOUBLE_BIT_ECC_ERR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_MASK 0x0000000000000002ULL #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_MULTI_ECC_ERR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_MASK 0x0000000000000001ULL #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_WIDTH 1 #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_ECC_ERR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_STATUS_RESERVED0_FIELD; #define XPORT_INTR_CPU_STATUS_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_STATUS_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_STATUS_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_STATUS_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_STATUS_LINK_UP_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_STATUS_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_STATUS_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_STATUS_XLMAC_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_STATUS_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_STATUS_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_STATUS_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_STATUS_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_STATUS_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_STATUS_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_CPU_STATUS_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_SET_RESERVED0_FIELD; #define XPORT_INTR_CPU_SET_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_SET_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_SET_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_SET_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_CPU_SET_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_SET_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_SET_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_SET_LINK_UP_INTR_FIELD; #define XPORT_INTR_CPU_SET_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_SET_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_SET_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_SET_XLMAC_INTR_FIELD; #define XPORT_INTR_CPU_SET_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_SET_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_SET_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_SET_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_SET_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_SET_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_CPU_SET_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_SET_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_SET_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_SET_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_SET_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_SET_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_CPU_SET_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_SET_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_SET_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_RESERVED0_FIELD; #define XPORT_INTR_CPU_CLEAR_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_CLEAR_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_CLEAR_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_LINK_UP_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_CLEAR_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_CLEAR_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_XLMAC_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_CLEAR_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_CPU_CLEAR_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_CLEAR_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_CPU_CLEAR_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_CPU_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_RESERVED0_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_MASK_STATUS_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_MASK_STATUS_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_MASK_STATUS_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_STATUS_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_RESERVED0_FIELD; #define XPORT_INTR_CPU_MASK_SET_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_MASK_SET_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_MASK_SET_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_MASK_SET_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_SET_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_RESERVED0_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_CPU_MASK_CLEAR_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_CPU_MASK_CLEAR_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_CPU_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_CPU_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_CPU_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_CPU_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_STATUS_RESERVED0_FIELD; #define XPORT_INTR_PCI_STATUS_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_STATUS_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_STATUS_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_STATUS_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_STATUS_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_STATUS_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_STATUS_LINK_UP_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_STATUS_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_STATUS_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_STATUS_XLMAC_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_STATUS_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_STATUS_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_STATUS_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_STATUS_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_STATUS_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_STATUS_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_STATUS_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_STATUS_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_STATUS_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_STATUS_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_PCI_STATUS_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_STATUS_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_STATUS_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_SET_RESERVED0_FIELD; #define XPORT_INTR_PCI_SET_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_SET_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_SET_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_SET_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_PCI_SET_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_SET_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_SET_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_SET_LINK_UP_INTR_FIELD; #define XPORT_INTR_PCI_SET_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_SET_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_SET_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_SET_XLMAC_INTR_FIELD; #define XPORT_INTR_PCI_SET_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_SET_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_SET_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_SET_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_SET_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_SET_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_SET_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_SET_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_PCI_SET_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_SET_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_SET_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_SET_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_SET_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_SET_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_SET_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_SET_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_PCI_SET_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_SET_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_SET_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_RESERVED0_FIELD; #define XPORT_INTR_PCI_CLEAR_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_CLEAR_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_CLEAR_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_LINK_DOWN_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_LINK_DOWN_INTR_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_CLEAR_LINK_DOWN_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_CLEAR_LINK_DOWN_INTR_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_LINK_UP_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_LINK_UP_INTR_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_CLEAR_LINK_UP_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_CLEAR_LINK_UP_INTR_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_XLMAC_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_XLMAC_INTR_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_CLEAR_XLMAC_INTR_FIELD_WIDTH 4 #define XPORT_INTR_PCI_CLEAR_XLMAC_INTR_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_CLEAR_MAC_REG_ERR_INTR_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_MAB_STATUS_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_MAB_STATUS_INTR_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_CLEAR_MAB_STATUS_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_CLEAR_MAB_STATUS_INTR_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_CLEAR_MIB_REG_ERR_INTR_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_CLEAR_UBUS_ERR_INTR_FIELD; #define XPORT_INTR_PCI_CLEAR_UBUS_ERR_INTR_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_CLEAR_UBUS_ERR_INTR_FIELD_WIDTH 1 #define XPORT_INTR_PCI_CLEAR_UBUS_ERR_INTR_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_RESERVED0_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_MASK_STATUS_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_MASK_STATUS_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_STATUS_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_STATUS_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_STATUS_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_MASK_STATUS_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_STATUS_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_STATUS_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_STATUS_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_STATUS_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_STATUS_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_RESERVED0_FIELD; #define XPORT_INTR_PCI_MASK_SET_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_MASK_SET_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_MASK_SET_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_SET_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_SET_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_SET_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_MASK_SET_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_SET_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_SET_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_SET_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_SET_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_SET_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_RESERVED0_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_RESERVED0_FIELD_MASK 0x00000000fff00000ULL #define XPORT_INTR_PCI_MASK_CLEAR_RESERVED0_FIELD_WIDTH 12 #define XPORT_INTR_PCI_MASK_CLEAR_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_MASK 0x00000000000f0000ULL #define XPORT_INTR_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_CLEAR_LINK_DOWN_INTR_MASK_FIELD_SHIFT 16 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_MASK 0x000000000000f000ULL #define XPORT_INTR_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_CLEAR_LINK_UP_INTR_MASK_FIELD_SHIFT 12 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_MASK 0x0000000000000f00ULL #define XPORT_INTR_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_CLEAR_TX_TIMESYNC_FIFO_ENTRY_VALID_INTR_MASK_FIELD_SHIFT 8 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_XLMAC_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_MASK 0x00000000000000f0ULL #define XPORT_INTR_PCI_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_WIDTH 4 #define XPORT_INTR_PCI_MASK_CLEAR_XLMAC_INTR_MASK_FIELD_SHIFT 4 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000008ULL #define XPORT_INTR_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_CLEAR_MAC_REG_ERR_INTR_MASK_FIELD_SHIFT 3 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_MASK 0x0000000000000004ULL #define XPORT_INTR_PCI_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_CLEAR_MAB_STATUS_INTR_MASK_FIELD_SHIFT 2 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_MASK 0x0000000000000002ULL #define XPORT_INTR_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_CLEAR_MIB_REG_ERR_INTR_MASK_FIELD_SHIFT 1 extern const ru_field_rec XPORT_INTR_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD; #define XPORT_INTR_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_MASK 0x0000000000000001ULL #define XPORT_INTR_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_WIDTH 1 #define XPORT_INTR_PCI_MASK_CLEAR_UBUS_ERR_INTR_MASK_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MAB_CONTROL_RESERVED0_FIELD; #define XPORT_MAB_CONTROL_RESERVED0_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_MAB_CONTROL_RESERVED0_FIELD_WIDTH 16 #define XPORT_MAB_CONTROL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec XPORT_MAB_CONTROL_TX_CREDIT_DISAB_FIELD; #define XPORT_MAB_CONTROL_TX_CREDIT_DISAB_FIELD_MASK 0x000000000000f000ULL #define XPORT_MAB_CONTROL_TX_CREDIT_DISAB_FIELD_WIDTH 4 #define XPORT_MAB_CONTROL_TX_CREDIT_DISAB_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MAB_CONTROL_TX_FIFO_RST_FIELD; #define XPORT_MAB_CONTROL_TX_FIFO_RST_FIELD_MASK 0x0000000000000f00ULL #define XPORT_MAB_CONTROL_TX_FIFO_RST_FIELD_WIDTH 4 #define XPORT_MAB_CONTROL_TX_FIFO_RST_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MAB_CONTROL_TX_PORT_RST_FIELD; #define XPORT_MAB_CONTROL_TX_PORT_RST_FIELD_MASK 0x00000000000000f0ULL #define XPORT_MAB_CONTROL_TX_PORT_RST_FIELD_WIDTH 4 #define XPORT_MAB_CONTROL_TX_PORT_RST_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MAB_CONTROL_RX_PORT_RST_FIELD; #define XPORT_MAB_CONTROL_RX_PORT_RST_FIELD_MASK 0x000000000000000fULL #define XPORT_MAB_CONTROL_RX_PORT_RST_FIELD_WIDTH 4 #define XPORT_MAB_CONTROL_RX_PORT_RST_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD; #define XPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_MASK 0x00000000fffe0000ULL #define XPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_WIDTH 15 #define XPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD; #define XPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_MASK 0x0000000000010000ULL #define XPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_WIDTH 1 #define XPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_SHIFT 16 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_P3_WEIGHT_FIELD; #define XPORT_MAB_TX_WRR_CTRL_P3_WEIGHT_FIELD_MASK 0x000000000000f000ULL #define XPORT_MAB_TX_WRR_CTRL_P3_WEIGHT_FIELD_WIDTH 4 #define XPORT_MAB_TX_WRR_CTRL_P3_WEIGHT_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_P2_WEIGHT_FIELD; #define XPORT_MAB_TX_WRR_CTRL_P2_WEIGHT_FIELD_MASK 0x0000000000000f00ULL #define XPORT_MAB_TX_WRR_CTRL_P2_WEIGHT_FIELD_WIDTH 4 #define XPORT_MAB_TX_WRR_CTRL_P2_WEIGHT_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_P1_WEIGHT_FIELD; #define XPORT_MAB_TX_WRR_CTRL_P1_WEIGHT_FIELD_MASK 0x00000000000000f0ULL #define XPORT_MAB_TX_WRR_CTRL_P1_WEIGHT_FIELD_WIDTH 4 #define XPORT_MAB_TX_WRR_CTRL_P1_WEIGHT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MAB_TX_WRR_CTRL_P0_WEIGHT_FIELD; #define XPORT_MAB_TX_WRR_CTRL_P0_WEIGHT_FIELD_MASK 0x000000000000000fULL #define XPORT_MAB_TX_WRR_CTRL_P0_WEIGHT_FIELD_WIDTH 4 #define XPORT_MAB_TX_WRR_CTRL_P0_WEIGHT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_XGMII3_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_XGMII3_TX_THRESHOLD_FIELD_MASK 0x00000000f0000000ULL #define XPORT_MAB_TX_THRESHOLD_XGMII3_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_XGMII3_TX_THRESHOLD_FIELD_SHIFT 28 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_XGMII2_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_XGMII2_TX_THRESHOLD_FIELD_MASK 0x000000000f000000ULL #define XPORT_MAB_TX_THRESHOLD_XGMII2_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_XGMII2_TX_THRESHOLD_FIELD_SHIFT 24 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_MASK 0x0000000000f00000ULL #define XPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_SHIFT 20 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_XGMII0_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_XGMII0_TX_THRESHOLD_FIELD_MASK 0x00000000000f0000ULL #define XPORT_MAB_TX_THRESHOLD_XGMII0_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_XGMII0_TX_THRESHOLD_FIELD_SHIFT 16 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_GMII3_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_GMII3_TX_THRESHOLD_FIELD_MASK 0x000000000000f000ULL #define XPORT_MAB_TX_THRESHOLD_GMII3_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_GMII3_TX_THRESHOLD_FIELD_SHIFT 12 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_GMII2_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_GMII2_TX_THRESHOLD_FIELD_MASK 0x0000000000000f00ULL #define XPORT_MAB_TX_THRESHOLD_GMII2_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_GMII2_TX_THRESHOLD_FIELD_SHIFT 8 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_GMII1_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_GMII1_TX_THRESHOLD_FIELD_MASK 0x00000000000000f0ULL #define XPORT_MAB_TX_THRESHOLD_GMII1_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_GMII1_TX_THRESHOLD_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MAB_TX_THRESHOLD_GMII0_TX_THRESHOLD_FIELD; #define XPORT_MAB_TX_THRESHOLD_GMII0_TX_THRESHOLD_FIELD_MASK 0x000000000000000fULL #define XPORT_MAB_TX_THRESHOLD_GMII0_TX_THRESHOLD_FIELD_WIDTH 4 #define XPORT_MAB_TX_THRESHOLD_GMII0_TX_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_MAB_STATUS_RESERVED0_FIELD; #define XPORT_MAB_STATUS_RESERVED0_FIELD_MASK 0x00000000f0000000ULL #define XPORT_MAB_STATUS_RESERVED0_FIELD_WIDTH 4 #define XPORT_MAB_STATUS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec XPORT_MAB_STATUS_TX_FRM_UNDERRUN_VECT_FIELD; #define XPORT_MAB_STATUS_TX_FRM_UNDERRUN_VECT_FIELD_MASK 0x000000000f000000ULL #define XPORT_MAB_STATUS_TX_FRM_UNDERRUN_VECT_FIELD_WIDTH 4 #define XPORT_MAB_STATUS_TX_FRM_UNDERRUN_VECT_FIELD_SHIFT 24 extern const ru_field_rec XPORT_MAB_STATUS_TX_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD; #define XPORT_MAB_STATUS_TX_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_MASK 0x0000000000f00000ULL #define XPORT_MAB_STATUS_TX_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_WIDTH 4 #define XPORT_MAB_STATUS_TX_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_SHIFT 20 extern const ru_field_rec XPORT_MAB_STATUS_TX_FIFO_OVERRUN_VECT_FIELD; #define XPORT_MAB_STATUS_TX_FIFO_OVERRUN_VECT_FIELD_MASK 0x00000000000f0000ULL #define XPORT_MAB_STATUS_TX_FIFO_OVERRUN_VECT_FIELD_WIDTH 4 #define XPORT_MAB_STATUS_TX_FIFO_OVERRUN_VECT_FIELD_SHIFT 16 extern const ru_field_rec XPORT_MAB_STATUS_RESERVED1_FIELD; #define XPORT_MAB_STATUS_RESERVED1_FIELD_MASK 0x000000000000fff0ULL #define XPORT_MAB_STATUS_RESERVED1_FIELD_WIDTH 12 #define XPORT_MAB_STATUS_RESERVED1_FIELD_SHIFT 4 extern const ru_field_rec XPORT_MAB_STATUS_RX_FIFO_OVERRUN_VECT_FIELD; #define XPORT_MAB_STATUS_RX_FIFO_OVERRUN_VECT_FIELD_MASK 0x000000000000000fULL #define XPORT_MAB_STATUS_RX_FIFO_OVERRUN_VECT_FIELD_WIDTH 4 #define XPORT_MAB_STATUS_RX_FIFO_OVERRUN_VECT_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_CTRL_RESERVED0_FIELD; #define XPORT_PORTRESET_P0_CTRL_RESERVED0_FIELD_MASK 0x00000000fffffffeULL #define XPORT_PORTRESET_P0_CTRL_RESERVED0_FIELD_WIDTH 31 #define XPORT_PORTRESET_P0_CTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P0_CTRL_PORT_SW_RESET_FIELD; #define XPORT_PORTRESET_P0_CTRL_PORT_SW_RESET_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P0_CTRL_PORT_SW_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_CTRL_PORT_SW_RESET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_CTRL_RESERVED0_FIELD; #define XPORT_PORTRESET_P1_CTRL_RESERVED0_FIELD_MASK 0x00000000fffffffeULL #define XPORT_PORTRESET_P1_CTRL_RESERVED0_FIELD_WIDTH 31 #define XPORT_PORTRESET_P1_CTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P1_CTRL_PORT_SW_RESET_FIELD; #define XPORT_PORTRESET_P1_CTRL_PORT_SW_RESET_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P1_CTRL_PORT_SW_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_CTRL_PORT_SW_RESET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_CTRL_RESERVED0_FIELD; #define XPORT_PORTRESET_P2_CTRL_RESERVED0_FIELD_MASK 0x00000000fffffffeULL #define XPORT_PORTRESET_P2_CTRL_RESERVED0_FIELD_WIDTH 31 #define XPORT_PORTRESET_P2_CTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P2_CTRL_PORT_SW_RESET_FIELD; #define XPORT_PORTRESET_P2_CTRL_PORT_SW_RESET_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P2_CTRL_PORT_SW_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_CTRL_PORT_SW_RESET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_CTRL_RESERVED0_FIELD; #define XPORT_PORTRESET_P3_CTRL_RESERVED0_FIELD_MASK 0x00000000fffffffeULL #define XPORT_PORTRESET_P3_CTRL_RESERVED0_FIELD_WIDTH 31 #define XPORT_PORTRESET_P3_CTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P3_CTRL_PORT_SW_RESET_FIELD; #define XPORT_PORTRESET_P3_CTRL_PORT_SW_RESET_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P3_CTRL_PORT_SW_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_CTRL_PORT_SW_RESET_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_CONFIG_RESERVED0_FIELD; #define XPORT_PORTRESET_CONFIG_RESERVED0_FIELD_MASK 0x00000000ff000000ULL #define XPORT_PORTRESET_CONFIG_RESERVED0_FIELD_WIDTH 8 #define XPORT_PORTRESET_CONFIG_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec XPORT_PORTRESET_CONFIG_LINK_DOWN_RST_EN_FIELD; #define XPORT_PORTRESET_CONFIG_LINK_DOWN_RST_EN_FIELD_MASK 0x0000000000f00000ULL #define XPORT_PORTRESET_CONFIG_LINK_DOWN_RST_EN_FIELD_WIDTH 4 #define XPORT_PORTRESET_CONFIG_LINK_DOWN_RST_EN_FIELD_SHIFT 20 extern const ru_field_rec XPORT_PORTRESET_CONFIG_ENABLE_SM_RUN_FIELD; #define XPORT_PORTRESET_CONFIG_ENABLE_SM_RUN_FIELD_MASK 0x00000000000f0000ULL #define XPORT_PORTRESET_CONFIG_ENABLE_SM_RUN_FIELD_WIDTH 4 #define XPORT_PORTRESET_CONFIG_ENABLE_SM_RUN_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_CONFIG_TICK_TIMER_NDIV_FIELD; #define XPORT_PORTRESET_CONFIG_TICK_TIMER_NDIV_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_CONFIG_TICK_TIMER_NDIV_FIELD_WIDTH 16 #define XPORT_PORTRESET_CONFIG_TICK_TIMER_NDIV_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD; #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_MASK 0x00000000fffe0000ULL #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_WIDTH 15 #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD; #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_MASK 0x0000000000010000ULL #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD; #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD; #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_MASK 0x00000000fffe0000ULL #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_WIDTH 15 #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD; #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_MASK 0x0000000000010000ULL #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD; #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD; #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_MASK 0x00000000fffe0000ULL #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_WIDTH 15 #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD; #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_MASK 0x0000000000010000ULL #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD; #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD; #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_MASK 0x00000000fffe0000ULL #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_WIDTH 15 #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD; #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_MASK 0x0000000000010000ULL #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DISABLE_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD; #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_DEBOUNCE_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_RESERVED0_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_RESERVED0_FIELD_MASK 0x00000000fffffc00ULL #define XPORT_PORTRESET_P0_SIG_EN_RESERVED0_FIELD_WIDTH 22 #define XPORT_PORTRESET_P0_SIG_EN_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_MASK 0x0000000000000200ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_SHIFT 9 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_MASK 0x0000000000000100ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_SHIFT 8 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_MASK 0x0000000000000080ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_SHIFT 7 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_MASK 0x0000000000000040ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_MASK 0x0000000000000020ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_SHIFT 5 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_MASK 0x0000000000000010ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_MASK 0x0000000000000008ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_SHIFT 3 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_MASK 0x0000000000000004ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_SHIFT 2 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_MASK 0x0000000000000002ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD; #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P0_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_RESERVED0_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_RESERVED0_FIELD_MASK 0x00000000fffffc00ULL #define XPORT_PORTRESET_P1_SIG_EN_RESERVED0_FIELD_WIDTH 22 #define XPORT_PORTRESET_P1_SIG_EN_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_MASK 0x0000000000000200ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_SHIFT 9 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_MASK 0x0000000000000100ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_SHIFT 8 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_MASK 0x0000000000000080ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_SHIFT 7 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_MASK 0x0000000000000040ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_MASK 0x0000000000000020ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_SHIFT 5 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_MASK 0x0000000000000010ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_MASK 0x0000000000000008ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_SHIFT 3 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_MASK 0x0000000000000004ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_SHIFT 2 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_MASK 0x0000000000000002ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD; #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P1_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_RESERVED0_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_RESERVED0_FIELD_MASK 0x00000000fffffc00ULL #define XPORT_PORTRESET_P2_SIG_EN_RESERVED0_FIELD_WIDTH 22 #define XPORT_PORTRESET_P2_SIG_EN_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_MASK 0x0000000000000200ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_SHIFT 9 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_MASK 0x0000000000000100ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_SHIFT 8 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_MASK 0x0000000000000080ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_SHIFT 7 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_MASK 0x0000000000000040ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_MASK 0x0000000000000020ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_SHIFT 5 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_MASK 0x0000000000000010ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_MASK 0x0000000000000008ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_SHIFT 3 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_MASK 0x0000000000000004ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_SHIFT 2 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_MASK 0x0000000000000002ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD; #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P2_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_RESERVED0_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_RESERVED0_FIELD_MASK 0x00000000fffffc00ULL #define XPORT_PORTRESET_P3_SIG_EN_RESERVED0_FIELD_WIDTH 22 #define XPORT_PORTRESET_P3_SIG_EN_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_MASK 0x0000000000000200ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_RX_DISAB_FIELD_SHIFT 9 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_MASK 0x0000000000000100ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISAB_FIELD_SHIFT 8 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_MASK 0x0000000000000080ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_TX_DISCARD_FIELD_SHIFT 7 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_MASK 0x0000000000000040ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_SOFT_RESET_FIELD_SHIFT 6 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_MASK 0x0000000000000020ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_RX_PORT_INIT_FIELD_SHIFT 5 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_MASK 0x0000000000000010ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_PORT_INIT_FIELD_SHIFT 4 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_MASK 0x0000000000000008ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_CREDIT_DISAB_FIELD_SHIFT 3 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_MASK 0x0000000000000004ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_MAB_TX_FIFO_INIT_FIELD_SHIFT 2 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_MASK 0x0000000000000002ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_PORT_IS_UNDER_RESET_FIELD_SHIFT 1 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD; #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_MASK 0x0000000000000001ULL #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_WIDTH 1 #define XPORT_PORTRESET_P3_SIG_EN_ENABLE_XLMAC_EP_DISCARD_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_RX_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_XLMAC_TX_DISAB_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_TXDISCARD_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_XLMAC_SOFT_RESET_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_RX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_MAB_TX_PORT_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_MAB_TX_FIFO_INIT_ASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_PORT_IS_UNDER_RESET_ASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_RX_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_XLMAC_TX_DISAB_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_TXDISCARD_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_XLMAC_SOFT_RESET_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_RX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_MAB_TX_PORT_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_CREDIT_DISAB_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_MAB_TX_FIFO_INIT_DEASSERT_TIME_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_MASK 0x00000000ffff0000ULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_PORT_IS_UNDER_RESET_DEASSERT_TIME_FIELD_SHIFT 16 extern const ru_field_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_MASK 0x000000000000ffffULL #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_WIDTH 16 #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec XPORT_PORTRESET_DEBUG_RESERVED0_FIELD; #define XPORT_PORTRESET_DEBUG_RESERVED0_FIELD_MASK 0x00000000ffffff00ULL #define XPORT_PORTRESET_DEBUG_RESERVED0_FIELD_WIDTH 24 #define XPORT_PORTRESET_DEBUG_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec XPORT_PORTRESET_DEBUG_P3_SM_STATE_FIELD; #define XPORT_PORTRESET_DEBUG_P3_SM_STATE_FIELD_MASK 0x00000000000000c0ULL #define XPORT_PORTRESET_DEBUG_P3_SM_STATE_FIELD_WIDTH 2 #define XPORT_PORTRESET_DEBUG_P3_SM_STATE_FIELD_SHIFT 6 extern const ru_field_rec XPORT_PORTRESET_DEBUG_P2_SM_STATE_FIELD; #define XPORT_PORTRESET_DEBUG_P2_SM_STATE_FIELD_MASK 0x0000000000000030ULL #define XPORT_PORTRESET_DEBUG_P2_SM_STATE_FIELD_WIDTH 2 #define XPORT_PORTRESET_DEBUG_P2_SM_STATE_FIELD_SHIFT 4 extern const ru_field_rec XPORT_PORTRESET_DEBUG_P1_SM_STATE_FIELD; #define XPORT_PORTRESET_DEBUG_P1_SM_STATE_FIELD_MASK 0x000000000000000cULL #define XPORT_PORTRESET_DEBUG_P1_SM_STATE_FIELD_WIDTH 2 #define XPORT_PORTRESET_DEBUG_P1_SM_STATE_FIELD_SHIFT 2 extern const ru_field_rec XPORT_PORTRESET_DEBUG_P0_SM_STATE_FIELD; #define XPORT_PORTRESET_DEBUG_P0_SM_STATE_FIELD_MASK 0x0000000000000003ULL #define XPORT_PORTRESET_DEBUG_P0_SM_STATE_FIELD_WIDTH 2 #define XPORT_PORTRESET_DEBUG_P0_SM_STATE_FIELD_SHIFT 0 /****************************************************************************** * Registers ******************************************************************************/ extern const ru_reg_rec XPORT_XLMAC_CORE_CTRL_REG; #define XPORT_XLMAC_CORE_CTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_XLMAC_CORE_MODE_REG; #define XPORT_XLMAC_CORE_MODE_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_XLMAC_CORE_SPARE0_REG; #define XPORT_XLMAC_CORE_SPARE0_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_XLMAC_CORE_SPARE1_REG; #define XPORT_XLMAC_CORE_SPARE1_REG_OFFSET 0x00000018 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_CTRL_REG; #define XPORT_XLMAC_CORE_TX_CTRL_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_MAC_SA_REG; #define XPORT_XLMAC_CORE_TX_MAC_SA_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_CTRL_REG; #define XPORT_XLMAC_CORE_RX_CTRL_REG_OFFSET 0x00000030 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_MAC_SA_REG; #define XPORT_XLMAC_CORE_RX_MAC_SA_REG_OFFSET 0x00000038 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_MAX_SIZE_REG; #define XPORT_XLMAC_CORE_RX_MAX_SIZE_REG_OFFSET 0x00000040 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_VLAN_TAG_REG; #define XPORT_XLMAC_CORE_RX_VLAN_TAG_REG_OFFSET 0x00000048 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_LSS_CTRL_REG; #define XPORT_XLMAC_CORE_RX_LSS_CTRL_REG_OFFSET 0x00000050 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_LSS_STATUS_REG; #define XPORT_XLMAC_CORE_RX_LSS_STATUS_REG_OFFSET 0x00000058 extern const ru_reg_rec XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_REG; #define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_REG_OFFSET 0x00000060 extern const ru_reg_rec XPORT_XLMAC_CORE_PAUSE_CTRL_REG; #define XPORT_XLMAC_CORE_PAUSE_CTRL_REG_OFFSET 0x00000068 extern const ru_reg_rec XPORT_XLMAC_CORE_PFC_CTRL_REG; #define XPORT_XLMAC_CORE_PFC_CTRL_REG_OFFSET 0x00000070 extern const ru_reg_rec XPORT_XLMAC_CORE_PFC_TYPE_REG; #define XPORT_XLMAC_CORE_PFC_TYPE_REG_OFFSET 0x00000078 extern const ru_reg_rec XPORT_XLMAC_CORE_PFC_OPCODE_REG; #define XPORT_XLMAC_CORE_PFC_OPCODE_REG_OFFSET 0x00000080 extern const ru_reg_rec XPORT_XLMAC_CORE_PFC_DA_REG; #define XPORT_XLMAC_CORE_PFC_DA_REG_OFFSET 0x00000088 extern const ru_reg_rec XPORT_XLMAC_CORE_LLFC_CTRL_REG; #define XPORT_XLMAC_CORE_LLFC_CTRL_REG_OFFSET 0x00000090 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_REG; #define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_REG_OFFSET 0x00000098 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_REG; #define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_REG_OFFSET 0x000000a0 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_REG; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_REG_OFFSET 0x000000a8 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_REG; #define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_REG_OFFSET 0x000000b0 extern const ru_reg_rec XPORT_XLMAC_CORE_FIFO_STATUS_REG; #define XPORT_XLMAC_CORE_FIFO_STATUS_REG_OFFSET 0x000000b8 extern const ru_reg_rec XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_REG; #define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_REG_OFFSET 0x000000c0 extern const ru_reg_rec XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_REG; #define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_REG_OFFSET 0x000000c8 extern const ru_reg_rec XPORT_XLMAC_CORE_EEE_CTRL_REG; #define XPORT_XLMAC_CORE_EEE_CTRL_REG_OFFSET 0x000000d0 extern const ru_reg_rec XPORT_XLMAC_CORE_EEE_TIMERS_REG; #define XPORT_XLMAC_CORE_EEE_TIMERS_REG_OFFSET 0x000000d8 extern const ru_reg_rec XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_REG; #define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_REG_OFFSET 0x000000e0 extern const ru_reg_rec XPORT_XLMAC_CORE_HIGIG_HDR_0_REG; #define XPORT_XLMAC_CORE_HIGIG_HDR_0_REG_OFFSET 0x000000e8 extern const ru_reg_rec XPORT_XLMAC_CORE_HIGIG_HDR_1_REG; #define XPORT_XLMAC_CORE_HIGIG_HDR_1_REG_OFFSET 0x000000f0 extern const ru_reg_rec XPORT_XLMAC_CORE_GMII_EEE_CTRL_REG; #define XPORT_XLMAC_CORE_GMII_EEE_CTRL_REG_OFFSET 0x000000f8 extern const ru_reg_rec XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_REG; #define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_REG_OFFSET 0x00000100 extern const ru_reg_rec XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_REG; #define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_REG_OFFSET 0x00000108 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_REG; #define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_REG_OFFSET 0x00000110 extern const ru_reg_rec XPORT_XLMAC_CORE_E2E_CTRL_REG; #define XPORT_XLMAC_CORE_E2E_CTRL_REG_OFFSET 0x00000118 extern const ru_reg_rec XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_REG; #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_REG_OFFSET 0x00000120 extern const ru_reg_rec XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_REG; #define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_REG_OFFSET 0x00000128 extern const ru_reg_rec XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_REG; #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_REG_OFFSET 0x00000130 extern const ru_reg_rec XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_REG; #define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_REG_OFFSET 0x00000138 extern const ru_reg_rec XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_REG; #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_REG_OFFSET 0x00000140 extern const ru_reg_rec XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_REG; #define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_REG_OFFSET 0x00000148 extern const ru_reg_rec XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_REG; #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_REG_OFFSET 0x00000150 extern const ru_reg_rec XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_REG; #define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_REG_OFFSET 0x00000158 extern const ru_reg_rec XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_REG; #define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_REG_OFFSET 0x00000160 extern const ru_reg_rec XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REG; #define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REG_OFFSET 0x00000168 extern const ru_reg_rec XPORT_XLMAC_CORE_MEM_CTRL_REG; #define XPORT_XLMAC_CORE_MEM_CTRL_REG_OFFSET 0x00000170 extern const ru_reg_rec XPORT_XLMAC_CORE_ECC_CTRL_REG; #define XPORT_XLMAC_CORE_ECC_CTRL_REG_OFFSET 0x00000178 extern const ru_reg_rec XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_REG; #define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_REG_OFFSET 0x00000180 extern const ru_reg_rec XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_REG; #define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_REG_OFFSET 0x00000188 extern const ru_reg_rec XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_REG; #define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_REG_OFFSET 0x00000190 extern const ru_reg_rec XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_REG; #define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_REG_OFFSET 0x00000198 extern const ru_reg_rec XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_REG; #define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_REG_OFFSET 0x000001a0 extern const ru_reg_rec XPORT_XLMAC_CORE_INTR_STATUS_REG; #define XPORT_XLMAC_CORE_INTR_STATUS_REG_OFFSET 0x000001a8 extern const ru_reg_rec XPORT_XLMAC_CORE_INTR_ENABLE_REG; #define XPORT_XLMAC_CORE_INTR_ENABLE_REG_OFFSET 0x000001b0 extern const ru_reg_rec XPORT_XLMAC_CORE_VERSION_ID_REG; #define XPORT_XLMAC_CORE_VERSION_ID_REG_OFFSET 0x000001b8 extern const ru_reg_rec XPORT_MIB_CORE_GRX64_REG; #define XPORT_MIB_CORE_GRX64_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_MIB_CORE_GRX127_REG; #define XPORT_MIB_CORE_GRX127_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_MIB_CORE_GRX255_REG; #define XPORT_MIB_CORE_GRX255_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_MIB_CORE_GRX511_REG; #define XPORT_MIB_CORE_GRX511_REG_OFFSET 0x00000018 extern const ru_reg_rec XPORT_MIB_CORE_GRX1023_REG; #define XPORT_MIB_CORE_GRX1023_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_MIB_CORE_GRX1518_REG; #define XPORT_MIB_CORE_GRX1518_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_MIB_CORE_GRX1522_REG; #define XPORT_MIB_CORE_GRX1522_REG_OFFSET 0x00000030 extern const ru_reg_rec XPORT_MIB_CORE_GRX2047_REG; #define XPORT_MIB_CORE_GRX2047_REG_OFFSET 0x00000038 extern const ru_reg_rec XPORT_MIB_CORE_GRX4095_REG; #define XPORT_MIB_CORE_GRX4095_REG_OFFSET 0x00000040 extern const ru_reg_rec XPORT_MIB_CORE_GRX9216_REG; #define XPORT_MIB_CORE_GRX9216_REG_OFFSET 0x00000048 extern const ru_reg_rec XPORT_MIB_CORE_GRX16383_REG; #define XPORT_MIB_CORE_GRX16383_REG_OFFSET 0x00000050 extern const ru_reg_rec XPORT_MIB_CORE_GRXPKT_REG; #define XPORT_MIB_CORE_GRXPKT_REG_OFFSET 0x00000058 extern const ru_reg_rec XPORT_MIB_CORE_GRXUCA_REG; #define XPORT_MIB_CORE_GRXUCA_REG_OFFSET 0x00000060 extern const ru_reg_rec XPORT_MIB_CORE_GRXMCA_REG; #define XPORT_MIB_CORE_GRXMCA_REG_OFFSET 0x00000068 extern const ru_reg_rec XPORT_MIB_CORE_GRXBCA_REG; #define XPORT_MIB_CORE_GRXBCA_REG_OFFSET 0x00000070 extern const ru_reg_rec XPORT_MIB_CORE_GRXFCS_REG; #define XPORT_MIB_CORE_GRXFCS_REG_OFFSET 0x00000078 extern const ru_reg_rec XPORT_MIB_CORE_GRXCF_REG; #define XPORT_MIB_CORE_GRXCF_REG_OFFSET 0x00000080 extern const ru_reg_rec XPORT_MIB_CORE_GRXPF_REG; #define XPORT_MIB_CORE_GRXPF_REG_OFFSET 0x00000088 extern const ru_reg_rec XPORT_MIB_CORE_GRXPP_REG; #define XPORT_MIB_CORE_GRXPP_REG_OFFSET 0x00000090 extern const ru_reg_rec XPORT_MIB_CORE_GRXUO_REG; #define XPORT_MIB_CORE_GRXUO_REG_OFFSET 0x00000098 extern const ru_reg_rec XPORT_MIB_CORE_GRXUDA_REG; #define XPORT_MIB_CORE_GRXUDA_REG_OFFSET 0x000000a0 extern const ru_reg_rec XPORT_MIB_CORE_GRXWSA_REG; #define XPORT_MIB_CORE_GRXWSA_REG_OFFSET 0x000000a8 extern const ru_reg_rec XPORT_MIB_CORE_GRXALN_REG; #define XPORT_MIB_CORE_GRXALN_REG_OFFSET 0x000000b0 extern const ru_reg_rec XPORT_MIB_CORE_GRXFLR_REG; #define XPORT_MIB_CORE_GRXFLR_REG_OFFSET 0x000000b8 extern const ru_reg_rec XPORT_MIB_CORE_GRXFRERR_REG; #define XPORT_MIB_CORE_GRXFRERR_REG_OFFSET 0x000000c0 extern const ru_reg_rec XPORT_MIB_CORE_GRXFCR_REG; #define XPORT_MIB_CORE_GRXFCR_REG_OFFSET 0x000000c8 extern const ru_reg_rec XPORT_MIB_CORE_GRXOVR_REG; #define XPORT_MIB_CORE_GRXOVR_REG_OFFSET 0x000000d0 extern const ru_reg_rec XPORT_MIB_CORE_GRXJBR_REG; #define XPORT_MIB_CORE_GRXJBR_REG_OFFSET 0x000000d8 extern const ru_reg_rec XPORT_MIB_CORE_GRXMTUE_REG; #define XPORT_MIB_CORE_GRXMTUE_REG_OFFSET 0x000000e0 extern const ru_reg_rec XPORT_MIB_CORE_GRXMCRC_REG; #define XPORT_MIB_CORE_GRXMCRC_REG_OFFSET 0x000000e8 extern const ru_reg_rec XPORT_MIB_CORE_GRXPRM_REG; #define XPORT_MIB_CORE_GRXPRM_REG_OFFSET 0x000000f0 extern const ru_reg_rec XPORT_MIB_CORE_GRXVLN_REG; #define XPORT_MIB_CORE_GRXVLN_REG_OFFSET 0x000000f8 extern const ru_reg_rec XPORT_MIB_CORE_GRXDVLN_REG; #define XPORT_MIB_CORE_GRXDVLN_REG_OFFSET 0x00000100 extern const ru_reg_rec XPORT_MIB_CORE_GRXTRFU_REG; #define XPORT_MIB_CORE_GRXTRFU_REG_OFFSET 0x00000108 extern const ru_reg_rec XPORT_MIB_CORE_GRXPOK_REG; #define XPORT_MIB_CORE_GRXPOK_REG_OFFSET 0x00000110 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF0_REG; #define XPORT_MIB_CORE_GRXPFCOFF0_REG_OFFSET 0x00000118 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF1_REG; #define XPORT_MIB_CORE_GRXPFCOFF1_REG_OFFSET 0x00000120 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF2_REG; #define XPORT_MIB_CORE_GRXPFCOFF2_REG_OFFSET 0x00000128 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF3_REG; #define XPORT_MIB_CORE_GRXPFCOFF3_REG_OFFSET 0x00000130 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF4_REG; #define XPORT_MIB_CORE_GRXPFCOFF4_REG_OFFSET 0x00000138 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF5_REG; #define XPORT_MIB_CORE_GRXPFCOFF5_REG_OFFSET 0x00000140 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF6_REG; #define XPORT_MIB_CORE_GRXPFCOFF6_REG_OFFSET 0x00000148 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCOFF7_REG; #define XPORT_MIB_CORE_GRXPFCOFF7_REG_OFFSET 0x00000150 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP0_REG; #define XPORT_MIB_CORE_GRXPFCP0_REG_OFFSET 0x00000158 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP1_REG; #define XPORT_MIB_CORE_GRXPFCP1_REG_OFFSET 0x00000160 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP2_REG; #define XPORT_MIB_CORE_GRXPFCP2_REG_OFFSET 0x00000168 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP3_REG; #define XPORT_MIB_CORE_GRXPFCP3_REG_OFFSET 0x00000170 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP4_REG; #define XPORT_MIB_CORE_GRXPFCP4_REG_OFFSET 0x00000178 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP5_REG; #define XPORT_MIB_CORE_GRXPFCP5_REG_OFFSET 0x00000180 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP6_REG; #define XPORT_MIB_CORE_GRXPFCP6_REG_OFFSET 0x00000188 extern const ru_reg_rec XPORT_MIB_CORE_GRXPFCP7_REG; #define XPORT_MIB_CORE_GRXPFCP7_REG_OFFSET 0x00000190 extern const ru_reg_rec XPORT_MIB_CORE_GRXSCHCRC_REG; #define XPORT_MIB_CORE_GRXSCHCRC_REG_OFFSET 0x00000198 extern const ru_reg_rec XPORT_MIB_CORE_GRXBYT_REG; #define XPORT_MIB_CORE_GRXBYT_REG_OFFSET 0x000001a0 extern const ru_reg_rec XPORT_MIB_CORE_GRXRPKT_REG; #define XPORT_MIB_CORE_GRXRPKT_REG_OFFSET 0x000001a8 extern const ru_reg_rec XPORT_MIB_CORE_GRXUND_REG; #define XPORT_MIB_CORE_GRXUND_REG_OFFSET 0x000001b0 extern const ru_reg_rec XPORT_MIB_CORE_GRXFRG_REG; #define XPORT_MIB_CORE_GRXFRG_REG_OFFSET 0x000001b8 extern const ru_reg_rec XPORT_MIB_CORE_GRXRBYT_REG; #define XPORT_MIB_CORE_GRXRBYT_REG_OFFSET 0x000001c0 extern const ru_reg_rec XPORT_MIB_CORE_GTX64_REG; #define XPORT_MIB_CORE_GTX64_REG_OFFSET 0x000001c8 extern const ru_reg_rec XPORT_MIB_CORE_GTX127_REG; #define XPORT_MIB_CORE_GTX127_REG_OFFSET 0x000001d0 extern const ru_reg_rec XPORT_MIB_CORE_GTX255_REG; #define XPORT_MIB_CORE_GTX255_REG_OFFSET 0x000001d8 extern const ru_reg_rec XPORT_MIB_CORE_GTX511_REG; #define XPORT_MIB_CORE_GTX511_REG_OFFSET 0x000001e0 extern const ru_reg_rec XPORT_MIB_CORE_GTX1023_REG; #define XPORT_MIB_CORE_GTX1023_REG_OFFSET 0x000001e8 extern const ru_reg_rec XPORT_MIB_CORE_GTX1518_REG; #define XPORT_MIB_CORE_GTX1518_REG_OFFSET 0x000001f0 extern const ru_reg_rec XPORT_MIB_CORE_GTX1522_REG; #define XPORT_MIB_CORE_GTX1522_REG_OFFSET 0x000001f8 extern const ru_reg_rec XPORT_MIB_CORE_GTX2047_REG; #define XPORT_MIB_CORE_GTX2047_REG_OFFSET 0x00000200 extern const ru_reg_rec XPORT_MIB_CORE_GTX4095_REG; #define XPORT_MIB_CORE_GTX4095_REG_OFFSET 0x00000208 extern const ru_reg_rec XPORT_MIB_CORE_GTX9216_REG; #define XPORT_MIB_CORE_GTX9216_REG_OFFSET 0x00000210 extern const ru_reg_rec XPORT_MIB_CORE_GTX16383_REG; #define XPORT_MIB_CORE_GTX16383_REG_OFFSET 0x00000218 extern const ru_reg_rec XPORT_MIB_CORE_GTXPOK_REG; #define XPORT_MIB_CORE_GTXPOK_REG_OFFSET 0x00000220 extern const ru_reg_rec XPORT_MIB_CORE_GTXPKT_REG; #define XPORT_MIB_CORE_GTXPKT_REG_OFFSET 0x00000228 extern const ru_reg_rec XPORT_MIB_CORE_GTXUCA_REG; #define XPORT_MIB_CORE_GTXUCA_REG_OFFSET 0x00000230 extern const ru_reg_rec XPORT_MIB_CORE_GTXMCA_REG; #define XPORT_MIB_CORE_GTXMCA_REG_OFFSET 0x00000238 extern const ru_reg_rec XPORT_MIB_CORE_GTXBCA_REG; #define XPORT_MIB_CORE_GTXBCA_REG_OFFSET 0x00000240 extern const ru_reg_rec XPORT_MIB_CORE_GTXPF_REG; #define XPORT_MIB_CORE_GTXPF_REG_OFFSET 0x00000248 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFC_REG; #define XPORT_MIB_CORE_GTXPFC_REG_OFFSET 0x00000250 extern const ru_reg_rec XPORT_MIB_CORE_GTXJBR_REG; #define XPORT_MIB_CORE_GTXJBR_REG_OFFSET 0x00000258 extern const ru_reg_rec XPORT_MIB_CORE_GTXFCS_REG; #define XPORT_MIB_CORE_GTXFCS_REG_OFFSET 0x00000260 extern const ru_reg_rec XPORT_MIB_CORE_GTXCF_REG; #define XPORT_MIB_CORE_GTXCF_REG_OFFSET 0x00000268 extern const ru_reg_rec XPORT_MIB_CORE_GTXOVR_REG; #define XPORT_MIB_CORE_GTXOVR_REG_OFFSET 0x00000270 extern const ru_reg_rec XPORT_MIB_CORE_GTXDFR_REG; #define XPORT_MIB_CORE_GTXDFR_REG_OFFSET 0x00000278 extern const ru_reg_rec XPORT_MIB_CORE_GTXEDF_REG; #define XPORT_MIB_CORE_GTXEDF_REG_OFFSET 0x00000280 extern const ru_reg_rec XPORT_MIB_CORE_GTXSCL_REG; #define XPORT_MIB_CORE_GTXSCL_REG_OFFSET 0x00000288 extern const ru_reg_rec XPORT_MIB_CORE_GTXMCL_REG; #define XPORT_MIB_CORE_GTXMCL_REG_OFFSET 0x00000290 extern const ru_reg_rec XPORT_MIB_CORE_GTXLCL_REG; #define XPORT_MIB_CORE_GTXLCL_REG_OFFSET 0x00000298 extern const ru_reg_rec XPORT_MIB_CORE_GTXXCL_REG; #define XPORT_MIB_CORE_GTXXCL_REG_OFFSET 0x000002a0 extern const ru_reg_rec XPORT_MIB_CORE_GTXFRG_REG; #define XPORT_MIB_CORE_GTXFRG_REG_OFFSET 0x000002a8 extern const ru_reg_rec XPORT_MIB_CORE_GTXERR_REG; #define XPORT_MIB_CORE_GTXERR_REG_OFFSET 0x000002b0 extern const ru_reg_rec XPORT_MIB_CORE_GTXVLN_REG; #define XPORT_MIB_CORE_GTXVLN_REG_OFFSET 0x000002b8 extern const ru_reg_rec XPORT_MIB_CORE_GTXDVLN_REG; #define XPORT_MIB_CORE_GTXDVLN_REG_OFFSET 0x000002c0 extern const ru_reg_rec XPORT_MIB_CORE_GTXRPKT_REG; #define XPORT_MIB_CORE_GTXRPKT_REG_OFFSET 0x000002c8 extern const ru_reg_rec XPORT_MIB_CORE_GTXUFL_REG; #define XPORT_MIB_CORE_GTXUFL_REG_OFFSET 0x000002d0 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP0_REG; #define XPORT_MIB_CORE_GTXPFCP0_REG_OFFSET 0x000002d8 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP1_REG; #define XPORT_MIB_CORE_GTXPFCP1_REG_OFFSET 0x000002e0 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP2_REG; #define XPORT_MIB_CORE_GTXPFCP2_REG_OFFSET 0x000002e8 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP3_REG; #define XPORT_MIB_CORE_GTXPFCP3_REG_OFFSET 0x000002f0 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP4_REG; #define XPORT_MIB_CORE_GTXPFCP4_REG_OFFSET 0x000002f8 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP5_REG; #define XPORT_MIB_CORE_GTXPFCP5_REG_OFFSET 0x00000300 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP6_REG; #define XPORT_MIB_CORE_GTXPFCP6_REG_OFFSET 0x00000308 extern const ru_reg_rec XPORT_MIB_CORE_GTXPFCP7_REG; #define XPORT_MIB_CORE_GTXPFCP7_REG_OFFSET 0x00000310 extern const ru_reg_rec XPORT_MIB_CORE_GTXNCL_REG; #define XPORT_MIB_CORE_GTXNCL_REG_OFFSET 0x00000318 extern const ru_reg_rec XPORT_MIB_CORE_GTXBYT_REG; #define XPORT_MIB_CORE_GTXBYT_REG_OFFSET 0x00000320 extern const ru_reg_rec XPORT_MIB_CORE_GRXLPI_REG; #define XPORT_MIB_CORE_GRXLPI_REG_OFFSET 0x00000328 extern const ru_reg_rec XPORT_MIB_CORE_GRXDLPI_REG; #define XPORT_MIB_CORE_GRXDLPI_REG_OFFSET 0x00000330 extern const ru_reg_rec XPORT_MIB_CORE_GTXLPI_REG; #define XPORT_MIB_CORE_GTXLPI_REG_OFFSET 0x00000338 extern const ru_reg_rec XPORT_MIB_CORE_GTXDLPI_REG; #define XPORT_MIB_CORE_GTXDLPI_REG_OFFSET 0x00000340 extern const ru_reg_rec XPORT_MIB_CORE_GRXPTLLFC_REG; #define XPORT_MIB_CORE_GRXPTLLFC_REG_OFFSET 0x00000348 extern const ru_reg_rec XPORT_MIB_CORE_GRXLTLLFC_REG; #define XPORT_MIB_CORE_GRXLTLLFC_REG_OFFSET 0x00000350 extern const ru_reg_rec XPORT_MIB_CORE_GRXLLFCFCS_REG; #define XPORT_MIB_CORE_GRXLLFCFCS_REG_OFFSET 0x00000358 extern const ru_reg_rec XPORT_MIB_CORE_GTXLTLLFC_REG; #define XPORT_MIB_CORE_GTXLTLLFC_REG_OFFSET 0x00000360 extern const ru_reg_rec XPORT_TOP_CONTROL_REG; #define XPORT_TOP_CONTROL_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_TOP_STATUS_REG; #define XPORT_TOP_STATUS_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_TOP_REVISION_REG; #define XPORT_TOP_REVISION_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_TOP_SPARE_CNTRL_REG; #define XPORT_TOP_SPARE_CNTRL_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG; #define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG; #define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_REG; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_REG; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG; #define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014 extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_REG; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018 extern const ru_reg_rec XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_REG; #define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c extern const ru_reg_rec XPORT_XLMAC_REG_CONFIG_REG; #define XPORT_XLMAC_REG_CONFIG_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_XLMAC_REG_INTERRUPT_CHECK_REG; #define XPORT_XLMAC_REG_INTERRUPT_CHECK_REG_OFFSET 0x00000024 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_0_RXERR_MASK_REG; #define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_1_RXERR_MASK_REG; #define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_REG_OFFSET 0x0000002c extern const ru_reg_rec XPORT_XLMAC_REG_PORT_2_RXERR_MASK_REG; #define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_REG_OFFSET 0x00000030 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_3_RXERR_MASK_REG; #define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_REG_OFFSET 0x00000034 extern const ru_reg_rec XPORT_XLMAC_REG_RMT_LPBK_CNTRL_REG; #define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_REG_OFFSET 0x00000038 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_REG; #define XPORT_XLMAC_REG_PORT_0_MIB_RSV_MASK_REG_OFFSET 0x0000003c extern const ru_reg_rec XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_REG; #define XPORT_XLMAC_REG_PORT_1_MIB_RSV_MASK_REG_OFFSET 0x00000040 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_REG; #define XPORT_XLMAC_REG_PORT_2_MIB_RSV_MASK_REG_OFFSET 0x00000044 extern const ru_reg_rec XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_REG; #define XPORT_XLMAC_REG_PORT_3_MIB_RSV_MASK_REG_OFFSET 0x00000048 extern const ru_reg_rec XPORT_MIB_REG_DIR_ACC_DATA_WRITE_REG; #define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_MIB_REG_DIR_ACC_DATA_READ_REG; #define XPORT_MIB_REG_DIR_ACC_DATA_READ_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG; #define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_REG; #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_REG; #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG; #define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG_OFFSET 0x00000014 extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_REG; #define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_REG_OFFSET 0x00000018 extern const ru_reg_rec XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_REG; #define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_REG_OFFSET 0x0000001c extern const ru_reg_rec XPORT_MIB_REG_CONTROL_REG; #define XPORT_MIB_REG_CONTROL_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_REG; #define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_REG_OFFSET 0x00000024 extern const ru_reg_rec XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_REG; #define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_REG; #define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_REG_OFFSET 0x0000002c extern const ru_reg_rec XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_REG; #define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_REG_OFFSET 0x00000030 extern const ru_reg_rec XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_REG; #define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_REG_OFFSET 0x00000034 extern const ru_reg_rec XPORT_MIB_REG_ECC_CNTRL_REG; #define XPORT_MIB_REG_ECC_CNTRL_REG_OFFSET 0x00000038 extern const ru_reg_rec XPORT_MIB_REG_FORCE_SB_ECC_ERR_REG; #define XPORT_MIB_REG_FORCE_SB_ECC_ERR_REG_OFFSET 0x0000003c extern const ru_reg_rec XPORT_MIB_REG_FORCE_DB_ECC_ERR_REG; #define XPORT_MIB_REG_FORCE_DB_ECC_ERR_REG_OFFSET 0x00000040 extern const ru_reg_rec XPORT_MIB_REG_RX_MEM0_ECC_STATUS_REG; #define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_REG_OFFSET 0x00000044 extern const ru_reg_rec XPORT_MIB_REG_RX_MEM1_ECC_STATUS_REG; #define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_REG_OFFSET 0x00000048 extern const ru_reg_rec XPORT_MIB_REG_RX_MEM2_ECC_STATUS_REG; #define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_REG_OFFSET 0x0000004c extern const ru_reg_rec XPORT_MIB_REG_RX_MEM3_ECC_STATUS_REG; #define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_REG_OFFSET 0x00000050 extern const ru_reg_rec XPORT_MIB_REG_RX_MEM4_ECC_STATUS_REG; #define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_REG_OFFSET 0x00000054 extern const ru_reg_rec XPORT_MIB_REG_TX_MEM0_ECC_STATUS_REG; #define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_REG_OFFSET 0x00000058 extern const ru_reg_rec XPORT_MIB_REG_TX_MEM1_ECC_STATUS_REG; #define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_REG_OFFSET 0x0000005c extern const ru_reg_rec XPORT_MIB_REG_TX_MEM2_ECC_STATUS_REG; #define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_REG_OFFSET 0x00000060 extern const ru_reg_rec XPORT_MIB_REG_TX_MEM3_ECC_STATUS_REG; #define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_REG_OFFSET 0x00000064 extern const ru_reg_rec XPORT_INTR_CPU_STATUS_REG; #define XPORT_INTR_CPU_STATUS_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_INTR_CPU_SET_REG; #define XPORT_INTR_CPU_SET_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_INTR_CPU_CLEAR_REG; #define XPORT_INTR_CPU_CLEAR_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_INTR_CPU_MASK_STATUS_REG; #define XPORT_INTR_CPU_MASK_STATUS_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_INTR_CPU_MASK_SET_REG; #define XPORT_INTR_CPU_MASK_SET_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_INTR_CPU_MASK_CLEAR_REG; #define XPORT_INTR_CPU_MASK_CLEAR_REG_OFFSET 0x00000014 extern const ru_reg_rec XPORT_INTR_PCI_STATUS_REG; #define XPORT_INTR_PCI_STATUS_REG_OFFSET 0x00000018 extern const ru_reg_rec XPORT_INTR_PCI_SET_REG; #define XPORT_INTR_PCI_SET_REG_OFFSET 0x0000001c extern const ru_reg_rec XPORT_INTR_PCI_CLEAR_REG; #define XPORT_INTR_PCI_CLEAR_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_INTR_PCI_MASK_STATUS_REG; #define XPORT_INTR_PCI_MASK_STATUS_REG_OFFSET 0x00000024 extern const ru_reg_rec XPORT_INTR_PCI_MASK_SET_REG; #define XPORT_INTR_PCI_MASK_SET_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_INTR_PCI_MASK_CLEAR_REG; #define XPORT_INTR_PCI_MASK_CLEAR_REG_OFFSET 0x0000002c extern const ru_reg_rec XPORT_MAB_CONTROL_REG; #define XPORT_MAB_CONTROL_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_MAB_TX_WRR_CTRL_REG; #define XPORT_MAB_TX_WRR_CTRL_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_MAB_TX_THRESHOLD_REG; #define XPORT_MAB_TX_THRESHOLD_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_MAB_STATUS_REG; #define XPORT_MAB_STATUS_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_PORTRESET_P0_CTRL_REG; #define XPORT_PORTRESET_P0_CTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec XPORT_PORTRESET_P1_CTRL_REG; #define XPORT_PORTRESET_P1_CTRL_REG_OFFSET 0x00000004 extern const ru_reg_rec XPORT_PORTRESET_P2_CTRL_REG; #define XPORT_PORTRESET_P2_CTRL_REG_OFFSET 0x00000008 extern const ru_reg_rec XPORT_PORTRESET_P3_CTRL_REG; #define XPORT_PORTRESET_P3_CTRL_REG_OFFSET 0x0000000c extern const ru_reg_rec XPORT_PORTRESET_CONFIG_REG; #define XPORT_PORTRESET_CONFIG_REG_OFFSET 0x00000010 extern const ru_reg_rec XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_REG; #define XPORT_PORTRESET_P0_LINK_STAT_DEBOUNCE_CFG_REG_OFFSET 0x00000020 extern const ru_reg_rec XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_REG; #define XPORT_PORTRESET_P1_LINK_STAT_DEBOUNCE_CFG_REG_OFFSET 0x00000024 extern const ru_reg_rec XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_REG; #define XPORT_PORTRESET_P2_LINK_STAT_DEBOUNCE_CFG_REG_OFFSET 0x00000028 extern const ru_reg_rec XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_REG; #define XPORT_PORTRESET_P3_LINK_STAT_DEBOUNCE_CFG_REG_OFFSET 0x0000002c extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_EN_REG; #define XPORT_PORTRESET_P0_SIG_EN_REG_OFFSET 0x00000030 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_0_REG_OFFSET 0x00000034 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_1_REG_OFFSET 0x00000038 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_2_REG_OFFSET 0x0000003c extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_3_REG_OFFSET 0x00000040 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P0_SIG_ASSERT_TIMES_4_REG_OFFSET 0x00000044 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_0_REG_OFFSET 0x00000048 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_1_REG_OFFSET 0x0000004c extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_2_REG_OFFSET 0x00000050 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_3_REG_OFFSET 0x00000054 extern const ru_reg_rec XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P0_SIG_DEASSERT_TIMES_4_REG_OFFSET 0x00000058 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_EN_REG; #define XPORT_PORTRESET_P1_SIG_EN_REG_OFFSET 0x00000060 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_0_REG_OFFSET 0x00000064 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_1_REG_OFFSET 0x00000068 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_2_REG_OFFSET 0x0000006c extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_3_REG_OFFSET 0x00000070 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P1_SIG_ASSERT_TIMES_4_REG_OFFSET 0x00000074 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_0_REG_OFFSET 0x00000078 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_1_REG_OFFSET 0x0000007c extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_2_REG_OFFSET 0x00000080 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_3_REG_OFFSET 0x00000084 extern const ru_reg_rec XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P1_SIG_DEASSERT_TIMES_4_REG_OFFSET 0x00000088 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_EN_REG; #define XPORT_PORTRESET_P2_SIG_EN_REG_OFFSET 0x00000090 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_0_REG_OFFSET 0x00000094 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_1_REG_OFFSET 0x00000098 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_2_REG_OFFSET 0x0000009c extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_3_REG_OFFSET 0x000000a0 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P2_SIG_ASSERT_TIMES_4_REG_OFFSET 0x000000a4 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_0_REG_OFFSET 0x000000a8 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_1_REG_OFFSET 0x000000ac extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_2_REG_OFFSET 0x000000b0 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_3_REG_OFFSET 0x000000b4 extern const ru_reg_rec XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P2_SIG_DEASSERT_TIMES_4_REG_OFFSET 0x000000b8 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_EN_REG; #define XPORT_PORTRESET_P3_SIG_EN_REG_OFFSET 0x000000c0 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_0_REG_OFFSET 0x000000c4 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_1_REG_OFFSET 0x000000c8 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_2_REG_OFFSET 0x000000cc extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_3_REG_OFFSET 0x000000d0 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P3_SIG_ASSERT_TIMES_4_REG_OFFSET 0x000000d4 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_REG; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_0_REG_OFFSET 0x000000d8 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_REG; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_1_REG_OFFSET 0x000000dc extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_REG; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_2_REG_OFFSET 0x000000e0 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_REG; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_3_REG_OFFSET 0x000000e4 extern const ru_reg_rec XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_REG; #define XPORT_PORTRESET_P3_SIG_DEASSERT_TIMES_4_REG_OFFSET 0x000000e8 extern const ru_reg_rec XPORT_PORTRESET_DEBUG_REG; #define XPORT_PORTRESET_DEBUG_REG_OFFSET 0x000000f0 /****************************************************************************** * Blocks ******************************************************************************/ extern const ru_block_rec XPORT_XLMAC_CORE_BLOCK; extern const ru_block_rec XPORT_MIB_CORE_BLOCK; extern const ru_block_rec XPORT_TOP_BLOCK; extern const ru_block_rec XPORT_XLMAC_REG_BLOCK; extern const ru_block_rec XPORT_MIB_REG_BLOCK; extern const ru_block_rec XPORT_INTR_BLOCK; extern const ru_block_rec XPORT_MAB_BLOCK; extern const ru_block_rec XPORT_PORTRESET_BLOCK; extern const ru_block_rec *RU_XPORT_BLOCKS[]; #define RU_BLK_COUNT 8 #define RU_REG_COUNT 284 #define RU_FLD_COUNT 802 #endif /* End of file .h */