/* <:copyright-BRCM:2013:DUAL/GPL:standard Copyright (c) 2013 Broadcom All Rights Reserved Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Not withstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. :> */ #ifndef __BCM63148_MAP_PART_H #define __BCM63148_MAP_PART_H #ifdef __cplusplus extern "C" { #endif #include "bcmtypes.h" #include "bcm_io_map.h" #if !defined(REG_BASE) #define REG_BASE 0x80000000 #endif #if !defined(PER_BASE) #define PER_BASE 0xfffe0000 #endif #define CHIP_FAMILY_ID_HEX 0x63148 #define PERF_PHYS_BASE (PER_BASE + 0x00008000) /* chip control */ #define TIMR_PHYS_BASE (PER_BASE + 0x00008080) /* timer registers */ #define NAND_INTR_PHYS_BASE (PER_BASE + 0x000080f0) /* NAND int register */ #define GPIO_PHYS_BASE (PER_BASE + 0x00008100) /* gpio registers */ #define I2C_BASE (PER_BASE + 0x0000be00) /* I2C regsiters */ #define MISC_PHYS_BASE (PER_BASE + 0x00008180) /* Miscellaneous Registers */ #define SOTP_PHYS_BASE (PER_BASE + 0x00008200) /* SOTP register */ #define PKA_PHYS_BASE (PER_BASE + 0x00008280) #define RNG_PHYS_BASE (PER_BASE + 0x00008300) #define UART0_PHYS_BASE (PER_BASE + 0x00008600) /* uart registers */ #define UART_PHYS_BASE UART0_PHYS_BASE #define UART1_PHYS_BASE (PER_BASE + 0x00008620) /* uart registers */ #define LED_PHYS_BASE (PER_BASE + 0x00008700) /* LED control registers */ #define I2S_PHYS_BASE (PER_BASE + 0x00008900) #define AES0_PHYS_BASE (PER_BASE + 0x00008980) #define AES1_PHYS_BASE (PER_BASE + 0x00008a00) #define HSSPIM_PHYS_BASE (PER_BASE + 0x00009000) /* High-Speed SPI registers */ #define NAND_REG_PHYS_BASE (PER_BASE + 0x0000a000) /* nand interrupt control */ #define NAND_CACHE_PHYS_BASE (PER_BASE + 0x0000a400) #define JTAG_OTP_PHYS_BASE (PER_BASE + 0x0000bb00) #define JTAG_IOTP_PHYS_BASE (PER_BASE + 0x0000bd00) #define BOOTLUT_PHYS_BASE (PER_BASE + 0x00010000) /*TODO change the naming of usbdevice regs to USB20D */ #define USB_CTL_PHYS_BASE (REG_BASE + 0x00001000) /* USB 2.0 device control */ #define USB_DMA_PHYS_BASE (REG_BASE + 0x00001800) /* USB 2.0 device DMA registers */ #define MEMC_PHYS_BASE (REG_BASE + 0x00002000) /* DDR IO Buf Control */ #define MEMC_BASE_OFF_4K (MEMC_PHYS_BASE + 0x00001000) #define DDRPHY_PHYS_BASE (REG_BASE + 0x00003000) #define SAR_PHYS_BASE (REG_BASE + 0x00004000) #define SAR_DMA_PHYS_BASE (REG_BASE + 0x00007800) /* ATM SAR DMA control */ #define SATA_PHYS_BASE (REG_BASE + 0x00008000) #define USBH_PHYS_BASE (REG_BASE + 0x0000c000) #define USBH_CFG_PHYS_BASE (REG_BASE + 0x0000c200) #define USB_EHCI_PHYS_BASE (REG_BASE + 0x0000c300) /* USB host registers */ #define USB_OHCI_PHYS_BASE (REG_BASE + 0x0000c400) /* USB host registers */ #define USB_XHCI_PHYS_BASE (REG_BASE + 0x0000d000) /* USB host registers */ #define USB_XHCI1_PHYS_BASE (REG_BASE + 0x0000e000) /* USB host registers */ #define ERROR_PORT_PHYS_BASE (REG_BASE + 0x00010000) #define AIP_PHYS_BASE (REG_BASE + 0x00018000) #define B15_CTRL_PHYS_BASE (REG_BASE + 0x00020000) #define B15_PHYS_BASE (REG_BASE + 0x00030000) #define GICD_PHYS_BASE (REG_BASE + 0x00031000) #define GICC_PHYS_BASE (REG_BASE + 0x00032000) #define DECT_PHYS_BASE (REG_BASE + 0x00040000) #define DECT_AHB_REG_PHYS_BASE DECT_PHYS_BASE #define DECT_SHIM_CTRL_PHYS_BASE (REG_BASE + 0x00050000) #define DECT_SHIM_DMA_CTRL_PHYS_BASE (REG_BASE + 0x00050050) #define DECT_APB_REG_PHYS_BASE (REG_BASE + 0x00050800) #define PCIE0_PHYS_BASE (REG_BASE + 0x00060000) #define PCIE1_PHYS_BASE (REG_BASE + 0x00070000) #define SF2_PHYS_BASE (REG_BASE + 0x00080000) #define SWITCH_PHYS_BASE SF2_PHYS_BASE #define APM_PHYS_BASE (REG_BASE + 0x00100000) #define RDP_PHYS_BASE (REG_BASE + 0x00200000) #define PMC_PHYS_BASE (REG_BASE + 0x00400000) #define PROC_MON_PHYS_BASE (REG_BASE + 0x00480000) #define DSLPHY_PHYS_BASE (REG_BASE + 0x00600000) #define DSLPHY_PHYS_TXPAF_BASE (REG_BASE + 0x00656800) #define DSLPHY_AFE_PHYS_BASE (REG_BASE + 0x00657300) #define DSLLMEM_PHYS_BASE (REG_BASE + 0x00700000) #define PCIE0_MEM_PHYS_BASE 0x90000000 #define PCIE0_MEM_SIZE 0x10000000 #define PCIE1_MEM_PHYS_BASE 0xa0000000 #define PCIE1_MEM_SIZE 0x10000000 /* Physical address for all the registers */ #define SPIFLASH_PHYS_BASE 0xffd00000 /* spi flash direct access address */ #define NANDFLASH_PHYS_BASE 0xffe00000 /* nand flash direct access address */ /* Physical and access(could be virtual or physical) bases address for * all the registers */ #define SPIFLASH_BASE BCM_IO_ADDR(SPIFLASH_PHYS_BASE) #define NANDFLASH_BASE BCM_IO_ADDR(NANDFLASH_PHYS_BASE) #define PERF_BASE BCM_IO_ADDR(PERF_PHYS_BASE) #define TIMR_BASE BCM_IO_ADDR(TIMR_PHYS_BASE) #define NAND_INTR_BASE BCM_IO_ADDR(NAND_INTR_PHYS_BASE) #define GPIO_BASE BCM_IO_ADDR(GPIO_PHYS_BASE) #define MISC_BASE BCM_IO_ADDR(MISC_PHYS_BASE) #define SOTP_BASE BCM_IO_ADDR(SOTP_PHYS_BASE) #define PKA_BASE BCM_IO_ADDR(PKA_PHYS_BASE) #define RNG_BASE BCM_IO_ADDR(RNG_PHYS_BASE) #define UART0_BASE BCM_IO_ADDR(UART0_PHYS_BASE) #define UART_BASE UART0_BASE #define UART1_BASE BCM_IO_ADDR(UART1_PHYS_BASE) #define LED_BASE BCM_IO_ADDR(LED_PHYS_BASE) #define I2S_BASE BCM_IO_ADDR(I2S_PHYS_BASE) #define AES0_BASE BCM_IO_ADDR(AES0_PHYS_BASE) #define AES1_BASE BCM_IO_ADDR(AES1_PHYS_BASE) #define HSSPIM_BASE BCM_IO_ADDR(HSSPIM_PHYS_BASE) #define NAND_REG_BASE BCM_IO_ADDR(NAND_REG_PHYS_BASE) #define NAND_CACHE_BASE BCM_IO_ADDR(NAND_CACHE_PHYS_BASE) #define BROM_SEC_BASE BCM_IO_ADDR(BROM_SEC_PHYS_BASE) #define SRAM_SEC_BASE BCM_IO_ADDR(SRAM_SEC_PHYS_BASE) #define PER_SEC_BASE BCM_IO_ADDR(PER_SEC_PHYS_BASE) #define JTAG_OTP_BASE BCM_IO_ADDR(JTAG_OTP_PHYS_BASE) #define JTAG_IOTP_BASE BCM_IO_ADDR(JTAG_IOTP_PHYS_BASE) #define BOOTLUT_BASE BCM_IO_ADDR(BOOTLUT_PHYS_BASE) /*TODO keep the naming convention same as RDB */ #define USB_CTL_BASE BCM_IO_ADDR(USB_CTL_PHYS_BASE) #define USB_DMA_BASE BCM_IO_ADDR(USB_DMA_PHYS_BASE) #define MEMC_BASE BCM_IO_ADDR(MEMC_PHYS_BASE) #define DDRPHY_BASE BCM_IO_ADDR(DDRPHY_PHYS_BASE) #define SAR_BASE BCM_IO_ADDR(SAR_PHYS_BASE) #define SAR_DMA_BASE BCM_IO_ADDR(SAR_DMA_PHYS_BASE) #define SATA_BASE BCM_IO_ADDR(SATA_PHYS_BASE) #define USBH_BASE BCM_IO_ADDR(USBH_PHYS_BASE) #define USBH_CFG_BASE BCM_IO_ADDR(USBH_CFG_PHYS_BASE) #define USB_EHCI_BASE BCM_IO_ADDR(USB_EHCI_PHYS_BASE) #define USB_OHCI_BASE BCM_IO_ADDR(USB_OHCI_PHYS_BASE) #define USB_XHCI_BASE BCM_IO_ADDR(USB_XHCI_PHYS_BASE) #define USB_XHCI1_BASE BCM_IO_ADDR(USB_XHCI1_PHYS_BASE) #define ERROR_PORT_BASE BCM_IO_ADDR(ERROR_PORT_PHYS_BASE) #define B15_CTRL_BASE BCM_IO_ADDR(B15_CTRL_PHYS_BASE) #define B15_BASE BCM_IO_ADDR(B15_PHYS_BASE) #define GICC_BASE BCM_IO_ADDR(GICC_PHYS_BASE) #define GICD_BASE BCM_IO_ADDR(GICD_PHYS_BASE) #define SWITCH_BASE BCM_IO_ADDR(SF2_PHYS_BASE) #define SWITCH_REG_BASE (SWITCH_BASE + 0x40000UL) #define SWITCH_DIRECT_DATA_WR_REG (SWITCH_REG_BASE + 0x00008UL) #define SWITCH_DIRECT_DATA_RD_REG (SWITCH_REG_BASE + 0x0000cUL) #define SWITCH_CROSSBAR_REG (SWITCH_REG_BASE + 0x000acUL) #define SWITCH_MDIO_BASE (SWITCH_BASE + SWITCH_MDIO_OFFSET) #define SWITCH_ACB_BASE (SWITCH_BASE + 0x40600UL) #define APM_BASE BCM_IO_ADDR(APM_PHYS_BASE) #define RDP_BASE BCM_IO_ADDR(RDP_PHYS_BASE) #if defined(_ATF_) #define PMC_BASE BCM_IO_ADDR(PMC_PHYS_BASE) #define PROC_MON_BASE BCM_IO_ADDR(PROC_MON_PHYS_BASE) #endif #define DSLPHY_BASE BCM_IO_ADDR(DSLPHY_PHYS_BASE) #define DSLPHY_AFE_BASE BCM_IO_ADDR(DSLPHY_AFE_PHYS_BASE) #define DSLLMEM_BASE BCM_IO_ADDR(DSLLMEM_PHYS_BASE) #define TXPAF_PROCESSOR_BASE BCM_IO_ADDR(DSLPHY_PHYS_TXPAF_BASE) #ifndef __ASSEMBLER__ typedef struct UBUSInterface { uint32 CFG; /* 0x00 */ #define UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT 0x0 #define UBUSIF_CFG_WRITE_REPLY_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_REPLY_MODE_SHIFT) #define UBUSIF_CFG_WRITE_BURST_MODE_SHIFT 0x1 #define UBUSIF_CFG_WRITE_BURST_MODE_MASK (0x1<< UBUSIF_CFG_WRITE_BURST_MODE_SHIFT) #define UBUSIF_CFG_INBAND_ERR_MASK_SHIFT 0x2 #define UBUSIF_CFG_INBAND_ERR_MASK_MASK (0x1<< UBUSIF_CFG_INBAND_ERR_MASK_SHIFT) #define UBUSIF_CFG_OOB_ERR_MASK_SHIFT 0x3 #define UBUSIF_CFG_OOB_ERR_MASK_MASK (0x1<< UBUSIF_CFG_OOB_ERR_MASK_SHIFT) uint32 SRC_QUEUE_CTRL_0; /* 0x04 */ uint32 SRC_QUEUE_CTRL_1; /* 0x08 */ uint32 SRC_QUEUE_CTRL_2; /* 0x0c */ uint32 SRC_QUEUE_CTRL_3; /* 0x10 */ uint32 REP_ARB_MODE; /* 0x14 */ #define UBUSIF_REP_ARB_MODE_FIFO_MODE_SHIFT 0x0 #define UBUSIF_REP_ARB_MODE_FIFO_MODE_MASK (0x1<> 5) & 0x07) : (0)) #define GPIO_NUM_TO_MASK(X) ((((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << (((X) & BP_GPIO_NUM_MASK) & 0x1f)) : (0)) #define GPIO_NUM_TO_ARRAY_SHIFT(X) (((X) & BP_GPIO_NUM_MASK) & 0x1f) /* * Misc Register Set Definitions. */ typedef struct Misc { #define MISC_PCIE_CTRL_CORE_SOFT_RESET_MASK (0x3) uint32 miscPCIECtrl; /* 0x00 */ uint32 miscStrapBus; /* 0x04 */ #define MISC_STRAP_BUS_SW_RESERVE_1 (0x3 << 24) #define MISC_STRAP_BUS_BISR_MEM_REPAIR (1 << 23) #define MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT 22 #define MISC_STRAP_BUS_RESET_OUT_DELAY_MASK (1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_RESET_OUT_DELAY_100MS (1 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_RESET_OUT_DELAY_50MS (0x0 << MISC_STRAP_BUS_RESET_OUT_DELAY_SHIFT) #define MISC_STRAP_BUS_SYS_BUS_FREQ (0x3 << 20) #define MISC_STRAP_BUS_A9_CORE0_BOOT (1 << 19) #define MISC_STRAP_BUS_PMC_BOOT_FLASH_N (1 << 18) #define MISC_STRAP_BUS_PMC_BOOT_AVS (1 << 17) #define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR (1 << 16) #define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST (1 << 15) #define MISC_STRAP_BUS_SW_RESERVE_0 (0x7 << 12) #define MISC_STRAP_BUS_B15_START_SLOW_FREQ (1 << 11) #define MISC_STRAP_BUS_PMC_ROM_BOOT_SHIFT 10 #define MISC_STRAP_BUS_PMC_ROM_BOOT (1< thresh, txfifophy_test_ctrl)) #define SPHY_CNTRL ((volatile unsigned int*)(ÐSW_REG->sphy_ctrl)) #define QPHY_CNTRL ((volatile unsigned int*)(ÐSW_REG->qphy_ctrl)) typedef struct EthernetSwitchMDIO { uint32 mdio_cmd; /* 0x0000 */ #define ETHSW_MDIO_BUSY (1 << 29) #define ETHSW_MDIO_FAIL (1 << 28) #define ETHSW_MDIO_CMD_SHIFT 26 #define ETHSW_MDIO_CMD_MASK (0x3<status3) + (x)/32) >> ((x) % 32) & 1) #define BTRM_OTP_READ_TIMEOUT_CNT 0x10000 /* row 17 */ #define OTP_BRCM_BTRM_BOOT_ENABLE_ROW 17 #define OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT 3 #define OTP_BRCM_BTRM_BOOT_ENABLE_MASK (1 << OTP_BRCM_BTRM_BOOT_ENABLE_SHIFT) #define OTP_BRCM_MEK_MIV_ROW 17 #define OTP_BRCM_MEK_MIV_SHIFT 7 #define OTP_BRCM_MEK_MIV_MASK (7 << OTP_BRCM_MEK_MIV_SHIFT) /* row 18 */ #define OTP_CUST_BTRM_BOOT_ENABLE_ROW 18 #define OTP_CUST_BTRM_BOOT_ENABLE_SHIFT 15 #define OTP_CUST_BTRM_BOOT_ENABLE_MASK (7 << OTP_CUST_BTRM_BOOT_ENABLE_SHIFT) /* row 24 */ #define OTP_CUST_MFG_MRKTID_ROW 24 #define OTP_CUST_MFG_MRKTID_SHIFT 0 #define OTP_CUST_MFG_MRKTID_MASK (0xffff << OTP_CUST_MFG_MRKTID_SHIFT) #define OTP_CUST_OP_INUSE_ROW 24 #define OTP_CUST_OP_INUSE_SHIFT 16 #define OTP_CUST_OP_INUSE_MASK (1 << OTP_CUST_OP_INUSE_SHIFT) /* row 25 */ #define OTP_CUST_OP_MRKTID_ROW 25 #define OTP_CUST_OP_MRKTID_SHIFT 0 #define OTP_CUST_OP_MRKTID_MASK (0xffff << OTP_CUST_OP_MRKTID_SHIFT) #endif #endif