#define GIC_DIST_BASE	0x81001000
#define GIC_CPUI_BASE	0x81002000

#define TIMER_HYP_PPI			10
#define TIMER_VIRT_PPI			11
#define TIMER_PHYS_SECURE_PPI		13
#define TIMER_PHYS_NONSECURE_PPI	14

#define PMU_CORE0_SPI			9
#define PMU_CORE1_SPI			10
#define PMU_CORE2_SPI			11
#define PMU_CORE3_SPI			12
#define SDIO_EMMC_SPI			85
#define SPU_GMAC_SPI			90
#define EMMC_DDR_1_8V

#include "bcm_b53_template.dtsi"

/ {   
	/* according to inclusion rules of device tree */
	reserved-memory {
#if defined (CONFIG_BCM_RDPA)
		dt_reserved_buffer {
			reg = <0x0 DRAM_OFFSET_RDP_PARAM1 0x0 RDP_PARAM1_DDR_SIZE>;
		};
		dt_reserved_flow {
			reg = <0x0 DRAM_OFFSET_RDP_PARAM2 0x0 RDP_PARAM2_DDR_SIZE>;
			no-map;
		};
#endif
	};

	/* Legacy UBUS base */
	ubus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x0 0x0 0xff800000 0x0 0x8000>;

		nand@ff801800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
			reg = <0x0 0x1800 0x0 0x600>, <0x0 0x2000 0x0 0x10>;
			reg-names = "nand", "nand-int-base";
			status = "okay";

			nandcs@0 {
				compatible = "brcm,nandcs";
				reg = <0>;
				nand-on-flash-bbt;
			};

		};

		watchdog@ff800428 {
			compatible = "brcm,bcm96xxx-wdt";
			reg = <0x0 0x428 0x0 0x10>;
			timeout-sec = <80>;
		};
	};

	pdc0: spu-pdc@0x8001c000 {
		compatible = "brcm,pdc";
		reg = <0x00000000 0x8001c000 0x00000000 0x448>;
		interrupts = <GIC_SPI SPU_GMAC_SPI IRQ_TYPE_LEVEL_HIGH>;
	};

	spu-crypto@0x8001d000 {
		compatible = "brcm,spu-crypto";
		reg = <0x00000000 0x8001d000 0x00000000 0x64>;
		brcm,num_spu = <1>;
		brcm,num_chan = <1>;
	};
	
	therm0: brcm-therm {
		compatible = "brcm,therm";
	};

};