/* Copyright (c) 2015 Broadcom All Rights Reserved <:label-BRCM:2015:DUAL/GPL:standard Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Not withstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. :> */ #ifndef _XRDP_AG_H_ #define _XRDP_AG_H_ #include "ru.h" /****************************************************************************** * XRDP_ Fields ******************************************************************************/ extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_MASK 0x00000002 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_MASK 0x00000004 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_FIELD_SHIFT 2 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_MASK 0x000000f8 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_MASK 0x00000100 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_MASK 0x00000200 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_FIELD_SHIFT 9 extern const ru_field_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_MASK 0xfffffc00 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_WIDTH 22 #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_MASK 0x00000002 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_MASK 0x00000004 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_FIELD_SHIFT 2 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_MASK 0x00000008 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_FIELD_SHIFT 3 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_MASK 0x00000010 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_FIELD_SHIFT 4 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_MASK 0x00000020 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_FIELD_SHIFT 5 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_MASK 0x00000040 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_FIELD_SHIFT 6 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_MASK 0x00000080 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_FIELD_SHIFT 7 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_MASK 0x00000100 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_MASK 0x00000200 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_FIELD_SHIFT 9 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_MASK 0x00000400 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_FIELD_SHIFT 10 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_MASK 0x00000800 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_FIELD_SHIFT 11 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_MASK 0x00001000 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_FIELD_SHIFT 12 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_MASK 0x00002000 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_FIELD_SHIFT 13 extern const ru_field_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_MASK 0xffffc000 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_WIDTH 18 #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABL_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABL_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABL_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABL_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENAB_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENAB_FIELD_MASK 0x00000002 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENAB_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENAB_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SE_FIELD_MASK 0x00000004 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SE_FIELD_SHIFT 2 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_S_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_S_FIELD_MASK 0x00000008 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_S_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_S_FIELD_SHIFT 3 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_MASK 0x00000010 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_FIELD_SHIFT 4 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_MASK 0x00000020 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_FIELD_SHIFT 5 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_MASK 0x00000040 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_FIELD_SHIFT 6 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_MASK 0x00000080 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_FIELD_SHIFT 7 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_MASK 0x00000100 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_MASK 0x00000200 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_FIELD_SHIFT 9 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_MASK 0x00000400 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_FIELD_SHIFT 10 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECIS_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECIS_FIELD_MASK 0x00000800 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECIS_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECIS_FIELD_SHIFT 11 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECIS_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECIS_FIELD_MASK 0x00001000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECIS_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECIS_FIELD_SHIFT 12 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_MASK 0x00002000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_FIELD_SHIFT 13 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_D_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_D_FIELD_MASK 0x00004000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_D_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_D_FIELD_SHIFT 14 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MEC_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MEC_FIELD_MASK 0x00008000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MEC_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MEC_FIELD_SHIFT 15 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_MASK 0x00010000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_MASK 0x00020000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_FIELD_SHIFT 17 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_MASK 0x00040000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_FIELD_SHIFT 18 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_A_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_A_FIELD_MASK 0x00080000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_A_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_A_FIELD_SHIFT 19 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_MASK 0x00100000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_FIELD_SHIFT 20 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_MASK 0x00200000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_FIELD_SHIFT 21 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_MASK 0x00400000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_FIELD_SHIFT 22 extern const ru_field_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_MASK 0xff800000 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_WIDTH 9 #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_MASK 0x00000002 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_MASK 0x000000fc #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_WIDTH 6 #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_MASK 0x00000300 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_MASK 0x0000fc00 #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_WIDTH 6 #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_MASK 0x007f0000 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_WIDTH 7 #define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD; #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_MASK 0xff800000 #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_WIDTH 9 #define QM_GLOBAL_CFG_FPM_CONTROL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABL_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABL_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABL_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABL_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_MASK 0xfffffffe #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 31 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_MASK 0x3fffffff #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_WIDTH 30 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_DDR_BYTES_LOWER_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_MASK 0xc0000000 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_MASK 0x3fffffff #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_WIDTH 30 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_MASK 0xc0000000 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_MASK 0x3fffffff #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_WIDTH 30 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_MASK 0xc0000000 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_MASK 0x000000fe #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 7 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_MASK 0x0000ff00 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_MASK 0x00ff0000 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_MASK 0xff000000 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD; #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_MASK 0x0fffffff #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_WIDTH 28 #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_MASK 0xf0000000 #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_WIDTH 4 #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD; #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_MASK 0x000001ff #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_WIDTH 9 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD; #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_WIDTH 7 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD; #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_MASK 0x00010000 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD; #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_MASK 0xfffe0000 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_WIDTH 15 #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD; #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_MASK 0x000003ff #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_WIDTH 10 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_MASK 0x0000fc00 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_WIDTH 6 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD; #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_MASK 0x00030000 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_MASK 0xfffc0000 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_WIDTH 14 #define QM_GLOBAL_CFG_AGGREGATION_CTRL_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD; #define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD; #define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD; #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_MASK 0x000007ff #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_WIDTH 11 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD; #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_MASK 0x0000f800 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD; #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_MASK 0x07ff0000 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_WIDTH 11 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD; #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_MASK 0xf8000000 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_RESERVED1_FIELD_SHIFT 27 extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_MASK 0x00000001 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_MASK 0x00000002 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_FIELD_SHIFT 1 extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_MASK 0x0000fffc #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_WIDTH 14 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_MASK 0x07ff0000 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_WIDTH 11 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_MASK 0xf8000000 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_RESERVED1_FIELD_SHIFT 27 extern const ru_field_rec QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD; #define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD; #define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD; #define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD; #define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_MASK 0xffffffff #define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_WIDTH 32 #define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD; #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_MASK 0x00000007 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_WIDTH 3 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_MASK 0x000000f8 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD; #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_MASK 0x00000700 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_WIDTH 3 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED1_FIELD; #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED1_FIELD_MASK 0xfffff800 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED1_FIELD_WIDTH 21 #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_RESERVED1_FIELD_SHIFT 11 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_0_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_0_FIELD_MASK 0x000000ff #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_0_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_0_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_1_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_1_FIELD_MASK 0x0000ff00 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_1_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_1_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_2_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_2_FIELD_MASK 0x00ff0000 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_2_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_2_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_3_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_3_FIELD_MASK 0xff000000 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_3_FIELD_WIDTH 8 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_RES_THR_3_FIELD_SHIFT 24 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RES_THR_GLOBAL_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RES_THR_GLOBAL_FIELD_MASK 0x0000ffff #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RES_THR_GLOBAL_FIELD_WIDTH 16 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RES_THR_GLOBAL_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RESERVED0_FIELD_WIDTH 16 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_MASK 0x0000003f #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_WIDTH 6 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_MASK 0x000000c0 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_WIDTH 2 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_MASK 0x00000f00 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_WIDTH 4 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_FIELD_SHIFT 8 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_MASK 0x0000f000 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_WIDTH 4 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_MASK 0x00010000 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_FIELD_SHIFT 16 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_MASK 0xfffe0000 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_WIDTH 15 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_QM_FLOW_CTRL_INTR_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_QM_FLOW_CTRL_INTR_FIELD_MASK 0x0000001f #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_QM_FLOW_CTRL_INTR_FIELD_WIDTH 5 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_QM_FLOW_CTRL_INTR_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_RESERVED0_FIELD_MASK 0xffffffe0 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_RESERVED0_FIELD_WIDTH 27 #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD; #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_MASK 0x0001ffff #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_WIDTH 17 #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_MASK 0xfffe0000 #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_WIDTH 15 #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD; #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_MASK 0x000001ff #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_WIDTH 9 #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_FIELD_SHIFT 0 extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD; #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_MASK 0x00000200 #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_WIDTH 1 #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_FIELD_SHIFT 9 extern const ru_field_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD; #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_MASK 0xfffffc00 #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_WIDTH 22 #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD; #define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_MASK 0x0000007f #define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_WIDTH 7 #define QM_FPM_POOLS_THR_FPM_LOWER_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_THR_RESERVED0_FIELD; #define QM_FPM_POOLS_THR_RESERVED0_FIELD_MASK 0x00000080 #define QM_FPM_POOLS_THR_RESERVED0_FIELD_WIDTH 1 #define QM_FPM_POOLS_THR_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD; #define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_MASK 0x00007f00 #define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_WIDTH 7 #define QM_FPM_POOLS_THR_FPM_HIGHER_THR_FIELD_SHIFT 8 extern const ru_field_rec QM_FPM_POOLS_THR_RESERVED1_FIELD; #define QM_FPM_POOLS_THR_RESERVED1_FIELD_MASK 0xffff8000 #define QM_FPM_POOLS_THR_RESERVED1_FIELD_WIDTH 17 #define QM_FPM_POOLS_THR_RESERVED1_FIELD_SHIFT 15 extern const ru_field_rec QM_FPM_POOLS_R_0_RESERVED0_FIELD; #define QM_FPM_POOLS_R_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_0_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_1_RESERVED0_FIELD; #define QM_FPM_POOLS_R_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_1_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_2_RESERVED0_FIELD; #define QM_FPM_POOLS_R_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_2_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_3_RESERVED0_FIELD; #define QM_FPM_POOLS_R_3_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_3_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_4_RESERVED0_FIELD; #define QM_FPM_POOLS_R_4_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_4_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_5_RESERVED0_FIELD; #define QM_FPM_POOLS_R_5_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_5_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_5_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOLS_R_6_RESERVED0_FIELD; #define QM_FPM_POOLS_R_6_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_POOLS_R_6_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_POOLS_R_6_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD; #define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_MASK 0x0000ffff #define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_LOWER_THR_FPM_GRP_LOWER_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD; #define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_LOWER_THR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD; #define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_MASK 0x0000ffff #define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD; #define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_MID_THR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD; #define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_MASK 0x0000ffff #define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD; #define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_HIGHER_THR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD; #define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_MASK 0x0000ffff #define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_CNT_RESERVED0_FIELD; #define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_MASK 0xffff0000 #define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_WIDTH 16 #define QM_FPM_USR_GRP_CNT_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_USR_GRP_R_0_RESERVED0_FIELD; #define QM_FPM_USR_GRP_R_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_USR_GRP_R_0_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_USR_GRP_R_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_R_1_RESERVED0_FIELD; #define QM_FPM_USR_GRP_R_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_USR_GRP_R_1_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_USR_GRP_R_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_R_2_RESERVED0_FIELD; #define QM_FPM_USR_GRP_R_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_USR_GRP_R_2_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_USR_GRP_R_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_USR_GRP_R_3_RESERVED0_FIELD; #define QM_FPM_USR_GRP_R_3_RESERVED0_FIELD_MASK 0xffffffff #define QM_FPM_USR_GRP_R_3_RESERVED0_FIELD_WIDTH 32 #define QM_FPM_USR_GRP_R_3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_MASK 0x0000003f #define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_WIDTH 6 #define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_MASK 0x000000c0 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_WIDTH 2 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_MASK 0x00000f00 #define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_WIDTH 4 #define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_FIELD_SHIFT 8 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_MASK 0x0000f000 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_WIDTH 4 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_MASK 0x00010000 #define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_WIDTH 1 #define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_FIELD_SHIFT 16 extern const ru_field_rec QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD; #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_MASK 0xfffe0000 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_WIDTH 15 #define QM_RUNNER_GRP_RNR_CONFIG_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD; #define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_MASK 0x000001ff #define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_WIDTH 9 #define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD; #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_WIDTH 7 #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD; #define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_MASK 0x01ff0000 #define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_WIDTH 9 #define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_FIELD_SHIFT 16 extern const ru_field_rec QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD; #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_MASK 0xfe000000 #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_WIDTH 7 #define QM_RUNNER_GRP_QUEUE_CONFIG_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD; #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_MASK 0x00000007 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_WIDTH 3 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD; #define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_MASK 0x00003ff8 #define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_WIDTH 11 #define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_FIELD_SHIFT 3 extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD; #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_MASK 0x0000c000 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_WIDTH 2 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD; #define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_MASK 0x00030000 #define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_WIDTH 2 #define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_FIELD_SHIFT 16 extern const ru_field_rec QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD; #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_MASK 0xfffc0000 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_WIDTH 14 #define QM_RUNNER_GRP_PDFIFO_CONFIG_RESERVED2_FIELD_SHIFT 18 extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_MASK 0x00000007 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_WIDTH 3 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_MASK 0x00003ff8 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_WIDTH 11 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_FIELD_SHIFT 3 extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_MASK 0x0000c000 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_WIDTH 2 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_MASK 0x00070000 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_WIDTH 3 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_FIELD_SHIFT 16 extern const ru_field_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_MASK 0xfff80000 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_WIDTH 13 #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_RESERVED2_FIELD_SHIFT 19 extern const ru_field_rec QM_RUNNER_GRP_R_0_RESERVED0_FIELD; #define QM_RUNNER_GRP_R_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_RUNNER_GRP_R_0_RESERVED0_FIELD_WIDTH 32 #define QM_RUNNER_GRP_R_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_R_1_RESERVED0_FIELD; #define QM_RUNNER_GRP_R_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_RUNNER_GRP_R_1_RESERVED0_FIELD_WIDTH 32 #define QM_RUNNER_GRP_R_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_R_2_RESERVED0_FIELD; #define QM_RUNNER_GRP_R_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_RUNNER_GRP_R_2_RESERVED0_FIELD_WIDTH 32 #define QM_RUNNER_GRP_R_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_RUNNER_GRP_R_3_RESERVED0_FIELD; #define QM_RUNNER_GRP_R_3_RESERVED0_FIELD_MASK 0xffffffff #define QM_RUNNER_GRP_R_3_RESERVED0_FIELD_WIDTH 32 #define QM_RUNNER_GRP_R_3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD; #define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_MASK 0x00000001 #define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD; #define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_MASK 0x00000002 #define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_FIELD_SHIFT 1 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD; #define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_MASK 0x00000004 #define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_FIELD_SHIFT 2 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD; #define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_MASK 0x00000008 #define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_FIELD_SHIFT 3 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD; #define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_MASK 0x00000010 #define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_FIELD_SHIFT 4 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CRE_FIELD; #define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CRE_FIELD_MASK 0x00000020 #define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CRE_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CRE_FIELD_SHIFT 5 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD; #define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_MASK 0x00000040 #define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_FIELD_SHIFT 6 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD; #define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_MASK 0x00000080 #define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_FIELD_SHIFT 7 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD; #define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_MASK 0x00000100 #define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_FIELD_SHIFT 8 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD; #define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_MASK 0x00000200 #define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_FIELD_SHIFT 9 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTIO_FIELD; #define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTIO_FIELD_MASK 0x00000400 #define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTIO_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTIO_FIELD_SHIFT 10 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD; #define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_MASK 0x00000800 #define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_1588_DROP_FIELD_SHIFT 11 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTIO_FIELD; #define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTIO_FIELD_MASK 0x00001000 #define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTIO_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTIO_FIELD_SHIFT 12 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_MASK 0x00002000 #define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_FIELD_SHIFT 13 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_MASK 0x00004000 #define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_FIELD_SHIFT 14 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_MASK 0x00008000 #define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_FIELD_SHIFT 15 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_MASK 0x00010000 #define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_FIELD_SHIFT 16 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_MASK 0x00020000 #define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_FIELD_SHIFT 17 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_MASK 0x00040000 #define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_FIELD_SHIFT 18 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_MASK 0x00080000 #define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_FIELD_SHIFT 19 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD; #define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_MASK 0x00100000 #define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_FIELD_SHIFT 20 extern const ru_field_rec QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD; #define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_MASK 0x00200000 #define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_WIDTH 1 #define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_FIELD_SHIFT 21 extern const ru_field_rec QM_INTR_CTRL_ISR_RESERVED0_FIELD; #define QM_INTR_CTRL_ISR_RESERVED0_FIELD_MASK 0xffc00000 #define QM_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 10 #define QM_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec QM_INTR_CTRL_ISM_ISM_FIELD; #define QM_INTR_CTRL_ISM_ISM_FIELD_MASK 0x001fffff #define QM_INTR_CTRL_ISM_ISM_FIELD_WIDTH 21 #define QM_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec QM_INTR_CTRL_ISM_RESERVED0_FIELD; #define QM_INTR_CTRL_ISM_RESERVED0_FIELD_MASK 0xffe00000 #define QM_INTR_CTRL_ISM_RESERVED0_FIELD_WIDTH 11 #define QM_INTR_CTRL_ISM_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec QM_INTR_CTRL_IER_IEM_FIELD; #define QM_INTR_CTRL_IER_IEM_FIELD_MASK 0x001fffff #define QM_INTR_CTRL_IER_IEM_FIELD_WIDTH 21 #define QM_INTR_CTRL_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec QM_INTR_CTRL_IER_RESERVED0_FIELD; #define QM_INTR_CTRL_IER_RESERVED0_FIELD_MASK 0xffe00000 #define QM_INTR_CTRL_IER_RESERVED0_FIELD_WIDTH 11 #define QM_INTR_CTRL_IER_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec QM_INTR_CTRL_ITR_IST_FIELD; #define QM_INTR_CTRL_ITR_IST_FIELD_MASK 0x001fffff #define QM_INTR_CTRL_ITR_IST_FIELD_WIDTH 21 #define QM_INTR_CTRL_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec QM_INTR_CTRL_ITR_RESERVED0_FIELD; #define QM_INTR_CTRL_ITR_RESERVED0_FIELD_MASK 0xffe00000 #define QM_INTR_CTRL_ITR_RESERVED0_FIELD_WIDTH 11 #define QM_INTR_CTRL_ITR_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_MASK 0x000001ff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_WIDTH 9 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_WIDTH 7 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_MASK 0x00030000 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_WIDTH 2 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_FIELD_SHIFT 16 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_MASK 0x00fc0000 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_WIDTH 6 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_MASK 0x01000000 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_WIDTH 1 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_FIELD_SHIFT 24 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_MASK 0x02000000 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_WIDTH 1 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_FIELD_SHIFT 25 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_MASK 0xfc000000 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_WIDTH 6 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_RESERVED2_FIELD_SHIFT 26 extern const ru_field_rec QM_CPU_INDR_PORT_R2_0_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R2_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R2_0_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R2_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R2_1_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R2_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R2_1_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R2_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R2_2_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R2_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R2_2_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R2_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R_0_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R_0_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R_1_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R_1_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R_2_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R_2_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_CPU_INDR_PORT_R_3_RESERVED0_FIELD; #define QM_CPU_INDR_PORT_R_3_RESERVED0_FIELD_MASK 0xffffffff #define QM_CPU_INDR_PORT_R_3_RESERVED0_FIELD_WIDTH 32 #define QM_CPU_INDR_PORT_R_3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_MASK 0x0000000f #define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_WIDTH 4 #define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_FIELD_SHIFT 0 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_MASK 0x00000070 #define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_WIDTH 3 #define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_FIELD_SHIFT 4 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_MASK 0x00000080 #define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_FIELD_SHIFT 7 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_MASK 0x00000100 #define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_FIELD_SHIFT 8 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_MASK 0x00000200 #define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_FIELD_SHIFT 9 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_MASK 0x00001c00 #define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_WIDTH 3 #define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_FIELD_SHIFT 10 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_MASK 0x00002000 #define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_FIELD_SHIFT 13 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_MASK 0x00004000 #define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_FIELD_SHIFT 14 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_MASK 0x00008000 #define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_SCI_FIELD_SHIFT 15 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_MASK 0x00010000 #define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_WIDTH 1 #define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_FIELD_SHIFT 16 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_MASK 0x000e0000 #define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_WIDTH 3 #define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_FIELD_SHIFT 17 extern const ru_field_rec QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD; #define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_MASK 0xfff00000 #define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_WIDTH 12 #define QM_QUEUE_CONTEXT_CONTEXT_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_MASK 0x00ffffff #define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_WIDTH 24 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_MASK 0x01000000 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_WIDTH 1 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_FIELD_SHIFT 24 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_MASK 0xfe000000 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_WIDTH 7 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_MASK 0x00ffffff #define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_WIDTH 24 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_MASK 0x01000000 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_WIDTH 1 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_FIELD_SHIFT 24 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_MASK 0xfe000000 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_WIDTH 7 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec QM_WRED_PROFILE_R0_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_R0_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R0_0_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R0_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_R0_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_R0_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R0_1_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R0_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD; #define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_MASK 0x00ffffff #define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_WIDTH 24 #define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_MASK 0xff000000 #define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_WIDTH 8 #define QM_WRED_PROFILE_COLOR_MAX_THR_0_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD; #define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_MASK 0x00ffffff #define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_WIDTH 24 #define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_MASK 0xff000000 #define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_WIDTH 8 #define QM_WRED_PROFILE_COLOR_MAX_THR_1_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec QM_WRED_PROFILE_R1_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_R1_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R1_0_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R1_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_R1_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_R1_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R1_1_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R1_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_MASK 0x000000ff #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_WIDTH 8 #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_MASK 0x00001f00 #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_WIDTH 5 #define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_FIELD_SHIFT 8 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_MASK 0xffffe000 #define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_WIDTH 19 #define QM_WRED_PROFILE_COLOR_SLOPE_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_MASK 0x000000ff #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_WIDTH 8 #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_MASK 0x00001f00 #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_WIDTH 5 #define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_FIELD_SHIFT 8 extern const ru_field_rec QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_MASK 0xffffe000 #define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_WIDTH 19 #define QM_WRED_PROFILE_COLOR_SLOPE_1_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec QM_WRED_PROFILE_R2_0_RESERVED0_FIELD; #define QM_WRED_PROFILE_R2_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R2_0_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R2_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_PROFILE_R2_1_RESERVED0_FIELD; #define QM_WRED_PROFILE_R2_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_WRED_PROFILE_R2_1_RESERVED0_FIELD_WIDTH 32 #define QM_WRED_PROFILE_R2_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD; #define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_MASK 0x3fffffff #define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_WIDTH 30 #define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_MASK 0x40000000 #define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_WIDTH 1 #define QM_COPY_DECISION_PROFILE_THR_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD; #define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_MASK 0x80000000 #define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_WIDTH 1 #define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_FIELD_SHIFT 31 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_0_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_0_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_0_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_0_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_1_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_1_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_1_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_1_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_2_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_2_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_2_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_3_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_3_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_3_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_4_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_4_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_4_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_4_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_5_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_5_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_5_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_5_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_COPY_DECISION_PROFILE_R_6_RESERVED0_FIELD; #define QM_COPY_DECISION_PROFILE_R_6_RESERVED0_FIELD_MASK 0xffffffff #define QM_COPY_DECISION_PROFILE_R_6_RESERVED0_FIELD_WIDTH 32 #define QM_COPY_DECISION_PROFILE_R_6_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD; #define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_MASK 0xffffffff #define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_WIDTH 32 #define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD; #define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_MASK 0xffffffff #define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_WIDTH 32 #define QM_DQM_VALID_COUNTER_COUNTER_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_DROP_COUNTER_COUNTER_DATA_FIELD; #define QM_DROP_COUNTER_COUNTER_DATA_FIELD_MASK 0xffffffff #define QM_DROP_COUNTER_COUNTER_DATA_FIELD_WIDTH 32 #define QM_DROP_COUNTER_COUNTER_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EPON_RPT_CNT_COUNTER_DATA_FIELD; #define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_MASK 0xffffffff #define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_WIDTH 32 #define QM_EPON_RPT_CNT_COUNTER_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD; #define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_MASK 0xffffffff #define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_WIDTH 32 #define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_FIELD_SHIFT 0 extern const ru_field_rec QM_RD_DATA_POOL0_DATA_FIELD; #define QM_RD_DATA_POOL0_DATA_FIELD_MASK 0xffffffff #define QM_RD_DATA_POOL0_DATA_FIELD_WIDTH 32 #define QM_RD_DATA_POOL0_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_RD_DATA_POOL1_DATA_FIELD; #define QM_RD_DATA_POOL1_DATA_FIELD_MASK 0xffffffff #define QM_RD_DATA_POOL1_DATA_FIELD_WIDTH 32 #define QM_RD_DATA_POOL1_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_RD_DATA_POOL2_DATA_FIELD; #define QM_RD_DATA_POOL2_DATA_FIELD_MASK 0xffffffff #define QM_RD_DATA_POOL2_DATA_FIELD_WIDTH 32 #define QM_RD_DATA_POOL2_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_RD_DATA_POOL3_DATA_FIELD; #define QM_RD_DATA_POOL3_DATA_FIELD_MASK 0xffffffff #define QM_RD_DATA_POOL3_DATA_FIELD_WIDTH 32 #define QM_RD_DATA_POOL3_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_PDFIFO_PTR_WR_PTR_FIELD; #define QM_PDFIFO_PTR_WR_PTR_FIELD_MASK 0x0000000f #define QM_PDFIFO_PTR_WR_PTR_FIELD_WIDTH 4 #define QM_PDFIFO_PTR_WR_PTR_FIELD_SHIFT 0 extern const ru_field_rec QM_PDFIFO_PTR_RESERVED0_FIELD; #define QM_PDFIFO_PTR_RESERVED0_FIELD_MASK 0x000000f0 #define QM_PDFIFO_PTR_RESERVED0_FIELD_WIDTH 4 #define QM_PDFIFO_PTR_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec QM_PDFIFO_PTR_RD_PTR_FIELD; #define QM_PDFIFO_PTR_RD_PTR_FIELD_MASK 0x00000f00 #define QM_PDFIFO_PTR_RD_PTR_FIELD_WIDTH 4 #define QM_PDFIFO_PTR_RD_PTR_FIELD_SHIFT 8 extern const ru_field_rec QM_PDFIFO_PTR_RESERVED1_FIELD; #define QM_PDFIFO_PTR_RESERVED1_FIELD_MASK 0xfffff000 #define QM_PDFIFO_PTR_RESERVED1_FIELD_WIDTH 20 #define QM_PDFIFO_PTR_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec QM_UPDATE_FIFO_PTR_WR_PTR_FIELD; #define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_MASK 0x000001ff #define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_WIDTH 9 #define QM_UPDATE_FIFO_PTR_WR_PTR_FIELD_SHIFT 0 extern const ru_field_rec QM_UPDATE_FIFO_PTR_RD_PTR_FIELD; #define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_MASK 0x0000fe00 #define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_WIDTH 7 #define QM_UPDATE_FIFO_PTR_RD_PTR_FIELD_SHIFT 9 extern const ru_field_rec QM_UPDATE_FIFO_PTR_RESERVED0_FIELD; #define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_WIDTH 16 #define QM_UPDATE_FIFO_PTR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_RD_DATA_DATA_FIELD; #define QM_RD_DATA_DATA_FIELD_MASK 0xffffffff #define QM_RD_DATA_DATA_FIELD_WIDTH 32 #define QM_RD_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_POP_POP_FIELD; #define QM_POP_POP_FIELD_MASK 0x00000001 #define QM_POP_POP_FIELD_WIDTH 1 #define QM_POP_POP_FIELD_SHIFT 0 extern const ru_field_rec QM_POP_RESERVED0_FIELD; #define QM_POP_RESERVED0_FIELD_MASK 0xfffffffe #define QM_POP_RESERVED0_FIELD_WIDTH 31 #define QM_POP_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD; #define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD; #define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_NORMAL_RMT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD; #define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD; #define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_EGRESS_DATA_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_RR_FIFO_DATA_DATA_FIELD; #define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_EGRESS_RR_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD; #define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD; #define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD; #define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_BB_OUTPUT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD; #define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_MASK 0xffffffff #define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_WIDTH 32 #define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_CONTEXT_DATA_DATA_FIELD; #define QM_CONTEXT_DATA_DATA_FIELD_MASK 0xffffffff #define QM_CONTEXT_DATA_DATA_FIELD_WIDTH 32 #define QM_CONTEXT_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_DEBUG_SEL_SELECT_FIELD; #define QM_DEBUG_SEL_SELECT_FIELD_MASK 0x0000001f #define QM_DEBUG_SEL_SELECT_FIELD_WIDTH 5 #define QM_DEBUG_SEL_SELECT_FIELD_SHIFT 0 extern const ru_field_rec QM_DEBUG_SEL_RESERVED0_FIELD; #define QM_DEBUG_SEL_RESERVED0_FIELD_MASK 0x7fffffe0 #define QM_DEBUG_SEL_RESERVED0_FIELD_WIDTH 26 #define QM_DEBUG_SEL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec QM_DEBUG_SEL_ENABLE_FIELD; #define QM_DEBUG_SEL_ENABLE_FIELD_MASK 0x80000000 #define QM_DEBUG_SEL_ENABLE_FIELD_WIDTH 1 #define QM_DEBUG_SEL_ENABLE_FIELD_SHIFT 31 extern const ru_field_rec QM_DEBUG_BUS_LSB_DATA_FIELD; #define QM_DEBUG_BUS_LSB_DATA_FIELD_MASK 0xffffffff #define QM_DEBUG_BUS_LSB_DATA_FIELD_WIDTH 32 #define QM_DEBUG_BUS_LSB_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_DEBUG_BUS_MSB_DATA_FIELD; #define QM_DEBUG_BUS_MSB_DATA_FIELD_MASK 0xffffffff #define QM_DEBUG_BUS_MSB_DATA_FIELD_WIDTH 32 #define QM_DEBUG_BUS_MSB_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_SPARE_CONFIG_DATA_FIELD; #define QM_QM_SPARE_CONFIG_DATA_FIELD_MASK 0xffffffff #define QM_QM_SPARE_CONFIG_DATA_FIELD_WIDTH 32 #define QM_QM_SPARE_CONFIG_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD; #define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_GOOD_LVL1_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD; #define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_WIDTH 32 #define QM_GOOD_LVL1_BYTES_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD; #define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_GOOD_LVL2_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD; #define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_WIDTH 32 #define QM_GOOD_LVL2_BYTES_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_COPIED_PKTS_CNT_COUNTER_FIELD; #define QM_COPIED_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_COPIED_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_COPIED_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_COPIED_BYTES_CNT_COUNTER_FIELD; #define QM_COPIED_BYTES_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_COPIED_BYTES_CNT_COUNTER_FIELD_WIDTH 32 #define QM_COPIED_BYTES_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_PKTS_CNT_COUNTER_FIELD; #define QM_AGG_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_BYTES_CNT_COUNTER_FIELD; #define QM_AGG_BYTES_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_BYTES_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_BYTES_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_1_PKTS_CNT_COUNTER_FIELD; #define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_1_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_2_PKTS_CNT_COUNTER_FIELD; #define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_2_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_3_PKTS_CNT_COUNTER_FIELD; #define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_3_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_AGG_4_PKTS_CNT_COUNTER_FIELD; #define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_WIDTH 32 #define QM_AGG_4_PKTS_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_WRED_DROP_CNT_COUNTER_FIELD; #define QM_WRED_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_WRED_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_WRED_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD; #define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_FPM_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD; #define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD; #define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD; #define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD; #define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_WIDTH 32 #define QM_QM_ABS_REQUEUE_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD; #define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD; #define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD; #define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD; #define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_FPM_PREFETCH_FIFO0_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD; #define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD; #define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD; #define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD; #define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_FPM_PREFETCH_FIFO1_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD; #define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD; #define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD; #define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD; #define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_FPM_PREFETCH_FIFO2_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD; #define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD; #define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD; #define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_WIDTH 1 #define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD; #define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_FPM_PREFETCH_FIFO3_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD; #define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD; #define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_NORMAL_RMT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD; #define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_NORMAL_RMT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD; #define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD; #define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD; #define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_NON_DELAYED_RMT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD; #define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD; #define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD; #define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_NON_DELAYED_OUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD; #define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_PRE_CM_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD; #define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_PRE_CM_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_FULL_FIELD; #define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_PRE_CM_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD; #define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_PRE_CM_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD; #define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD; #define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_CM_RD_PD_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD; #define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_CM_RD_PD_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD; #define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_CM_RD_PD_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD; #define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD; #define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_CM_WR_PD_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD; #define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_CM_WR_PD_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD; #define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_CM_WR_PD_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD; #define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD; #define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD; #define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_CM_COMMON_INPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD; #define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD; #define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_BB0_OUTPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD; #define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_BB0_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD; #define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD; #define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_BB1_OUTPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD; #define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_BB1_OUTPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD; #define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD; #define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_BB1_INPUT_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD; #define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_BB1_INPUT_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD; #define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_BB1_INPUT_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD; #define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD; #define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD; #define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_EGRESS_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD; #define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_EGRESS_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD; #define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x0000ffff #define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 16 #define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 0 extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD; #define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_MASK 0x00010000 #define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define QM_EGRESS_RR_FIFO_STATUS_EMPTY_FIELD_SHIFT 16 extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD; #define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_MASK 0x00020000 #define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define QM_EGRESS_RR_FIFO_STATUS_FULL_FIELD_SHIFT 17 extern const ru_field_rec QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD; #define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_MASK 0xfffc0000 #define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 14 #define QM_EGRESS_RR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec QM_BB_ROUTE_OVR_OVR_EN_FIELD; #define QM_BB_ROUTE_OVR_OVR_EN_FIELD_MASK 0x00000001 #define QM_BB_ROUTE_OVR_OVR_EN_FIELD_WIDTH 1 #define QM_BB_ROUTE_OVR_OVR_EN_FIELD_SHIFT 0 extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED0_FIELD; #define QM_BB_ROUTE_OVR_RESERVED0_FIELD_MASK 0x000000fe #define QM_BB_ROUTE_OVR_RESERVED0_FIELD_WIDTH 7 #define QM_BB_ROUTE_OVR_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_BB_ROUTE_OVR_DEST_ID_FIELD; #define QM_BB_ROUTE_OVR_DEST_ID_FIELD_MASK 0x00003f00 #define QM_BB_ROUTE_OVR_DEST_ID_FIELD_WIDTH 6 #define QM_BB_ROUTE_OVR_DEST_ID_FIELD_SHIFT 8 extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED1_FIELD; #define QM_BB_ROUTE_OVR_RESERVED1_FIELD_MASK 0x0000c000 #define QM_BB_ROUTE_OVR_RESERVED1_FIELD_WIDTH 2 #define QM_BB_ROUTE_OVR_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD; #define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_MASK 0x03ff0000 #define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_WIDTH 10 #define QM_BB_ROUTE_OVR_ROUTE_ADDR_FIELD_SHIFT 16 extern const ru_field_rec QM_BB_ROUTE_OVR_RESERVED2_FIELD; #define QM_BB_ROUTE_OVR_RESERVED2_FIELD_MASK 0xfc000000 #define QM_BB_ROUTE_OVR_RESERVED2_FIELD_WIDTH 6 #define QM_BB_ROUTE_OVR_RESERVED2_FIELD_SHIFT 26 extern const ru_field_rec QM_QM_INGRESS_STAT_STAT_FIELD; #define QM_QM_INGRESS_STAT_STAT_FIELD_MASK 0xffffffff #define QM_QM_INGRESS_STAT_STAT_FIELD_WIDTH 32 #define QM_QM_INGRESS_STAT_STAT_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_EGRESS_STAT_STAT_FIELD; #define QM_QM_EGRESS_STAT_STAT_FIELD_MASK 0xffffffff #define QM_QM_EGRESS_STAT_STAT_FIELD_WIDTH 32 #define QM_QM_EGRESS_STAT_STAT_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_CM_STAT_STAT_FIELD; #define QM_QM_CM_STAT_STAT_FIELD_MASK 0xffffffff #define QM_QM_CM_STAT_STAT_FIELD_WIDTH 32 #define QM_QM_CM_STAT_STAT_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_FPM_PREFETCH_STAT_STAT_FIELD; #define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_MASK 0xffffffff #define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_WIDTH 32 #define QM_QM_FPM_PREFETCH_STAT_STAT_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD; #define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_MASK 0x000000ff #define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_WIDTH 8 #define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD; #define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_MASK 0xffffff00 #define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_WIDTH 24 #define QM_QM_CONNECT_ACK_COUNTER_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD; #define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_MASK 0x000000ff #define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_WIDTH 8 #define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD; #define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_MASK 0xffffff00 #define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_WIDTH 24 #define QM_QM_DDR_WR_REPLY_COUNTER_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD; #define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_MASK 0x0fffffff #define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_WIDTH 28 #define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD; #define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_MASK 0xf0000000 #define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_WIDTH 4 #define QM_QM_DDR_PIPE_BYTE_COUNTER_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD; #define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_MASK 0x00007fff #define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_WIDTH 15 #define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD; #define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_MASK 0xffff8000 #define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_WIDTH 17 #define QM_QM_ABS_REQUEUE_VALID_COUNTER_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD; #define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_MASK 0xffffffff #define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_WIDTH 32 #define QM_QM_ILLEGAL_PD_CAPTURE_PD_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD; #define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_MASK 0xffffffff #define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_WIDTH 32 #define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_FIELD_SHIFT 0 extern const ru_field_rec QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD; #define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_MASK 0xffffffff #define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_WIDTH 32 #define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_POOL_DROP_CNT_COUNTER_FIELD; #define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_FPM_POOL_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_GRP_DROP_CNT_COUNTER_FIELD; #define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_FPM_GRP_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD; #define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_MASK 0xffffffff #define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_WIDTH 32 #define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec QM_DATA_DATA_FIELD; #define QM_DATA_DATA_FIELD_MASK 0xffffffff #define QM_DATA_DATA_FIELD_WIDTH 32 #define QM_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_RESERVED0_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_RESERVED0_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_RESERVED0_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_FIELD; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_FIELD_MASK 0xffffffff #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_FIELD_WIDTH 32 #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_MASK 0x00000007 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_WIDTH 3 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_MASK 0xfffffff8 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_WIDTH 29 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_MASK 0x0000003f #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_MASK 0x000000c0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_MASK 0x00003f00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_MASK 0x0000c000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_MASK 0x003f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_MASK 0x00c00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_SHIFT 22 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_MASK 0x3f000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_MASK 0xc0000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_MASK 0x0000003f #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_MASK 0x000000c0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_MASK 0x00003f00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_MASK 0x0000c000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_MASK 0x003f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_MASK 0x00c00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_SHIFT 22 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_MASK 0x3f000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_MASK 0xc0000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_MASK 0x00000007 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_WIDTH 3 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_MASK 0x00000008 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_SHIFT 3 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_MASK 0x00001ff0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_SHIFT 4 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_MASK 0x0000e000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_WIDTH 3 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_MASK 0x007f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_MASK 0x00800000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_SHIFT 23 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_MASK 0x7f000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_MASK 0x80000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_SHIFT 31 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_MASK 0x000f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_WIDTH 4 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_MASK 0xfff00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_WIDTH 12 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_MASK 0x0000003f #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_MASK 0x00000fc0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_MASK 0x0000f000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_WIDTH 4 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_MASK 0x003f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_MASK 0x00c00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_SHIFT 22 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_MASK 0x01000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_MASK 0xfe000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_MASK 0x0000003f #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_MASK 0x00000fc0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_MASK 0x0000f000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_WIDTH 4 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_MASK 0x003f0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_MASK 0x00c00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_SHIFT 22 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_MASK 0x01000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_MASK 0xfe000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_MASK 0x00000002 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_MASK 0x000000fc #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_MASK 0x00001f00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_WIDTH 5 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_MASK 0xffffe000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_WIDTH 19 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_MASK 0x000000ff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_WIDTH 8 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_MASK 0xffffff00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_WIDTH 24 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_MASK 0x000003ff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_WIDTH 10 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_MASK 0x000ffc00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_WIDTH 10 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_SHIFT 10 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_MASK 0x3ff00000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_WIDTH 10 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_SHIFT 20 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_MASK 0xc0000000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_WIDTH 2 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_MASK 0xfffffffe #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_WIDTH 31 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_MASK 0x000003ff #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_WIDTH 10 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_MASK 0x0000fc00 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_WIDTH 6 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_SHIFT 10 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_MASK 0x00010000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_MASK 0xfffe0000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_WIDTH 15 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_MASK 0x00000002 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_MASK 0xfffffffc #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_WIDTH 30 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_MASK 0x00000002 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_MASK 0x00000004 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_SHIFT 2 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_MASK 0x00000008 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_SHIFT 3 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_MASK 0x00000010 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_SHIFT 4 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_MASK 0x00000020 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_SHIFT 5 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_MASK 0x00000040 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_MASK 0x00000080 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_SHIFT 7 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_MASK 0x00000100 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_MASK 0x00000200 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_SHIFT 9 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_MASK 0x00000400 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_SHIFT 10 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_MASK 0x00000800 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_SHIFT 11 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_MASK 0x00001000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_SHIFT 12 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_MASK 0x00002000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_SHIFT 13 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_MASK 0x00004000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_SHIFT 14 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_MASK 0xffff8000 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_WIDTH 17 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_MASK 0x0000001f #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_WIDTH 5 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_MASK 0xffffffe0 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_WIDTH 27 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_MASK 0x000001ff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_MASK 0x01ff0000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_MASK 0xfe000000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK 0x000001ff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK 0x01ff0000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK 0xfe000000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK 0x000000ff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK 0x0000ff00 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK 0xfffffffe #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK 0x000000ff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK 0xffffff00 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_MASK 0x000001ff #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_MASK 0x0000fe00 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_MASK 0x01ff0000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_WIDTH 9 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_MASK 0xfe000000 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_WIDTH 7 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_EN_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_EN_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_EN_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_EN_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_MASK 0xfffffffe #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_WIDTH 31 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_EN_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_EN_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_EN_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK 0xfffffffe #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 31 #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_MASK 0x0000ffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_MASK 0xffff0000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_WIDTH 16 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_MASK 0x00000001 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_MASK 0x00000002 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_SHIFT 1 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_MASK 0x00000004 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_SHIFT 2 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_MASK 0x00000008 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_SHIFT 3 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_MASK 0x00000010 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_SHIFT 4 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_MASK 0x00000020 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_SHIFT 5 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_MASK 0x00000040 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_SHIFT 6 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_MASK 0x00000080 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_SHIFT 7 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_MASK 0x00000100 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_SHIFT 8 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_MASK 0x00000200 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_SHIFT 9 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_MASK 0x00000400 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_SHIFT 10 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_MASK 0x00000800 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_SHIFT 11 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_MASK 0x00001000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_SHIFT 12 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_MASK 0x00002000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_SHIFT 13 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_MASK 0x00004000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_SHIFT 14 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_MASK 0x00008000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_SHIFT 15 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_MASK 0x00010000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_SHIFT 16 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_MASK 0x00020000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_SHIFT 17 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_MASK 0x00040000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_SHIFT 18 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_MASK 0x00080000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_SHIFT 19 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_MASK 0x00100000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_SHIFT 20 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_MASK 0x00200000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_SHIFT 21 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_MASK 0x00400000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_SHIFT 22 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_MASK 0x00800000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_SHIFT 23 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_MASK 0x01000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_SHIFT 24 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_MASK 0x02000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_SHIFT 25 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_MASK 0x04000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_SHIFT 26 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_MASK 0x08000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_SHIFT 27 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_MASK 0x10000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_SHIFT 28 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_MASK 0x20000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_SHIFT 29 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_MASK 0x40000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_SHIFT 30 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_MASK 0x80000000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_WIDTH 1 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_SHIFT 31 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_MASK 0x000007ff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_WIDTH 11 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_MASK 0xfffff800 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_WIDTH 21 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_MASK 0xffffffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_WIDTH 32 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_MASK 0x001fffff #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_WIDTH 21 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_SHIFT 0 extern const ru_field_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_RESERVED0_FIELD; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_RESERVED0_FIELD_MASK 0xffe00000 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_RESERVED0_FIELD_WIDTH 11 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_MASK 0x000000c0 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_WIDTH 2 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_MASK 0x0003ff00 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_WIDTH 10 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_SHIFT 8 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_MASK 0x00fc0000 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_MASK 0x01000000 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_SHIFT 24 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_MASK 0xfe000000 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_WIDTH 7 #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_FIELD; #define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED0_FIELD_MASK 0x000000c0 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED0_FIELD_WIDTH 2 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD; #define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_MASK 0x00003f00 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_SHIFT 8 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED1_FIELD; #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED1_FIELD_MASK 0xffffc000 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED1_FIELD_WIDTH 18 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_FIELD; #define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_FIELD_MASK 0x0000000f #define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_FIELD_WIDTH 4 #define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_FIELD; #define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_FIELD_MASK 0x000000f0 #define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_FIELD_WIDTH 4 #define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_FIELD_SHIFT 4 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PRI_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_PRI_RESERVED0_FIELD_MASK 0xffffff00 #define QM_DMA_QM_DMA_CONFIG_PRI_RESERVED0_FIELD_WIDTH 24 #define QM_DMA_QM_DMA_CONFIG_PRI_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD; #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_MASK 0x000000c0 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_WIDTH 2 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD; #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_MASK 0x00003f00 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_SHIFT 8 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD; #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_MASK 0xffffc000 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_WIDTH 18 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD; #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_MASK 0x00000007 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_WIDTH 3 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED0_FIELD_MASK 0x000000f8 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED0_FIELD_WIDTH 5 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD; #define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_MASK 0x00000700 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_WIDTH 3 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_SHIFT 8 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED1_FIELD; #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED1_FIELD_MASK 0xfffff800 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED1_FIELD_WIDTH 21 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_RESERVED1_FIELD_SHIFT 11 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_FIELD; #define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_FIELD_MASK 0x0000ffff #define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_PTRRST_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_PTRRST_RESERVED0_FIELD_MASK 0xffff0000 #define QM_DMA_QM_DMA_CONFIG_PTRRST_RESERVED0_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_CONFIG_PTRRST_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_FIELD; #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_MAX_OTF_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_DBG_SEL_SEL_FIELD; #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_SEL_FIELD_MASK 0x00000003 #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_SEL_FIELD_WIDTH 2 #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_CONFIG_DBG_SEL_RESERVED0_FIELD; #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_MASK 0xfffffffc #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_WIDTH 30 #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_FIELD; #define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_FIELD_MASK 0x0000ffff #define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_NEMPTY_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_NEMPTY_RESERVED0_FIELD_MASK 0xffff0000 #define QM_DMA_QM_DMA_DEBUG_NEMPTY_RESERVED0_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_DEBUG_NEMPTY_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_FIELD; #define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_FIELD_MASK 0x0000ffff #define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_URGNT_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_URGNT_RESERVED0_FIELD_MASK 0xffff0000 #define QM_DMA_QM_DMA_DEBUG_URGNT_RESERVED0_FIELD_WIDTH 16 #define QM_DMA_QM_DMA_DEBUG_URGNT_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_FIELD; #define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_SELSRC_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_SELSRC_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_DEBUG_SELSRC_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_DEBUG_SELSRC_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_MASK 0x0000003f #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_MASK 0xffffffc0 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_WIDTH 26 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_MASK 0xffffffff #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_WIDTH 32 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_MASK 0xffffffff #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_WIDTH 32 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_FIELD_MASK 0x000003ff #define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_FIELD_WIDTH 10 #define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED0_FIELD_MASK 0x0000fc00 #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED0_FIELD_WIDTH 6 #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_FIELD_MASK 0x00010000 #define QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_FIELD_SHIFT 16 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_FIELD_MASK 0x00020000 #define QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_FIELD_SHIFT 17 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_FIELD_MASK 0x00040000 #define QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_FIELD_SHIFT 18 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED1_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED1_FIELD_MASK 0xfff80000 #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED1_FIELD_WIDTH 13 #define QM_DMA_QM_DMA_DEBUG_RDADD_RESERVED1_FIELD_SHIFT 19 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_FIELD_MASK 0x00000001 #define QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDVALID_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDVALID_RESERVED0_FIELD_MASK 0xfffffffe #define QM_DMA_QM_DMA_DEBUG_RDVALID_RESERVED0_FIELD_WIDTH 31 #define QM_DMA_QM_DMA_DEBUG_RDVALID_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_FIELD_MASK 0xffffffff #define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_FIELD_WIDTH 32 #define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_FIELD_MASK 0x00000001 #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_FIELD_WIDTH 1 #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_FIELD_SHIFT 0 extern const ru_field_rec QM_DMA_QM_DMA_DEBUG_RDDATARDY_RESERVED0_FIELD; #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_MASK 0xfffffffe #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_WIDTH 31 #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DQM_FPM_ADDR_FPMADDRESS_FIELD; #define DQM_FPM_ADDR_FPMADDRESS_FIELD_MASK 0xffffffff #define DQM_FPM_ADDR_FPMADDRESS_FIELD_WIDTH 32 #define DQM_FPM_ADDR_FPMADDRESS_FIELD_SHIFT 0 extern const ru_field_rec DQM_IRQ_STS_RESERVED0_FIELD; #define DQM_IRQ_STS_RESERVED0_FIELD_MASK 0xfffffffc #define DQM_IRQ_STS_RESERVED0_FIELD_WIDTH 30 #define DQM_IRQ_STS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DQM_IRQ_STS_PUSHFULLQ_FIELD; #define DQM_IRQ_STS_PUSHFULLQ_FIELD_MASK 0x00000002 #define DQM_IRQ_STS_PUSHFULLQ_FIELD_WIDTH 1 #define DQM_IRQ_STS_PUSHFULLQ_FIELD_SHIFT 1 extern const ru_field_rec DQM_IRQ_STS_POPEMPTYQ_FIELD; #define DQM_IRQ_STS_POPEMPTYQ_FIELD_MASK 0x00000001 #define DQM_IRQ_STS_POPEMPTYQ_FIELD_WIDTH 1 #define DQM_IRQ_STS_POPEMPTYQ_FIELD_SHIFT 0 extern const ru_field_rec DQM_IRQ_MSK_RESERVED0_FIELD; #define DQM_IRQ_MSK_RESERVED0_FIELD_MASK 0xfffffffc #define DQM_IRQ_MSK_RESERVED0_FIELD_WIDTH 30 #define DQM_IRQ_MSK_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DQM_IRQ_MSK_PUSHFULLQ_FIELD; #define DQM_IRQ_MSK_PUSHFULLQ_FIELD_MASK 0x00000002 #define DQM_IRQ_MSK_PUSHFULLQ_FIELD_WIDTH 1 #define DQM_IRQ_MSK_PUSHFULLQ_FIELD_SHIFT 1 extern const ru_field_rec DQM_IRQ_MSK_POPEMPTYQ_FIELD; #define DQM_IRQ_MSK_POPEMPTYQ_FIELD_MASK 0x00000001 #define DQM_IRQ_MSK_POPEMPTYQ_FIELD_WIDTH 1 #define DQM_IRQ_MSK_POPEMPTYQ_FIELD_SHIFT 0 extern const ru_field_rec DQM_BUF_SIZE_RESERVED0_FIELD; #define DQM_BUF_SIZE_RESERVED0_FIELD_MASK 0xfffffffc #define DQM_BUF_SIZE_RESERVED0_FIELD_WIDTH 30 #define DQM_BUF_SIZE_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DQM_BUF_SIZE_POOL_0_SIZE_FIELD; #define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_MASK 0x00000003 #define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_WIDTH 2 #define DQM_BUF_SIZE_POOL_0_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DQM_BUF_BASE_BASE_FIELD; #define DQM_BUF_BASE_BASE_FIELD_MASK 0xffffffff #define DQM_BUF_BASE_BASE_FIELD_WIDTH 32 #define DQM_BUF_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec DQM_TOKENS_USED_COUNT_FIELD; #define DQM_TOKENS_USED_COUNT_FIELD_MASK 0xffffffff #define DQM_TOKENS_USED_COUNT_FIELD_WIDTH 32 #define DQM_TOKENS_USED_COUNT_FIELD_SHIFT 0 extern const ru_field_rec DQM_NUM_PUSHED_COUNT_FIELD; #define DQM_NUM_PUSHED_COUNT_FIELD_MASK 0xffffffff #define DQM_NUM_PUSHED_COUNT_FIELD_WIDTH 32 #define DQM_NUM_PUSHED_COUNT_FIELD_SHIFT 0 extern const ru_field_rec DQM_NUM_POPPED_COUNT_FIELD; #define DQM_NUM_POPPED_COUNT_FIELD_MASK 0xffffffff #define DQM_NUM_POPPED_COUNT_FIELD_WIDTH 32 #define DQM_NUM_POPPED_COUNT_FIELD_SHIFT 0 extern const ru_field_rec DQM_DIAG_SEL_RESERVED0_FIELD; #define DQM_DIAG_SEL_RESERVED0_FIELD_MASK 0xffffff00 #define DQM_DIAG_SEL_RESERVED0_FIELD_WIDTH 24 #define DQM_DIAG_SEL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec DQM_DIAG_SEL_SEL_FIELD; #define DQM_DIAG_SEL_SEL_FIELD_MASK 0x000000ff #define DQM_DIAG_SEL_SEL_FIELD_WIDTH 8 #define DQM_DIAG_SEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec DQM_DIAG_DATA_DATA_FIELD; #define DQM_DIAG_DATA_DATA_FIELD_MASK 0xffffffff #define DQM_DIAG_DATA_DATA_FIELD_WIDTH 32 #define DQM_DIAG_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec DQM_IRQ_TST_RESERVED0_FIELD; #define DQM_IRQ_TST_RESERVED0_FIELD_MASK 0xfffffffc #define DQM_IRQ_TST_RESERVED0_FIELD_WIDTH 30 #define DQM_IRQ_TST_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DQM_IRQ_TST_PUSHFULLQTST_FIELD; #define DQM_IRQ_TST_PUSHFULLQTST_FIELD_MASK 0x00000002 #define DQM_IRQ_TST_PUSHFULLQTST_FIELD_WIDTH 1 #define DQM_IRQ_TST_PUSHFULLQTST_FIELD_SHIFT 1 extern const ru_field_rec DQM_IRQ_TST_POPEMPTYQTST_FIELD; #define DQM_IRQ_TST_POPEMPTYQTST_FIELD_MASK 0x00000001 #define DQM_IRQ_TST_POPEMPTYQTST_FIELD_WIDTH 1 #define DQM_IRQ_TST_POPEMPTYQTST_FIELD_SHIFT 0 extern const ru_field_rec DQM_TOKEN_FIFO_TOKEN_FIELD; #define DQM_TOKEN_FIFO_TOKEN_FIELD_MASK 0xffffffff #define DQM_TOKEN_FIFO_TOKEN_FIELD_WIDTH 32 #define DQM_TOKEN_FIFO_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec DQM_STATUS_RESERVED0_FIELD; #define DQM_STATUS_RESERVED0_FIELD_MASK 0xf0000000 #define DQM_STATUS_RESERVED0_FIELD_WIDTH 4 #define DQM_STATUS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec DQM_STATUS_Q_AVL_TKN_SPACE_FIELD; #define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_MASK 0x0fffffff #define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_WIDTH 28 #define DQM_STATUS_Q_AVL_TKN_SPACE_FIELD_SHIFT 0 extern const ru_field_rec DQM_HEAD_PTR_RESERVED0_FIELD; #define DQM_HEAD_PTR_RESERVED0_FIELD_MASK 0xf0000000 #define DQM_HEAD_PTR_RESERVED0_FIELD_WIDTH 4 #define DQM_HEAD_PTR_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec DQM_HEAD_PTR_Q_HEAD_PTR_FIELD; #define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_MASK 0x0fffffff #define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_WIDTH 28 #define DQM_HEAD_PTR_Q_HEAD_PTR_FIELD_SHIFT 0 extern const ru_field_rec DQM_TAIL_PTR_RESERVED0_FIELD; #define DQM_TAIL_PTR_RESERVED0_FIELD_MASK 0xf0000000 #define DQM_TAIL_PTR_RESERVED0_FIELD_WIDTH 4 #define DQM_TAIL_PTR_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec DQM_TAIL_PTR_Q_TAIL_PTR_FIELD; #define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_MASK 0x0fffffff #define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_WIDTH 28 #define DQM_TAIL_PTR_Q_TAIL_PTR_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_SIZE_RESERVED0_FIELD; #define DQM_DQMOL_SIZE_RESERVED0_FIELD_MASK 0xff800000 #define DQM_DQMOL_SIZE_RESERVED0_FIELD_WIDTH 9 #define DQM_DQMOL_SIZE_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD; #define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_MASK 0x007ffff0 #define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_WIDTH 19 #define DQM_DQMOL_SIZE_MAX_ENTRIES_FIELD_SHIFT 4 extern const ru_field_rec DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD; #define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_MASK 0x00000008 #define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_WIDTH 1 #define DQM_DQMOL_SIZE_Q_DISABLE_OFFLOAD_FIELD_SHIFT 3 extern const ru_field_rec DQM_DQMOL_SIZE_RESERVED1_FIELD; #define DQM_DQMOL_SIZE_RESERVED1_FIELD_MASK 0x00000004 #define DQM_DQMOL_SIZE_RESERVED1_FIELD_WIDTH 1 #define DQM_DQMOL_SIZE_RESERVED1_FIELD_SHIFT 2 extern const ru_field_rec DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD; #define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_MASK 0x00000003 #define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_WIDTH 2 #define DQM_DQMOL_SIZE_Q_TKN_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_CFGA_Q_SIZE_FIELD; #define DQM_DQMOL_CFGA_Q_SIZE_FIELD_MASK 0xffff0000 #define DQM_DQMOL_CFGA_Q_SIZE_FIELD_WIDTH 16 #define DQM_DQMOL_CFGA_Q_SIZE_FIELD_SHIFT 16 extern const ru_field_rec DQM_DQMOL_CFGA_Q_START_ADDR_FIELD; #define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_MASK 0x0000ffff #define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_WIDTH 16 #define DQM_DQMOL_CFGA_Q_START_ADDR_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_CFGB_ENABLE_FIELD; #define DQM_DQMOL_CFGB_ENABLE_FIELD_MASK 0x80000000 #define DQM_DQMOL_CFGB_ENABLE_FIELD_WIDTH 1 #define DQM_DQMOL_CFGB_ENABLE_FIELD_SHIFT 31 extern const ru_field_rec DQM_DQMOL_CFGB_RESERVED0_FIELD; #define DQM_DQMOL_CFGB_RESERVED0_FIELD_MASK 0x7fffffff #define DQM_DQMOL_CFGB_RESERVED0_FIELD_WIDTH 31 #define DQM_DQMOL_CFGB_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_CFGC_RESERVED0_FIELD; #define DQM_DQMOL_CFGC_RESERVED0_FIELD_MASK 0xffffffff #define DQM_DQMOL_CFGC_RESERVED0_FIELD_WIDTH 32 #define DQM_DQMOL_CFGC_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD; #define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_MASK 0xffffffff #define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_WIDTH 32 #define DQM_DQMOL_PUSHTOKEN_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD; #define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_MASK 0xffffffff #define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_WIDTH 32 #define DQM_DQMOL_PUSHTOKENNEXT_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_POPTOKEN_TOKEN_FIELD; #define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_MASK 0xffffffff #define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_WIDTH 32 #define DQM_DQMOL_POPTOKEN_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD; #define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_MASK 0xffffffff #define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_WIDTH 32 #define DQM_DQMOL_POPTOKENNEXT_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec DQM_QSM_DATA_DATA_FIELD; #define DQM_QSM_DATA_DATA_FIELD_MASK 0xffffffff #define DQM_QSM_DATA_DATA_FIELD_WIDTH 32 #define DQM_QSM_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_CTL_TP_MUX_CNTRL_FIELD; #define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_MASK 0xf8000000 #define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_WIDTH 5 #define FPM_FPM_CTL_TP_MUX_CNTRL_FIELD_SHIFT 27 extern const ru_field_rec FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_FIELD; #define FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_FIELD_MASK 0x04000000 #define FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_FIELD_WIDTH 1 #define FPM_FPM_CTL_ENABLE_HIGH_TOK_ALWAYS_FIELD_SHIFT 26 extern const ru_field_rec FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD; #define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_MASK 0x02000000 #define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_WIDTH 1 #define FPM_FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_FIELD_SHIFT 25 extern const ru_field_rec FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD; #define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_MASK 0x01000000 #define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_WIDTH 1 #define FPM_FPM_CTL_STOP_ALLOC_CACHE_LOAD_FIELD_SHIFT 24 extern const ru_field_rec FPM_FPM_CTL_RESERVED0_FIELD; #define FPM_FPM_CTL_RESERVED0_FIELD_MASK 0x00fc0000 #define FPM_FPM_CTL_RESERVED0_FIELD_WIDTH 6 #define FPM_FPM_CTL_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_FPM_CTL_POOL2_ENABLE_FIELD; #define FPM_FPM_CTL_POOL2_ENABLE_FIELD_MASK 0x00020000 #define FPM_FPM_CTL_POOL2_ENABLE_FIELD_WIDTH 1 #define FPM_FPM_CTL_POOL2_ENABLE_FIELD_SHIFT 17 extern const ru_field_rec FPM_FPM_CTL_POOL1_ENABLE_FIELD; #define FPM_FPM_CTL_POOL1_ENABLE_FIELD_MASK 0x00010000 #define FPM_FPM_CTL_POOL1_ENABLE_FIELD_WIDTH 1 #define FPM_FPM_CTL_POOL1_ENABLE_FIELD_SHIFT 16 extern const ru_field_rec FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_FIELD; #define FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_FIELD_MASK 0x00008000 #define FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_FIELD_WIDTH 1 #define FPM_FPM_CTL_STRICT_PRIORITY_REQUEST_TYPE_FIELD_SHIFT 15 extern const ru_field_rec FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD; #define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_MASK 0x00004000 #define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_WIDTH 1 #define FPM_FPM_CTL_FPM_BB_SOFT_RESET_FIELD_SHIFT 14 extern const ru_field_rec FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_FIELD; #define FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_FIELD_MASK 0x00003f00 #define FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_FIELD_WIDTH 6 #define FPM_FPM_CTL_WEIGHT_FOR_ROUND_ROBIN_POLICY_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_CTL_ARBITRATION_POLICY_FIELD; #define FPM_FPM_CTL_ARBITRATION_POLICY_FIELD_MASK 0x000000e0 #define FPM_FPM_CTL_ARBITRATION_POLICY_FIELD_WIDTH 3 #define FPM_FPM_CTL_ARBITRATION_POLICY_FIELD_SHIFT 5 extern const ru_field_rec FPM_FPM_CTL_INIT_MEM_FIELD; #define FPM_FPM_CTL_INIT_MEM_FIELD_MASK 0x00000010 #define FPM_FPM_CTL_INIT_MEM_FIELD_WIDTH 1 #define FPM_FPM_CTL_INIT_MEM_FIELD_SHIFT 4 extern const ru_field_rec FPM_FPM_CTL_INIT_MEM_POOL2_FIELD; #define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_MASK 0x00000008 #define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_WIDTH 1 #define FPM_FPM_CTL_INIT_MEM_POOL2_FIELD_SHIFT 3 extern const ru_field_rec FPM_FPM_CTL_RESERVED1_FIELD; #define FPM_FPM_CTL_RESERVED1_FIELD_MASK 0x00000007 #define FPM_FPM_CTL_RESERVED1_FIELD_WIDTH 3 #define FPM_FPM_CTL_RESERVED1_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_CFG1_RESERVED0_FIELD; #define FPM_FPM_CFG1_RESERVED0_FIELD_MASK 0xffffff00 #define FPM_FPM_CFG1_RESERVED0_FIELD_WIDTH 24 #define FPM_FPM_CFG1_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_FIELD; #define FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_FIELD_MASK 0x00000080 #define FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL4_CACHE_BYPASS_EN_FIELD_SHIFT 7 extern const ru_field_rec FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_FIELD; #define FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_FIELD_MASK 0x00000040 #define FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL3_CACHE_BYPASS_EN_FIELD_SHIFT 6 extern const ru_field_rec FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_FIELD; #define FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_FIELD_MASK 0x00000020 #define FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL2_CACHE_BYPASS_EN_FIELD_SHIFT 5 extern const ru_field_rec FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_FIELD; #define FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_FIELD_MASK 0x00000010 #define FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL1_CACHE_BYPASS_EN_FIELD_SHIFT 4 extern const ru_field_rec FPM_FPM_CFG1_POOL4_SEARCH_MODE_FIELD; #define FPM_FPM_CFG1_POOL4_SEARCH_MODE_FIELD_MASK 0x00000008 #define FPM_FPM_CFG1_POOL4_SEARCH_MODE_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL4_SEARCH_MODE_FIELD_SHIFT 3 extern const ru_field_rec FPM_FPM_CFG1_POOL3_SEARCH_MODE_FIELD; #define FPM_FPM_CFG1_POOL3_SEARCH_MODE_FIELD_MASK 0x00000004 #define FPM_FPM_CFG1_POOL3_SEARCH_MODE_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL3_SEARCH_MODE_FIELD_SHIFT 2 extern const ru_field_rec FPM_FPM_CFG1_POOL2_SEARCH_MODE_FIELD; #define FPM_FPM_CFG1_POOL2_SEARCH_MODE_FIELD_MASK 0x00000002 #define FPM_FPM_CFG1_POOL2_SEARCH_MODE_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL2_SEARCH_MODE_FIELD_SHIFT 1 extern const ru_field_rec FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD; #define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_MASK 0x00000001 #define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_WIDTH 1 #define FPM_FPM_CFG1_POOL1_SEARCH_MODE_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD; #define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_MASK 0xff000000 #define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_WIDTH 8 #define FPM_FPM_WEIGHT_DDR1_FREE_WEIGHT_FIELD_SHIFT 24 extern const ru_field_rec FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD; #define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_MASK 0x00ff0000 #define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_WIDTH 8 #define FPM_FPM_WEIGHT_DDR1_ALLOC_WEIGHT_FIELD_SHIFT 16 extern const ru_field_rec FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD; #define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_MASK 0x0000ff00 #define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_WIDTH 8 #define FPM_FPM_WEIGHT_DDR0_FREE_WEIGHT_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD; #define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_MASK 0x000000ff #define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_WIDTH 8 #define FPM_FPM_WEIGHT_DDR0_ALLOC_WEIGHT_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_CFG_RESERVED0_FIELD; #define FPM_FPM_BB_CFG_RESERVED0_FIELD_MASK 0xfffffffc #define FPM_FPM_BB_CFG_RESERVED0_FIELD_WIDTH 30 #define FPM_FPM_BB_CFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD; #define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_MASK 0x00000003 #define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_WIDTH 2 #define FPM_FPM_BB_CFG_BB_DDR_SEL_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_INTR_MSK_RESERVED0_FIELD; #define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_MASK 0xffff8000 #define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_WIDTH 17 #define FPM_POOL1_INTR_MSK_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD; #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_MASK 0x00004000 #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_SHIFT 14 extern const ru_field_rec FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD; #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_MASK 0x00002000 #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_SHIFT 13 extern const ru_field_rec FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD; #define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_MASK 0x00001000 #define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD; #define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_MASK 0x00000800 #define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_SHIFT 11 extern const ru_field_rec FPM_POOL1_INTR_MSK_XON_MSK_FIELD; #define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_MASK 0x00000400 #define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_XON_MSK_FIELD_SHIFT 10 extern const ru_field_rec FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD; #define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_MASK 0x00000200 #define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_XOFF_MSK_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD; #define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_MASK 0x00000100 #define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD; #define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_MASK 0x00000080 #define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD; #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK 0x00000040 #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD; #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_MASK 0x00000020 #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD; #define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK 0x00000010 #define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD; #define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_MASK 0x00000008 #define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD; #define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_MASK 0x00000004 #define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_POOL_FULL_MSK_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD; #define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_MASK 0x00000002 #define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_SHIFT 1 extern const ru_field_rec FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD; #define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_MASK 0x00000001 #define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_INTR_STS_RESERVED0_FIELD; #define FPM_POOL1_INTR_STS_RESERVED0_FIELD_MASK 0xffff8000 #define FPM_POOL1_INTR_STS_RESERVED0_FIELD_WIDTH 17 #define FPM_POOL1_INTR_STS_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD; #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_MASK 0x00004000 #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_SHIFT 14 extern const ru_field_rec FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD; #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_MASK 0x00002000 #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_SHIFT 13 extern const ru_field_rec FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD; #define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_MASK 0x00001000 #define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD; #define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_MASK 0x00000800 #define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_SHIFT 11 extern const ru_field_rec FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD; #define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_MASK 0x00000400 #define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_XON_STATE_STS_FIELD_SHIFT 10 extern const ru_field_rec FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD; #define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_MASK 0x00000200 #define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_XOFF_STATE_STS_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD; #define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_MASK 0x00000100 #define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_MEMORY_CORRUPT_STS_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD; #define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_MASK 0x00000080 #define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD; #define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK 0x00000040 #define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD; #define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_MASK 0x00000020 #define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD; #define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK 0x00000010 #define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD; #define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_MASK 0x00000008 #define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD; #define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_MASK 0x00000004 #define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_POOL_FULL_STS_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD; #define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_MASK 0x00000002 #define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_FREE_FIFO_FULL_STS_FIELD_SHIFT 1 extern const ru_field_rec FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD; #define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_MASK 0x00000001 #define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED0_FIELD; #define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_MASK 0xfffffe00 #define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_WIDTH 23 #define FPM_POOL1_STALL_MSK_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD; #define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_MASK 0x00000100 #define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED1_FIELD; #define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_MASK 0x00000080 #define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_RESERVED1_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD; #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK 0x00000040 #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD; #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK 0x00000020 #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD; #define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK 0x00000010 #define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD; #define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK 0x00000008 #define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL1_STALL_MSK_RESERVED2_FIELD; #define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_MASK 0x00000007 #define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_WIDTH 3 #define FPM_POOL1_STALL_MSK_RESERVED2_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_INTR_MSK_RESERVED0_FIELD; #define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_MASK 0xffff8000 #define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_WIDTH 17 #define FPM_POOL2_INTR_MSK_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD; #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_MASK 0x00004000 #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_FIELD_SHIFT 14 extern const ru_field_rec FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD; #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_MASK 0x00002000 #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_FIELD_SHIFT 13 extern const ru_field_rec FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD; #define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_MASK 0x00001000 #define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD; #define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_MASK 0x00000800 #define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_FIELD_SHIFT 11 extern const ru_field_rec FPM_POOL2_INTR_MSK_XON_MSK_FIELD; #define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_MASK 0x00000400 #define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_XON_MSK_FIELD_SHIFT 10 extern const ru_field_rec FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD; #define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_MASK 0x00000200 #define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_XOFF_MSK_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD; #define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_MASK 0x00000100 #define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD; #define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_MASK 0x00000080 #define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD; #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK 0x00000040 #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD; #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_MASK 0x00000020 #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD; #define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_MASK 0x00000010 #define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD; #define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_MASK 0x00000008 #define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD; #define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_MASK 0x00000004 #define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_POOL_FULL_MSK_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD; #define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_MASK 0x00000002 #define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_FIELD_SHIFT 1 extern const ru_field_rec FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD; #define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_MASK 0x00000001 #define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_INTR_STS_RESERVED0_FIELD; #define FPM_POOL2_INTR_STS_RESERVED0_FIELD_MASK 0xffff8000 #define FPM_POOL2_INTR_STS_RESERVED0_FIELD_WIDTH 17 #define FPM_POOL2_INTR_STS_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD; #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_MASK 0x00004000 #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_FIELD_SHIFT 14 extern const ru_field_rec FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD; #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_MASK 0x00002000 #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_FIELD_SHIFT 13 extern const ru_field_rec FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD; #define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_MASK 0x00001000 #define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD; #define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_MASK 0x00000800 #define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_FIELD_SHIFT 11 extern const ru_field_rec FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD; #define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_MASK 0x00000400 #define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_XON_STATE_STS_FIELD_SHIFT 10 extern const ru_field_rec FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD; #define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_MASK 0x00000200 #define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_XOFF_STATE_STS_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD; #define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_MASK 0x00000100 #define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_MEMORY_CORRUPT_STS_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD; #define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_MASK 0x00000080 #define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD; #define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK 0x00000040 #define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD; #define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_MASK 0x00000020 #define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD; #define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_MASK 0x00000010 #define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD; #define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_MASK 0x00000008 #define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD; #define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_MASK 0x00000004 #define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_POOL_FULL_STS_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD; #define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_MASK 0x00000002 #define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_FREE_FIFO_FULL_STS_FIELD_SHIFT 1 extern const ru_field_rec FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD; #define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_MASK 0x00000001 #define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_WIDTH 1 #define FPM_POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED0_FIELD; #define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_MASK 0xfffffe00 #define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_WIDTH 23 #define FPM_POOL2_STALL_MSK_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD; #define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_MASK 0x00000100 #define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_FIELD_SHIFT 8 extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED1_FIELD; #define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_MASK 0x00000080 #define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_RESERVED1_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD; #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK 0x00000040 #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 6 extern const ru_field_rec FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD; #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK 0x00000020 #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 5 extern const ru_field_rec FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD; #define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_MASK 0x00000010 #define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_FIELD_SHIFT 4 extern const ru_field_rec FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD; #define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_MASK 0x00000008 #define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_WIDTH 1 #define FPM_POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_FIELD_SHIFT 3 extern const ru_field_rec FPM_POOL2_STALL_MSK_RESERVED2_FIELD; #define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_MASK 0x00000007 #define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_WIDTH 3 #define FPM_POOL2_STALL_MSK_RESERVED2_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_CFG1_RESERVED0_FIELD; #define FPM_POOL1_CFG1_RESERVED0_FIELD_MASK 0xf8000000 #define FPM_POOL1_CFG1_RESERVED0_FIELD_WIDTH 5 #define FPM_POOL1_CFG1_RESERVED0_FIELD_SHIFT 27 extern const ru_field_rec FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD; #define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_MASK 0x07000000 #define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_WIDTH 3 #define FPM_POOL1_CFG1_FPM_BUF_SIZE_FIELD_SHIFT 24 extern const ru_field_rec FPM_POOL1_CFG1_RESERVED1_FIELD; #define FPM_POOL1_CFG1_RESERVED1_FIELD_MASK 0x00ffffff #define FPM_POOL1_CFG1_RESERVED1_FIELD_WIDTH 24 #define FPM_POOL1_CFG1_RESERVED1_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD; #define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_MASK 0xfffffffc #define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_WIDTH 30 #define FPM_POOL1_CFG2_POOL_BASE_ADDRESS_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL1_CFG2_RESERVED0_FIELD; #define FPM_POOL1_CFG2_RESERVED0_FIELD_MASK 0x00000003 #define FPM_POOL1_CFG2_RESERVED0_FIELD_WIDTH 2 #define FPM_POOL1_CFG2_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD; #define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_MASK 0xfffffffc #define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_WIDTH 30 #define FPM_POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_FIELD_SHIFT 2 extern const ru_field_rec FPM_POOL1_CFG3_RESERVED0_FIELD; #define FPM_POOL1_CFG3_RESERVED0_FIELD_MASK 0x00000003 #define FPM_POOL1_CFG3_RESERVED0_FIELD_WIDTH 2 #define FPM_POOL1_CFG3_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT1_OVRFL_FIELD; #define FPM_POOL1_STAT1_OVRFL_FIELD_MASK 0xffff0000 #define FPM_POOL1_STAT1_OVRFL_FIELD_WIDTH 16 #define FPM_POOL1_STAT1_OVRFL_FIELD_SHIFT 16 extern const ru_field_rec FPM_POOL1_STAT1_UNDRFL_FIELD; #define FPM_POOL1_STAT1_UNDRFL_FIELD_MASK 0x0000ffff #define FPM_POOL1_STAT1_UNDRFL_FIELD_WIDTH 16 #define FPM_POOL1_STAT1_UNDRFL_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT2_POOL_FULL_FIELD; #define FPM_POOL1_STAT2_POOL_FULL_FIELD_MASK 0x80000000 #define FPM_POOL1_STAT2_POOL_FULL_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_POOL_FULL_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL1_STAT2_RESERVED0_FIELD; #define FPM_POOL1_STAT2_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL1_STAT2_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD; #define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_MASK 0x20000000 #define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_FREE_FIFO_FULL_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD; #define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_MASK 0x10000000 #define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_FREE_FIFO_EMPTY_FIELD_SHIFT 28 extern const ru_field_rec FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD; #define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_MASK 0x08000000 #define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_ALLOC_FIFO_FULL_FIELD_SHIFT 27 extern const ru_field_rec FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD; #define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_MASK 0x04000000 #define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_POOL1_STAT2_ALLOC_FIFO_EMPTY_FIELD_SHIFT 26 extern const ru_field_rec FPM_POOL1_STAT2_RESERVED1_FIELD; #define FPM_POOL1_STAT2_RESERVED1_FIELD_MASK 0x03fc0000 #define FPM_POOL1_STAT2_RESERVED1_FIELD_WIDTH 8 #define FPM_POOL1_STAT2_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD; #define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_MASK 0x0003ffff #define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_WIDTH 18 #define FPM_POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT3_RESERVED0_FIELD; #define FPM_POOL1_STAT3_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL1_STAT3_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL1_STAT3_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD; #define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_MASK 0x0003ffff #define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_WIDTH 18 #define FPM_POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT4_RESERVED0_FIELD; #define FPM_POOL1_STAT4_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL1_STAT4_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL1_STAT4_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD; #define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_MASK 0x0003ffff #define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_WIDTH 18 #define FPM_POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD; #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD; #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_WIDTH 31 #define FPM_POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD; #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD; #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_WIDTH 31 #define FPM_POOL1_STAT6_INVALID_FREE_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD; #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD; #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_WIDTH 31 #define FPM_POOL1_STAT7_INVALID_MCAST_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_STAT8_RESERVED0_FIELD; #define FPM_POOL1_STAT8_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL1_STAT8_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL1_STAT8_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD; #define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_MASK 0x0003ffff #define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_WIDTH 18 #define FPM_POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT1_OVRFL_FIELD; #define FPM_POOL2_STAT1_OVRFL_FIELD_MASK 0xffff0000 #define FPM_POOL2_STAT1_OVRFL_FIELD_WIDTH 16 #define FPM_POOL2_STAT1_OVRFL_FIELD_SHIFT 16 extern const ru_field_rec FPM_POOL2_STAT1_UNDRFL_FIELD; #define FPM_POOL2_STAT1_UNDRFL_FIELD_MASK 0x0000ffff #define FPM_POOL2_STAT1_UNDRFL_FIELD_WIDTH 16 #define FPM_POOL2_STAT1_UNDRFL_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT2_POOL_FULL_FIELD; #define FPM_POOL2_STAT2_POOL_FULL_FIELD_MASK 0x80000000 #define FPM_POOL2_STAT2_POOL_FULL_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_POOL_FULL_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL2_STAT2_RESERVED0_FIELD; #define FPM_POOL2_STAT2_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL2_STAT2_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD; #define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_MASK 0x20000000 #define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_FREE_FIFO_FULL_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD; #define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_MASK 0x10000000 #define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_FREE_FIFO_EMPTY_FIELD_SHIFT 28 extern const ru_field_rec FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD; #define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_MASK 0x08000000 #define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_ALLOC_FIFO_FULL_FIELD_SHIFT 27 extern const ru_field_rec FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD; #define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_MASK 0x04000000 #define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_POOL2_STAT2_ALLOC_FIFO_EMPTY_FIELD_SHIFT 26 extern const ru_field_rec FPM_POOL2_STAT2_RESERVED1_FIELD; #define FPM_POOL2_STAT2_RESERVED1_FIELD_MASK 0x03fc0000 #define FPM_POOL2_STAT2_RESERVED1_FIELD_WIDTH 8 #define FPM_POOL2_STAT2_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD; #define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_MASK 0x0003ffff #define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_WIDTH 18 #define FPM_POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT3_RESERVED0_FIELD; #define FPM_POOL2_STAT3_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL2_STAT3_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL2_STAT3_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD; #define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_MASK 0x0003ffff #define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_WIDTH 18 #define FPM_POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT4_RESERVED0_FIELD; #define FPM_POOL2_STAT4_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL2_STAT4_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL2_STAT4_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD; #define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_MASK 0x0003ffff #define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_WIDTH 18 #define FPM_POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD; #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD; #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_WIDTH 31 #define FPM_POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD; #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD; #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_WIDTH 31 #define FPM_POOL2_STAT6_INVALID_FREE_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD; #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD; #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_MASK 0x7fffffff #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_WIDTH 31 #define FPM_POOL2_STAT7_INVALID_MCAST_TOKEN_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_STAT8_RESERVED0_FIELD; #define FPM_POOL2_STAT8_RESERVED0_FIELD_MASK 0xfffc0000 #define FPM_POOL2_STAT8_RESERVED0_FIELD_WIDTH 14 #define FPM_POOL2_STAT8_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD; #define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_MASK 0x0003ffff #define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_WIDTH 18 #define FPM_POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD; #define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_MASK 0xffff0000 #define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_WIDTH 16 #define FPM_POOL1_XON_XOFF_CFG_XON_THRESHOLD_FIELD_SHIFT 16 extern const ru_field_rec FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD; #define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_MASK 0x0000ffff #define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_WIDTH 16 #define FPM_POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD; #define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_MASK 0xffffffc0 #define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_WIDTH 26 #define FPM_FPM_NOT_EMPTY_CFG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD; #define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_MASK 0x0000003f #define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_WIDTH 6 #define FPM_FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec FPM_MEM_CTL_MEM_WR_FIELD; #define FPM_MEM_CTL_MEM_WR_FIELD_MASK 0x80000000 #define FPM_MEM_CTL_MEM_WR_FIELD_WIDTH 1 #define FPM_MEM_CTL_MEM_WR_FIELD_SHIFT 31 extern const ru_field_rec FPM_MEM_CTL_MEM_RD_FIELD; #define FPM_MEM_CTL_MEM_RD_FIELD_MASK 0x40000000 #define FPM_MEM_CTL_MEM_RD_FIELD_WIDTH 1 #define FPM_MEM_CTL_MEM_RD_FIELD_SHIFT 30 extern const ru_field_rec FPM_MEM_CTL_MEM_SEL_FIELD; #define FPM_MEM_CTL_MEM_SEL_FIELD_MASK 0x30000000 #define FPM_MEM_CTL_MEM_SEL_FIELD_WIDTH 2 #define FPM_MEM_CTL_MEM_SEL_FIELD_SHIFT 28 extern const ru_field_rec FPM_MEM_CTL_RESERVED0_FIELD; #define FPM_MEM_CTL_RESERVED0_FIELD_MASK 0x0ffc0000 #define FPM_MEM_CTL_RESERVED0_FIELD_WIDTH 10 #define FPM_MEM_CTL_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec FPM_MEM_CTL_MEM_ADDR_FIELD; #define FPM_MEM_CTL_MEM_ADDR_FIELD_MASK 0x0003fffc #define FPM_MEM_CTL_MEM_ADDR_FIELD_WIDTH 16 #define FPM_MEM_CTL_MEM_ADDR_FIELD_SHIFT 2 extern const ru_field_rec FPM_MEM_CTL_RESERVED1_FIELD; #define FPM_MEM_CTL_RESERVED1_FIELD_MASK 0x00000003 #define FPM_MEM_CTL_RESERVED1_FIELD_WIDTH 2 #define FPM_MEM_CTL_RESERVED1_FIELD_SHIFT 0 extern const ru_field_rec FPM_MEM_DATA1_MEM_DATA1_FIELD; #define FPM_MEM_DATA1_MEM_DATA1_FIELD_MASK 0xffffffff #define FPM_MEM_DATA1_MEM_DATA1_FIELD_WIDTH 32 #define FPM_MEM_DATA1_MEM_DATA1_FIELD_SHIFT 0 extern const ru_field_rec FPM_MEM_DATA2_MEM_DATA2_FIELD; #define FPM_MEM_DATA2_MEM_DATA2_FIELD_MASK 0xffffffff #define FPM_MEM_DATA2_MEM_DATA2_FIELD_WIDTH 32 #define FPM_MEM_DATA2_MEM_DATA2_FIELD_SHIFT 0 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD; #define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_MASK 0xffffff80 #define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_WIDTH 25 #define FPM_TOKEN_RECOVER_CTL_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD; #define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_MASK 0x00000040 #define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_FIELD_SHIFT 6 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD; #define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_MASK 0x00000020 #define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_FIELD_SHIFT 5 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD; #define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_MASK 0x00000010 #define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_FIELD_SHIFT 4 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD; #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_MASK 0x00000008 #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_FIELD_SHIFT 3 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD; #define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_MASK 0x00000004 #define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_FIELD_SHIFT 2 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD; #define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_MASK 0x00000002 #define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_FIELD_SHIFT 1 extern const ru_field_rec FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD; #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_MASK 0x00000001 #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_WIDTH 1 #define FPM_TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_FIELD_SHIFT 0 extern const ru_field_rec FPM_SHORT_AGING_TIMER_TIMER_FIELD; #define FPM_SHORT_AGING_TIMER_TIMER_FIELD_MASK 0xffffffff #define FPM_SHORT_AGING_TIMER_TIMER_FIELD_WIDTH 32 #define FPM_SHORT_AGING_TIMER_TIMER_FIELD_SHIFT 0 extern const ru_field_rec FPM_LONG_AGING_TIMER_TIMER_FIELD; #define FPM_LONG_AGING_TIMER_TIMER_FIELD_MASK 0xffffffff #define FPM_LONG_AGING_TIMER_TIMER_FIELD_WIDTH 32 #define FPM_LONG_AGING_TIMER_TIMER_FIELD_SHIFT 0 extern const ru_field_rec FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD; #define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_MASK 0xffff0000 #define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_WIDTH 16 #define FPM_CACHE_RECYCLE_TIMER_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD; #define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_MASK 0x0000ffff #define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_WIDTH 16 #define FPM_CACHE_RECYCLE_TIMER_RECYCLE_TIMER_FIELD_SHIFT 0 extern const ru_field_rec FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD; #define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_MASK 0xffffffff #define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_WIDTH 32 #define FPM_EXPIRED_TOKEN_COUNT_POOL1_COUNT_FIELD_SHIFT 0 extern const ru_field_rec FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD; #define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_MASK 0xffffffff #define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_WIDTH 32 #define FPM_RECOVERED_TOKEN_COUNT_POOL1_COUNT_FIELD_SHIFT 0 extern const ru_field_rec FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD; #define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_MASK 0xffffffff #define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_WIDTH 32 #define FPM_EXPIRED_TOKEN_COUNT_POOL2_COUNT_FIELD_SHIFT 0 extern const ru_field_rec FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD; #define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_MASK 0xffffffff #define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_WIDTH 32 #define FPM_RECOVERED_TOKEN_COUNT_POOL2_COUNT_FIELD_SHIFT 0 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_MASK 0xf0000000 #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_WIDTH 4 #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_MASK 0x0fff0000 #define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_WIDTH 12 #define FPM_TOKEN_RECOVER_START_END_POOL1_START_INDEX_FIELD_SHIFT 16 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_MASK 0x0000f000 #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_WIDTH 4 #define FPM_TOKEN_RECOVER_START_END_POOL1_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_MASK 0x00000fff #define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_WIDTH 12 #define FPM_TOKEN_RECOVER_START_END_POOL1_END_INDEX_FIELD_SHIFT 0 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_MASK 0xf0000000 #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_WIDTH 4 #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_MASK 0x0fff0000 #define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_WIDTH 12 #define FPM_TOKEN_RECOVER_START_END_POOL2_START_INDEX_FIELD_SHIFT 16 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_MASK 0x0000f000 #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_WIDTH 4 #define FPM_TOKEN_RECOVER_START_END_POOL2_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD; #define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_MASK 0x00000fff #define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_WIDTH 12 #define FPM_TOKEN_RECOVER_START_END_POOL2_END_INDEX_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD; #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD; #define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL1_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD; #define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_MASK 0x20000000 #define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1 #define FPM_POOL1_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD; #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK 0x1ffff000 #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17 #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD; #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK 0x00000fff #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12 #define FPM_POOL1_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD; #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD; #define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL2_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD; #define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_MASK 0x20000000 #define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1 #define FPM_POOL2_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD; #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK 0x1ffff000 #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17 #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD; #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK 0x00000fff #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12 #define FPM_POOL2_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD; #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD; #define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL3_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD; #define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_MASK 0x20000000 #define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1 #define FPM_POOL3_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD; #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK 0x1ffff000 #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17 #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD; #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK 0x00000fff #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12 #define FPM_POOL3_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD; #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD; #define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL4_ALLOC_DEALLOC_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD; #define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_MASK 0x20000000 #define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_WIDTH 1 #define FPM_POOL4_ALLOC_DEALLOC_DDR_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD; #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_MASK 0x1ffff000 #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_WIDTH 17 #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_INDEX_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD; #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_MASK 0x00000fff #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_WIDTH 12 #define FPM_POOL4_ALLOC_DEALLOC_TOKEN_SIZE_FIELD_SHIFT 0 extern const ru_field_rec FPM_SPARE_SPARE_BITS_FIELD; #define FPM_SPARE_SPARE_BITS_FIELD_MASK 0xffffffff #define FPM_SPARE_SPARE_BITS_FIELD_WIDTH 32 #define FPM_SPARE_SPARE_BITS_FIELD_SHIFT 0 extern const ru_field_rec FPM_POOL_MULTI_TOKEN_VALID_FIELD; #define FPM_POOL_MULTI_TOKEN_VALID_FIELD_MASK 0x80000000 #define FPM_POOL_MULTI_TOKEN_VALID_FIELD_WIDTH 1 #define FPM_POOL_MULTI_TOKEN_VALID_FIELD_SHIFT 31 extern const ru_field_rec FPM_POOL_MULTI_RESERVED0_FIELD; #define FPM_POOL_MULTI_RESERVED0_FIELD_MASK 0x40000000 #define FPM_POOL_MULTI_RESERVED0_FIELD_WIDTH 1 #define FPM_POOL_MULTI_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec FPM_POOL_MULTI_DDR_FIELD; #define FPM_POOL_MULTI_DDR_FIELD_MASK 0x20000000 #define FPM_POOL_MULTI_DDR_FIELD_WIDTH 1 #define FPM_POOL_MULTI_DDR_FIELD_SHIFT 29 extern const ru_field_rec FPM_POOL_MULTI_TOKEN_INDEX_FIELD; #define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_MASK 0x1ffff000 #define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_WIDTH 17 #define FPM_POOL_MULTI_TOKEN_INDEX_FIELD_SHIFT 12 extern const ru_field_rec FPM_POOL_MULTI_UPDATE_TYPE_FIELD; #define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_MASK 0x00000800 #define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_WIDTH 1 #define FPM_POOL_MULTI_UPDATE_TYPE_FIELD_SHIFT 11 extern const ru_field_rec FPM_POOL_MULTI_RESERVED1_FIELD; #define FPM_POOL_MULTI_RESERVED1_FIELD_MASK 0x00000780 #define FPM_POOL_MULTI_RESERVED1_FIELD_WIDTH 4 #define FPM_POOL_MULTI_RESERVED1_FIELD_SHIFT 7 extern const ru_field_rec FPM_POOL_MULTI_TOKEN_MULTI_FIELD; #define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_MASK 0x0000007f #define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_WIDTH 7 #define FPM_POOL_MULTI_TOKEN_MULTI_FIELD_SHIFT 0 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_RESERVED0_FIELD; #define FPM_SEARCH_MEMORY_HIGH_RESERVED0_FIELD_MASK 0xffff0000 #define FPM_SEARCH_MEMORY_HIGH_RESERVED0_FIELD_WIDTH 16 #define FPM_SEARCH_MEMORY_HIGH_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA15_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA15_FIELD_MASK 0x0000e000 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA15_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA15_FIELD_SHIFT 13 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA14_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA14_FIELD_MASK 0x00001c00 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA14_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA14_FIELD_SHIFT 10 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA13_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA13_FIELD_MASK 0x00000380 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA13_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA13_FIELD_SHIFT 7 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA12_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA12_FIELD_MASK 0x00000070 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA12_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA12_FIELD_SHIFT 4 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA11_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA11_FIELD_MASK 0x0000000e #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA11_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA11_FIELD_SHIFT 1 extern const ru_field_rec FPM_SEARCH_MEMORY_HIGH_SEARCHDATA10_FIELD; #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA10_FIELD_MASK 0x00000001 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA10_FIELD_WIDTH 1 #define FPM_SEARCH_MEMORY_HIGH_SEARCHDATA10_FIELD_SHIFT 0 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA10_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA10_FIELD_MASK 0xc0000000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA10_FIELD_WIDTH 2 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA10_FIELD_SHIFT 30 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA9_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA9_FIELD_MASK 0x38000000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA9_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA9_FIELD_SHIFT 27 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA8_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA8_FIELD_MASK 0x07000000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA8_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA8_FIELD_SHIFT 24 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA7_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA7_FIELD_MASK 0x00e00000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA7_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA7_FIELD_SHIFT 21 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA6_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA6_FIELD_MASK 0x001c0000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA6_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA6_FIELD_SHIFT 18 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA5_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA5_FIELD_MASK 0x00038000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA5_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA5_FIELD_SHIFT 15 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA4_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA4_FIELD_MASK 0x00007000 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA4_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA4_FIELD_SHIFT 12 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA3_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA3_FIELD_MASK 0x00000e00 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA3_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA3_FIELD_SHIFT 9 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA2_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA2_FIELD_MASK 0x000001c0 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA2_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA2_FIELD_SHIFT 6 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA1_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA1_FIELD_MASK 0x00000038 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA1_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA1_FIELD_SHIFT 3 extern const ru_field_rec FPM_SEARCH_MEMORY_LOW_SEARCHDATA0_FIELD; #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA0_FIELD_MASK 0x00000007 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA0_FIELD_WIDTH 3 #define FPM_SEARCH_MEMORY_LOW_SEARCHDATA0_FIELD_SHIFT 0 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_TOKENMARK7_FIELD; #define FPM_MCAST_MEMORY_HIGH_TOKENMARK7_FIELD_MASK 0x80000000 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK7_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK7_FIELD_SHIFT 31 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_MULTICAST7_FIELD; #define FPM_MCAST_MEMORY_HIGH_MULTICAST7_FIELD_MASK 0x7f000000 #define FPM_MCAST_MEMORY_HIGH_MULTICAST7_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_HIGH_MULTICAST7_FIELD_SHIFT 24 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_TOKENMARK6_FIELD; #define FPM_MCAST_MEMORY_HIGH_TOKENMARK6_FIELD_MASK 0x00800000 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK6_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK6_FIELD_SHIFT 23 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_MULTICAST6_FIELD; #define FPM_MCAST_MEMORY_HIGH_MULTICAST6_FIELD_MASK 0x007f0000 #define FPM_MCAST_MEMORY_HIGH_MULTICAST6_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_HIGH_MULTICAST6_FIELD_SHIFT 16 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_TOKENMARK5_FIELD; #define FPM_MCAST_MEMORY_HIGH_TOKENMARK5_FIELD_MASK 0x00008000 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK5_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK5_FIELD_SHIFT 15 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_MULTICAST5_FIELD; #define FPM_MCAST_MEMORY_HIGH_MULTICAST5_FIELD_MASK 0x00007f00 #define FPM_MCAST_MEMORY_HIGH_MULTICAST5_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_HIGH_MULTICAST5_FIELD_SHIFT 8 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_TOKENMARK4_FIELD; #define FPM_MCAST_MEMORY_HIGH_TOKENMARK4_FIELD_MASK 0x00000080 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK4_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_HIGH_TOKENMARK4_FIELD_SHIFT 7 extern const ru_field_rec FPM_MCAST_MEMORY_HIGH_MULTICAST4_FIELD; #define FPM_MCAST_MEMORY_HIGH_MULTICAST4_FIELD_MASK 0x0000007f #define FPM_MCAST_MEMORY_HIGH_MULTICAST4_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_HIGH_MULTICAST4_FIELD_SHIFT 0 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_TOKENMARK3_FIELD; #define FPM_MCAST_MEMORY_LOW_TOKENMARK3_FIELD_MASK 0x80000000 #define FPM_MCAST_MEMORY_LOW_TOKENMARK3_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_LOW_TOKENMARK3_FIELD_SHIFT 31 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_MULTICAST3_FIELD; #define FPM_MCAST_MEMORY_LOW_MULTICAST3_FIELD_MASK 0x7f000000 #define FPM_MCAST_MEMORY_LOW_MULTICAST3_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_LOW_MULTICAST3_FIELD_SHIFT 24 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_TOKENMARK2_FIELD; #define FPM_MCAST_MEMORY_LOW_TOKENMARK2_FIELD_MASK 0x00800000 #define FPM_MCAST_MEMORY_LOW_TOKENMARK2_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_LOW_TOKENMARK2_FIELD_SHIFT 23 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_MULTICAST2_FIELD; #define FPM_MCAST_MEMORY_LOW_MULTICAST2_FIELD_MASK 0x007f0000 #define FPM_MCAST_MEMORY_LOW_MULTICAST2_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_LOW_MULTICAST2_FIELD_SHIFT 16 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_TOKENMARK1_FIELD; #define FPM_MCAST_MEMORY_LOW_TOKENMARK1_FIELD_MASK 0x00008000 #define FPM_MCAST_MEMORY_LOW_TOKENMARK1_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_LOW_TOKENMARK1_FIELD_SHIFT 15 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_MULTICAST1_FIELD; #define FPM_MCAST_MEMORY_LOW_MULTICAST1_FIELD_MASK 0x00007f00 #define FPM_MCAST_MEMORY_LOW_MULTICAST1_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_LOW_MULTICAST1_FIELD_SHIFT 8 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_TOKENMARK0_FIELD; #define FPM_MCAST_MEMORY_LOW_TOKENMARK0_FIELD_MASK 0x00000080 #define FPM_MCAST_MEMORY_LOW_TOKENMARK0_FIELD_WIDTH 1 #define FPM_MCAST_MEMORY_LOW_TOKENMARK0_FIELD_SHIFT 7 extern const ru_field_rec FPM_MCAST_MEMORY_LOW_MULTICAST0_FIELD; #define FPM_MCAST_MEMORY_LOW_MULTICAST0_FIELD_MASK 0x0000007f #define FPM_MCAST_MEMORY_LOW_MULTICAST0_FIELD_WIDTH 7 #define FPM_MCAST_MEMORY_LOW_MULTICAST0_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_FORCE_FORCE_FIELD; #define FPM_FPM_BB_FORCE_FORCE_FIELD_MASK 0x00000001 #define FPM_FPM_BB_FORCE_FORCE_FIELD_WIDTH 1 #define FPM_FPM_BB_FORCE_FORCE_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_FORCE_RESERVED0_FIELD; #define FPM_FPM_BB_FORCE_RESERVED0_FIELD_MASK 0xfffffffe #define FPM_FPM_BB_FORCE_RESERVED0_FIELD_WIDTH 31 #define FPM_FPM_BB_FORCE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD; #define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_MASK 0x00000fff #define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_WIDTH 12 #define FPM_FPM_BB_FORCED_CTRL_CTRL_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD; #define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_MASK 0xfffff000 #define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_WIDTH 20 #define FPM_FPM_BB_FORCED_CTRL_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD; #define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_MASK 0x0000ffff #define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_WIDTH 16 #define FPM_FPM_BB_FORCED_ADDR_TA_ADDR_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD; #define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_MASK 0x003f0000 #define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_WIDTH 6 #define FPM_FPM_BB_FORCED_ADDR_DEST_ADDR_FIELD_SHIFT 16 extern const ru_field_rec FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD; #define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_MASK 0xffc00000 #define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_WIDTH 10 #define FPM_FPM_BB_FORCED_ADDR_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec FPM_FPM_BB_FORCED_DATA_DATA_FIELD; #define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_FORCED_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD; #define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_MASK 0x0000003f #define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_WIDTH 6 #define FPM_FPM_BB_DECODE_CFG_DEST_ID_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD; #define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_MASK 0x00000040 #define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_WIDTH 1 #define FPM_FPM_BB_DECODE_CFG_OVERRIDE_EN_FIELD_SHIFT 6 extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD; #define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_MASK 0x0001ff80 #define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_WIDTH 10 #define FPM_FPM_BB_DECODE_CFG_ROUTE_ADDR_FIELD_SHIFT 7 extern const ru_field_rec FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD; #define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_MASK 0xfffe0000 #define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_WIDTH 15 #define FPM_FPM_BB_DECODE_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD; #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_MASK 0x0000000f #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_WIDTH 4 #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD; #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_MASK 0x000000f0 #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_WIDTH 4 #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_FIELD_SHIFT 4 extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD; #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_MASK 0x00000100 #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_CFG_RXFIFO_SW_RST_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD; #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_MASK 0x00000200 #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_CFG_TXFIFO_SW_RST_FIELD_SHIFT 9 extern const ru_field_rec FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD; #define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_MASK 0xfffffc00 #define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_WIDTH 22 #define FPM_FPM_BB_DBG_CFG_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_MASK 0x00000001 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_MASK 0x00000002 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_FIELD_SHIFT 1 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_MASK 0x000000fc #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_WIDTH 6 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_MASK 0x00001f00 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_MASK 0x0000e000 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_MASK 0x001f0000 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_FIELD_SHIFT 16 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_MASK 0x00e00000 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED2_FIELD_SHIFT 21 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_MASK 0x1f000000 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_FIELD_SHIFT 24 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_MASK 0xe0000000 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_RXFIFO_STS_RESERVED3_FIELD_SHIFT 29 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_MASK 0x00000001 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_MASK 0x00000002 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_WIDTH 1 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_FIELD_SHIFT 1 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_MASK 0x000000fc #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_WIDTH 6 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_MASK 0x00001f00 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_FIELD_SHIFT 8 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_MASK 0x0000e000 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_MASK 0x001f0000 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_FIELD_SHIFT 16 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_MASK 0x00e00000 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED2_FIELD_SHIFT 21 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_MASK 0x1f000000 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_WIDTH 5 #define FPM_FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_FIELD_SHIFT 24 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_MASK 0xe0000000 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_WIDTH 3 #define FPM_FPM_BB_DBG_TXFIFO_STS_RESERVED3_FIELD_SHIFT 29 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_DBG_RXFIFO_DATA1_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD; #define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_DBG_RXFIFO_DATA2_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_DBG_TXFIFO_DATA1_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_DBG_TXFIFO_DATA2_DATA_FIELD_SHIFT 0 extern const ru_field_rec FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD; #define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_MASK 0xffffffff #define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_WIDTH 32 #define FPM_FPM_BB_DBG_TXFIFO_DATA3_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_MEM_HIGH_DATA_MEM_FIELD; #define RNR_MEM_HIGH_DATA_MEM_FIELD_MASK 0xffffffff #define RNR_MEM_HIGH_DATA_MEM_FIELD_WIDTH 32 #define RNR_MEM_HIGH_DATA_MEM_FIELD_SHIFT 0 extern const ru_field_rec RNR_MEM_LOW_DATA_MEM_FIELD; #define RNR_MEM_LOW_DATA_MEM_FIELD_MASK 0xffffffff #define RNR_MEM_LOW_DATA_MEM_FIELD_WIDTH 32 #define RNR_MEM_LOW_DATA_MEM_FIELD_SHIFT 0 extern const ru_field_rec RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD; #define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_MASK 0xffffffff #define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_WIDTH 32 #define RNR_INST_MEM_ENTRY_INSTRUCTION_FIELD_SHIFT 0 extern const ru_field_rec RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD; #define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_MASK 0xffffffff #define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_WIDTH 32 #define RNR_CNTXT_MEM_ENTRY_CONTEXT_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD; #define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_MASK 0x0000ffff #define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_WIDTH 16 #define RNR_PRED_MEM_ENTRY_PRED_MEM_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD; #define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_MASK 0x00000001 #define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_GLOBAL_CTRL_EN_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD; #define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_MASK 0x00000002 #define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_WIDTH 1 #define RNR_REGS_CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_FIELD_SHIFT 1 extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD; #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_MASK 0x000000fc #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_WIDTH 6 #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD; #define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_MASK 0x0003ff00 #define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_WIDTH 10 #define RNR_REGS_CFG_GLOBAL_CTRL_MICRO_SEC_VAL_FIELD_SHIFT 8 extern const ru_field_rec RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD; #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_MASK 0xfffc0000 #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_WIDTH 14 #define RNR_REGS_CFG_GLOBAL_CTRL_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD; #define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_MASK 0x0000000f #define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_WIDTH 4 #define RNR_REGS_CFG_CPU_WAKEUP_THREAD_NUM_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD; #define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_MASK 0xfffffff0 #define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_WIDTH 28 #define RNR_REGS_CFG_CPU_WAKEUP_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_MASK 0x000000ff #define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_WIDTH 8 #define RNR_REGS_CFG_INT_CTRL_INT0_STS_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_MASK 0x0000ff00 #define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_WIDTH 8 #define RNR_REGS_CFG_INT_CTRL_INT1_STS_FIELD_SHIFT 8 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_MASK 0x00010000 #define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT2_STS_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_MASK 0x00020000 #define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT3_STS_FIELD_SHIFT 17 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_MASK 0x00040000 #define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT4_STS_FIELD_SHIFT 18 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_MASK 0x00080000 #define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT5_STS_FIELD_SHIFT 19 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_MASK 0x00100000 #define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT6_STS_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_MASK 0x00200000 #define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT7_STS_FIELD_SHIFT 21 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_MASK 0x00400000 #define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT8_STS_FIELD_SHIFT 22 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_MASK 0x00800000 #define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_INT9_STS_FIELD_SHIFT 23 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD; #define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_MASK 0x7f000000 #define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_WIDTH 7 #define RNR_REGS_CFG_INT_CTRL_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD; #define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_MASK 0x80000000 #define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_CTRL_FIT_FAIL_STS_FIELD_SHIFT 31 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_MASK 0x000000ff #define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_WIDTH 8 #define RNR_REGS_CFG_INT_MASK_INT0_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_MASK 0x0000ff00 #define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_WIDTH 8 #define RNR_REGS_CFG_INT_MASK_INT1_MASK_FIELD_SHIFT 8 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_MASK 0x00010000 #define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT2_MASK_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_MASK 0x00020000 #define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT3_MASK_FIELD_SHIFT 17 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_MASK 0x00040000 #define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT4_MASK_FIELD_SHIFT 18 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_MASK 0x00080000 #define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT5_MASK_FIELD_SHIFT 19 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_MASK 0x00100000 #define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT6_MASK_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_MASK 0x00200000 #define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT7_MASK_FIELD_SHIFT 21 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_MASK 0x00400000 #define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT8_MASK_FIELD_SHIFT 22 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD; #define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_MASK 0x00800000 #define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_INT_MASK_INT9_MASK_FIELD_SHIFT 23 extern const ru_field_rec RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD; #define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_MASK 0xff000000 #define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_WIDTH 8 #define RNR_REGS_CFG_INT_MASK_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD; #define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_MASK 0x00000001 #define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_WIDTH 1 #define RNR_REGS_CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD; #define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_MASK 0x00000002 #define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_WIDTH 1 #define RNR_REGS_CFG_GEN_CFG_TEST_FIT_FAIL_FIELD_SHIFT 1 extern const ru_field_rec RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_MASK 0xfffffffc #define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_WIDTH 30 #define RNR_REGS_CFG_GEN_CFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD; #define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_MASK 0x0000ffff #define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_WIDTH 16 #define RNR_REGS_CFG_CAM_CFG_STOP_VALUE_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_WIDTH 16 #define RNR_REGS_CFG_CAM_CFG_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD; #define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_MASK 0x000fffff #define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_WIDTH 20 #define RNR_REGS_CFG_DDR_CFG_DMA_BASE_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD; #define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_MASK 0x00700000 #define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_WIDTH 3 #define RNR_REGS_CFG_DDR_CFG_DMA_BUF_SIZE_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_DDR_CFG_RESERVED0_FIELD_MASK 0x00800000 #define RNR_REGS_CFG_DDR_CFG_RESERVED0_FIELD_WIDTH 1 #define RNR_REGS_CFG_DDR_CFG_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD; #define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_MASK 0xff000000 #define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_WIDTH 8 #define RNR_REGS_CFG_DDR_CFG_DMA_STATIC_OFFSET_FIELD_SHIFT 24 extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD; #define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_MASK 0x000fffff #define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_WIDTH 20 #define RNR_REGS_CFG_PSRAM_CFG_DMA_BASE_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD; #define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_MASK 0x00700000 #define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_WIDTH 3 #define RNR_REGS_CFG_PSRAM_CFG_DMA_BUF_SIZE_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_PSRAM_CFG_RESERVED0_FIELD_MASK 0x00800000 #define RNR_REGS_CFG_PSRAM_CFG_RESERVED0_FIELD_WIDTH 1 #define RNR_REGS_CFG_PSRAM_CFG_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD; #define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_MASK 0xff000000 #define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_WIDTH 8 #define RNR_REGS_CFG_PSRAM_CFG_DMA_STATIC_OFFSET_FIELD_SHIFT 24 extern const ru_field_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD; #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_MASK 0x0000ffff #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_WIDTH 16 #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK0_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD; #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_MASK 0xffff0000 #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_WIDTH 16 #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_MASK1_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD; #define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_MASK 0x00000007 #define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_WIDTH 3 #define RNR_REGS_CFG_SCH_CFG_SCHEDULER_MODE_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_MASK 0xfffffff8 #define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_WIDTH 29 #define RNR_REGS_CFG_SCH_CFG_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_MASK 0x00000001 #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_EN_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_MASK 0x00000002 #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_0_USE_THREAD_FIELD_SHIFT 1 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_MASK 0x00000004 #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_EN_FIELD_SHIFT 2 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_MASK 0x00000008 #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_1_USE_THREAD_FIELD_SHIFT 3 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_MASK 0x00000010 #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_EN_FIELD_SHIFT 4 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_MASK 0x00000020 #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_2_USE_THREAD_FIELD_SHIFT 5 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_MASK 0x00000040 #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_EN_FIELD_SHIFT 6 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_MASK 0x00000080 #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_3_USE_THREAD_FIELD_SHIFT 7 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_MASK 0x00000100 #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_EN_FIELD_SHIFT 8 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_MASK 0x00000200 #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_4_USE_THREAD_FIELD_SHIFT 9 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_MASK 0x00000400 #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_EN_FIELD_SHIFT 10 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_MASK 0x00000800 #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_5_USE_THREAD_FIELD_SHIFT 11 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_MASK 0x00001000 #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_EN_FIELD_SHIFT 12 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_MASK 0x00002000 #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_6_USE_THREAD_FIELD_SHIFT 13 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_MASK 0x00004000 #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_EN_FIELD_SHIFT 14 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD; #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_MASK 0x00008000 #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_BKPT_7_USE_THREAD_FIELD_SHIFT 15 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD; #define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_MASK 0x00010000 #define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_CFG_STEP_MODE_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD; #define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_MASK 0x000e0000 #define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_REGS_CFG_BKPT_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD; #define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_MASK 0x00f00000 #define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_WIDTH 4 #define RNR_REGS_CFG_BKPT_CFG_NEW_FLAGS_VAL_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD; #define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_MASK 0xff000000 #define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_WIDTH 8 #define RNR_REGS_CFG_BKPT_CFG_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD; #define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_MASK 0x00000001 #define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_IMM_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD; #define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_MASK 0xfffffffe #define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_WIDTH 31 #define RNR_REGS_CFG_BKPT_IMM_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD; #define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_MASK 0x00001fff #define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_WIDTH 13 #define RNR_REGS_CFG_BKPT_STS_BKPT_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD; #define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_WIDTH 3 #define RNR_REGS_CFG_BKPT_STS_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD; #define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_MASK 0x00010000 #define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_WIDTH 1 #define RNR_REGS_CFG_BKPT_STS_ACTIVE_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD; #define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_MASK 0xfffe0000 #define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_WIDTH 15 #define RNR_REGS_CFG_BKPT_STS_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD; #define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_MASK 0x00001fff #define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_WIDTH 13 #define RNR_REGS_CFG_PC_STS_CURRENT_PC_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_PC_STS_RESERVED0_FIELD; #define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_WIDTH 3 #define RNR_REGS_CFG_PC_STS_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_REGS_CFG_PC_STS_PC_RET_FIELD; #define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_MASK 0x1fff0000 #define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_WIDTH 13 #define RNR_REGS_CFG_PC_STS_PC_RET_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_PC_STS_RESERVED1_FIELD; #define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_MASK 0xe0000000 #define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_WIDTH 3 #define RNR_REGS_CFG_PC_STS_RESERVED1_FIELD_SHIFT 29 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD; #define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_MASK 0x00001fff #define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_WIDTH 13 #define RNR_REGS_CFG_PROFILING_STS_TRACE_WRITE_PNT_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD; #define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_MASK 0x00002000 #define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_STS_IDLE_NO_ACTIVE_TASK_FIELD_SHIFT 13 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD; #define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_MASK 0x0003c000 #define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_WIDTH 4 #define RNR_REGS_CFG_PROFILING_STS_CURR_THREAD_NUM_FIELD_SHIFT 14 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD; #define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_MASK 0x00040000 #define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_STS_PROFILING_ACTIVE_FIELD_SHIFT 18 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD; #define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_MASK 0x00080000 #define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_STS_TRACE_FIFO_OVERRUN_FIELD_SHIFT 19 extern const ru_field_rec RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD; #define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_MASK 0xfff00000 #define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_WIDTH 12 #define RNR_REGS_CFG_PROFILING_STS_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_MASK 0x00001fff #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_WIDTH 13 #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_BASE_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_WIDTH 3 #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_MASK 0x1fff0000 #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_WIDTH 13 #define RNR_REGS_CFG_PROFILING_CFG_0_TRACE_MAX_ADDR_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_MASK 0xe0000000 #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_WIDTH 3 #define RNR_REGS_CFG_PROFILING_CFG_0_RESERVED1_FIELD_SHIFT 29 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_MASK 0x00000001 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_WRAPAROUND_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_MASK 0x00000002 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_MODE_FIELD_SHIFT 1 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_MASK 0x00000004 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_IDLE_IN_FIELD_SHIFT 2 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_MASK 0x00000008 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_DISABLE_WAKEUP_LOG_FIELD_SHIFT 3 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_MASK 0x000000f0 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_WIDTH 4 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_TASK_FIELD_SHIFT 4 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_MASK 0x00000100 #define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_IDLE_COUNTER_SOURCE_SEL_FIELD_SHIFT 8 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_MASK 0x3ffffe00 #define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_WIDTH 21 #define RNR_REGS_CFG_PROFILING_CFG_1_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_MASK 0x40000000 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_RESET_EVENT_FIFO_FIELD_SHIFT 30 extern const ru_field_rec RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD; #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_MASK 0x80000000 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_WIDTH 1 #define RNR_REGS_CFG_PROFILING_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_FIELD_SHIFT 31 extern const ru_field_rec RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD; #define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_MASK 0xffffffff #define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_WIDTH 32 #define RNR_REGS_CFG_PROFILING_COUNTER_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_STALL_CNT1_LD_STALL_CNT_FIELD; #define RNR_REGS_CFG_STALL_CNT1_LD_STALL_CNT_FIELD_MASK 0x0000ffff #define RNR_REGS_CFG_STALL_CNT1_LD_STALL_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_STALL_CNT1_LD_STALL_CNT_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_STALL_CNT1_ACC_STALL_CNT_FIELD; #define RNR_REGS_CFG_STALL_CNT1_ACC_STALL_CNT_FIELD_MASK 0xffff0000 #define RNR_REGS_CFG_STALL_CNT1_ACC_STALL_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_STALL_CNT1_ACC_STALL_CNT_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_STALL_CNT2_LDIO_STALL_CNT_FIELD; #define RNR_REGS_CFG_STALL_CNT2_LDIO_STALL_CNT_FIELD_MASK 0x0000ffff #define RNR_REGS_CFG_STALL_CNT2_LDIO_STALL_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_STALL_CNT2_LDIO_STALL_CNT_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_STALL_CNT2_STORE_STALL_CNT_FIELD; #define RNR_REGS_CFG_STALL_CNT2_STORE_STALL_CNT_FIELD_MASK 0xffff0000 #define RNR_REGS_CFG_STALL_CNT2_STORE_STALL_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_STALL_CNT2_STORE_STALL_CNT_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD; #define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_MASK 0xffffffff #define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_WIDTH 32 #define RNR_REGS_CFG_IDLE_CNT1_IDLE_CNT_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD; #define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_MASK 0x0000ffff #define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_JMP_CNT_UNTAKEN_JMP_CNT_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD; #define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_MASK 0xffff0000 #define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_WIDTH 16 #define RNR_REGS_CFG_JMP_CNT_TAKEN_JMP_CNT_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD; #define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_MASK 0xffffffff #define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_WIDTH 32 #define RNR_REGS_CFG_METAL_FIX_REG_METAL_FIX_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_DBG_SEL_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_DBG_SEL_FIELD_MASK 0x0000001f #define RNR_REGS_DBG_DESIGN_DBG_CTRL_DBG_SEL_FIELD_WIDTH 5 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_DBG_SEL_FIELD_SHIFT 0 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED0_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED0_FIELD_MASK 0x0000ffe0 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED0_FIELD_WIDTH 11 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_DIS_PER_SCHED_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_DIS_PER_SCHED_FIELD_MASK 0x00010000 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_DIS_PER_SCHED_FIELD_WIDTH 1 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_DIS_PER_SCHED_FIELD_SHIFT 16 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_DIS_PER_SCHED_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_DIS_PER_SCHED_FIELD_MASK 0x00020000 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_DIS_PER_SCHED_FIELD_WIDTH 1 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_DIS_PER_SCHED_FIELD_SHIFT 17 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_FW_SELF_IS_SYNC_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_FW_SELF_IS_SYNC_FIELD_MASK 0x00040000 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_FW_SELF_IS_SYNC_FIELD_WIDTH 1 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_MAIN_FW_SELF_IS_SYNC_FIELD_SHIFT 18 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_FW_SELF_IS_SYNC_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_FW_SELF_IS_SYNC_FIELD_MASK 0x00080000 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_FW_SELF_IS_SYNC_FIELD_WIDTH 1 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_PICO_FW_SELF_IS_SYNC_FIELD_SHIFT 19 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED1_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED1_FIELD_WIDTH 12 #define RNR_REGS_DBG_DESIGN_DBG_CTRL_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_REGS_DBG_DESIGN_DBG_DATA_DBG_DATA_FIELD; #define RNR_REGS_DBG_DESIGN_DBG_DATA_DBG_DATA_FIELD_MASK 0xffffffff #define RNR_REGS_DBG_DESIGN_DBG_DATA_DBG_DATA_FIELD_WIDTH 32 #define RNR_REGS_DBG_DESIGN_DBG_DATA_DBG_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_MASK_ID_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_MASK_ID_FIELD_MASK 0x000000ff #define RNR_QUAD_UBUS_SLV_RES_CNTRL_MASK_ID_FIELD_WIDTH 8 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_MASK_ID_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_RESERVED0_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_RESERVED0_FIELD_MASK 0x0000ff00 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_RESERVED0_FIELD_WIDTH 8 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_REPIN_ESWAP_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REPIN_ESWAP_FIELD_MASK 0x00010000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REPIN_ESWAP_FIELD_WIDTH 1 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REPIN_ESWAP_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_REQOUT_ESWAP_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REQOUT_ESWAP_FIELD_MASK 0x00020000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REQOUT_ESWAP_FIELD_WIDTH 1 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REQOUT_ESWAP_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_CLKEN_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_CLKEN_FIELD_MASK 0x00040000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_CLKEN_FIELD_WIDTH 1 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_CLKEN_FIELD_SHIFT 18 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_ERR_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_ERR_FIELD_MASK 0x00080000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_ERR_FIELD_WIDTH 1 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_ERR_FIELD_SHIFT 19 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_EN_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_EN_FIELD_MASK 0x00100000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_EN_FIELD_WIDTH 1 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_EN_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_FIELD; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_FIELD_MASK 0xffe00000 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_FIELD_WIDTH 11 #define RNR_QUAD_UBUS_SLV_RES_CNTRL_DEV_TIMEOUT_FIELD_SHIFT 21 extern const ru_field_rec RNR_QUAD_UBUS_SLV_VPB_BASE_BASE_FIELD; #define RNR_QUAD_UBUS_SLV_VPB_BASE_BASE_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_VPB_BASE_BASE_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_VPB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_VPB_MASK_MASK_FIELD; #define RNR_QUAD_UBUS_SLV_VPB_MASK_MASK_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_VPB_MASK_MASK_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_VPB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_APB_BASE_BASE_FIELD; #define RNR_QUAD_UBUS_SLV_APB_BASE_BASE_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_APB_BASE_BASE_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_APB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_APB_MASK_MASK_FIELD; #define RNR_QUAD_UBUS_SLV_APB_MASK_MASK_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_APB_MASK_MASK_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_APB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_DQM_BASE_BASE_FIELD; #define RNR_QUAD_UBUS_SLV_DQM_BASE_BASE_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_DQM_BASE_BASE_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_DQM_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_SLV_DQM_MASK_MASK_FIELD; #define RNR_QUAD_UBUS_SLV_DQM_MASK_MASK_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_SLV_DQM_MASK_MASK_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_SLV_DQM_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_CFG_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_MASK 0x00003fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_WIDTH 14 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_EXCEPTION_EN_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED0_FIELD_MASK 0x0000c000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED0_FIELD_WIDTH 2 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_MASK 0x00ff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_WIDTH 8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_TCP_FLAGS_FILT_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED1_FIELD_MASK 0x0f000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED1_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_MASK 0x70000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_PROFILE_US_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED2_FIELD_MASK 0x80000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED2_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_RESERVED2_FIELD_SHIFT 31 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_MASK 0x00007000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_MASK 0x00008000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_MASK 0x0fff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_MASK 0x70000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED1_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_MASK 0x80000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_FIELD_SHIFT 31 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_MASK 0x00007000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_MASK 0x00008000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_MASK 0x0fff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_MASK 0x70000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED1_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_MASK 0x80000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_FIELD_SHIFT 31 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_MASK 0x00007000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_MASK 0x00008000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_MASK 0x0fff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_MASK 0x70000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED1_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_MASK 0x80000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_FIELD_SHIFT 31 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_MASK 0x00007000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_MASK 0x00008000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_MASK 0x0fff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_MASK 0x70000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED1_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_MASK 0x80000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_FIELD_SHIFT 31 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_MASK 0x00000001 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_MASK 0x00000002 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_MASK 0x00000004 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_MASK 0x00000008 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_MASK 0x00000010 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_MASK 0x00000020 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_MASK 0x00000040 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_MASK 0x00000080 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_FIELD_SHIFT 7 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_MASK 0xffffff00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_WIDTH 24 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_MASK 0x00ffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_WIDTH 24 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_MASK 0x01000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_FIELD_SHIFT 24 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_MASK 0x02000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_FIELD_SHIFT 25 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_MASK 0xfc000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_WIDTH 6 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED0_FIELD_SHIFT 26 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_MASK 0x00000003 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_WIDTH 2 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_MASK 0x0000000c #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_WIDTH 2 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_MASK 0x00000030 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_WIDTH 2 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_MASK 0x000000c0 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_WIDTH 2 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_MASK 0x00000f00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_MASK 0x0000f000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_MASK 0x000f0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_MASK 0x00f00000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_MASK 0x0f000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_FIELD_SHIFT 24 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_MASK 0xf0000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_WIDTH 4 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_FIELD_SHIFT 28 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_MASK 0x00000001 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_MASK 0x00000002 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_MASK 0x00000004 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_MASK 0xfffffff8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_WIDTH 29 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_MASK 0x00000007 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_MASK 0x00000038 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_1_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_MASK 0x000001c0 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_0_PROFILE_2_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_MASK 0x00000e00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_0_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_MASK 0x00007000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_1_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_MASK 0x00038000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_WIDTH 3 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG_NEST_1_PROFILE_2_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_MASK 0xfffc0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_WIDTH 14 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_MASK 0xfffff000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_WIDTH 20 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_MASK 0xfffff000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_WIDTH 20 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_MASK 0x00000fff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_WIDTH 12 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_MASK 0xfffff000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_WIDTH 20 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_MASK 0x000000ff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_WIDTH 8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_MASK 0x0000ff00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_WIDTH 8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_MASK 0x00ff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_WIDTH 8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_MASK 0xff000000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_WIDTH 8 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_FIELD_SHIFT 24 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_DA_FILT_LSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_DA_FILT_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT_MASK_L_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_MASK 0xffffffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_WIDTH 32 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT_MASK_L_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_MASK 0x00000001 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_MASK 0x00000002 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_MASK 0x00000004 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_MASK 0x00000008 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_MASK 0x00000010 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_MASK 0x00000020 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_MASK 0x00000040 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_MASK 0x00000080 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_FIELD_SHIFT 7 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_MASK 0x00000100 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_MASK 0xfffffe00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_WIDTH 23 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_MASK 0x00000001 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_MASK 0x00000002 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_MASK 0x00000004 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_MASK 0x00000008 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_MASK 0x00000010 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_MASK 0x00000020 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_MASK 0x00000040 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_MASK 0x00000080 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_FIELD_SHIFT 7 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_MASK 0x00000100 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_MASK 0xfffffe00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_WIDTH 23 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_MASK 0x00000001 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_MASK 0x00000002 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_MASK 0x00000004 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_MASK 0x00000008 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_MASK 0x00000010 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_MASK 0x00000020 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_MASK 0x00000040 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_FIELD_SHIFT 6 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_MASK 0x00000080 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_FIELD_SHIFT 7 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_MASK 0x00000100 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_MASK 0xfffffe00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_WIDTH 23 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_MASK 0x0000ffff #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_MASK 0xffff0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_WIDTH 16 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_MASK 0x0000001f #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_WIDTH 5 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_0_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_MASK 0x000003e0 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_WIDTH 5 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_1_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_MASK 0x00007c00 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_WIDTH 5 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_SIZE_PROFILE_2_FIELD_SHIFT 10 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_MASK 0x00008000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_0_FIELD_SHIFT 15 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_MASK 0x00010000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_1_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_MASK 0x00020000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_WIDTH 1 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_PRE_DA_DPROFILE_2_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_MASK 0xfffc0000 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_WIDTH 14 #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_MASK 0x00000001 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_MASK 0x00000002 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_MASK 0x00000004 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_MASK 0x00000008 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_FIELD_MASK 0x000001f0 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_FIELD_WIDTH 5 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED1_FIELD_MASK 0xfffffe00 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED1_FIELD_WIDTH 23 #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_WIDTH 32 #define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_MASK 0x0000001f #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_WIDTH 5 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_COUNTER_LSB_SEL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_MASK 0x000000e0 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_MASK 0x00000100 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_0_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_MASK 0x00000200 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_MASK 0x00000400 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_2_FIELD_SHIFT 10 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_MASK 0x00000800 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_3_FIELD_SHIFT 11 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_MASK 0x00001000 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_4_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_MASK 0x00002000 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_ENABLE_TRACE_CORE_5_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_MASK 0xffffc000 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_WIDTH 18 #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_MASK 0x000f0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_WIDTH 4 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_THREAD_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_MASK 0x00001fff #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_MASK 0x0000e000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_MASK 0x1fff0000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_WIDTH 13 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_MASK 0xe0000000 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_RESERVED1_FIELD_SHIFT 29 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_MASK 0x000000ff #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_WIDTH 8 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_MASK 0x00000100 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_MASK 0x00000200 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_MASK 0x00000400 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_FIELD_SHIFT 10 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_MASK 0x00000800 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_FIELD_SHIFT 11 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_MASK 0x00001000 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_MASK 0x00002000 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_MASK 0xffffc000 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_WIDTH 18 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_MASK 0x00000001 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_MASK 0x00000002 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_MASK 0x00000004 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_MASK 0x00000008 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_WIDTH 1 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_MASK 0xfffffff0 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_WIDTH 28 #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_MASK 0x00000001 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_MASK 0x00000002 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_MASK 0x00000004 #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_MASK 0x000000f8 #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_MASK 0x00000f00 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_WIDTH 4 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_MASK 0x0000f000 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_WIDTH 4 #define RNR_QUAD_DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_MASK 0x000f0000 #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_WIDTH 4 #define RNR_QUAD_DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD; #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_MASK 0xfff00000 #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_WIDTH 12 #define RNR_QUAD_DEBUG_FIFO_CONFIG_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_MASK 0x00000001 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_MASK 0x00000002 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_MASK 0x0000000c #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 2 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK 0x000001f0 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_MASK 0x00000e00 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK 0x0001f000 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_MASK 0x000e0000 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x01f00000 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_MASK 0xfe000000 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_MASK 0x00000001 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_MASK 0x00000002 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_MASK 0x00000004 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK 0x00000008 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK 0x000001f0 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_MASK 0x00000e00 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK 0x0001f000 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_MASK 0x000e0000 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x01f00000 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_MASK 0xfe000000 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_MASK 0x00000001 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_FULL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_MASK 0x00000002 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_MASK 0x0000000c #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_WIDTH 2 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_MASK 0x000001f0 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_MASK 0x00000e00 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_MASK 0x0001f000 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_FIELD_SHIFT 12 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_MASK 0x000e0000 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_MASK 0x01f00000 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_WIDTH 5 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_FIELD_SHIFT 20 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_MASK 0xfe000000 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_WIDTH 7 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_RESERVED3_FIELD_SHIFT 25 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_MASK 0x00000001 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_FULL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_MASK 0x00000002 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_MASK 0x00000004 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_FIELD_SHIFT 2 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_MASK 0x00000008 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_WIDTH 1 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_MASK 0x00001ff0 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_WIDTH 9 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_FIELD_SHIFT 4 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_MASK 0x0000e000 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_WIDTH 3 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_MASK 0x01ff0000 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_WIDTH 9 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_FIELD_SHIFT 16 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_MASK 0xfe000000 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_WIDTH 7 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_MASK 0x000000ff #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_WIDTH 8 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_MASK 0x0001ff00 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_WIDTH 9 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_FIELD_SHIFT 8 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_MASK 0xfffe0000 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_WIDTH 15 #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_MASK 0xffffffff #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_WIDTH 32 #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_DATA_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD; #define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_WIDTH 32 #define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD; #define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_FIELD_SHIFT 0 extern const ru_field_rec RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD; #define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_MASK 0xffffffff #define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_WIDTH 32 #define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_MASK 0x00000001 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_EN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_MASK 0x000000fe #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_WIDTH 7 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_MASK 0x00000100 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_MASK 0x0000fe00 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_WIDTH 7 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_MASK 0x00010000 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_MASK 0x00020000 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_MASK 0xfffc0000 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_WIDTH 14 #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_RESERVED2_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD; #define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_MASK 0xffffffff #define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_WIDTH 32 #define DSPTCHR_REORDER_CFG_VQ_EN_EN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_MASK 0x0000003f #define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_WIDTH 6 #define DSPTCHR_REORDER_CFG_BB_CFG_SRC_ID_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_MASK 0x000000c0 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_WIDTH 2 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_MASK 0x00003f00 #define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_WIDTH 6 #define DSPTCHR_REORDER_CFG_BB_CFG_DST_ID_OVRIDE_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_MASK 0x0000c000 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_WIDTH 2 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_MASK 0x03ff0000 #define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_WIDTH 10 #define DSPTCHR_REORDER_CFG_BB_CFG_ROUTE_OVRIDE_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_MASK 0x0c000000 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_WIDTH 2 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED2_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_MASK 0x10000000 #define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_BB_CFG_OVRIDE_EN_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD; #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_MASK 0xe0000000 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_WIDTH 3 #define DSPTCHR_REORDER_CFG_BB_CFG_RESERVED3_FIELD_SHIFT 29 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD; #define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_MASK 0x00000fff #define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD; #define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_MASK 0x00fff000 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD; #define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_MASK 0xff000000 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD; #define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_MASK 0x00000fff #define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD; #define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_MASK 0x00fff000 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD; #define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_MASK 0xff000000 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD; #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_MASK 0x00000fff #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD; #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_MASK 0x00fff000 #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD; #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_MASK 0xff000000 #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_WIDTH 8 #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD; #define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_MASK 0x00000fff #define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_GLBL_CONGSTN_FRST_LVL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD; #define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_MASK 0x00fff000 #define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_WIDTH 12 #define DSPTCHR_CONGESTION_GLBL_CONGSTN_SCND_LVL_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD; #define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_MASK 0xff000000 #define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_WIDTH 8 #define DSPTCHR_CONGESTION_GLBL_CONGSTN_HYST_THRS_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_MASK 0x00000003 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_MASK 0x000000fc #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_WIDTH 6 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_MASK 0x00000300 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_MASK 0x0000fc00 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_WIDTH 6 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_MASK 0x00030000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_MASK 0x00fc0000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_WIDTH 6 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED2_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_MASK 0x03000000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_STCKY_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_MASK 0x0c000000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_STCKY_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_MASK 0x30000000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_STCKY_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_MASK 0xc0000000 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_WIDTH 2 #define DSPTCHR_CONGESTION_CONGSTN_STATUS_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD; #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_MASK 0xffffffff #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_WIDTH 32 #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD; #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_MASK 0xffffffff #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_WIDTH 32 #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD; #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_MASK 0xffffffff #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_WIDTH 32 #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD; #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_MASK 0xffffffff #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_WIDTH 32 #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_MASK 0x000003ff #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_WIDTH 10 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_MASK 0x000003ff #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_WIDTH 10 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_MASK 0x000ffc00 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_WIDTH 10 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_MASK 0xfff00000 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_WIDTH 12 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_MASK 0x000003ff #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_WIDTH 10 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_MASK 0x00000400 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_WIDTH 1 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_MASK 0xfffff800 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_WIDTH 21 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_FIELD_SHIFT 11 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD; #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_MASK 0x000000ff #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_WIDTH 8 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_BB_ID_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD; #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_MASK 0x0000ff00 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_WIDTH 8 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD; #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_MASK 0xffff0000 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_WIDTH 16 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD; #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_MASK 0x0000ffff #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_WIDTH 16 #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD; #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_MASK 0xffff0000 #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_WIDTH 16 #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_MASK 0x00000001 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_MASK 0x00000002 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q1_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_MASK 0x00000004 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q2_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_MASK 0x00000008 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q3_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_MASK 0x00000010 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q4_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_MASK 0x00000020 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q5_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_MASK 0x00000040 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q6_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_MASK 0x00000080 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q7_FIELD_SHIFT 7 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_MASK 0x00000100 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q8_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_MASK 0x00000200 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q9_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_MASK 0x00000400 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q10_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_MASK 0x00000800 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q11_FIELD_SHIFT 11 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_MASK 0x00001000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q12_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_MASK 0x00002000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q13_FIELD_SHIFT 13 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_MASK 0x00004000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q14_FIELD_SHIFT 14 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_MASK 0x00008000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q15_FIELD_SHIFT 15 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_MASK 0x00010000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q16_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_MASK 0x00020000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q17_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_MASK 0x00040000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q18_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_MASK 0x00080000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q19_FIELD_SHIFT 19 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_MASK 0x00100000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q20_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_MASK 0x00200000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q21_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_MASK 0x00400000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q22_FIELD_SHIFT 22 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_MASK 0x00800000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q23_FIELD_SHIFT 23 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_MASK 0x01000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q24_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_MASK 0x02000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q25_FIELD_SHIFT 25 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_MASK 0x04000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q26_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_MASK 0x08000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q27_FIELD_SHIFT 27 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_MASK 0x10000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q28_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_MASK 0x20000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q29_FIELD_SHIFT 29 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_MASK 0x40000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q30_FIELD_SHIFT 30 extern const ru_field_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_MASK 0x80000000 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_WIDTH 1 #define DSPTCHR_QUEUE_MAPPING_Q_DEST_Q31_FIELD_SHIFT 31 extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD; #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_POOL_LMT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD; #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD; #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_POOL_LMT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD; #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD; #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_WIDTH 10 #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD; #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD; #define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_MASK 0xffffffff #define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_WIDTH 32 #define DSPTCHR_MASK_MSK_TSK_255_0_MASK_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_MASK_MSK_Q_MASK_FIELD; #define DSPTCHR_MASK_MSK_Q_MASK_FIELD_MASK 0xffffffff #define DSPTCHR_MASK_MSK_Q_MASK_FIELD_WIDTH 32 #define DSPTCHR_MASK_MSK_Q_MASK_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_MASK_DLY_Q_MASK_FIELD; #define DSPTCHR_MASK_DLY_Q_MASK_FIELD_MASK 0xffffffff #define DSPTCHR_MASK_DLY_Q_MASK_FIELD_WIDTH 32 #define DSPTCHR_MASK_DLY_Q_MASK_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD; #define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_MASK 0xffffffff #define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_WIDTH 32 #define DSPTCHR_MASK_NON_DLY_Q_MASK_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD; #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_MASK 0x000000ff #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_WIDTH 8 #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD; #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_MASK 0xffffff00 #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_WIDTH 24 #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD; #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_MASK 0x000000ff #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_WIDTH 8 #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD; #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_MASK 0xffffff00 #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_WIDTH 24 #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD; #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_WIDTH 10 #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD; #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD; #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_MASK 0x000003ff #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_WIDTH 10 #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD; #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_MASK 0x00000001 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_MASK 0x00000002 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q1_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_MASK 0x00000004 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q2_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_MASK 0x00000008 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q3_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_MASK 0x00000010 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q4_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_MASK 0x00000020 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q5_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_MASK 0x00000040 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q6_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_MASK 0x00000080 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q7_FIELD_SHIFT 7 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_MASK 0x00000100 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q8_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_MASK 0x00000200 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q9_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_MASK 0x00000400 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q10_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_MASK 0x00000800 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q11_FIELD_SHIFT 11 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_MASK 0x00001000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q12_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_MASK 0x00002000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q13_FIELD_SHIFT 13 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_MASK 0x00004000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q14_FIELD_SHIFT 14 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_MASK 0x00008000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q15_FIELD_SHIFT 15 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_MASK 0x00010000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q16_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_MASK 0x00020000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q17_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_MASK 0x00040000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q18_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_MASK 0x00080000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q19_FIELD_SHIFT 19 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_MASK 0x00100000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q20_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_MASK 0x00200000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q21_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_MASK 0x00400000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q22_FIELD_SHIFT 22 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_MASK 0x00800000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q23_FIELD_SHIFT 23 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_MASK 0x01000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q24_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_MASK 0x02000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q25_FIELD_SHIFT 25 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_MASK 0x04000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q26_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_MASK 0x08000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q27_FIELD_SHIFT 27 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_MASK 0x10000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q28_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_MASK 0x20000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q29_FIELD_SHIFT 29 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_MASK 0x40000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q30_FIELD_SHIFT 30 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_MASK 0x80000000 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_WIDTH 1 #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_Q31_FIELD_SHIFT 31 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_MASK 0x000003ff #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_WIDTH 10 #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD; #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_MASK 0x000fffff #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_WIDTH 20 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_MASK 0x00100000 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_NGTV_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_MASK 0xffe00000 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_WIDTH 11 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_MASK 0x00000001 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_MASK 0x00000002 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q1_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_MASK 0x00000004 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q2_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_MASK 0x00000008 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q3_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_MASK 0x00000010 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q4_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_MASK 0x00000020 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q5_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_MASK 0x00000040 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q6_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_MASK 0x00000080 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q7_FIELD_SHIFT 7 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_MASK 0x00000100 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q8_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_MASK 0x00000200 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q9_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_MASK 0x00000400 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q10_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_MASK 0x00000800 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q11_FIELD_SHIFT 11 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_MASK 0x00001000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q12_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_MASK 0x00002000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q13_FIELD_SHIFT 13 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_MASK 0x00004000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q14_FIELD_SHIFT 14 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_MASK 0x00008000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q15_FIELD_SHIFT 15 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_MASK 0x00010000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q16_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_MASK 0x00020000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q17_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_MASK 0x00040000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q18_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_MASK 0x00080000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q19_FIELD_SHIFT 19 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_MASK 0x00100000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q20_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_MASK 0x00200000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q21_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_MASK 0x00400000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q22_FIELD_SHIFT 22 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_MASK 0x00800000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q23_FIELD_SHIFT 23 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_MASK 0x01000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q24_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_MASK 0x02000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q25_FIELD_SHIFT 25 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_MASK 0x04000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q26_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_MASK 0x08000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q27_FIELD_SHIFT 27 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_MASK 0x10000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q28_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_MASK 0x20000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q29_FIELD_SHIFT 29 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_MASK 0x40000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q30_FIELD_SHIFT 30 extern const ru_field_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_MASK 0x80000000 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_WIDTH 1 #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_Q31_FIELD_SHIFT 31 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD; #define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_MASK 0x00000001 #define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_WIDTH 1 #define DSPTCHR_LOAD_BALANCING_LB_CFG_LB_MODE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD; #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_MASK 0x000000fe #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_WIDTH 7 #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD; #define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_MASK 0x00001f00 #define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_WIDTH 5 #define DSPTCHR_LOAD_BALANCING_LB_CFG_SP_THRSHLD_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD; #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_MASK 0xffffe000 #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_WIDTH 19 #define DSPTCHR_LOAD_BALANCING_LB_CFG_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_RNR1_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR2_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_RNR3_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR4_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_RNR5_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR6_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_RNR7_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR8_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_RNR9_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR10_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_RNR11_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR12_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_RNR13_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_MASK 0x0000ffff #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR14_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_MASK 0xffff0000 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_WIDTH 16 #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_RNR15_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_MASK 0x00000007 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_MASK 0x00000038 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_MASK 0x000001c0 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_MASK 0x00000e00 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_MASK 0x00007000 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_MASK 0x00038000 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_FIELD_SHIFT 15 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_MASK 0x001c0000 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_MASK 0x00e00000 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_WIDTH 3 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_MASK 0xff000000 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_MASK 0x000000ff #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_MASK 0x0000ff00 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_MASK 0x00ff0000 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_MASK 0xff000000 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_MASK 0x000000ff #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_MASK 0x0000ff00 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_MASK 0x00ff0000 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_MASK 0xff000000 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_WIDTH 8 #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_MASK 0x00000001 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_MASK 0x00000002 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_MASK 0x00000004 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_MASK 0x00000008 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_MASK 0x00000010 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_MASK 0xffffffe0 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_WIDTH 27 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_MASK 0x00000001 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_MASK 0x00000002 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_MASK 0x00000004 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_MASK 0x00000008 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_FIELD_SHIFT 3 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_MASK 0x00000010 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_MASK 0x00000020 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_MASK 0x00000040 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_FIELD_SHIFT 6 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_MASK 0x00000080 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_FIELD_SHIFT 7 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_MASK 0x00000100 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_MASK 0x00000200 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_MASK 0x00000400 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_MASK 0x00000800 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_FIELD_SHIFT 11 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_MASK 0x00001000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_MASK 0x00002000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_FIELD_SHIFT 13 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_MASK 0x00004000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_FIELD_SHIFT 14 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_MASK 0x00008000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_FIELD_SHIFT 15 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_MASK 0x00010000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_MASK 0x00020000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_FIELD_SHIFT 17 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_MASK 0x00040000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_FIELD_SHIFT 18 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_MASK 0x00080000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_FIELD_SHIFT 19 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_MASK 0x00100000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_MASK 0x00200000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_FIELD_SHIFT 21 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_MASK 0x00400000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_FIELD_SHIFT 22 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_MASK 0x00800000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_FIELD_SHIFT 23 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_MASK 0x01000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_MASK 0x02000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_FIELD_SHIFT 25 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_MASK 0x04000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_FIELD_SHIFT 26 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_MASK 0x08000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_FIELD_SHIFT 27 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_MASK 0x10000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_MASK 0x20000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_FIELD_SHIFT 29 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_MASK 0x40000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_FIELD_SHIFT 30 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_MASK 0x80000000 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_WIDTH 1 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_FIELD_SHIFT 31 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_MASK 0xffffffff #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_WIDTH 32 #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_MASK 0x00000001 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_WIDTH 1 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_EN_BYP_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_WIDTH 7 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_MASK 0x0000ff00 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_WIDTH 8 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_MASK 0x00ff0000 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_WIDTH 8 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_MASK 0xff000000 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_WIDTH 8 #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_MASK 0x0000000f #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_MASK 0x000000f0 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_MASK 0x00000f00 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_MASK 0x0000f000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_MASK 0x000f0000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_MASK 0x00f00000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_MASK 0x0f000000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_MASK 0xf0000000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_MASK 0x0000000f #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_MASK 0x000000f0 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_FIELD_SHIFT 4 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_MASK 0x00000f00 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_MASK 0x0000f000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_MASK 0x000f0000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_MASK 0x00f00000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_MASK 0x0f000000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_FIELD_SHIFT 24 extern const ru_field_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_MASK 0xf0000000 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_FIELD_SHIFT 28 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD; #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_MASK 0x0000001f #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_WIDTH 5 #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_DBG_SEL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD; #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_MASK 0xffffffe0 #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_WIDTH 27 #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_0_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_1_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_2_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_3_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_4_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_5_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_6_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_7_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_8_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_9_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_10_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_11_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_12_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_13_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_14_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_15_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_16_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_17_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_18_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_19_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_20_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_21_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_22_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_DBG_VEC_23_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_MASK 0x00000003 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_WIDTH 2 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_MASK 0x000000fc #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_WIDTH 6 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_MASK 0x00000100 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_WIDTH 1 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_FIELD_SHIFT 8 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_MASK 0x00000200 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_WIDTH 1 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_FIELD_SHIFT 9 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_MASK 0x0000fc00 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_WIDTH 6 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_MASK 0x000f0000 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_WIDTH 4 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_FIELD_SHIFT 16 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_MASK 0xfff00000 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_WIDTH 12 #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_RESERVED2_FIELD_SHIFT 20 extern const ru_field_rec DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD; #define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_MASK 0xffffffff #define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_WIDTH 32 #define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_HEAD_HEAD_FIELD; #define DSPTCHR_QDES_HEAD_HEAD_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_HEAD_HEAD_FIELD_WIDTH 32 #define DSPTCHR_QDES_HEAD_HEAD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_BFOUT_BFOUT_FIELD; #define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_WIDTH 32 #define DSPTCHR_QDES_BFOUT_BFOUT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_BUFIN_BUFIN_FIELD; #define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_WIDTH 32 #define DSPTCHR_QDES_BUFIN_BUFIN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_TAIL_TAIL_FIELD; #define DSPTCHR_QDES_TAIL_TAIL_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_TAIL_TAIL_FIELD_WIDTH 32 #define DSPTCHR_QDES_TAIL_TAIL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD; #define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_MASK 0x00000001 #define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_WIDTH 1 #define DSPTCHR_QDES_FBDNULL_FBDNULL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD; #define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_MASK 0xfffffffe #define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_WIDTH 31 #define DSPTCHR_QDES_FBDNULL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_QDES_NULLBD_NULLBD_FIELD; #define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_WIDTH 32 #define DSPTCHR_QDES_NULLBD_NULLBD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD; #define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_WIDTH 32 #define DSPTCHR_QDES_BUFAVAIL_BUFAVAIL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_RESERVED_RESERVED0_FIELD; #define DSPTCHR_QDES_RESERVED_RESERVED0_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_RESERVED_RESERVED0_FIELD_WIDTH 32 #define DSPTCHR_QDES_RESERVED_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD; #define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_MASK 0x000003ff #define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_WIDTH 10 #define DSPTCHR_QDES_REG_Q_HEAD_HEAD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD; #define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_MASK 0xfffffc00 #define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_WIDTH 22 #define DSPTCHR_QDES_REG_Q_HEAD_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD; #define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_WIDTH 32 #define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD; #define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_WIDTH 32 #define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD; #define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_MASK 0xffffffff #define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_WIDTH 32 #define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD; #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_MASK 0x00000001 #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_WIDTH 1 #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD; #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_MASK 0x00000002 #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_WIDTH 1 #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_FIELD_SHIFT 1 extern const ru_field_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD; #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_MASK 0xfffffffc #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_WIDTH 30 #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_FLLDES_HEAD_HEAD_FIELD; #define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_HEAD_HEAD_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_BFOUT_COUNT_FIELD; #define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_BFOUT_COUNT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_BFIN_BFIN_FIELD; #define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_BFIN_BFIN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_TAIL_TAIL_FIELD; #define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_TAIL_TAIL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD; #define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_FLLDROP_DRPCNT_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_LTINT_MINBUF_FIELD; #define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_LTINT_MINBUF_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD; #define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_BUFAVAIL_BUFAVAIL_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD; #define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_MASK 0xffffffff #define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_WIDTH 32 #define DSPTCHR_FLLDES_FREEMIN_FREEMIN_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_BDRAM_DATA_RESERVED0_FIELD; #define DSPTCHR_BDRAM_DATA_RESERVED0_FIELD_MASK 0x00000003 #define DSPTCHR_BDRAM_DATA_RESERVED0_FIELD_WIDTH 2 #define DSPTCHR_BDRAM_DATA_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec DSPTCHR_BDRAM_DATA_DATA_FIELD; #define DSPTCHR_BDRAM_DATA_DATA_FIELD_MASK 0x00000ffc #define DSPTCHR_BDRAM_DATA_DATA_FIELD_WIDTH 10 #define DSPTCHR_BDRAM_DATA_DATA_FIELD_SHIFT 2 extern const ru_field_rec DSPTCHR_BDRAM_DATA_RESERVED1_FIELD; #define DSPTCHR_BDRAM_DATA_RESERVED1_FIELD_MASK 0xfffff000 #define DSPTCHR_BDRAM_DATA_RESERVED1_FIELD_WIDTH 20 #define DSPTCHR_BDRAM_DATA_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec DSPTCHR_PDRAM_DATA_DATA_FIELD; #define DSPTCHR_PDRAM_DATA_DATA_FIELD_MASK 0xffffffff #define DSPTCHR_PDRAM_DATA_DATA_FIELD_WIDTH 32 #define DSPTCHR_PDRAM_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_MASK 0x00000007 #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_WIDTH 3 #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_TYPE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_MASK 0xfffffff8 #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_WIDTH 29 #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_MASK 0x0000003f #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_DMASRC_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_MASK 0x00003f00 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SDMASRC_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_MASK 0x0000c000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_MASK 0x003f0000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_SBPMSRC_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_MASK 0x00c00000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED2_FIELD_SHIFT 22 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_MASK 0x3f000000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_FPMSRC_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_MASK 0xc0000000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_MASK 0x0000003f #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR0SRC_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_MASK 0x00003f00 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_PDRNR1SRC_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_MASK 0x0000c000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_MASK 0x003f0000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_STSRNRSRC_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_MASK 0x00c00000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED2_FIELD_SHIFT 22 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_MASK 0x3f000000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_MSGRNRSRC_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_MASK 0xc0000000 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_MASK 0x00000007 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_WIDTH 3 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BUFSIZE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_MASK 0x00000008 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_BYTERESUL_FIELD_SHIFT 3 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_MASK 0x00001ff0 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_WIDTH 9 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_DDRTXOFFSET_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_MASK 0x0000e000 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_WIDTH 3 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_MASK 0x007f0000 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_WIDTH 7 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_MASK 0x00800000 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED1_FIELD_SHIFT 23 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_MASK 0x7f000000 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_WIDTH 7 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_HNSIZE1_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_MASK 0x80000000 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_RESERVED2_FIELD_SHIFT 31 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_MASK 0x0000ffff #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_WIDTH 16 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_TCONTADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_MASK 0xffff0000 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_WIDTH 16 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_SKBADDR_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_MASK 0x0000ffff #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_WIDTH 16 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_PTRADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_MASK 0x000f0000 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_TASK_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_MASK 0xfff00000 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_WIDTH 12 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_MASK 0x0000003f #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCBASE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_MASK 0x00000fc0 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_DESCSIZE_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_MASK 0x0000f000 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_MASK 0x003f0000 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_MAXREQ_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_MASK 0x00c00000 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED1_FIELD_SHIFT 22 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_MASK 0x01000000 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_EPNURGNT_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_MASK 0xfe000000 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_WIDTH 7 #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_MASK 0x0000003f #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCBASE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_MASK 0x00000fc0 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_DESCSIZE_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_MASK 0x0000f000 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_MASK 0x003f0000 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_MAXREQ_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_MASK 0x00c00000 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED1_FIELD_SHIFT 22 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_MASK 0x01000000 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_EPNURGNT_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_MASK 0xfe000000 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_WIDTH 7 #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_MASK 0x00000001 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_FREENOCNTXT_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_MASK 0x00000002 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_SPECIALFREE_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_MASK 0x000000fc #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_MASK 0x00001f00 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_WIDTH 5 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_MAXGN_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_MASK 0xffffe000 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_WIDTH 19 #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_MASK 0xffffffff #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_WIDTH 32 #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_DDRTMBASE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_MASK 0x000000ff #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_WIDTH 8 #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_DDRTMBASE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_MASK 0x000003ff #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_WIDTH 10 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMSIZE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_MASK 0x000ffc00 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_WIDTH 10 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_DDRSIZE_FIELD_SHIFT 10 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_MASK 0x3ff00000 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_WIDTH 10 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_PSRAMBASE_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_MASK 0xc0000000 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_WIDTH 2 #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_MASK 0x00000001 #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_HIGHTRXQ_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_MASK 0x000003ff #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_WIDTH 10 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_ROUTE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_MASK 0x0000fc00 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_WIDTH 6 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_DEST_FIELD_SHIFT 10 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_MASK 0x00010000 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_EN_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_MASK 0xfffe0000 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_WIDTH 15 #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_MASK 0x00000001 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_MASK 0x00000002 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_Q1_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_MASK 0xfffffffc #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_WIDTH 30 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_MASK 0x0000000f #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_MASK 0x000000f0 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK1_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_MASK 0x00000f00 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK2_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_MASK 0x0000f000 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK3_FIELD_SHIFT 12 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_MASK 0x000f0000 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK4_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_MASK 0x00f00000 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK5_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_MASK 0x0f000000 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK6_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_MASK 0xf0000000 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_WIDTH 4 #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_TASK7_FIELD_SHIFT 28 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_MASK 0x00000001 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_CNTXTRST_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_MASK 0x00000002 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_PDFIFORST_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_MASK 0x00000004 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DMAPTRRST_FIELD_SHIFT 2 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_MASK 0x00000008 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SDMAPTRRST_FIELD_SHIFT 3 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_MASK 0x00000010 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_BPMFIFORST_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_MASK 0x00000020 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SBPMFIFORST_FIELD_SHIFT 5 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_MASK 0x00000040 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_OKFIFORST_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_MASK 0x00000080 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_DDRFIFORST_FIELD_SHIFT 7 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_MASK 0x00000100 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SRAMFIFORST_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_MASK 0x00000200 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_SKBPTRRST_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_MASK 0x00000400 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_STSFIFORST_FIELD_SHIFT 10 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_MASK 0x00000800 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REQFIFORST_FIELD_SHIFT 11 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_MASK 0x00001000 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_MSGFIFORST_FIELD_SHIFT 12 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_MASK 0x00002000 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_GNXTFIFORST_FIELD_SHIFT 13 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_MASK 0x00004000 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_FBNFIFORST_FIELD_SHIFT 14 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_MASK 0xffff8000 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_WIDTH 17 #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_RESERVED0_FIELD_SHIFT 15 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_MASK 0x0000001f #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_WIDTH 5 #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_DBGSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_MASK 0xffffffe0 #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_WIDTH 27 #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_MASK 0x000001ff #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_WIDTH 9 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_MASK 0x01ff0000 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_WIDTH 9 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK 0x000001ff #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK 0x01ff0000 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK 0x000000ff #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK 0x0000ff00 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK 0x00ff0000 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_MASK 0xff000000 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK 0xffff0000 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK 0x00000001 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK 0x000000ff #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_TCONTADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_PTRADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_MASK 0x000f0000 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_WIDTH 4 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_TASK_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_MASK 0xfff00000 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_WIDTH 12 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_TCONTADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_PTRADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_MASK 0x000f0000 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_WIDTH 4 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_TASK_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_MASK 0xfff00000 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_WIDTH 12 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_MASK 0x00000001 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_STPLENERR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_MASK 0x00000002 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CMP_WIDTH_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_MASK 0x00000004 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_CONSIDERFULL_FIELD_SHIFT 2 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_MASK 0x00000008 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_ADDCRC_FIELD_SHIFT 3 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_MASK 0xfffffff0 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_WIDTH 28 #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_MASK 0x0003ffff #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_WIDTH 18 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_WDATA_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_MASK 0x03fc0000 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_WIDTH 8 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_A_FIELD_SHIFT 18 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_MASK 0x04000000 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_CMD_FIELD_SHIFT 26 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_MASK 0xf8000000 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_WIDTH 5 #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_RESERVED0_FIELD_SHIFT 27 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_MASK 0x00000001 #define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_WAN_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_MAXWLEN_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_MAXWLEN_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_MAXWLEN_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_MAXWLEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLUSH_FLUSH_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_FLUSH_FIELD_MASK 0x0000ffff #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_FLUSH_FIELD_WIDTH 16 #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_FLUSH_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLUSH_RESERVED0_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_RESERVED0_FIELD_MASK 0x7fff0000 #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_RESERVED0_FIELD_WIDTH 15 #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_WAN_CONFIGURATIONS_FLUSH_SRST_N_FIELD; #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_SRST_N_FIELD_MASK 0x80000000 #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_SRST_N_FIELD_WIDTH 1 #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_SRST_N_FIELD_SHIFT 31 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_MASK 0x000001ff #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_MASK 0x01ff0000 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK 0x000001ff #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK 0x01ff0000 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK 0x000000ff #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8 #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK 0x0000ff00 #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8 #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK 0x0000ffff #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK 0xffff0000 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK 0x00000001 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK 0x000000ff #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8 #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_MASK 0x000001ff #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_DDRTHRESH_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_MASK 0x01ff0000 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_WIDTH 9 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_SRAMTHRESH_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_MASK 0x00000001 #define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_WIDTH 1 #define BBH_TX_LAN_CONFIGURATIONS_EEE_EN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_LAN_CONFIGURATIONS_EEE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_MASK 0x00000001 #define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_WIDTH 1 #define BBH_TX_LAN_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD; #define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_LAN_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_MASK 0x000001ff #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_MASK 0x01ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_MASK 0x000001ff #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_MASK 0x01ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_MASK 0x0000ff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_WKUPTHRESH1_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_MASK 0x0000ffff #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_WIDTH 16 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_MASK 0xffff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_WIDTH 16 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_PDLIMIT1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_MASK 0x00000001 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_WIDTH 1 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_PDLIMITEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_WIDTH 31 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_EMPTY_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_MASK 0x000001ff #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_DDRTHRESH_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_MASK 0x01ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_SRAMTHRESH_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_EN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_EN_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_WIDTH 24 #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_MASK 0x000007ff #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_WIDTH 11 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_MASK 0x0000f800 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_WIDTH 5 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_MASK 0x07ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_WIDTH 11 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_MASK 0xf8000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_WIDTH 5 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_RESERVED1_FIELD_SHIFT 27 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_MASK 0x000007ff #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_WIDTH 11 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_MASK 0x0000f800 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_WIDTH 5 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_MASK 0x07ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_WIDTH 11 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_MASK 0xf8000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_WIDTH 5 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_RESERVED1_FIELD_SHIFT 27 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_MASK 0x0000ff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_MASK 0x00ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_FIFOBASE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_MASK 0xff000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_MASK 0x000000ff #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_MASK 0x0000ff00 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_MASK 0x00ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_FIFOSIZE1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_MASK 0xff000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_WIDTH 8 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_RESERVED1_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_MASK 0x0000000f #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_WIDTH 4 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_MASK 0x0000fff0 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_WIDTH 12 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_MASK 0x000f0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_WIDTH 4 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_W1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_MASK 0xfff00000 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_WIDTH 12 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_MASK 0x000001ff #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH0_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_MASK 0x0000fe00 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_MASK 0x01ff0000 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_WIDTH 9 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_THRESH1_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_MASK 0xfe000000 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_WIDTH 7 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD; #define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_SRAMPD_SRAMPD_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD; #define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_DDRPD_DDRPD_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD; #define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_PDDROP_PDDROP_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_PDDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD; #define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_STSCNT_STSCNT_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD; #define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_STSDROP_STSDROP_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_STSDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD; #define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_MSGCNT_MSGCNT_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD; #define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_MSGDROP_MSGDROP_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_MSGDROP_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD; #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD; #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD; #define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_LENERR_LENERR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_LENERR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD; #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_MASK 0x0000ffff #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_WIDTH 16 #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD; #define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD; #define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_DDRPKT_DDRPKT_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD; #define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD; #define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_MASK 0x00000001 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_MASK 0x00000002 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDVSEL_FIELD_SHIFT 1 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_MASK 0x00000004 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_FIELD_SHIFT 2 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_MASK 0x00000008 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_FIELD_SHIFT 3 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_MASK 0x00000010 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_FIELD_SHIFT 4 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_MASK 0x00000020 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_FIELD_SHIFT 5 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_MASK 0x00000040 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNSEL_FIELD_SHIFT 6 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_MASK 0x00000080 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_FIELD_SHIFT 7 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_MASK 0x00000100 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_FIELD_SHIFT 8 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_MASK 0x00000200 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_FIELD_SHIFT 9 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_MASK 0x00000400 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_FIELD_SHIFT 10 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_MASK 0x00000800 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_FIELD_SHIFT 11 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_MASK 0x00001000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_FIELD_SHIFT 12 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_MASK 0x00002000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_FIELD_SHIFT 13 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_MASK 0x00004000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_FIELD_SHIFT 14 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_MASK 0x00008000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMSEL_FIELD_SHIFT 15 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_MASK 0x00010000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_FIELD_SHIFT 16 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_MASK 0x00020000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_FIELD_SHIFT 17 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_MASK 0x00040000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_FIELD_SHIFT 18 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_MASK 0x00080000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSSEL_FIELD_SHIFT 19 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_MASK 0x00100000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSVSEL_FIELD_SHIFT 20 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_MASK 0x00200000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_FIELD_SHIFT 21 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_MASK 0x00400000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_FIELD_SHIFT 22 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_MASK 0x00800000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_FIELD_SHIFT 23 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_MASK 0x01000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_FIELD_SHIFT 24 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_MASK 0x02000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGSEL_FIELD_SHIFT 25 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_MASK 0x04000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_FIELD_SHIFT 26 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_MASK 0x08000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_FIELD_SHIFT 27 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_MASK 0x10000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_DATASEL_FIELD_SHIFT 28 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_MASK 0x20000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_FIELD_SHIFT 29 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_MASK 0x40000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_FIELD_SHIFT 30 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_MASK 0x80000000 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_WIDTH 1 #define BBH_TX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_FIELD_SHIFT 31 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_MASK 0x000007ff #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_WIDTH 11 #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RDADDR_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_MASK 0xfffff800 #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_WIDTH 21 #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD; #define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_SWRDDATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD; #define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD; #define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_FIELD_SHIFT 0 extern const ru_field_rec BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD; #define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_MASK 0xffffffff #define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_WIDTH 32 #define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_MASK 0x0000003f #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SDMABBID_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_MASK 0x00003f00 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_DISPBBID_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_MASK 0x0000c000 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_MASK 0x003f0000 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_SBPMBBID_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_MASK 0xffc00000 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_WIDTH 10 #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_RESERVED2_FIELD_SHIFT 22 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_MASK 0x0000001f #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_WIDTH 5 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_NORMALVIQ_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_MASK 0x000000e0 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_MASK 0x00001f00 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_WIDTH 5 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_EXCLVIQ_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_MASK 0xffffe000 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_WIDTH 19 #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_PATTERNDATALSB_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_PATTERNDATAMSB_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_PATTERNMASKLSB_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_PATTERNMASKMSB_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PLOAMEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_MASK 0x00000002 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PRI3EN_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_MASK 0x00000004 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PAUSEEN_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_MASK 0x00000008 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PFCEN_FIELD_SHIFT 3 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_MASK 0x00000010 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_CTRLEN_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_MASK 0x00000020 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_MULTEN_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_MASK 0x00000f00 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_WIDTH 4 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTENOFFSET_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_MASK 0x0000f000 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_WIDTH 4 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_MASK 0x00010000 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_PATTERNEN_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_MASK 0x000e0000 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_WIDTH 3 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_MASK 0x00100000 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_EXCEN_FIELD_SHIFT 20 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_MASK 0xffe00000 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_WIDTH 11 #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_RESERVED3_FIELD_SHIFT 21 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_MASK 0x0000003f #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DATABASE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_MASK 0x00003f00 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_DESCBASE_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_MASK 0xffffc000 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_WIDTH 18 #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_MASK 0x0000007f #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_WIDTH 7 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_NUMOFCD_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_MASK 0x00000080 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_MASK 0x00007f00 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_WIDTH 7 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_EXCLTH_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_MASK 0x00008000 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED1_FIELD_SHIFT 15 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_MASK 0x00010000 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_COHERENCYEN_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_MASK 0xfffe0000 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_WIDTH 15 #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_RESERVED2_FIELD_SHIFT 17 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_MASK 0x000000ff #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT0_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_MASK 0x0000ff00 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT1_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_MASK 0x00ff0000 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT2_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_MASK 0xff000000 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_MINPKT3_FIELD_SHIFT 24 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_MASK 0x00003fff #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_WIDTH 14 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT0_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_MASK 0x0000c000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_MASK 0x3fff0000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_WIDTH 14 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_MAXPKT1_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_MASK 0xc0000000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_MASK 0x00003fff #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_WIDTH 14 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT2_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_MASK 0x0000c000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_MASK 0x3fff0000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_WIDTH 14 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_MAXPKT3_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_MASK 0xc0000000 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_MASK 0x0000007f #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_WIDTH 7 #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_SOPOFFSET_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_MASK 0xffffff80 #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_WIDTH 25 #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_MASK 0x00ffffff #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_WIDTH 24 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_TIMER_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_MASK 0x01000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_DISPDROPDIS_FIELD_SHIFT 24 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_MASK 0x02000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SDMADROPDIS_FIELD_SHIFT 25 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_MASK 0x04000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_SBPMDROPDIS_FIELD_SHIFT 26 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_MASK 0x08000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED0_FIELD_SHIFT 27 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_MASK 0x10000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_FCFORCE_FIELD_SHIFT 28 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_MASK 0xe0000000 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_WIDTH 3 #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_RESERVED1_FIELD_SHIFT 29 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_CRCOMITDIS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_MASK 0xfffffffe #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_WIDTH 31 #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_PKTEN_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_MASK 0x00000002 #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_SBPMEN_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_MASK 0xfffffffc #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_WIDTH 30 #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_MASK 0x00000002 #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_BYTES4_7ENABLE_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_MASK 0xfffffffc #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_WIDTH 30 #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_MASK 0x000000ff #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_FLOWTH_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_WIDTH 24 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_MASK 0x00000003 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL0_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_MASK 0x0000000c #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL0_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_MASK 0x00000030 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MINPKTSEL1_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_MASK 0x000000c0 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_MAXPKTSEL1_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_WIDTH 24 #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_MINPKTSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_MINPKTSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_MAXPKTSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_MASK 0xffffffff #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_WIDTH 32 #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_MAXPKTSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_MACMODE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_MASK 0x00000002 #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_GPONMODE_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_MASK 0xfffffffc #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_WIDTH 30 #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_MASK 0x0000000f #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_WIDTH 4 #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_MAXREQ_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_MASK 0xfffffff0 #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_WIDTH 28 #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INBUFRST_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_MASK 0x00000002 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_BURSTBUFRST_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_MASK 0x00000004 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_INGRESSCNTXT_FIELD_SHIFT 2 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_MASK 0x00000008 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CMDFIFORST_FIELD_SHIFT 3 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_MASK 0x00000010 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SBPMFIFORST_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_MASK 0x00000020 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_COHERENCYFIFORST_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_MASK 0x00000040 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_CNTXTRST_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_MASK 0x00000080 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_SDMARST_FIELD_SHIFT 7 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_MASK 0xffffff00 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_WIDTH 24 #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_MASK 0x0000000f #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_WIDTH 4 #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RXDBGSEL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_MASK 0xfffffff0 #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_WIDTH 28 #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_MASK 0x0000003f #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_ID_2OVERWR_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_MASK 0x000000c0 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_MASK 0x0003ff00 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_WIDTH 10 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_RA_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_MASK 0x00fc0000 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_WIDTH 6 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_MASK 0x01000000 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_OVERWR_EN_FIELD_SHIFT 24 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_MASK 0xfe000000 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_WIDTH 7 #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_MASK 0x000000ff #define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_NONETH_FLOWID_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_MASK 0x00000100 #define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_NONETH_ENABLE_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_MASK 0xfffffe00 #define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_WIDTH 23 #define BBH_RX_GENERAL_CONFIGURATION_NONETH_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD; #define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_INPKT_INPKT_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_THIRDFLOW_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_SOPASOP_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_TOOSHORT_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_TOOLONG_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_CRCERROR_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_ENCRYPTERROR_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_DISPCONG_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_NOSBPMSBN_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_NOSDMACD_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD; #define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_INPLOAM_INPLOAM_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_MASK 0xffffffff #define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_WIDTH 32 #define BBH_RX_PM_COUNTERS_EPONTYPERROR_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD; #define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_MASK 0x0000ffff #define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_WIDTH 16 #define BBH_RX_PM_COUNTERS_RUNTERROR_PMVALUE_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD; #define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_MASK 0xffff0000 #define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_WIDTH 16 #define BBH_RX_PM_COUNTERS_RUNTERROR_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD; #define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_MASK 0x00000001 #define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX0LSB_INREASS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_MASK 0x000000fe #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_WIDTH 7 #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD; #define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_MASK 0x0000ff00 #define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_WIDTH 8 #define BBH_RX_DEBUG_CNTXTX0LSB_FLOWID_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD; #define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_MASK 0x3fff0000 #define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_WIDTH 14 #define BBH_RX_DEBUG_CNTXTX0LSB_CUROFFSET_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_MASK 0xc0000000 #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX0LSB_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD; #define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_MASK 0x00001fff #define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_WIDTH 13 #define BBH_RX_DEBUG_CNTXTX0MSB_CURBN_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_MASK 0x0000e000 #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD; #define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_MASK 0x7fff0000 #define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_WIDTH 15 #define BBH_RX_DEBUG_CNTXTX0MSB_FIRSTBN_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_MASK 0x80000000 #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX0MSB_RESERVED1_FIELD_SHIFT 31 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD; #define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_MASK 0x00000001 #define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX1LSB_INREASS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_MASK 0x000000fe #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_WIDTH 7 #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD; #define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_MASK 0x0000ff00 #define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_WIDTH 8 #define BBH_RX_DEBUG_CNTXTX1LSB_FLOWID_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD; #define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_MASK 0x3fff0000 #define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_WIDTH 14 #define BBH_RX_DEBUG_CNTXTX1LSB_CUROFFSET_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_MASK 0xc0000000 #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX1LSB_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD; #define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_MASK 0x00001fff #define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_WIDTH 13 #define BBH_RX_DEBUG_CNTXTX1MSB_CURBN_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_MASK 0x0000e000 #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD; #define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_MASK 0x7fff0000 #define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_WIDTH 15 #define BBH_RX_DEBUG_CNTXTX1MSB_FIRSTBN_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_MASK 0x80000000 #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX1MSB_RESERVED1_FIELD_SHIFT 31 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_MASK 0x00000001 #define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX0INGRESS_INREASS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_MASK 0x0000000e #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_MASK 0x00000010 #define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX0INGRESS_SOP_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_MASK 0x00000020 #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED1_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_MASK 0x000000c0 #define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX0INGRESS_PRIORITY_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_MASK 0x0000ff00 #define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_WIDTH 8 #define BBH_RX_DEBUG_CNTXTX0INGRESS_FLOWID_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_MASK 0x3fff0000 #define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_WIDTH 14 #define BBH_RX_DEBUG_CNTXTX0INGRESS_CUROFFSET_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD; #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_MASK 0xc0000000 #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX0INGRESS_RESERVED2_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_MASK 0x00000001 #define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX1INGRESS_INREASS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_MASK 0x0000000e #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_MASK 0x00000010 #define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX1INGRESS_SOP_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_MASK 0x00000020 #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_WIDTH 1 #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED1_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_MASK 0x000000c0 #define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX1INGRESS_PRIORITY_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_MASK 0x0000ff00 #define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_WIDTH 8 #define BBH_RX_DEBUG_CNTXTX1INGRESS_FLOWID_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_MASK 0x3fff0000 #define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_WIDTH 14 #define BBH_RX_DEBUG_CNTXTX1INGRESS_CUROFFSET_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD; #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_MASK 0xc0000000 #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_WIDTH 2 #define BBH_RX_DEBUG_CNTXTX1INGRESS_RESERVED2_FIELD_SHIFT 30 extern const ru_field_rec BBH_RX_DEBUG_IBUW_UW_FIELD; #define BBH_RX_DEBUG_IBUW_UW_FIELD_MASK 0x00000007 #define BBH_RX_DEBUG_IBUW_UW_FIELD_WIDTH 3 #define BBH_RX_DEBUG_IBUW_UW_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_IBUW_RESERVED0_FIELD; #define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_MASK 0xfffffff8 #define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_WIDTH 29 #define BBH_RX_DEBUG_IBUW_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec BBH_RX_DEBUG_BBUW_UW_FIELD; #define BBH_RX_DEBUG_BBUW_UW_FIELD_MASK 0x0000000f #define BBH_RX_DEBUG_BBUW_UW_FIELD_WIDTH 4 #define BBH_RX_DEBUG_BBUW_UW_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_BBUW_RESERVED0_FIELD; #define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_MASK 0xfffffff0 #define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_WIDTH 28 #define BBH_RX_DEBUG_BBUW_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BBH_RX_DEBUG_CFUW_UW_FIELD; #define BBH_RX_DEBUG_CFUW_UW_FIELD_MASK 0x0000003f #define BBH_RX_DEBUG_CFUW_UW_FIELD_WIDTH 6 #define BBH_RX_DEBUG_CFUW_UW_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CFUW_RESERVED0_FIELD; #define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_MASK 0xffffffc0 #define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_WIDTH 26 #define BBH_RX_DEBUG_CFUW_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_SDMA_FIELD; #define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_MASK 0x0000001f #define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_WIDTH 5 #define BBH_RX_DEBUG_ACKCNT_SDMA_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD; #define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_MASK 0x000000e0 #define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_ACKCNT_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD; #define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_MASK 0x00001f00 #define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_WIDTH 5 #define BBH_RX_DEBUG_ACKCNT_CONNECT_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD; #define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_MASK 0xffffe000 #define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_WIDTH 19 #define BBH_RX_DEBUG_ACKCNT_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_MASK 0x0000001f #define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_WIDTH 5 #define BBH_RX_DEBUG_COHERENCYCNT_NORMAL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_MASK 0x000000e0 #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_MASK 0x00001f00 #define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_WIDTH 5 #define BBH_RX_DEBUG_COHERENCYCNT_EXCLUSIVE_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_MASK 0xffffe000 #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_WIDTH 19 #define BBH_RX_DEBUG_COHERENCYCNT_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD; #define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_MASK 0x001fffff #define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_WIDTH 21 #define BBH_RX_DEBUG_DBGVEC_DBGVEC_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD; #define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_MASK 0xffe00000 #define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_WIDTH 11 #define BBH_RX_DEBUG_DBGVEC_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec BBH_RX_DEBUG_UFUW_UW_FIELD; #define BBH_RX_DEBUG_UFUW_UW_FIELD_MASK 0x00000007 #define BBH_RX_DEBUG_UFUW_UW_FIELD_WIDTH 3 #define BBH_RX_DEBUG_UFUW_UW_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_UFUW_RESERVED0_FIELD; #define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_MASK 0xfffffff8 #define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_WIDTH 29 #define BBH_RX_DEBUG_UFUW_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD; #define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_MASK 0x0000001f #define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_WIDTH 5 #define BBH_RX_DEBUG_CREDITCNT_NORMAL_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD; #define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_MASK 0x000000e0 #define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CREDITCNT_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD; #define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_MASK 0x00001f00 #define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_WIDTH 5 #define BBH_RX_DEBUG_CREDITCNT_EXCLUSIVE_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD; #define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_MASK 0xffffe000 #define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_WIDTH 19 #define BBH_RX_DEBUG_CREDITCNT_RESERVED1_FIELD_SHIFT 13 extern const ru_field_rec BBH_RX_DEBUG_SDMACNT_UCD_FIELD; #define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_MASK 0x0000007f #define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_WIDTH 7 #define BBH_RX_DEBUG_SDMACNT_UCD_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD; #define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_MASK 0xffffff80 #define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_WIDTH 25 #define BBH_RX_DEBUG_SDMACNT_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec BBH_RX_DEBUG_CMFUW_UW_FIELD; #define BBH_RX_DEBUG_CMFUW_UW_FIELD_MASK 0x00000007 #define BBH_RX_DEBUG_CMFUW_UW_FIELD_WIDTH 3 #define BBH_RX_DEBUG_CMFUW_UW_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD; #define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_MASK 0xfffffff8 #define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_WIDTH 29 #define BBH_RX_DEBUG_CMFUW_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD; #define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_MASK 0x00003fff #define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_WIDTH 14 #define BBH_RX_DEBUG_SBNFIFO_BNENTRY_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD; #define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_MASK 0x0000c000 #define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_DEBUG_SBNFIFO_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_VALID_FIELD; #define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_MASK 0x00010000 #define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_WIDTH 1 #define BBH_RX_DEBUG_SBNFIFO_VALID_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD; #define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_MASK 0xfffe0000 #define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_WIDTH 15 #define BBH_RX_DEBUG_SBNFIFO_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD; #define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_MASK 0xffffffff #define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_WIDTH 32 #define BBH_RX_DEBUG_CMDFIFO_CMDENTRY_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD; #define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_MASK 0x00003fff #define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_WIDTH 14 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_BNENTRY_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD; #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_MASK 0x0000c000 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_WIDTH 2 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD; #define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_MASK 0x00010000 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_WIDTH 1 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_VALID_FIELD_SHIFT 16 extern const ru_field_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD; #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_MASK 0xfffe0000 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_WIDTH 15 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_MASK 0x0000007f #define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_WIDTH 7 #define BBH_RX_DEBUG_COHERENCYCNT2_CDSENT_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_MASK 0x00000080 #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_WIDTH 1 #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_MASK 0x00007f00 #define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_WIDTH 7 #define BBH_RX_DEBUG_COHERENCYCNT2_ACKRECEIVED_FIELD_SHIFT 8 extern const ru_field_rec BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD; #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_MASK 0xffff8000 #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_WIDTH 17 #define BBH_RX_DEBUG_COHERENCYCNT2_RESERVED1_FIELD_SHIFT 15 extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD; #define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_MASK 0x00000001 #define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_DROPSTATUS_DISPSTATUS_FIELD_SHIFT 0 extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD; #define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_MASK 0x00000002 #define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_WIDTH 1 #define BBH_RX_DEBUG_DROPSTATUS_SDMASTATUS_FIELD_SHIFT 1 extern const ru_field_rec BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD; #define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_MASK 0xfffffffc #define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_WIDTH 30 #define BBH_RX_DEBUG_DROPSTATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec UBUS_MSTR_EN_EN_FIELD; #define UBUS_MSTR_EN_EN_FIELD_MASK 0x00000001 #define UBUS_MSTR_EN_EN_FIELD_WIDTH 1 #define UBUS_MSTR_EN_EN_FIELD_SHIFT 0 extern const ru_field_rec UBUS_MSTR_EN_RESERVED0_FIELD; #define UBUS_MSTR_EN_RESERVED0_FIELD_MASK 0xfffffffe #define UBUS_MSTR_EN_RESERVED0_FIELD_WIDTH 31 #define UBUS_MSTR_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_PKT_ID_FIELD; #define UBUS_MSTR_REQ_CNTRL_PKT_ID_FIELD_MASK 0x000000ff #define UBUS_MSTR_REQ_CNTRL_PKT_ID_FIELD_WIDTH 8 #define UBUS_MSTR_REQ_CNTRL_PKT_ID_FIELD_SHIFT 0 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_PKT_TAG_FIELD; #define UBUS_MSTR_REQ_CNTRL_PKT_TAG_FIELD_MASK 0x00000100 #define UBUS_MSTR_REQ_CNTRL_PKT_TAG_FIELD_WIDTH 1 #define UBUS_MSTR_REQ_CNTRL_PKT_TAG_FIELD_SHIFT 8 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_RESERVED0_FIELD; #define UBUS_MSTR_REQ_CNTRL_RESERVED0_FIELD_MASK 0x0000fe00 #define UBUS_MSTR_REQ_CNTRL_RESERVED0_FIELD_WIDTH 7 #define UBUS_MSTR_REQ_CNTRL_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_ENDIAN_MODE_FIELD; #define UBUS_MSTR_REQ_CNTRL_ENDIAN_MODE_FIELD_MASK 0x00030000 #define UBUS_MSTR_REQ_CNTRL_ENDIAN_MODE_FIELD_WIDTH 2 #define UBUS_MSTR_REQ_CNTRL_ENDIAN_MODE_FIELD_SHIFT 16 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_REPIN_ESWAP_FIELD; #define UBUS_MSTR_REQ_CNTRL_REPIN_ESWAP_FIELD_MASK 0x00040000 #define UBUS_MSTR_REQ_CNTRL_REPIN_ESWAP_FIELD_WIDTH 1 #define UBUS_MSTR_REQ_CNTRL_REPIN_ESWAP_FIELD_SHIFT 18 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_REQOUT_ESWAP_FIELD; #define UBUS_MSTR_REQ_CNTRL_REQOUT_ESWAP_FIELD_MASK 0x00080000 #define UBUS_MSTR_REQ_CNTRL_REQOUT_ESWAP_FIELD_WIDTH 1 #define UBUS_MSTR_REQ_CNTRL_REQOUT_ESWAP_FIELD_SHIFT 19 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_DEV_ERR_FIELD; #define UBUS_MSTR_REQ_CNTRL_DEV_ERR_FIELD_MASK 0x00100000 #define UBUS_MSTR_REQ_CNTRL_DEV_ERR_FIELD_WIDTH 1 #define UBUS_MSTR_REQ_CNTRL_DEV_ERR_FIELD_SHIFT 20 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_RESERVED1_FIELD; #define UBUS_MSTR_REQ_CNTRL_RESERVED1_FIELD_MASK 0x00e00000 #define UBUS_MSTR_REQ_CNTRL_RESERVED1_FIELD_WIDTH 3 #define UBUS_MSTR_REQ_CNTRL_RESERVED1_FIELD_SHIFT 21 extern const ru_field_rec UBUS_MSTR_REQ_CNTRL_MAX_PKT_LEN_FIELD; #define UBUS_MSTR_REQ_CNTRL_MAX_PKT_LEN_FIELD_MASK 0xff000000 #define UBUS_MSTR_REQ_CNTRL_MAX_PKT_LEN_FIELD_WIDTH 8 #define UBUS_MSTR_REQ_CNTRL_MAX_PKT_LEN_FIELD_SHIFT 24 extern const ru_field_rec UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD; #define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_MASK 0x000003ff #define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_WIDTH 10 #define UBUS_MSTR_HYST_CTRL_CMD_SPACE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD; #define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_MASK 0x0000fc00 #define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_WIDTH 6 #define UBUS_MSTR_HYST_CTRL_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD; #define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_MASK 0x03ff0000 #define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_WIDTH 10 #define UBUS_MSTR_HYST_CTRL_DATA_SPACE_FIELD_SHIFT 16 extern const ru_field_rec UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD; #define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_MASK 0xfc000000 #define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_WIDTH 6 #define UBUS_MSTR_HYST_CTRL_RESERVED1_FIELD_SHIFT 26 extern const ru_field_rec UBUS_MSTR_HP_HP_EN_FIELD; #define UBUS_MSTR_HP_HP_EN_FIELD_MASK 0x00000001 #define UBUS_MSTR_HP_HP_EN_FIELD_WIDTH 1 #define UBUS_MSTR_HP_HP_EN_FIELD_SHIFT 0 extern const ru_field_rec UBUS_MSTR_HP_HP_SEL_FIELD; #define UBUS_MSTR_HP_HP_SEL_FIELD_MASK 0x00000002 #define UBUS_MSTR_HP_HP_SEL_FIELD_WIDTH 1 #define UBUS_MSTR_HP_HP_SEL_FIELD_SHIFT 1 extern const ru_field_rec UBUS_MSTR_HP_HP_COMB_FIELD; #define UBUS_MSTR_HP_HP_COMB_FIELD_MASK 0x00000004 #define UBUS_MSTR_HP_HP_COMB_FIELD_WIDTH 1 #define UBUS_MSTR_HP_HP_COMB_FIELD_SHIFT 2 extern const ru_field_rec UBUS_MSTR_HP_RESERVED0_FIELD; #define UBUS_MSTR_HP_RESERVED0_FIELD_MASK 0x000000f8 #define UBUS_MSTR_HP_RESERVED0_FIELD_WIDTH 5 #define UBUS_MSTR_HP_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec UBUS_MSTR_HP_HP_CNT_HIGH_FIELD; #define UBUS_MSTR_HP_HP_CNT_HIGH_FIELD_MASK 0x00000f00 #define UBUS_MSTR_HP_HP_CNT_HIGH_FIELD_WIDTH 4 #define UBUS_MSTR_HP_HP_CNT_HIGH_FIELD_SHIFT 8 extern const ru_field_rec UBUS_MSTR_HP_RESERVED1_FIELD; #define UBUS_MSTR_HP_RESERVED1_FIELD_MASK 0x0000f000 #define UBUS_MSTR_HP_RESERVED1_FIELD_WIDTH 4 #define UBUS_MSTR_HP_RESERVED1_FIELD_SHIFT 12 extern const ru_field_rec UBUS_MSTR_HP_HP_CNT_TOTAL_FIELD; #define UBUS_MSTR_HP_HP_CNT_TOTAL_FIELD_MASK 0x000f0000 #define UBUS_MSTR_HP_HP_CNT_TOTAL_FIELD_WIDTH 4 #define UBUS_MSTR_HP_HP_CNT_TOTAL_FIELD_SHIFT 16 extern const ru_field_rec UBUS_MSTR_HP_RESERVED2_FIELD; #define UBUS_MSTR_HP_RESERVED2_FIELD_MASK 0xfff00000 #define UBUS_MSTR_HP_RESERVED2_FIELD_WIDTH 12 #define UBUS_MSTR_HP_RESERVED2_FIELD_SHIFT 20 extern const ru_field_rec UBUS_MSTR_REPLY_ADD_ADD_FIELD; #define UBUS_MSTR_REPLY_ADD_ADD_FIELD_MASK 0xffffffff #define UBUS_MSTR_REPLY_ADD_ADD_FIELD_WIDTH 32 #define UBUS_MSTR_REPLY_ADD_ADD_FIELD_SHIFT 0 extern const ru_field_rec UBUS_MSTR_REPLY_DATA_DATA_FIELD; #define UBUS_MSTR_REPLY_DATA_DATA_FIELD_MASK 0xffffffff #define UBUS_MSTR_REPLY_DATA_DATA_FIELD_WIDTH 32 #define UBUS_MSTR_REPLY_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_RESERVED_RESERVED0_FIELD; #define UBUS_SLV_RESERVED_RESERVED0_FIELD_MASK 0xffffffff #define UBUS_SLV_RESERVED_RESERVED0_FIELD_WIDTH 32 #define UBUS_SLV_RESERVED_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_VPB_BASE_BASE_FIELD; #define UBUS_SLV_VPB_BASE_BASE_FIELD_MASK 0xffffffff #define UBUS_SLV_VPB_BASE_BASE_FIELD_WIDTH 32 #define UBUS_SLV_VPB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_VPB_MASK_MASK_FIELD; #define UBUS_SLV_VPB_MASK_MASK_FIELD_MASK 0xffffffff #define UBUS_SLV_VPB_MASK_MASK_FIELD_WIDTH 32 #define UBUS_SLV_VPB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_APB_BASE_BASE_FIELD; #define UBUS_SLV_APB_BASE_BASE_FIELD_MASK 0xffffffff #define UBUS_SLV_APB_BASE_BASE_FIELD_WIDTH 32 #define UBUS_SLV_APB_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_APB_MASK_MASK_FIELD; #define UBUS_SLV_APB_MASK_MASK_FIELD_MASK 0xffffffff #define UBUS_SLV_APB_MASK_MASK_FIELD_WIDTH 32 #define UBUS_SLV_APB_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_DQM_BASE_BASE_FIELD; #define UBUS_SLV_DQM_BASE_BASE_FIELD_MASK 0xffffffff #define UBUS_SLV_DQM_BASE_BASE_FIELD_WIDTH 32 #define UBUS_SLV_DQM_BASE_BASE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_DQM_MASK_MASK_FIELD; #define UBUS_SLV_DQM_MASK_MASK_FIELD_MASK 0xffffffff #define UBUS_SLV_DQM_MASK_MASK_FIELD_WIDTH 32 #define UBUS_SLV_DQM_MASK_MASK_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD; #define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_MASK 0xffffffff #define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_WIDTH 32 #define UBUS_SLV_RNR_INTR_CTRL_ISR_IST_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD; #define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_MASK 0xffffffff #define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32 #define UBUS_SLV_RNR_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD; #define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_MASK 0xffffffff #define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_WIDTH 32 #define UBUS_SLV_RNR_INTR_CTRL_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD; #define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_MASK 0xffffffff #define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_WIDTH 32 #define UBUS_SLV_RNR_INTR_CTRL_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD; #define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_MASK 0x00000001 #define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_WIDTH 1 #define UBUS_SLV_PROFILING_CFG_COUNTER_ENABLE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD; #define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_MASK 0x00000002 #define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_WIDTH 1 #define UBUS_SLV_PROFILING_CFG_PROFILING_START_FIELD_SHIFT 1 extern const ru_field_rec UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD; #define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_MASK 0x00000004 #define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_WIDTH 1 #define UBUS_SLV_PROFILING_CFG_MANUAL_STOP_MODE_FIELD_SHIFT 2 extern const ru_field_rec UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD; #define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_MASK 0x00000008 #define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_WIDTH 1 #define UBUS_SLV_PROFILING_CFG_DO_MANUAL_STOP_FIELD_SHIFT 3 extern const ru_field_rec UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD; #define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_MASK 0xfffffff0 #define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_WIDTH 28 #define UBUS_SLV_PROFILING_CFG_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD; #define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_MASK 0x00000001 #define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_WIDTH 1 #define UBUS_SLV_PROFILING_STATUS_PROFILING_ON_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD; #define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_MASK 0xfffffffe #define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_WIDTH 31 #define UBUS_SLV_PROFILING_STATUS_CYCLES_COUNTER_FIELD_SHIFT 1 extern const ru_field_rec UBUS_SLV_PROFILING_COUNTER_VAL_FIELD; #define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_MASK 0xffffffff #define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_WIDTH 32 #define UBUS_SLV_PROFILING_COUNTER_VAL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD; #define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_MASK 0xffffffff #define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_WIDTH 32 #define UBUS_SLV_PROFILING_START_VALUE_VAL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD; #define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_MASK 0xffffffff #define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_WIDTH 32 #define UBUS_SLV_PROFILING_STOP_VALUE_VAL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD; #define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_MASK 0xffffffff #define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_WIDTH 32 #define UBUS_SLV_PROFILING_CYCLE_NUM_PROFILING_CYCLES_NUM_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD; #define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_MASK 0x00000001 #define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_RGMII_MODE_EN_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD; #define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_MASK 0x00000002 #define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_ID_MODE_DIS_FIELD_SHIFT 1 extern const ru_field_rec UBUS_SLV__CNTRL_PORT_MODE_FIELD; #define UBUS_SLV__CNTRL_PORT_MODE_FIELD_MASK 0x0000001c #define UBUS_SLV__CNTRL_PORT_MODE_FIELD_WIDTH 3 #define UBUS_SLV__CNTRL_PORT_MODE_FIELD_SHIFT 2 extern const ru_field_rec UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD; #define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_MASK 0x00000020 #define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_RVMII_REF_SEL_FIELD_SHIFT 5 extern const ru_field_rec UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD; #define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_RX_PAUSE_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD; #define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_MASK 0x00000080 #define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_TX_PAUSE_EN_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD; #define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_MASK 0x00000100 #define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_TX_CLK_STOP_EN_FIELD_SHIFT 8 extern const ru_field_rec UBUS_SLV__CNTRL_LPI_COUNT_FIELD; #define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_MASK 0x00003e00 #define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_WIDTH 5 #define UBUS_SLV__CNTRL_LPI_COUNT_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD; #define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_MASK 0x00004000 #define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_RX_ERR_MASK_FIELD_SHIFT 14 extern const ru_field_rec UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD; #define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_MASK 0x00008000 #define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_WIDTH 1 #define UBUS_SLV__CNTRL_COL_CRS_MASK_FIELD_SHIFT 15 extern const ru_field_rec UBUS_SLV__CNTRL_RESERVED0_FIELD; #define UBUS_SLV__CNTRL_RESERVED0_FIELD_MASK 0xffff0000 #define UBUS_SLV__CNTRL_RESERVED0_FIELD_WIDTH 16 #define UBUS_SLV__CNTRL_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD; #define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_MASK 0x00000003 #define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_WIDTH 2 #define UBUS_SLV__IB_STATUS_SPEED_DECODE_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD; #define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_MASK 0x00000004 #define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_WIDTH 1 #define UBUS_SLV__IB_STATUS_DUPLEX_DECODE_FIELD_SHIFT 2 extern const ru_field_rec UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD; #define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_MASK 0x00000008 #define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_WIDTH 1 #define UBUS_SLV__IB_STATUS_LINK_DECODE_FIELD_SHIFT 3 extern const ru_field_rec UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD; #define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_MASK 0x00000010 #define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_WIDTH 1 #define UBUS_SLV__IB_STATUS_IB_STATUS_OVRD_FIELD_SHIFT 4 extern const ru_field_rec UBUS_SLV__IB_STATUS_RESERVED0_FIELD; #define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_MASK 0xffffffe0 #define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_WIDTH 27 #define UBUS_SLV__IB_STATUS_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_MASK 0x00000003 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_WIDTH 2 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_CTRI_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_MASK 0x0000000c #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_WIDTH 2 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DRNG_FIELD_SHIFT 2 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_MASK 0x00000010 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_WIDTH 1 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_IDDQ_FIELD_SHIFT 4 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_MASK 0x00000020 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_WIDTH 1 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_BYPASS_FIELD_SHIFT 5 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_MASK 0x00000040 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_WIDTH 1 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_SEL_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_MASK 0x00000080 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_WIDTH 1 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_DLY_OVERRIDE_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_MASK 0x00000100 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_WIDTH 1 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESET_FIELD_SHIFT 8 extern const ru_field_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_MASK 0xfffffe00 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_WIDTH 23 #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_EXPECTED_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_MASK 0x03fc0000 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_WIDTH 8 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_GOOD_COUNT_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_MASK 0x04000000 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_WIDTH 1 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_PKT_COUNT_RST_FIELD_SHIFT 26 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_MASK 0x08000000 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_WIDTH 1 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_ATE_EN_FIELD_SHIFT 27 extern const ru_field_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_MASK 0xf0000000 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_WIDTH 4 #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD; #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD; #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_EXP_DATA_1_EXPECTED_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD; #define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_MASK 0xfffc0000 #define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_WIDTH 14 #define UBUS_SLV__ATE_RX_EXP_DATA_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD; #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD; #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_STATUS_0_RECEIVED_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD; #define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_MASK 0x00040000 #define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_WIDTH 1 #define UBUS_SLV__ATE_RX_STATUS_0_RX_OK_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD; #define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_MASK 0xfff80000 #define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_WIDTH 13 #define UBUS_SLV__ATE_RX_STATUS_0_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD; #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD; #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_WIDTH 9 #define UBUS_SLV__ATE_RX_STATUS_1_RECEIVED_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD; #define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_MASK 0xfffc0000 #define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_WIDTH 14 #define UBUS_SLV__ATE_RX_STATUS_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_MASK 0x00000001 #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_WIDTH 1 #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_OVRD_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_MASK 0x00000002 #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_WIDTH 1 #define UBUS_SLV__ATE_TX_CNTRL_START_STOP_FIELD_SHIFT 1 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_MASK 0x00000004 #define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_WIDTH 1 #define UBUS_SLV__ATE_TX_CNTRL_PKT_GEN_EN_FIELD_SHIFT 2 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_MASK 0x000007f8 #define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_WIDTH 8 #define UBUS_SLV__ATE_TX_CNTRL_PKT_CNT_FIELD_SHIFT 3 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_MASK 0x003ff800 #define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_WIDTH 11 #define UBUS_SLV__ATE_TX_CNTRL_PAYLOAD_LENGTH_FIELD_SHIFT 11 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_MASK 0x0fc00000 #define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_WIDTH 6 #define UBUS_SLV__ATE_TX_CNTRL_PKT_IPG_FIELD_SHIFT 22 extern const ru_field_rec UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD; #define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_MASK 0xf0000000 #define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_WIDTH 4 #define UBUS_SLV__ATE_TX_CNTRL_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD; #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_WIDTH 9 #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_0_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD; #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_WIDTH 9 #define UBUS_SLV__ATE_TX_DATA_0_TX_DATA_1_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD; #define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_MASK 0xfffc0000 #define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_WIDTH 14 #define UBUS_SLV__ATE_TX_DATA_0_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD; #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_MASK 0x000001ff #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_WIDTH 9 #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_2_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD; #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_MASK 0x0003fe00 #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_WIDTH 9 #define UBUS_SLV__ATE_TX_DATA_1_TX_DATA_3_FIELD_SHIFT 9 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD; #define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_MASK 0xfffc0000 #define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_WIDTH 14 #define UBUS_SLV__ATE_TX_DATA_1_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD; #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_MASK 0x000000ff #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_WIDTH 8 #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_4_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD; #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_MASK 0x0000ff00 #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_WIDTH 8 #define UBUS_SLV__ATE_TX_DATA_2_TX_DATA_5_FIELD_SHIFT 8 extern const ru_field_rec UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD; #define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_MASK 0xffff0000 #define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_WIDTH 16 #define UBUS_SLV__ATE_TX_DATA_2_ETHER_TYPE_FIELD_SHIFT 16 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_MASK 0x0000003f #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD0_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_MASK 0x00001f80 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_MASK 0x00002000 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD1_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_MASK 0x000fc000 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_MASK 0x00100000 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD2_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_MASK 0x07e00000 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_MASK 0x08000000 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_0_TXD3_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK 0xf0000000 #define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4 #define UBUS_SLV__TX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_MASK 0x0000003f #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCTL_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_MASK 0x00000780 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_WIDTH 4 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_MASK 0x00000800 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_DEL_OVRD_EN_FIELD_SHIFT 11 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_MASK 0x0000f000 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_WIDTH 4 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_SEL_FIELD_SHIFT 12 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_MASK 0x00010000 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__TX_DELAY_CNTRL_1_TXCLK_ID_DEL_OVRD_EN_FIELD_SHIFT 16 extern const ru_field_rec UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD; #define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK 0xfffe0000 #define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 15 #define UBUS_SLV__TX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_MASK 0x0000003f #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD0_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_MASK 0x00001f80 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_MASK 0x00002000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD1_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_MASK 0x000fc000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_MASK 0x00100000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD2_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_MASK 0x07e00000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_MASK 0x08000000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_0_RXD3_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_MASK 0xf0000000 #define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_WIDTH 4 #define UBUS_SLV__RX_DELAY_CNTRL_0_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_MASK 0x0000003f #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD4_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_MASK 0x00001f80 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_MASK 0x00002000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD5_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_MASK 0x000fc000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_MASK 0x00100000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD6_DEL_OVRD_EN_FIELD_SHIFT 20 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_MASK 0x07e00000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_SEL_FIELD_SHIFT 21 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_MASK 0x08000000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_1_RXD7_DEL_OVRD_EN_FIELD_SHIFT 27 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_MASK 0xf0000000 #define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_WIDTH 4 #define UBUS_SLV__RX_DELAY_CNTRL_1_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_MASK 0x0000003f #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_SEL_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_MASK 0x00000040 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_POS_DEL_OVRD_EN_FIELD_SHIFT 6 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_MASK 0x00001f80 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_WIDTH 6 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_SEL_FIELD_SHIFT 7 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_MASK 0x00002000 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCTL_NEG_DEL_OVRD_EN_FIELD_SHIFT 13 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_MASK 0x0003c000 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_WIDTH 4 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_SEL_FIELD_SHIFT 14 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_MASK 0x00040000 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_WIDTH 1 #define UBUS_SLV__RX_DELAY_CNTRL_2_RXCLK_DEL_OVRD_EN_FIELD_SHIFT 18 extern const ru_field_rec UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD; #define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_MASK 0xfff80000 #define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_WIDTH 13 #define UBUS_SLV__RX_DELAY_CNTRL_2_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD; #define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_MASK 0x00000001 #define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_WIDTH 1 #define UBUS_SLV__CLK_RST_CTRL_SWINIT_FIELD_SHIFT 0 extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD; #define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_MASK 0x00000002 #define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_WIDTH 1 #define UBUS_SLV__CLK_RST_CTRL_CLK250EN_FIELD_SHIFT 1 extern const ru_field_rec UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD; #define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_MASK 0xfffffffc #define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_WIDTH 30 #define UBUS_SLV__CLK_RST_CTRL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD; #define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_MASK 0x00003fff #define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_WIDTH 14 #define SBPM_REGS_INIT_FREE_LIST_INIT_BASE_ADDR_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD; #define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_MASK 0x0fffc000 #define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_WIDTH 14 #define SBPM_REGS_INIT_FREE_LIST_INIT_OFFSET_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD; #define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_MASK 0x30000000 #define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_INIT_FREE_LIST_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_BSY_FIELD; #define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_MASK 0x40000000 #define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_WIDTH 1 #define SBPM_REGS_INIT_FREE_LIST_BSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_INIT_FREE_LIST_RDY_FIELD; #define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_WIDTH 1 #define SBPM_REGS_INIT_FREE_LIST_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RESERVED0_FIELD; #define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_MASK 0x00003fff #define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_WIDTH 14 #define SBPM_REGS_BN_ALLOC_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_ALLOC_SA_FIELD; #define SBPM_REGS_BN_ALLOC_SA_FIELD_MASK 0x000fc000 #define SBPM_REGS_BN_ALLOC_SA_FIELD_WIDTH 6 #define SBPM_REGS_BN_ALLOC_SA_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RESERVED1_FIELD; #define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_MASK 0xfff00000 #define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_WIDTH 12 #define SBPM_REGS_BN_ALLOC_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_MASK 0x00000001 #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_MASK 0x00007ffe #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_ALLOC_RPLY_ALLOC_BN_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_MASK 0x00008000 #define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_ACK_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_MASK 0x00010000 #define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_NACK_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_MASK 0x00020000 #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_HIGH_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_MASK 0x00040000 #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_EXCL_LOW_FIELD_SHIFT 18 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_MASK 0x3ff80000 #define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_WIDTH 11 #define SBPM_REGS_BN_ALLOC_RPLY_RESERVED0_FIELD_SHIFT 19 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_MASK 0x40000000 #define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_BUSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD; #define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_BN_ALLOC_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_MASK 0x000fc000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_WIDTH 6 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_SA_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_MASK 0x00f00000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_WIDTH 4 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_MASK 0x7f000000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_WIDTH 7 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_FIELD_SHIFT 24 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_ACK_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_MASK 0xffffc000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_WIDTH 18 #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_MCST_INC_BN_FIELD; #define SBPM_REGS_MCST_INC_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_MCST_INC_BN_FIELD_WIDTH 14 #define SBPM_REGS_MCST_INC_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_MCST_INC_MCST_VAL_FIELD; #define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_MASK 0x003fc000 #define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_WIDTH 8 #define SBPM_REGS_MCST_INC_MCST_VAL_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_MCST_INC_ACK_REQ_FIELD; #define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_MASK 0x00400000 #define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_WIDTH 1 #define SBPM_REGS_MCST_INC_ACK_REQ_FIELD_SHIFT 22 extern const ru_field_rec SBPM_REGS_MCST_INC_RESERVED0_FIELD; #define SBPM_REGS_MCST_INC_RESERVED0_FIELD_MASK 0xff800000 #define SBPM_REGS_MCST_INC_RESERVED0_FIELD_WIDTH 9 #define SBPM_REGS_MCST_INC_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD; #define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_MASK 0x00000001 #define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_WIDTH 1 #define SBPM_REGS_MCST_INC_RPLY_MCST_ACK_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD; #define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_MASK 0x3ffffffe #define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_WIDTH 29 #define SBPM_REGS_MCST_INC_RPLY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_BSY_FIELD; #define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_MASK 0x40000000 #define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_WIDTH 1 #define SBPM_REGS_MCST_INC_RPLY_BSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_MCST_INC_RPLY_RDY_FIELD; #define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_MCST_INC_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_CONNECT_BN_FIELD; #define SBPM_REGS_BN_CONNECT_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_BN_CONNECT_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_CONNECT_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD; #define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_MASK 0x00004000 #define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_WIDTH 1 #define SBPM_REGS_BN_CONNECT_ACK_REQ_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_BN_CONNECT_WR_REQ_FIELD; #define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_MASK 0x00008000 #define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_WIDTH 1 #define SBPM_REGS_BN_CONNECT_WR_REQ_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD; #define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_MASK 0x3fff0000 #define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_CONNECT_POINTED_BN_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_BN_CONNECT_RESERVED0_FIELD; #define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_MASK 0xc0000000 #define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_BN_CONNECT_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD; #define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_MASK 0x00000001 #define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_CONNECT_RPLY_CONNECT_ACK_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD; #define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_MASK 0x3ffffffe #define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_WIDTH 29 #define SBPM_REGS_BN_CONNECT_RPLY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD; #define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_MASK 0x40000000 #define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_WIDTH 1 #define SBPM_REGS_BN_CONNECT_RPLY_BUSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD; #define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_BN_CONNECT_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_GET_NEXT_BN_FIELD; #define SBPM_REGS_GET_NEXT_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_GET_NEXT_BN_FIELD_WIDTH 14 #define SBPM_REGS_GET_NEXT_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_GET_NEXT_RESERVED0_FIELD; #define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_MASK 0xffffc000 #define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_WIDTH 18 #define SBPM_REGS_GET_NEXT_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_MASK 0x00000001 #define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_WIDTH 1 #define SBPM_REGS_GET_NEXT_RPLY_BN_VALID_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_MASK 0x00007ffe #define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_WIDTH 14 #define SBPM_REGS_GET_NEXT_RPLY_NEXT_BN_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_MASK 0x00008000 #define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_WIDTH 1 #define SBPM_REGS_GET_NEXT_RPLY_BN_NULL_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_MASK 0x00ff0000 #define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_WIDTH 8 #define SBPM_REGS_GET_NEXT_RPLY_MCNT_VAL_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_MASK 0x3f000000 #define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_WIDTH 6 #define SBPM_REGS_GET_NEXT_RPLY_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_MASK 0x40000000 #define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_WIDTH 1 #define SBPM_REGS_GET_NEXT_RPLY_BUSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD; #define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_GET_NEXT_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_MASK 0x00700000 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_WIDTH 3 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_MASK 0x00003fff #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_WIDTH 14 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_MASK 0x000fc000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_WIDTH 6 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_SA_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_MASK 0x7ff00000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_WIDTH 11 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RESERVED0_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_MASK 0x00000001 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_MASK 0x00007ffe #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_WIDTH 14 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_MASK 0x00008000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_MASK 0x00010000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_MASK 0x00020000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_MASK 0x00040000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_FIELD_SHIFT 18 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_MASK 0x3ff80000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_WIDTH 11 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RESERVED1_FIELD_SHIFT 19 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_MASK 0x40000000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_MASK 0x00000001 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_MASK 0x00007ffe #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_WIDTH 14 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_MASK 0x00008000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_MASK 0x00010000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_MASK 0x00020000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_MASK 0x00040000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_FIELD_SHIFT 18 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_MASK 0x3ff80000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_WIDTH 11 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RESERVED1_FIELD_SHIFT 19 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_MASK 0x40000000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_MASK 0x80000000 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_WIDTH 1 #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_FIELD_SHIFT 31 extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD; #define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_GL_TRSH_GL_BAT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_GL_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD; #define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_GL_TRSH_GL_BAH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_GL_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD; #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD; #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_TRSH_UG_BAH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD; #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD; #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_TRSH_UG_BAH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD; #define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_MASK 0x0000000f #define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_SELECT_BUS_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_RESERVED0_FIELD; #define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_MASK 0xfffffff0 #define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_WIDTH 28 #define SBPM_REGS_SBPM_DBG_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD; #define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_BAC_UG0BAC_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_MASK 0xffffc000 #define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_WIDTH 18 #define SBPM_REGS_SBPM_UG0_BAC_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD; #define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_BAC_UG1BAC_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_MASK 0xffffc000 #define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_WIDTH 18 #define SBPM_REGS_SBPM_UG1_BAC_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_GL_BAC_BAC_FIELD; #define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_GL_BAC_BAC_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD; #define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_MASK 0xffffc000 #define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_WIDTH 18 #define SBPM_REGS_SBPM_GL_BAC_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_MASK 0x0000c000 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_MASK 0x3fff0000 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_RESERVED1_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD; #define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_MASK 0x00000003 #define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG_STATUS_UG_ACK_STTS_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_MASK 0x0000fffc #define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG_STATUS_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD; #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_MASK 0x00030000 #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD; #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_MASK 0x000c0000 #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_FIELD_SHIFT 18 extern const ru_field_rec SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD; #define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_MASK 0xfff00000 #define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_WIDTH 12 #define SBPM_REGS_SBPM_UG_STATUS_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD; #define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_MASK 0x0000007f #define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_WIDTH 7 #define SBPM_REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD; #define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_MASK 0x00000080 #define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_WIDTH 1 #define SBPM_REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_FIELD_SHIFT 7 extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD; #define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_MASK 0x00000100 #define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_WIDTH 1 #define SBPM_REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_FIELD_SHIFT 8 extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD; #define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_MASK 0x00000200 #define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_WIDTH 1 #define SBPM_REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_FIELD_SHIFT 9 extern const ru_field_rec SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD; #define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_MASK 0xfffffc00 #define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_WIDTH 22 #define SBPM_REGS_ERROR_HANDLING_PARAMS_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec SBPM_REGS_SBPM_IIR_LOW_CMD_SA_FIELD; #define SBPM_REGS_SBPM_IIR_LOW_CMD_SA_FIELD_MASK 0x0000003f #define SBPM_REGS_SBPM_IIR_LOW_CMD_SA_FIELD_WIDTH 6 #define SBPM_REGS_SBPM_IIR_LOW_CMD_SA_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_IIR_LOW_CMD_TA_FIELD; #define SBPM_REGS_SBPM_IIR_LOW_CMD_TA_FIELD_MASK 0x000001c0 #define SBPM_REGS_SBPM_IIR_LOW_CMD_TA_FIELD_WIDTH 3 #define SBPM_REGS_SBPM_IIR_LOW_CMD_TA_FIELD_SHIFT 6 extern const ru_field_rec SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_FIELD; #define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_FIELD_MASK 0xfffffe00 #define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_FIELD_WIDTH 23 #define SBPM_REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_FIELD_SHIFT 9 extern const ru_field_rec SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_FIELD; #define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_MASK 0x00000003 #define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_DBG_VEC0_ALLOC_SM_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_MASK 0x00000004 #define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC0_CNNCT_SM_FIELD_SHIFT 2 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_MASK 0x00000078 #define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_VEC0_MCINT_SM_FIELD_SHIFT 3 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_MASK 0x00000780 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_FIELD_SHIFT 7 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_MASK 0x00007800 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_FIELD_SHIFT 11 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_MASK 0x00018000 #define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_DBG_VEC0_GN_SM_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_MASK 0x001e0000 #define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_VEC0_MULTI_GN_SM_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD; #define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_MASK 0xffe00000 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_WIDTH 11 #define SBPM_REGS_SBPM_DBG_VEC0_FREE_LST_HD_FIELD_SHIFT 21 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_MASK 0x00000001 #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_VALID_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_MASK 0x0000001e #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_MASK 0x00000060 #define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_DBG_VEC1_UG_ACTIVE_FIELD_SHIFT 5 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_MASK 0x00000080 #define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_TX_CMD_FULL_FIELD_SHIFT 7 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_MASK 0x00000100 #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_POP_FIELD_SHIFT 8 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_MASK 0x00000200 #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_START_FIELD_SHIFT 9 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_MASK 0x00000400 #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_FIELD_SHIFT 10 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_MASK 0x001ff800 #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_WIDTH 10 #define SBPM_REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_FIELD_SHIFT 11 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_MASK 0x00200000 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_DECODE_FIELD_SHIFT 21 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_MASK 0x00400000 #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_IN2E_DECODE_FIELD_SHIFT 22 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_MASK 0x00800000 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_FIELD_SHIFT 23 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_MASK 0x01000000 #define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_FIELD_SHIFT 24 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_MASK 0x02000000 #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_FIELD_SHIFT 25 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_MASK 0x04000000 #define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_CNCT_DECODE_FIELD_SHIFT 26 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_MASK 0x08000000 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_FREE_W_DECODE_FIELD_SHIFT 27 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_MASK 0x10000000 #define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_MCIN_DECODE_FIELD_SHIFT 28 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_MASK 0x20000000 #define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC1_ALLOC_DECODE_FIELD_SHIFT 29 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD; #define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_MASK 0xc0000000 #define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_DBG_VEC1_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_MASK 0x00000001 #define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_TX_DATA_FULL_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_MASK 0x00000002 #define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_MASK 0x00000004 #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_FIELD_SHIFT 2 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_MASK 0x00000008 #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_FIELD_SHIFT 3 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_MASK 0x00000010 #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FULL_FIELD_SHIFT 4 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_MASK 0x00000020 #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_FIELD_SHIFT 5 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_MASK 0x00000fc0 #define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_WIDTH 6 #define SBPM_REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_FIELD_SHIFT 6 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_MASK 0x00001000 #define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_FIELD_SHIFT 12 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_MASK 0x0007e000 #define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_WIDTH 6 #define SBPM_REGS_SBPM_DBG_VEC2_SP_2SEND_FIELD_SHIFT 13 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_MASK 0x00380000 #define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_WIDTH 3 #define SBPM_REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_FIELD_SHIFT 19 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_MASK 0x00400000 #define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_CPU_ACCESS_FIELD_SHIFT 22 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_MASK 0x00800000 #define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_BBH_ACCESS_FIELD_SHIFT 23 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_MASK 0x01000000 #define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC2_RNR_ACCESS_FIELD_SHIFT 24 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD; #define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_MASK 0xfe000000 #define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_WIDTH 7 #define SBPM_REGS_SBPM_DBG_VEC2_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_MASK 0x00000001 #define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_ALLOC_RPLY_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_MASK 0x00000ffe #define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_WIDTH 11 #define SBPM_REGS_SBPM_DBG_VEC3_BN_RPLY_FIELD_SHIFT 1 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_MASK 0x00001000 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_FIELD_SHIFT 12 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_MASK 0x00002000 #define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_FIELD_SHIFT 13 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_MASK 0x00004000 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_MASK 0x00008000 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_FIELD_SHIFT 15 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_MASK 0x00010000 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_MASK 0x00060000 #define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_WIDTH 2 #define SBPM_REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_MASK 0x00080000 #define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_SEND_STT_SM_FIELD_SHIFT 19 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_MASK 0x00100000 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_FIELD_SHIFT 20 extern const ru_field_rec SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD; #define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_MASK 0xffe00000 #define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_WIDTH 11 #define SBPM_REGS_SBPM_DBG_VEC3_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD; #define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD; #define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD; #define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD; #define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD; #define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD; #define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD; #define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD; #define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD; #define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD; #define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_MASK 0xffffffff #define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_WIDTH 32 #define SBPM_REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD; #define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_MASK 0x0000003f #define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_WIDTH 6 #define SBPM_REGS_SBPM_RADDR_DECODER_ID_2OVERWR_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD; #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_MASK 0x0000ffc0 #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_WIDTH 10 #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_RA_FIELD_SHIFT 6 extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD; #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_MASK 0x00010000 #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_RADDR_DECODER_OVERWR_VALID_FIELD_SHIFT 16 extern const ru_field_rec SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD; #define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_MASK 0xfffe0000 #define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_WIDTH 15 #define SBPM_REGS_SBPM_RADDR_DECODER_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD; #define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_MASK 0x003fffff #define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_WIDTH 22 #define SBPM_REGS_SBPM_WR_DATA_SBPM_WR_DATA_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD; #define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_MASK 0xffc00000 #define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_WIDTH 10 #define SBPM_REGS_SBPM_WR_DATA_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD; #define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_MASK 0x00003fff #define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG_BAC_MAX_UG0BACMAX_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD; #define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_MASK 0x0fffc000 #define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_WIDTH 14 #define SBPM_REGS_SBPM_UG_BAC_MAX_UG1BACMAX_FIELD_SHIFT 14 extern const ru_field_rec SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD; #define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_MASK 0xf0000000 #define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_WIDTH 4 #define SBPM_REGS_SBPM_UG_BAC_MAX_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD; #define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_MASK 0x00000001 #define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_WIDTH 1 #define SBPM_REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD; #define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_MASK 0xfffffffe #define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_WIDTH 31 #define SBPM_REGS_SBPM_SPARE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD; #define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_MASK 0x00000001 #define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_BAC_UNDERRUN_FIELD_SHIFT 0 extern const ru_field_rec SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD; #define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_MASK 0x00000002 #define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_MCST_OVERFLOW_FIELD_SHIFT 1 extern const ru_field_rec SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD; #define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_MASK 0x00000004 #define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_CHECK_LAST_ERR_FIELD_SHIFT 2 extern const ru_field_rec SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD; #define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_MASK 0x00000008 #define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_MAX_SEARCH_ERR_FIELD_SHIFT 3 extern const ru_field_rec SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD; #define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_MASK 0x00000010 #define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_INVALID_IN2E_FIELD_SHIFT 4 extern const ru_field_rec SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD; #define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_MASK 0x00000020 #define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_FIELD_SHIFT 5 extern const ru_field_rec SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD; #define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_MASK 0x00000040 #define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_CNCT_NULL_FIELD_SHIFT 6 extern const ru_field_rec SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD; #define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_MASK 0x00000080 #define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_WIDTH 1 #define SBPM_INTR_CTRL_ISR_ALLOC_NULL_FIELD_SHIFT 7 extern const ru_field_rec SBPM_INTR_CTRL_ISR_RESERVED0_FIELD; #define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_MASK 0xffffff00 #define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 24 #define SBPM_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec SBPM_INTR_CTRL_ISM_ISM_FIELD; #define SBPM_INTR_CTRL_ISM_ISM_FIELD_MASK 0xffffffff #define SBPM_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32 #define SBPM_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec SBPM_INTR_CTRL_IER_IEM_FIELD; #define SBPM_INTR_CTRL_IER_IEM_FIELD_MASK 0xffffffff #define SBPM_INTR_CTRL_IER_IEM_FIELD_WIDTH 32 #define SBPM_INTR_CTRL_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec SBPM_INTR_CTRL_ITR_IST_FIELD; #define SBPM_INTR_CTRL_ITR_IST_FIELD_MASK 0xffffffff #define SBPM_INTR_CTRL_ITR_IST_FIELD_WIDTH 32 #define SBPM_INTR_CTRL_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_DEST_FIELD; #define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_MASK 0x0000003f #define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_WIDTH 6 #define DMA_CONFIG_BBROUTEOVRD_DEST_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD; #define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_MASK 0x000000c0 #define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_WIDTH 2 #define DMA_CONFIG_BBROUTEOVRD_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD; #define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_MASK 0x0003ff00 #define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_WIDTH 10 #define DMA_CONFIG_BBROUTEOVRD_ROUTE_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD; #define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_MASK 0x00fc0000 #define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_WIDTH 6 #define DMA_CONFIG_BBROUTEOVRD_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD; #define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_MASK 0x01000000 #define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_WIDTH 1 #define DMA_CONFIG_BBROUTEOVRD_OVRD_FIELD_SHIFT 24 extern const ru_field_rec DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD; #define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_MASK 0xfe000000 #define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_WIDTH 7 #define DMA_CONFIG_BBROUTEOVRD_RESERVED2_FIELD_SHIFT 25 extern const ru_field_rec DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD; #define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_MASK 0x0000003f #define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_WIDTH 6 #define DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD; #define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_WIDTH 26 #define DMA_CONFIG_NUM_OF_WRITES_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD; #define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_MASK 0x0000003f #define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_WIDTH 6 #define DMA_CONFIG_NUM_OF_READS_RR_NUM_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD; #define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_WIDTH 26 #define DMA_CONFIG_NUM_OF_READS_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_U_THRESH_INTO_U_FIELD; #define DMA_CONFIG_U_THRESH_INTO_U_FIELD_MASK 0x0000003f #define DMA_CONFIG_U_THRESH_INTO_U_FIELD_WIDTH 6 #define DMA_CONFIG_U_THRESH_INTO_U_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_U_THRESH_RESERVED0_FIELD; #define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_MASK 0x000000c0 #define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_WIDTH 2 #define DMA_CONFIG_U_THRESH_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD; #define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_MASK 0x00003f00 #define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_WIDTH 6 #define DMA_CONFIG_U_THRESH_OUT_OF_U_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_U_THRESH_RESERVED1_FIELD; #define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_MASK 0xffffc000 #define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_WIDTH 18 #define DMA_CONFIG_U_THRESH_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec DMA_CONFIG_PRI_RXPRI_FIELD; #define DMA_CONFIG_PRI_RXPRI_FIELD_MASK 0x0000000f #define DMA_CONFIG_PRI_RXPRI_FIELD_WIDTH 4 #define DMA_CONFIG_PRI_RXPRI_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_PRI_TXPRI_FIELD; #define DMA_CONFIG_PRI_TXPRI_FIELD_MASK 0x000000f0 #define DMA_CONFIG_PRI_TXPRI_FIELD_WIDTH 4 #define DMA_CONFIG_PRI_TXPRI_FIELD_SHIFT 4 extern const ru_field_rec DMA_CONFIG_PRI_RESERVED0_FIELD; #define DMA_CONFIG_PRI_RESERVED0_FIELD_MASK 0xffffff00 #define DMA_CONFIG_PRI_RESERVED0_FIELD_WIDTH 24 #define DMA_CONFIG_PRI_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD; #define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_MASK 0x0000003f #define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_WIDTH 6 #define DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD; #define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_MASK 0x000000c0 #define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_WIDTH 2 #define DMA_CONFIG_PERIPH_SOURCE_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD; #define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_MASK 0x00003f00 #define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_WIDTH 6 #define DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD; #define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_MASK 0xffffc000 #define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_WIDTH 18 #define DMA_CONFIG_PERIPH_SOURCE_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD; #define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_MASK 0x00000007 #define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_WIDTH 3 #define DMA_CONFIG_WEIGHT_RXWEIGHT_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_WEIGHT_RESERVED0_FIELD; #define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_MASK 0x000000f8 #define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_WIDTH 5 #define DMA_CONFIG_WEIGHT_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD; #define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_MASK 0x00000700 #define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_WIDTH 3 #define DMA_CONFIG_WEIGHT_TXWEIGHT_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_WEIGHT_RESERVED1_FIELD; #define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_MASK 0xfffff800 #define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_WIDTH 21 #define DMA_CONFIG_WEIGHT_RESERVED1_FIELD_SHIFT 11 extern const ru_field_rec DMA_CONFIG_PTRRST_RSTVEC_FIELD; #define DMA_CONFIG_PTRRST_RSTVEC_FIELD_MASK 0x0000ffff #define DMA_CONFIG_PTRRST_RSTVEC_FIELD_WIDTH 16 #define DMA_CONFIG_PTRRST_RSTVEC_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_PTRRST_RESERVED0_FIELD; #define DMA_CONFIG_PTRRST_RESERVED0_FIELD_MASK 0xffff0000 #define DMA_CONFIG_PTRRST_RESERVED0_FIELD_WIDTH 16 #define DMA_CONFIG_PTRRST_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec DMA_CONFIG_MAX_OTF_MAX_FIELD; #define DMA_CONFIG_MAX_OTF_MAX_FIELD_MASK 0x0000003f #define DMA_CONFIG_MAX_OTF_MAX_FIELD_WIDTH 6 #define DMA_CONFIG_MAX_OTF_MAX_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_MAX_OTF_RESERVED0_FIELD; #define DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_WIDTH 26 #define DMA_CONFIG_MAX_OTF_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define DMA_CONFIG_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec DMA_CONFIG_DBG_SEL_DBGSEL_FIELD; #define DMA_CONFIG_DBG_SEL_DBGSEL_FIELD_MASK 0x00000003 #define DMA_CONFIG_DBG_SEL_DBGSEL_FIELD_WIDTH 2 #define DMA_CONFIG_DBG_SEL_DBGSEL_FIELD_SHIFT 0 extern const ru_field_rec DMA_CONFIG_DBG_SEL_RESERVED0_FIELD; #define DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_MASK 0xfffffffc #define DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_WIDTH 30 #define DMA_CONFIG_DBG_SEL_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec DMA_DEBUG_NEMPTY_NEMPTY_FIELD; #define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_MASK 0x0000ffff #define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_WIDTH 16 #define DMA_DEBUG_NEMPTY_NEMPTY_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_NEMPTY_RESERVED0_FIELD; #define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_MASK 0xffff0000 #define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_WIDTH 16 #define DMA_DEBUG_NEMPTY_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec DMA_DEBUG_URGNT_URGNT_FIELD; #define DMA_DEBUG_URGNT_URGNT_FIELD_MASK 0x0000ffff #define DMA_DEBUG_URGNT_URGNT_FIELD_WIDTH 16 #define DMA_DEBUG_URGNT_URGNT_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_URGNT_RESERVED0_FIELD; #define DMA_DEBUG_URGNT_RESERVED0_FIELD_MASK 0xffff0000 #define DMA_DEBUG_URGNT_RESERVED0_FIELD_WIDTH 16 #define DMA_DEBUG_URGNT_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec DMA_DEBUG_SELSRC_SEL_SRC_FIELD; #define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_MASK 0x0000003f #define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_WIDTH 6 #define DMA_DEBUG_SELSRC_SEL_SRC_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_SELSRC_RESERVED0_FIELD; #define DMA_DEBUG_SELSRC_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_DEBUG_SELSRC_RESERVED0_FIELD_WIDTH 26 #define DMA_DEBUG_SELSRC_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD; #define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_MASK 0x0000003f #define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_WIDTH 6 #define DMA_DEBUG_REQ_CNT_RX_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD; #define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_WIDTH 26 #define DMA_DEBUG_REQ_CNT_RX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD; #define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_MASK 0x0000003f #define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_WIDTH 6 #define DMA_DEBUG_REQ_CNT_TX_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD; #define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_MASK 0xffffffc0 #define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_WIDTH 26 #define DMA_DEBUG_REQ_CNT_TX_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD; #define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_MASK 0xffffffff #define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_WIDTH 32 #define DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD; #define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_MASK 0xffffffff #define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_WIDTH 32 #define DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_RDADD_ADDRESS_FIELD; #define DMA_DEBUG_RDADD_ADDRESS_FIELD_MASK 0x000003ff #define DMA_DEBUG_RDADD_ADDRESS_FIELD_WIDTH 10 #define DMA_DEBUG_RDADD_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_RDADD_RESERVED0_FIELD; #define DMA_DEBUG_RDADD_RESERVED0_FIELD_MASK 0x0000fc00 #define DMA_DEBUG_RDADD_RESERVED0_FIELD_WIDTH 6 #define DMA_DEBUG_RDADD_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec DMA_DEBUG_RDADD_DATACS_FIELD; #define DMA_DEBUG_RDADD_DATACS_FIELD_MASK 0x00010000 #define DMA_DEBUG_RDADD_DATACS_FIELD_WIDTH 1 #define DMA_DEBUG_RDADD_DATACS_FIELD_SHIFT 16 extern const ru_field_rec DMA_DEBUG_RDADD_CDCS_FIELD; #define DMA_DEBUG_RDADD_CDCS_FIELD_MASK 0x00020000 #define DMA_DEBUG_RDADD_CDCS_FIELD_WIDTH 1 #define DMA_DEBUG_RDADD_CDCS_FIELD_SHIFT 17 extern const ru_field_rec DMA_DEBUG_RDADD_RRCS_FIELD; #define DMA_DEBUG_RDADD_RRCS_FIELD_MASK 0x00040000 #define DMA_DEBUG_RDADD_RRCS_FIELD_WIDTH 1 #define DMA_DEBUG_RDADD_RRCS_FIELD_SHIFT 18 extern const ru_field_rec DMA_DEBUG_RDADD_RESERVED1_FIELD; #define DMA_DEBUG_RDADD_RESERVED1_FIELD_MASK 0xfff80000 #define DMA_DEBUG_RDADD_RESERVED1_FIELD_WIDTH 13 #define DMA_DEBUG_RDADD_RESERVED1_FIELD_SHIFT 19 extern const ru_field_rec DMA_DEBUG_RDVALID_VALID_FIELD; #define DMA_DEBUG_RDVALID_VALID_FIELD_MASK 0x00000001 #define DMA_DEBUG_RDVALID_VALID_FIELD_WIDTH 1 #define DMA_DEBUG_RDVALID_VALID_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_RDVALID_RESERVED0_FIELD; #define DMA_DEBUG_RDVALID_RESERVED0_FIELD_MASK 0xfffffffe #define DMA_DEBUG_RDVALID_RESERVED0_FIELD_WIDTH 31 #define DMA_DEBUG_RDVALID_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec DMA_DEBUG_RDDATA_DATA_FIELD; #define DMA_DEBUG_RDDATA_DATA_FIELD_MASK 0xffffffff #define DMA_DEBUG_RDDATA_DATA_FIELD_WIDTH 32 #define DMA_DEBUG_RDDATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_RDDATARDY_READY_FIELD; #define DMA_DEBUG_RDDATARDY_READY_FIELD_MASK 0x00000001 #define DMA_DEBUG_RDDATARDY_READY_FIELD_WIDTH 1 #define DMA_DEBUG_RDDATARDY_READY_FIELD_SHIFT 0 extern const ru_field_rec DMA_DEBUG_RDDATARDY_RESERVED0_FIELD; #define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_MASK 0xfffffffe #define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_WIDTH 31 #define DMA_DEBUG_RDDATARDY_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_MEMORY_DATA_DATA_FIELD; #define PSRAM_MEMORY_DATA_DATA_FIELD_MASK 0xffffffff #define PSRAM_MEMORY_DATA_DATA_FIELD_WIDTH 32 #define PSRAM_MEMORY_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_MASK 0x00000001 #define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_PERM_EN_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_MASK 0x00000002 #define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_COMB_EN_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_MASK 0x00000004 #define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_COMB_FULL_FIELD_SHIFT 2 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_MASK 0x00000008 #define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_BANKS8_FIELD_SHIFT 3 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_MASK 0x00000010 #define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB0_REQIN_ESWAP_FIELD_SHIFT 4 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_MASK 0x00000020 #define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB0_REPOUT_ESWAP_FIELD_SHIFT 5 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_MASK 0x00000040 #define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB1_REQIN_ESWAP_FIELD_SHIFT 6 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_MASK 0x00000080 #define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB1_REPOUT_ESWAP_FIELD_SHIFT 7 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_MASK 0x00000100 #define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB2_REQIN_ESWAP_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_MASK 0x00000200 #define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB2_REPOUT_ESWAP_FIELD_SHIFT 9 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_MASK 0x00000400 #define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB3_REQIN_ESWAP_FIELD_SHIFT 10 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_MASK 0x00000800 #define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_UB3_REPOUT_ESWAP_FIELD_SHIFT 11 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_MASK 0x00001000 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC0_FIELD_SHIFT 12 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_MASK 0x00002000 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC1_FIELD_SHIFT 13 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_MASK 0x00004000 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_COH_EN_EC2_FIELD_SHIFT 14 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_MASK 0x00038000 #define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_WIDTH 3 #define PSRAM_CONFIGURATIONS_CTRL_WT_0_FIELD_SHIFT 15 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_MASK 0x001c0000 #define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_WIDTH 3 #define PSRAM_CONFIGURATIONS_CTRL_WT_1_FIELD_SHIFT 18 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_MASK 0x00e00000 #define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_WIDTH 3 #define PSRAM_CONFIGURATIONS_CTRL_WT_2_FIELD_SHIFT 21 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_MASK 0x01000000 #define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CTRL_ARB_RR_FIELD_SHIFT 24 extern const ru_field_rec PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD; #define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_MASK 0xfe000000 #define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_WIDTH 7 #define PSRAM_CONFIGURATIONS_CTRL_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_MASK 0x00000001 #define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL0MEN_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_MASK 0x00000002 #define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL1MEN_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_MASK 0x00000004 #define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL2MEN_FIELD_SHIFT 2 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_MASK 0x00000008 #define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL3MEN_FIELD_SHIFT 3 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_MASK 0x00000010 #define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL4MEN_FIELD_SHIFT 4 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_MASK 0x00000020 #define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL5MEN_FIELD_SHIFT 5 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD; #define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_MASK 0x00000040 #define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_MUEN_CL6MEN_FIELD_SHIFT 6 extern const ru_field_rec PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD; #define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_MASK 0xffffff80 #define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_WIDTH 25 #define PSRAM_PM_COUNTERS_MUEN_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec PSRAM_PM_COUNTERS_BWCL_TW_FIELD; #define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BWCL_TW_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD; #define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_MASK 0x00000001 #define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_BWEN_BWCEN_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD; #define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_MASK 0x000000fe #define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_WIDTH 7 #define PSRAM_PM_COUNTERS_BWEN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD; #define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_MASK 0x00000100 #define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_WIDTH 1 #define PSRAM_PM_COUNTERS_BWEN_CBWCEN_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD; #define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_MASK 0xfffffe00 #define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_WIDTH 23 #define PSRAM_PM_COUNTERS_BWEN_RESERVED1_FIELD_SHIFT 9 extern const ru_field_rec PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD; #define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_MAX_TIME_MAX_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD; #define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ACC_TIME_MAX_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD; #define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ACC_REQ_REQ_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD; #define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD; #define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD; #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD; #define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ARB_REQ_VAL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD; #define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ARB_ARB_VAL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD; #define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ARB_COMB_VAL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD; #define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD; #define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_MASK 0xffffffff #define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_WIDTH 32 #define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBGSEL_VS_FIELD; #define PSRAM_DEBUG_DBGSEL_VS_FIELD_MASK 0x000000ff #define PSRAM_DEBUG_DBGSEL_VS_FIELD_WIDTH 8 #define PSRAM_DEBUG_DBGSEL_VS_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD; #define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_MASK 0xffffff00 #define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_WIDTH 24 #define PSRAM_DEBUG_DBGSEL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_DEBUG_DBGBUS_VB_FIELD; #define PSRAM_DEBUG_DBGBUS_VB_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBGBUS_VB_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBGBUS_VB_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_MASK 0x00000001 #define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_MASK 0x00000002 #define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_FIELD_SHIFT 1 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_MASK 0x00000004 #define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_FIELD_SHIFT 2 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_MASK 0x00000008 #define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_FIELD_SHIFT 3 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_MASK 0x00000010 #define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_FIELD_SHIFT 4 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD; #define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_MASK 0x00000020 #define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_WIDTH 1 #define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_FIELD_SHIFT 5 extern const ru_field_rec PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD; #define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_MASK 0xffffffc0 #define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_WIDTH 26 #define PSRAM_DEBUG_REQ_VEC_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_MASK 0x00000007 #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_WIDTH 3 #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_MASK 0x00000008 #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_WIDTH 1 #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_MASK 0x0000fff0 #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_WIDTH 12 #define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_FIELD_SHIFT 4 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_MASK 0x00010000 #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_WIDTH 1 #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_FIELD_SHIFT 16 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_MASK 0x00020000 #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_WIDTH 1 #define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_FIELD_SHIFT 17 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_MASK 0xfffc0000 #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_WIDTH 14 #define PSRAM_DEBUG_DBG_CAP_CFG1_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_MASK 0x000000ff #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_WIDTH 8 #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_MASK 0x0000ff00 #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_WIDTH 8 #define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_MASK 0x00010000 #define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_WIDTH 1 #define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_FIELD_SHIFT 16 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_MASK 0x00020000 #define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_WIDTH 1 #define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_FIELD_SHIFT 17 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD; #define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_MASK 0xfffc0000 #define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_WIDTH 14 #define PSRAM_DEBUG_DBG_CAP_CFG2_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD; #define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_MASK 0x000000ff #define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_WIDTH 8 #define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD; #define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_MASK 0x0000ff00 #define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_WIDTH 8 #define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_FIELD_SHIFT 8 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_W0_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_W1_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_W2_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_W3_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_WMSK_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_R0_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_R1_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_R2_CV_FIELD_SHIFT 0 extern const ru_field_rec PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD; #define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_MASK 0xffffffff #define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_WIDTH 32 #define PSRAM_DEBUG_DBG_CAP_R3_CV_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_UMAC_DUMMY_RESERVED0_FIELD; #define UNIMAC_RDP_UMAC_DUMMY_RESERVED0_FIELD_MASK 0xffffff00 #define UNIMAC_RDP_UMAC_DUMMY_RESERVED0_FIELD_WIDTH 24 #define UNIMAC_RDP_UMAC_DUMMY_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_RDP_UMAC_DUMMY_UMAC_DUMMY_FIELD; #define UNIMAC_RDP_UMAC_DUMMY_UMAC_DUMMY_FIELD_MASK 0x000000ff #define UNIMAC_RDP_UMAC_DUMMY_UMAC_DUMMY_FIELD_WIDTH 8 #define UNIMAC_RDP_UMAC_DUMMY_UMAC_DUMMY_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_HD_BKP_CNTL_RESERVED0_FIELD; #define UNIMAC_RDP_HD_BKP_CNTL_RESERVED0_FIELD_MASK 0xffffff80 #define UNIMAC_RDP_HD_BKP_CNTL_RESERVED0_FIELD_WIDTH 25 #define UNIMAC_RDP_HD_BKP_CNTL_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_RDP_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD; #define UNIMAC_RDP_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_MASK 0x0000007c #define UNIMAC_RDP_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_WIDTH 5 #define UNIMAC_RDP_HD_BKP_CNTL_IPG_CONFIG_RX_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD; #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_MASK 0x00000002 #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_WIDTH 1 #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_BKOFF_OK_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_HD_BKP_CNTL_HD_FC_ENA_FIELD; #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_ENA_FIELD_MASK 0x00000001 #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_HD_BKP_CNTL_HD_FC_ENA_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_CMD_RESERVED0_FIELD; #define UNIMAC_RDP_CMD_RESERVED0_FIELD_MASK 0x80000000 #define UNIMAC_RDP_CMD_RESERVED0_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RESERVED0_FIELD_SHIFT 31 extern const ru_field_rec UNIMAC_RDP_CMD_RUNT_FILTER_DIS_FIELD; #define UNIMAC_RDP_CMD_RUNT_FILTER_DIS_FIELD_MASK 0x40000000 #define UNIMAC_RDP_CMD_RUNT_FILTER_DIS_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RUNT_FILTER_DIS_FIELD_SHIFT 30 extern const ru_field_rec UNIMAC_RDP_CMD_TXRX_EN_CONFIG_FIELD; #define UNIMAC_RDP_CMD_TXRX_EN_CONFIG_FIELD_MASK 0x20000000 #define UNIMAC_RDP_CMD_TXRX_EN_CONFIG_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_TXRX_EN_CONFIG_FIELD_SHIFT 29 extern const ru_field_rec UNIMAC_RDP_CMD_TX_PAUSE_IGNORE_FIELD; #define UNIMAC_RDP_CMD_TX_PAUSE_IGNORE_FIELD_MASK 0x10000000 #define UNIMAC_RDP_CMD_TX_PAUSE_IGNORE_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_TX_PAUSE_IGNORE_FIELD_SHIFT 28 extern const ru_field_rec UNIMAC_RDP_CMD_PRBL_ENA_FIELD; #define UNIMAC_RDP_CMD_PRBL_ENA_FIELD_MASK 0x08000000 #define UNIMAC_RDP_CMD_PRBL_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_PRBL_ENA_FIELD_SHIFT 27 extern const ru_field_rec UNIMAC_RDP_CMD_RX_ERR_DISC_FIELD; #define UNIMAC_RDP_CMD_RX_ERR_DISC_FIELD_MASK 0x04000000 #define UNIMAC_RDP_CMD_RX_ERR_DISC_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RX_ERR_DISC_FIELD_SHIFT 26 extern const ru_field_rec UNIMAC_RDP_CMD_RMT_LOOP_ENA_FIELD; #define UNIMAC_RDP_CMD_RMT_LOOP_ENA_FIELD_MASK 0x02000000 #define UNIMAC_RDP_CMD_RMT_LOOP_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RMT_LOOP_ENA_FIELD_SHIFT 25 extern const ru_field_rec UNIMAC_RDP_CMD_NO_LGTH_CHECK_FIELD; #define UNIMAC_RDP_CMD_NO_LGTH_CHECK_FIELD_MASK 0x01000000 #define UNIMAC_RDP_CMD_NO_LGTH_CHECK_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_NO_LGTH_CHECK_FIELD_SHIFT 24 extern const ru_field_rec UNIMAC_RDP_CMD_CNTL_FRM_ENA_FIELD; #define UNIMAC_RDP_CMD_CNTL_FRM_ENA_FIELD_MASK 0x00800000 #define UNIMAC_RDP_CMD_CNTL_FRM_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_CNTL_FRM_ENA_FIELD_SHIFT 23 extern const ru_field_rec UNIMAC_RDP_CMD_ENA_EXT_CONFIG_FIELD; #define UNIMAC_RDP_CMD_ENA_EXT_CONFIG_FIELD_MASK 0x00400000 #define UNIMAC_RDP_CMD_ENA_EXT_CONFIG_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_ENA_EXT_CONFIG_FIELD_SHIFT 22 extern const ru_field_rec UNIMAC_RDP_CMD_RESERVED1_FIELD; #define UNIMAC_RDP_CMD_RESERVED1_FIELD_MASK 0x003f0000 #define UNIMAC_RDP_CMD_RESERVED1_FIELD_WIDTH 6 #define UNIMAC_RDP_CMD_RESERVED1_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_CMD_LCL_LOOP_ENA_FIELD; #define UNIMAC_RDP_CMD_LCL_LOOP_ENA_FIELD_MASK 0x00008000 #define UNIMAC_RDP_CMD_LCL_LOOP_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_LCL_LOOP_ENA_FIELD_SHIFT 15 extern const ru_field_rec UNIMAC_RDP_CMD_RESERVED2_FIELD; #define UNIMAC_RDP_CMD_RESERVED2_FIELD_MASK 0x00004000 #define UNIMAC_RDP_CMD_RESERVED2_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RESERVED2_FIELD_SHIFT 14 extern const ru_field_rec UNIMAC_RDP_CMD_SW_RESET_FIELD; #define UNIMAC_RDP_CMD_SW_RESET_FIELD_MASK 0x00002000 #define UNIMAC_RDP_CMD_SW_RESET_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_SW_RESET_FIELD_SHIFT 13 extern const ru_field_rec UNIMAC_RDP_CMD_RESERVED3_FIELD; #define UNIMAC_RDP_CMD_RESERVED3_FIELD_MASK 0x00001800 #define UNIMAC_RDP_CMD_RESERVED3_FIELD_WIDTH 2 #define UNIMAC_RDP_CMD_RESERVED3_FIELD_SHIFT 11 extern const ru_field_rec UNIMAC_RDP_CMD_HD_ENA_FIELD; #define UNIMAC_RDP_CMD_HD_ENA_FIELD_MASK 0x00000400 #define UNIMAC_RDP_CMD_HD_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_HD_ENA_FIELD_SHIFT 10 extern const ru_field_rec UNIMAC_RDP_CMD_TX_ADDR_INS_FIELD; #define UNIMAC_RDP_CMD_TX_ADDR_INS_FIELD_MASK 0x00000200 #define UNIMAC_RDP_CMD_TX_ADDR_INS_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_TX_ADDR_INS_FIELD_SHIFT 9 extern const ru_field_rec UNIMAC_RDP_CMD_RX_PAUSE_IGNORE_FIELD; #define UNIMAC_RDP_CMD_RX_PAUSE_IGNORE_FIELD_MASK 0x00000100 #define UNIMAC_RDP_CMD_RX_PAUSE_IGNORE_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RX_PAUSE_IGNORE_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_RDP_CMD_PAUSE_FWD_FIELD; #define UNIMAC_RDP_CMD_PAUSE_FWD_FIELD_MASK 0x00000080 #define UNIMAC_RDP_CMD_PAUSE_FWD_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_PAUSE_FWD_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_RDP_CMD_CRC_FWD_FIELD; #define UNIMAC_RDP_CMD_CRC_FWD_FIELD_MASK 0x00000040 #define UNIMAC_RDP_CMD_CRC_FWD_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_CRC_FWD_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_RDP_CMD_PAD_EN_FIELD; #define UNIMAC_RDP_CMD_PAD_EN_FIELD_MASK 0x00000020 #define UNIMAC_RDP_CMD_PAD_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_PAD_EN_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_RDP_CMD_PROMIS_EN_FIELD; #define UNIMAC_RDP_CMD_PROMIS_EN_FIELD_MASK 0x00000010 #define UNIMAC_RDP_CMD_PROMIS_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_PROMIS_EN_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_CMD_ETH_SPEED_FIELD; #define UNIMAC_RDP_CMD_ETH_SPEED_FIELD_MASK 0x0000000c #define UNIMAC_RDP_CMD_ETH_SPEED_FIELD_WIDTH 2 #define UNIMAC_RDP_CMD_ETH_SPEED_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_CMD_RX_ENA_FIELD; #define UNIMAC_RDP_CMD_RX_ENA_FIELD_MASK 0x00000002 #define UNIMAC_RDP_CMD_RX_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_RX_ENA_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_CMD_TX_ENA_FIELD; #define UNIMAC_RDP_CMD_TX_ENA_FIELD_MASK 0x00000001 #define UNIMAC_RDP_CMD_TX_ENA_FIELD_WIDTH 1 #define UNIMAC_RDP_CMD_TX_ENA_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MAC0_MAC_0_FIELD; #define UNIMAC_RDP_MAC0_MAC_0_FIELD_MASK 0xffffffff #define UNIMAC_RDP_MAC0_MAC_0_FIELD_WIDTH 32 #define UNIMAC_RDP_MAC0_MAC_0_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MAC1_RESERVED0_FIELD; #define UNIMAC_RDP_MAC1_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_MAC1_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_MAC1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_MAC1_MAC_1_FIELD; #define UNIMAC_RDP_MAC1_MAC_1_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_MAC1_MAC_1_FIELD_WIDTH 16 #define UNIMAC_RDP_MAC1_MAC_1_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_FRM_LEN_RESERVED0_FIELD; #define UNIMAC_RDP_FRM_LEN_RESERVED0_FIELD_MASK 0xffffc000 #define UNIMAC_RDP_FRM_LEN_RESERVED0_FIELD_WIDTH 18 #define UNIMAC_RDP_FRM_LEN_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec UNIMAC_RDP_FRM_LEN_FRAME_LENGTH_FIELD; #define UNIMAC_RDP_FRM_LEN_FRAME_LENGTH_FIELD_MASK 0x00003fff #define UNIMAC_RDP_FRM_LEN_FRAME_LENGTH_FIELD_WIDTH 14 #define UNIMAC_RDP_FRM_LEN_FRAME_LENGTH_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_PAUSE_QUNAT_RESERVED0_FIELD; #define UNIMAC_RDP_PAUSE_QUNAT_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_PAUSE_QUNAT_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_PAUSE_QUNAT_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_PAUSE_QUNAT_PAUSE_QUANT_FIELD; #define UNIMAC_RDP_PAUSE_QUNAT_PAUSE_QUANT_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_PAUSE_QUNAT_PAUSE_QUANT_FIELD_WIDTH 16 #define UNIMAC_RDP_PAUSE_QUNAT_PAUSE_QUANT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_SFD_OFFSET_TEMP_FIELD; #define UNIMAC_RDP_SFD_OFFSET_TEMP_FIELD_MASK 0xffffffff #define UNIMAC_RDP_SFD_OFFSET_TEMP_FIELD_WIDTH 32 #define UNIMAC_RDP_SFD_OFFSET_TEMP_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MODE_RESERVED0_FIELD; #define UNIMAC_RDP_MODE_RESERVED0_FIELD_MASK 0xffffffc0 #define UNIMAC_RDP_MODE_RESERVED0_FIELD_WIDTH 26 #define UNIMAC_RDP_MODE_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_RDP_MODE_MAC_LINK_STAT_FIELD; #define UNIMAC_RDP_MODE_MAC_LINK_STAT_FIELD_MASK 0x00000020 #define UNIMAC_RDP_MODE_MAC_LINK_STAT_FIELD_WIDTH 1 #define UNIMAC_RDP_MODE_MAC_LINK_STAT_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_RDP_MODE_MAC_TX_PAUSE_FIELD; #define UNIMAC_RDP_MODE_MAC_TX_PAUSE_FIELD_MASK 0x00000010 #define UNIMAC_RDP_MODE_MAC_TX_PAUSE_FIELD_WIDTH 1 #define UNIMAC_RDP_MODE_MAC_TX_PAUSE_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_MODE_MAC_RX_PAUSE_FIELD; #define UNIMAC_RDP_MODE_MAC_RX_PAUSE_FIELD_MASK 0x00000008 #define UNIMAC_RDP_MODE_MAC_RX_PAUSE_FIELD_WIDTH 1 #define UNIMAC_RDP_MODE_MAC_RX_PAUSE_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_RDP_MODE_MAC_DUPLEX_FIELD; #define UNIMAC_RDP_MODE_MAC_DUPLEX_FIELD_MASK 0x00000004 #define UNIMAC_RDP_MODE_MAC_DUPLEX_FIELD_WIDTH 1 #define UNIMAC_RDP_MODE_MAC_DUPLEX_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_MODE_MAC_SPEED_FIELD; #define UNIMAC_RDP_MODE_MAC_SPEED_FIELD_MASK 0x00000003 #define UNIMAC_RDP_MODE_MAC_SPEED_FIELD_WIDTH 2 #define UNIMAC_RDP_MODE_MAC_SPEED_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_FRM_TAG0_RESERVED0_FIELD; #define UNIMAC_RDP_FRM_TAG0_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_FRM_TAG0_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_FRM_TAG0_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_FRM_TAG0_OUTER_TAG_FIELD; #define UNIMAC_RDP_FRM_TAG0_OUTER_TAG_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_FRM_TAG0_OUTER_TAG_FIELD_WIDTH 16 #define UNIMAC_RDP_FRM_TAG0_OUTER_TAG_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_FRM_TAG1_RESERVED0_FIELD; #define UNIMAC_RDP_FRM_TAG1_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_FRM_TAG1_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_FRM_TAG1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_FRM_TAG1_INNER_TAG_FIELD; #define UNIMAC_RDP_FRM_TAG1_INNER_TAG_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_FRM_TAG1_INNER_TAG_FIELD_WIDTH 16 #define UNIMAC_RDP_FRM_TAG1_INNER_TAG_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_IPG_LEN_RESERVED0_FIELD; #define UNIMAC_RDP_TX_IPG_LEN_RESERVED0_FIELD_MASK 0xffffff80 #define UNIMAC_RDP_TX_IPG_LEN_RESERVED0_FIELD_WIDTH 25 #define UNIMAC_RDP_TX_IPG_LEN_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_RDP_TX_IPG_LEN_TX_IPG_LEN_FIELD; #define UNIMAC_RDP_TX_IPG_LEN_TX_IPG_LEN_FIELD_MASK 0x0000007f #define UNIMAC_RDP_TX_IPG_LEN_TX_IPG_LEN_FIELD_WIDTH 7 #define UNIMAC_RDP_TX_IPG_LEN_TX_IPG_LEN_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_RESERVED0_FIELD; #define UNIMAC_RDP_EEE_CTRL_RESERVED0_FIELD_MASK 0xffffff00 #define UNIMAC_RDP_EEE_CTRL_RESERVED0_FIELD_WIDTH 24 #define UNIMAC_RDP_EEE_CTRL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD; #define UNIMAC_RDP_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_MASK 0x00000080 #define UNIMAC_RDP_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_LP_IDLE_PREDICTION_MODE_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_DIS_EEE_10M_FIELD; #define UNIMAC_RDP_EEE_CTRL_DIS_EEE_10M_FIELD_MASK 0x00000040 #define UNIMAC_RDP_EEE_CTRL_DIS_EEE_10M_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_DIS_EEE_10M_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_EEE_TXCLK_DIS_FIELD; #define UNIMAC_RDP_EEE_CTRL_EEE_TXCLK_DIS_FIELD_MASK 0x00000020 #define UNIMAC_RDP_EEE_CTRL_EEE_TXCLK_DIS_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_EEE_TXCLK_DIS_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_RX_FIFO_CHECK_FIELD; #define UNIMAC_RDP_EEE_CTRL_RX_FIFO_CHECK_FIELD_MASK 0x00000010 #define UNIMAC_RDP_EEE_CTRL_RX_FIFO_CHECK_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_RX_FIFO_CHECK_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_EEE_EN_FIELD; #define UNIMAC_RDP_EEE_CTRL_EEE_EN_FIELD_MASK 0x00000008 #define UNIMAC_RDP_EEE_CTRL_EEE_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_EEE_EN_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PAUSE_FIELD; #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PAUSE_FIELD_MASK 0x00000004 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PAUSE_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PAUSE_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PFC_FIELD; #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PFC_FIELD_MASK 0x00000002 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PFC_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_TX_PFC_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_EEE_CTRL_EN_LPI_RX_PAUSE_FIELD; #define UNIMAC_RDP_EEE_CTRL_EN_LPI_RX_PAUSE_FIELD_MASK 0x00000001 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_RX_PAUSE_FIELD_WIDTH 1 #define UNIMAC_RDP_EEE_CTRL_EN_LPI_RX_PAUSE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_EEE_LPI_TIMER_EEE_LPI_TIMER_FIELD; #define UNIMAC_RDP_EEE_LPI_TIMER_EEE_LPI_TIMER_FIELD_MASK 0xffffffff #define UNIMAC_RDP_EEE_LPI_TIMER_EEE_LPI_TIMER_FIELD_WIDTH 32 #define UNIMAC_RDP_EEE_LPI_TIMER_EEE_LPI_TIMER_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_EEE_WAKE_TIMER_RESERVED0_FIELD; #define UNIMAC_RDP_EEE_WAKE_TIMER_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_EEE_WAKE_TIMER_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_EEE_WAKE_TIMER_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_EEE_WAKE_TIMER_EEE_WAKE_TIMER_FIELD; #define UNIMAC_RDP_EEE_WAKE_TIMER_EEE_WAKE_TIMER_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_EEE_WAKE_TIMER_EEE_WAKE_TIMER_FIELD_WIDTH 16 #define UNIMAC_RDP_EEE_WAKE_TIMER_EEE_WAKE_TIMER_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_EEE_REF_COUNT_RESERVED0_FIELD; #define UNIMAC_RDP_EEE_REF_COUNT_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_EEE_REF_COUNT_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_EEE_REF_COUNT_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_EEE_REF_COUNT_EEE_REFERENCE_COUNT_FIELD; #define UNIMAC_RDP_EEE_REF_COUNT_EEE_REFERENCE_COUNT_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_EEE_REF_COUNT_EEE_REFERENCE_COUNT_FIELD_WIDTH 16 #define UNIMAC_RDP_EEE_REF_COUNT_EEE_REFERENCE_COUNT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_PKT_DROP_STATUS_RESERVED0_FIELD; #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_RX_PKT_DROP_STATUS_RX_IPG_INVALID_FIELD; #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RX_IPG_INVALID_FIELD_MASK 0x00000001 #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RX_IPG_INVALID_FIELD_WIDTH 1 #define UNIMAC_RDP_RX_PKT_DROP_STATUS_RX_IPG_INVALID_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD; #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_WIDTH 16 #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD; #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_WIDTH 16 #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_THRESHOLD_VALUE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD; #define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_MASK 0xffffffff #define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_WIDTH 32 #define UNIMAC_RDP_MACSEC_PROG_TX_CRC_MACSEC_PROG_TX_CRC_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD; #define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_MASK 0xfffffff8 #define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_WIDTH 29 #define UNIMAC_RDP_MACSEC_CNTRL_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD; #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_MASK 0x00000004 #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_WIDTH 1 #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_PROGRAM_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORRUPT_EN_FIELD; #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORRUPT_EN_FIELD_MASK 0x00000002 #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORRUPT_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_MACSEC_CNTRL_TX_CRC_CORRUPT_EN_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_MACSEC_CNTRL_TX_LANUCH_EN_FIELD; #define UNIMAC_RDP_MACSEC_CNTRL_TX_LANUCH_EN_FIELD_MASK 0x00000001 #define UNIMAC_RDP_MACSEC_CNTRL_TX_LANUCH_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_MACSEC_CNTRL_TX_LANUCH_EN_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TS_STATUS_CNTRL_RESERVED0_FIELD; #define UNIMAC_RDP_TS_STATUS_CNTRL_RESERVED0_FIELD_MASK 0xfffffff0 #define UNIMAC_RDP_TS_STATUS_CNTRL_RESERVED0_FIELD_WIDTH 28 #define UNIMAC_RDP_TS_STATUS_CNTRL_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_TS_STATUS_CNTRL_WORD_AVAIL_FIELD; #define UNIMAC_RDP_TS_STATUS_CNTRL_WORD_AVAIL_FIELD_MASK 0x0000000c #define UNIMAC_RDP_TS_STATUS_CNTRL_WORD_AVAIL_FIELD_WIDTH 2 #define UNIMAC_RDP_TS_STATUS_CNTRL_WORD_AVAIL_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_FIELD; #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_FIELD_MASK 0x00000002 #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_FIELD_WIDTH 1 #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_FIELD; #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_FIELD_MASK 0x00000001 #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_FIELD_WIDTH 1 #define UNIMAC_RDP_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD; #define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_MASK 0xffffffff #define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_WIDTH 32 #define UNIMAC_RDP_TX_TS_DATA_TX_TS_DATA_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_PAUSE_CNTRL_RESERVED0_FIELD; #define UNIMAC_RDP_PAUSE_CNTRL_RESERVED0_FIELD_MASK 0xfffc0000 #define UNIMAC_RDP_PAUSE_CNTRL_RESERVED0_FIELD_WIDTH 14 #define UNIMAC_RDP_PAUSE_CNTRL_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UNIMAC_RDP_PAUSE_CNTRL_PAUSE_CONTROL_EN_FIELD; #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_CONTROL_EN_FIELD_MASK 0x00020000 #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_CONTROL_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_CONTROL_EN_FIELD_SHIFT 17 extern const ru_field_rec UNIMAC_RDP_PAUSE_CNTRL_PAUSE_TIMER_FIELD; #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_TIMER_FIELD_MASK 0x0001ffff #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_TIMER_FIELD_WIDTH 17 #define UNIMAC_RDP_PAUSE_CNTRL_PAUSE_TIMER_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TXFIFO_FLUSH_RESERVED0_FIELD; #define UNIMAC_RDP_TXFIFO_FLUSH_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_RDP_TXFIFO_FLUSH_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_RDP_TXFIFO_FLUSH_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_TXFIFO_FLUSH_TX_FLUSH_FIELD; #define UNIMAC_RDP_TXFIFO_FLUSH_TX_FLUSH_FIELD_MASK 0x00000001 #define UNIMAC_RDP_TXFIFO_FLUSH_TX_FLUSH_FIELD_WIDTH 1 #define UNIMAC_RDP_TXFIFO_FLUSH_TX_FLUSH_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD; #define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_MASK 0xfffffffc #define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_WIDTH 30 #define UNIMAC_RDP_RXFIFO_STAT_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_RXFIFO_STAT_RXFIFO_STATUS_FIELD; #define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_STATUS_FIELD_MASK 0x00000003 #define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_STATUS_FIELD_WIDTH 2 #define UNIMAC_RDP_RXFIFO_STAT_RXFIFO_STATUS_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD; #define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_MASK 0xfffffffc #define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_WIDTH 30 #define UNIMAC_RDP_TXFIFO_STAT_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD; #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_MASK 0x00000002 #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_WIDTH 1 #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_OVERRUN_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD; #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_MASK 0x00000001 #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_WIDTH 1 #define UNIMAC_RDP_TXFIFO_STAT_TXFIFO_UNDERRUN_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_RESERVED0_FIELD; #define UNIMAC_RDP_PPP_CNTRL_RESERVED0_FIELD_MASK 0xffffffc0 #define UNIMAC_RDP_PPP_CNTRL_RESERVED0_FIELD_WIDTH 26 #define UNIMAC_RDP_PPP_CNTRL_RESERVED0_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_PFC_STATS_EN_FIELD; #define UNIMAC_RDP_PPP_CNTRL_PFC_STATS_EN_FIELD_MASK 0x00000020 #define UNIMAC_RDP_PPP_CNTRL_PFC_STATS_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_PFC_STATS_EN_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_RX_PASS_PFC_FRM_FIELD; #define UNIMAC_RDP_PPP_CNTRL_RX_PASS_PFC_FRM_FIELD_MASK 0x00000010 #define UNIMAC_RDP_PPP_CNTRL_RX_PASS_PFC_FRM_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_RX_PASS_PFC_FRM_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_RESERVED1_FIELD; #define UNIMAC_RDP_PPP_CNTRL_RESERVED1_FIELD_MASK 0x00000008 #define UNIMAC_RDP_PPP_CNTRL_RESERVED1_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_RESERVED1_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_FORCE_PPP_XON_FIELD; #define UNIMAC_RDP_PPP_CNTRL_FORCE_PPP_XON_FIELD_MASK 0x00000004 #define UNIMAC_RDP_PPP_CNTRL_FORCE_PPP_XON_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_FORCE_PPP_XON_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_PPP_EN_RX_FIELD; #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_RX_FIELD_MASK 0x00000002 #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_RX_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_RX_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_PPP_CNTRL_PPP_EN_TX_FIELD; #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_TX_FIELD_MASK 0x00000001 #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_TX_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_CNTRL_PPP_EN_TX_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_TIMER_FIELD; #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_TIMER_FIELD_MASK 0xffff0000 #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_TIMER_FIELD_WIDTH 16 #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_TIMER_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_PPP_REFRESH_CNTRL_RESERVED0_FIELD; #define UNIMAC_RDP_PPP_REFRESH_CNTRL_RESERVED0_FIELD_MASK 0x0000fffe #define UNIMAC_RDP_PPP_REFRESH_CNTRL_RESERVED0_FIELD_WIDTH 15 #define UNIMAC_RDP_PPP_REFRESH_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_EN_FIELD; #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_EN_FIELD_MASK 0x00000001 #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_EN_FIELD_WIDTH 1 #define UNIMAC_RDP_PPP_REFRESH_CNTRL_PPP_REFRESH_EN_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_PAUSE_PREL0_TX_PAUSE_PRB0_FIELD; #define UNIMAC_RDP_TX_PAUSE_PREL0_TX_PAUSE_PRB0_FIELD_MASK 0xffffffff #define UNIMAC_RDP_TX_PAUSE_PREL0_TX_PAUSE_PRB0_FIELD_WIDTH 32 #define UNIMAC_RDP_TX_PAUSE_PREL0_TX_PAUSE_PRB0_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_PAUSE_PREL1_TX_PAUSE_PRB1_FIELD; #define UNIMAC_RDP_TX_PAUSE_PREL1_TX_PAUSE_PRB1_FIELD_MASK 0xffffffff #define UNIMAC_RDP_TX_PAUSE_PREL1_TX_PAUSE_PRB1_FIELD_WIDTH 32 #define UNIMAC_RDP_TX_PAUSE_PREL1_TX_PAUSE_PRB1_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_PAUSE_PREL2_TX_PAUSE_PRB2_FIELD; #define UNIMAC_RDP_TX_PAUSE_PREL2_TX_PAUSE_PRB2_FIELD_MASK 0xffffffff #define UNIMAC_RDP_TX_PAUSE_PREL2_TX_PAUSE_PRB2_FIELD_WIDTH 32 #define UNIMAC_RDP_TX_PAUSE_PREL2_TX_PAUSE_PRB2_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_TX_PAUSE_PREL3_TX_PAUSE_PRB3_FIELD; #define UNIMAC_RDP_TX_PAUSE_PREL3_TX_PAUSE_PRB3_FIELD_MASK 0xffffffff #define UNIMAC_RDP_TX_PAUSE_PREL3_TX_PAUSE_PRB3_FIELD_WIDTH 32 #define UNIMAC_RDP_TX_PAUSE_PREL3_TX_PAUSE_PRB3_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_PREL0_RX_PAUSE_PRB0_FIELD; #define UNIMAC_RDP_RX_PAUSE_PREL0_RX_PAUSE_PRB0_FIELD_MASK 0xffffffff #define UNIMAC_RDP_RX_PAUSE_PREL0_RX_PAUSE_PRB0_FIELD_WIDTH 32 #define UNIMAC_RDP_RX_PAUSE_PREL0_RX_PAUSE_PRB0_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_PREL1_RX_PAUSE_PRB1_FIELD; #define UNIMAC_RDP_RX_PAUSE_PREL1_RX_PAUSE_PRB1_FIELD_MASK 0xffffffff #define UNIMAC_RDP_RX_PAUSE_PREL1_RX_PAUSE_PRB1_FIELD_WIDTH 32 #define UNIMAC_RDP_RX_PAUSE_PREL1_RX_PAUSE_PRB1_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_PREL2_RX_PAUSE_PRB2_FIELD; #define UNIMAC_RDP_RX_PAUSE_PREL2_RX_PAUSE_PRB2_FIELD_MASK 0xffffffff #define UNIMAC_RDP_RX_PAUSE_PREL2_RX_PAUSE_PRB2_FIELD_WIDTH 32 #define UNIMAC_RDP_RX_PAUSE_PREL2_RX_PAUSE_PRB2_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_PAUSE_PREL3_RX_PAUSE_PRB3_FIELD; #define UNIMAC_RDP_RX_PAUSE_PREL3_RX_PAUSE_PRB3_FIELD_MASK 0xffffffff #define UNIMAC_RDP_RX_PAUSE_PREL3_RX_PAUSE_PRB3_FIELD_WIDTH 32 #define UNIMAC_RDP_RX_PAUSE_PREL3_RX_PAUSE_PRB3_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RXERR_MASK_RESERVED0_FIELD; #define UNIMAC_RDP_RXERR_MASK_RESERVED0_FIELD_MASK 0xfffc0000 #define UNIMAC_RDP_RXERR_MASK_RESERVED0_FIELD_WIDTH 14 #define UNIMAC_RDP_RXERR_MASK_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UNIMAC_RDP_RXERR_MASK_MAC_RXERR_MASK_FIELD; #define UNIMAC_RDP_RXERR_MASK_MAC_RXERR_MASK_FIELD_MASK 0x0003ffff #define UNIMAC_RDP_RXERR_MASK_MAC_RXERR_MASK_FIELD_WIDTH 18 #define UNIMAC_RDP_RXERR_MASK_MAC_RXERR_MASK_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_RX_MAX_PKT_SIZE_RESERVED0_FIELD; #define UNIMAC_RDP_RX_MAX_PKT_SIZE_RESERVED0_FIELD_MASK 0xffffc000 #define UNIMAC_RDP_RX_MAX_PKT_SIZE_RESERVED0_FIELD_WIDTH 18 #define UNIMAC_RDP_RX_MAX_PKT_SIZE_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec UNIMAC_RDP_RX_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD; #define UNIMAC_RDP_RX_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_MASK 0x00003fff #define UNIMAC_RDP_RX_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_WIDTH 14 #define UNIMAC_RDP_RX_MAX_PKT_SIZE_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_RESERVED0_FIELD; #define UNIMAC_RDP_MDIO_CMD_RESERVED0_FIELD_MASK 0xc0000000 #define UNIMAC_RDP_MDIO_CMD_RESERVED0_FIELD_WIDTH 2 #define UNIMAC_RDP_MDIO_CMD_RESERVED0_FIELD_SHIFT 30 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_MDIO_BUSY_FIELD; #define UNIMAC_RDP_MDIO_CMD_MDIO_BUSY_FIELD_MASK 0x20000000 #define UNIMAC_RDP_MDIO_CMD_MDIO_BUSY_FIELD_WIDTH 1 #define UNIMAC_RDP_MDIO_CMD_MDIO_BUSY_FIELD_SHIFT 29 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_FAIL_FIELD; #define UNIMAC_RDP_MDIO_CMD_FAIL_FIELD_MASK 0x10000000 #define UNIMAC_RDP_MDIO_CMD_FAIL_FIELD_WIDTH 1 #define UNIMAC_RDP_MDIO_CMD_FAIL_FIELD_SHIFT 28 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_OP_CODE_FIELD; #define UNIMAC_RDP_MDIO_CMD_OP_CODE_FIELD_MASK 0x0c000000 #define UNIMAC_RDP_MDIO_CMD_OP_CODE_FIELD_WIDTH 2 #define UNIMAC_RDP_MDIO_CMD_OP_CODE_FIELD_SHIFT 26 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_PHY_PRT_ADDR_FIELD; #define UNIMAC_RDP_MDIO_CMD_PHY_PRT_ADDR_FIELD_MASK 0x03e00000 #define UNIMAC_RDP_MDIO_CMD_PHY_PRT_ADDR_FIELD_WIDTH 5 #define UNIMAC_RDP_MDIO_CMD_PHY_PRT_ADDR_FIELD_SHIFT 21 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_REG_DEC_ADDR_FIELD; #define UNIMAC_RDP_MDIO_CMD_REG_DEC_ADDR_FIELD_MASK 0x001f0000 #define UNIMAC_RDP_MDIO_CMD_REG_DEC_ADDR_FIELD_WIDTH 5 #define UNIMAC_RDP_MDIO_CMD_REG_DEC_ADDR_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_RDP_MDIO_CMD_DATA_ADDR_FIELD; #define UNIMAC_RDP_MDIO_CMD_DATA_ADDR_FIELD_MASK 0x0000ffff #define UNIMAC_RDP_MDIO_CMD_DATA_ADDR_FIELD_WIDTH 16 #define UNIMAC_RDP_MDIO_CMD_DATA_ADDR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MDIO_CFG_RESERVED0_FIELD; #define UNIMAC_RDP_MDIO_CFG_RESERVED0_FIELD_MASK 0xfffffc00 #define UNIMAC_RDP_MDIO_CFG_RESERVED0_FIELD_WIDTH 22 #define UNIMAC_RDP_MDIO_CFG_RESERVED0_FIELD_SHIFT 10 extern const ru_field_rec UNIMAC_RDP_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD; #define UNIMAC_RDP_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_MASK 0x000003f0 #define UNIMAC_RDP_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_WIDTH 6 #define UNIMAC_RDP_MDIO_CFG_MDIO_CLK_DIVIDER_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_RDP_MDIO_CFG_RESERVED1_FIELD; #define UNIMAC_RDP_MDIO_CFG_RESERVED1_FIELD_MASK 0x0000000e #define UNIMAC_RDP_MDIO_CFG_RESERVED1_FIELD_WIDTH 3 #define UNIMAC_RDP_MDIO_CFG_RESERVED1_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_RDP_MDIO_CFG_MDIO_CLAUSE_FIELD; #define UNIMAC_RDP_MDIO_CFG_MDIO_CLAUSE_FIELD_MASK 0x00000001 #define UNIMAC_RDP_MDIO_CFG_MDIO_CLAUSE_FIELD_WIDTH 1 #define UNIMAC_RDP_MDIO_CFG_MDIO_CLAUSE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_MDF_CNT_MDF_PACKET_COUNTER_FIELD; #define UNIMAC_RDP_MDF_CNT_MDF_PACKET_COUNTER_FIELD_MASK 0xffffffff #define UNIMAC_RDP_MDF_CNT_MDF_PACKET_COUNTER_FIELD_WIDTH 32 #define UNIMAC_RDP_MDF_CNT_MDF_PACKET_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_RDP_DIAG_SEL_RESERVED0_FIELD; #define UNIMAC_RDP_DIAG_SEL_RESERVED0_FIELD_MASK 0xffffc000 #define UNIMAC_RDP_DIAG_SEL_RESERVED0_FIELD_WIDTH 18 #define UNIMAC_RDP_DIAG_SEL_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec UNIMAC_RDP_DIAG_SEL_DIAG_HI_SELECT_FIELD; #define UNIMAC_RDP_DIAG_SEL_DIAG_HI_SELECT_FIELD_MASK 0x00003f00 #define UNIMAC_RDP_DIAG_SEL_DIAG_HI_SELECT_FIELD_WIDTH 6 #define UNIMAC_RDP_DIAG_SEL_DIAG_HI_SELECT_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_RDP_DIAG_SEL_RESERVED1_FIELD; #define UNIMAC_RDP_DIAG_SEL_RESERVED1_FIELD_MASK 0x000000c0 #define UNIMAC_RDP_DIAG_SEL_RESERVED1_FIELD_WIDTH 2 #define UNIMAC_RDP_DIAG_SEL_RESERVED1_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_RDP_DIAG_SEL_DIAG_LO_SELECT_FIELD; #define UNIMAC_RDP_DIAG_SEL_DIAG_LO_SELECT_FIELD_MASK 0x0000003f #define UNIMAC_RDP_DIAG_SEL_DIAG_LO_SELECT_FIELD_WIDTH 6 #define UNIMAC_RDP_DIAG_SEL_DIAG_LO_SELECT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR64_GR_FIELD; #define UNIMAC_MIB_GR64_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR64_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR64_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR127_GR_FIELD; #define UNIMAC_MIB_GR127_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR127_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR127_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR255_GR_FIELD; #define UNIMAC_MIB_GR255_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR255_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR255_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR511_GR_FIELD; #define UNIMAC_MIB_GR511_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR511_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR511_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR1023_GR_FIELD; #define UNIMAC_MIB_GR1023_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR1023_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR1023_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR1518_GR_FIELD; #define UNIMAC_MIB_GR1518_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR1518_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR1518_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRMGV_GR_FIELD; #define UNIMAC_MIB_GRMGV_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRMGV_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRMGV_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR2047_GR_FIELD; #define UNIMAC_MIB_GR2047_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR2047_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR2047_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR4095_GR_FIELD; #define UNIMAC_MIB_GR4095_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR4095_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR4095_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GR9216_GR_FIELD; #define UNIMAC_MIB_GR9216_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GR9216_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GR9216_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRPKT_GR_FIELD; #define UNIMAC_MIB_GRPKT_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRPKT_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRPKT_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRBYT_GR_FIELD; #define UNIMAC_MIB_GRBYT_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRBYT_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRBYT_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRMCA_GR_FIELD; #define UNIMAC_MIB_GRMCA_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRMCA_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRMCA_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRBCA_GR_FIELD; #define UNIMAC_MIB_GRBCA_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRBCA_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRBCA_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRFCS_GR_FIELD; #define UNIMAC_MIB_GRFCS_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRFCS_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRFCS_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRXCF_GR_FIELD; #define UNIMAC_MIB_GRXCF_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRXCF_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRXCF_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRXPF_GR_FIELD; #define UNIMAC_MIB_GRXPF_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRXPF_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRXPF_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRXUO_GR_FIELD; #define UNIMAC_MIB_GRXUO_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRXUO_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRXUO_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRALN_GR_FIELD; #define UNIMAC_MIB_GRALN_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRALN_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRALN_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRFLR_GR_FIELD; #define UNIMAC_MIB_GRFLR_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRFLR_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRFLR_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRCDE_GR_FIELD; #define UNIMAC_MIB_GRCDE_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRCDE_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRCDE_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRFCR_GR_FIELD; #define UNIMAC_MIB_GRFCR_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRFCR_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRFCR_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GROVR_GR_FIELD; #define UNIMAC_MIB_GROVR_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GROVR_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GROVR_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRJBR_GR_FIELD; #define UNIMAC_MIB_GRJBR_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRJBR_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRJBR_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRMTUE_GR_FIELD; #define UNIMAC_MIB_GRMTUE_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRMTUE_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRMTUE_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRPOK_GR_FIELD; #define UNIMAC_MIB_GRPOK_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRPOK_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRPOK_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRUC_GR_FIELD; #define UNIMAC_MIB_GRUC_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRUC_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRUC_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRPPP_GR_FIELD; #define UNIMAC_MIB_GRPPP_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRPPP_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRPPP_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GRCRC_GR_FIELD; #define UNIMAC_MIB_GRCRC_GR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GRCRC_GR_FIELD_WIDTH 32 #define UNIMAC_MIB_GRCRC_GR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR64_TR_FIELD; #define UNIMAC_MIB_TR64_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR64_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR64_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR127_TR_FIELD; #define UNIMAC_MIB_TR127_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR127_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR127_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR255_TR_FIELD; #define UNIMAC_MIB_TR255_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR255_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR255_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR511_TR_FIELD; #define UNIMAC_MIB_TR511_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR511_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR511_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR1023_TR_FIELD; #define UNIMAC_MIB_TR1023_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR1023_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR1023_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR1518_TR_FIELD; #define UNIMAC_MIB_TR1518_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR1518_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR1518_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TRMGV_TR_FIELD; #define UNIMAC_MIB_TRMGV_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TRMGV_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TRMGV_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR2047_TR_FIELD; #define UNIMAC_MIB_TR2047_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR2047_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR2047_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_RRPKT_RR_FIELD; #define UNIMAC_MIB_RRPKT_RR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_RRPKT_RR_FIELD_WIDTH 32 #define UNIMAC_MIB_RRPKT_RR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_RRUND_RR_FIELD; #define UNIMAC_MIB_RRUND_RR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_RRUND_RR_FIELD_WIDTH 32 #define UNIMAC_MIB_RRUND_RR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_RRFRG_RR_FIELD; #define UNIMAC_MIB_RRFRG_RR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_RRFRG_RR_FIELD_WIDTH 32 #define UNIMAC_MIB_RRFRG_RR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_RRBYT_RR_FIELD; #define UNIMAC_MIB_RRBYT_RR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_RRBYT_RR_FIELD_WIDTH 32 #define UNIMAC_MIB_RRBYT_RR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_MIB_CNTRL_RESERVED0_FIELD; #define UNIMAC_MIB_MIB_CNTRL_RESERVED0_FIELD_MASK 0xfffffff8 #define UNIMAC_MIB_MIB_CNTRL_RESERVED0_FIELD_WIDTH 29 #define UNIMAC_MIB_MIB_CNTRL_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_MIB_MIB_CNTRL_TX_CNT_RST_FIELD; #define UNIMAC_MIB_MIB_CNTRL_TX_CNT_RST_FIELD_MASK 0x00000004 #define UNIMAC_MIB_MIB_CNTRL_TX_CNT_RST_FIELD_WIDTH 1 #define UNIMAC_MIB_MIB_CNTRL_TX_CNT_RST_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_MIB_MIB_CNTRL_RUNT_CNT_RST_FIELD; #define UNIMAC_MIB_MIB_CNTRL_RUNT_CNT_RST_FIELD_MASK 0x00000002 #define UNIMAC_MIB_MIB_CNTRL_RUNT_CNT_RST_FIELD_WIDTH 1 #define UNIMAC_MIB_MIB_CNTRL_RUNT_CNT_RST_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MIB_MIB_CNTRL_RX_CNT_ST_FIELD; #define UNIMAC_MIB_MIB_CNTRL_RX_CNT_ST_FIELD_MASK 0x00000001 #define UNIMAC_MIB_MIB_CNTRL_RX_CNT_ST_FIELD_WIDTH 1 #define UNIMAC_MIB_MIB_CNTRL_RX_CNT_ST_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR4095_TR_FIELD; #define UNIMAC_MIB_TR4095_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR4095_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR4095_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_TR9216_TR_FIELD; #define UNIMAC_MIB_TR9216_TR_FIELD_MASK 0xffffffff #define UNIMAC_MIB_TR9216_TR_FIELD_WIDTH 32 #define UNIMAC_MIB_TR9216_TR_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTPKT_GT_FIELD; #define UNIMAC_MIB_GTPKT_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTPKT_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTPKT_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTMCA_GT_FIELD; #define UNIMAC_MIB_GTMCA_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTMCA_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTMCA_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTBCA_GT_FIELD; #define UNIMAC_MIB_GTBCA_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTBCA_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTBCA_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTXPF_GT_FIELD; #define UNIMAC_MIB_GTXPF_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTXPF_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTXPF_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTXCF_GT_FIELD; #define UNIMAC_MIB_GTXCF_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTXCF_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTXCF_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTFCS_GT_FIELD; #define UNIMAC_MIB_GTFCS_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTFCS_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTFCS_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTOVR_GT_FIELD; #define UNIMAC_MIB_GTOVR_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTOVR_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTOVR_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTDRF_GT_FIELD; #define UNIMAC_MIB_GTDRF_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTDRF_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTDRF_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTEDF_GT_FIELD; #define UNIMAC_MIB_GTEDF_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTEDF_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTEDF_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTSCL_GT_FIELD; #define UNIMAC_MIB_GTSCL_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTSCL_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTSCL_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTMCL_GT_FIELD; #define UNIMAC_MIB_GTMCL_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTMCL_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTMCL_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTLCL_GT_FIELD; #define UNIMAC_MIB_GTLCL_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTLCL_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTLCL_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTXCL_GT_FIELD; #define UNIMAC_MIB_GTXCL_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTXCL_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTXCL_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTFRG_GT_FIELD; #define UNIMAC_MIB_GTFRG_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTFRG_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTFRG_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTNCL_GT_FIELD; #define UNIMAC_MIB_GTNCL_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTNCL_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTNCL_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTJBR_GT_FIELD; #define UNIMAC_MIB_GTJBR_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTJBR_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTJBR_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTBYT_GT_FIELD; #define UNIMAC_MIB_GTBYT_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTBYT_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTBYT_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTPOK_GT_FIELD; #define UNIMAC_MIB_GTPOK_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTPOK_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTPOK_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MIB_GTUC_GT_FIELD; #define UNIMAC_MIB_GTUC_GT_FIELD_MASK 0xffffffff #define UNIMAC_MIB_GTUC_GT_FIELD_WIDTH 32 #define UNIMAC_MIB_GTUC_GT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_DIRECT_GMII_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_DIRECT_GMII_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_DIRECT_GMII_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_DIRECT_GMII_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_GPORT_MODE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_GPORT_MODE_FIELD_MASK 0x00000002 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_GPORT_MODE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_GPORT_MODE_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_SS_MODE_MII_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_SS_MODE_MII_FIELD_MASK 0x00000004 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_SS_MODE_MII_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_SS_MODE_MII_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_TXCRCER_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_TXCRCER_FIELD_MASK 0x00000008 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_TXCRCER_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_TXCRCER_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_MASK 0x00000010 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_FWD_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_MASK 0x00000020 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_MAC_CRC_OWRT_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_EXT_TX_FLOW_CONTROL_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_EXT_TX_FLOW_CONTROL_FIELD_MASK 0x00000040 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_EXT_TX_FLOW_CONTROL_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_EXT_TX_FLOW_CONTROL_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_LAUNCH_ENABLE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_LAUNCH_ENABLE_FIELD_MASK 0x00000080 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_LAUNCH_ENABLE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_LAUNCH_ENABLE_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_PSE_EN_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_PSE_EN_FIELD_MASK 0x0000ff00 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_PSE_EN_FIELD_WIDTH 8 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_PSE_EN_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_GEN_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_GEN_FIELD_MASK 0x00010000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_GEN_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_PP_GEN_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_MASK 0xfffe0000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_WIDTH 15 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_RESERVED0_FIELD_SHIFT 17 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_MASK 0x00003fff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_WIDTH 14 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_MAX_PKT_SIZE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_MASK 0x0000c000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_WIDTH 2 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED0_FIELD_SHIFT 14 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_MASK 0x01ff0000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_WIDTH 9 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RXFIFO_CONGESTION_THRESHOLD_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_MASK 0xfe000000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_WIDTH 7 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_MASK 0x000001ff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_WIDTH 9 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RXFIFO_PAUSE_THRESHOLD_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_MASK 0x0000fe00 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_WIDTH 7 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_MASK 0x00010000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_INT_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_MASK 0x00020000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_BACKPRESSURE_ENABLE_EXT_FIELD_SHIFT 17 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_MASK 0x00040000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_FIFO_OVERRUN_CTL_EN_FIELD_SHIFT 18 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_MASK 0x00080000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REMOTE_LOOPBACK_EN_FIELD_SHIFT 19 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_MASK 0xfff00000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_WIDTH 12 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_RESERVED1_FIELD_SHIFT 20 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_GPORT_STAT_UPDATE_MASK_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_GPORT_STAT_UPDATE_MASK_FIELD_MASK 0x0003ffff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_GPORT_STAT_UPDATE_MASK_FIELD_WIDTH 18 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_GPORT_STAT_UPDATE_MASK_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_RESERVED0_FIELD_MASK 0xfffc0000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_RESERVED0_FIELD_WIDTH 14 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_AUTO_CONFIG_EN_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_AUTO_CONFIG_EN_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_AUTO_CONFIG_EN_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_AUTO_CONFIG_EN_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_DUPLEX_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_DUPLEX_FIELD_MASK 0x00000002 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_DUPLEX_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_DUPLEX_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_SPEED_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_SPEED_FIELD_MASK 0x0000000c #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_SPEED_FIELD_WIDTH 2 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_ETH_SPEED_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_FIFO_DAT_AVL_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_FIFO_DAT_AVL_FIELD_MASK 0x00000010 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_FIFO_DAT_AVL_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_FIFO_DAT_AVL_FIELD_SHIFT 4 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_IN_PAUSE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_IN_PAUSE_FIELD_MASK 0x00000020 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_IN_PAUSE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_IN_PAUSE_FIELD_SHIFT 5 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_TX_EMPTY_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_TX_EMPTY_FIELD_MASK 0x00000040 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_TX_EMPTY_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_TX_EMPTY_FIELD_SHIFT 6 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LAUNCH_ACK_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LAUNCH_ACK_FIELD_MASK 0x00000080 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LAUNCH_ACK_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LAUNCH_ACK_FIELD_SHIFT 7 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_MASK 0x00000100 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_TX_DETECT_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_MASK 0x00000200 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_LPI_RX_DETECT_FIELD_SHIFT 9 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_OUT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_OUT_FIELD_MASK 0x00000400 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_OUT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_OUT_FIELD_SHIFT 10 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_DELETE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_DELETE_FIELD_MASK 0x00000800 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_DELETE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RX_SOP_DELETE_FIELD_SHIFT 11 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_STATS_UPDATE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_STATS_UPDATE_FIELD_MASK 0x00001000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_STATS_UPDATE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_MAC_STATS_UPDATE_FIELD_SHIFT 12 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_MASK 0x0000e000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_WIDTH 3 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED0_FIELD_SHIFT 13 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_MASK 0x00ff0000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_WIDTH 8 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_FIELD_SHIFT 16 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_MASK 0x01000000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_PP_STATS_VALID_FIELD_SHIFT 24 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED1_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED1_FIELD_MASK 0xfe000000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED1_FIELD_WIDTH 7 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_RESERVED1_FIELD_SHIFT 25 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_MASK 0x000000ff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_WIDTH 8 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_DEBUG_SEL_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_MASK 0xffffff00 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_WIDTH 24 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_UNIMAC_RST_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_GPORT_RSV_MASK_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_GPORT_RSV_MASK_FIELD_MASK 0x0003ffff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_GPORT_RSV_MASK_FIELD_WIDTH 18 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_GPORT_RSV_MASK_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_RESERVED0_FIELD_MASK 0xfffc0000 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_RESERVED0_FIELD_WIDTH 14 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_RESERVED0_FIELD_SHIFT 18 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_MASK 0xffffffff #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_WIDTH 32 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_OVERRUN_COUNTER_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_TSI_SIGN_EXT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_MASK 0x00000002 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_OSTS_TIMER_DIS_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_MASK 0x00000004 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_EGR_1588_TS_MODE_FIELD_SHIFT 2 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_MASK 0xfffffff8 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_WIDTH 29 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_GEN_INT_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_VALUE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_VALUE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_MASK 0x00000001 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_WIDTH 1 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_VALUE_FIELD_SHIFT 0 extern const ru_field_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_MASK 0xfffffffe #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_WIDTH 31 #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD; #define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_MASK 0xffffffff #define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_WIDTH 32 #define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_FIELD_SHIFT 0 extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD; #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_MASK 0x000000ff #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_WIDTH 8 #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD; #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_MASK 0xffffff00 #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_WIDTH 24 #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD; #define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_MASK 0xffffffff #define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_WIDTH 32 #define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_MASK 0xffffffff #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_WIDTH 32 #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_FIELD_SHIFT 0 extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_MASK 0xffffffff #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_WIDTH 32 #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_FIELD_SHIFT 0 extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_MASK 0xffffffff #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_WIDTH 32 #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_FIELD_SHIFT 0 extern const ru_field_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_MASK 0xffffffff #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_WIDTH 32 #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_MASK 0x0000000f #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_WIDTH 4 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_MASK 0xfffffff0 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_WIDTH 28 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_MASK 0x00000001 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_WIDTH 1 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_MASK 0xfffffffe #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_WIDTH 31 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_MASK 0x00000001 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_WIDTH 1 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_MASK 0x000007fe #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_WIDTH 10 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_SHIFT 1 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_MASK 0xfffff800 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_WIDTH 21 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_MASK 0x00000001 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_WIDTH 1 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_MASK 0xfffffffe #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_WIDTH 31 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_MASK 0x00000001 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_WIDTH 1 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_MASK 0xfffffffe #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_WIDTH 31 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_MASK 0x00000001 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_WIDTH 1 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_MASK 0x0000000e #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_WIDTH 3 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_MASK 0x00003ff0 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_WIDTH 10 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_FIELD_SHIFT 4 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_MASK 0xffffc000 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_WIDTH 18 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_RESERVED1_FIELD_SHIFT 14 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_MASK 0xffffffff #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_WIDTH 32 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_MASK 0xffffffff #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_WIDTH 32 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD; #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_MASK 0x00000003 #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_WIDTH 2 #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_SELECT_MODULE_FIELD_SHIFT 0 extern const ru_field_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD; #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_MASK 0xfffffffc #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_WIDTH 30 #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD; #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_MASK 0x00000001 #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_WIDTH 1 #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD; #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_WIDTH 31 #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD; #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_MASK 0x0fffffff #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_WIDTH 28 #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD; #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_MASK 0xf0000000 #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_WIDTH 4 #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD; #define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_MASK 0xffffffff #define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_WIDTH 32 #define HASH_GENERAL_CONFIGURATION_PAD_LOW_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD; #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_MASK 0x0000000f #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_WIDTH 4 #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD; #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_MASK 0xfffffff0 #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_WIDTH 28 #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD; #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_MASK 0x00000001 #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_WIDTH 1 #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_FRST_MUL_HIT_FIELD_SHIFT 0 extern const ru_field_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD; #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_WIDTH 31 #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_PM_COUNTERS_HITS_CNT_FIELD; #define HASH_PM_COUNTERS_HITS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_HITS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_HITS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_SRCHS_CNT_FIELD; #define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_SRCHS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_MISS_CNT_FIELD; #define HASH_PM_COUNTERS_MISS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_MISS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_MISS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD; #define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD; #define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD; #define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD; #define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_MASK 0xffffffff #define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_WIDTH 32 #define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD; #define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_MASK 0x00000001 #define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_WIDTH 1 #define HASH_PM_COUNTERS_FRZ_CNT_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD; #define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_WIDTH 31 #define HASH_PM_COUNTERS_FRZ_CNT_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_MASK 0x000007ff #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_WIDTH 11 #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_FIELD_SHIFT 0 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_MASK 0x0000f800 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_WIDTH 5 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_MASK 0x00070000 #define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_WIDTH 3 #define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_FIELD_SHIFT 16 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_MASK 0x00080000 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED1_FIELD_SHIFT 19 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_MASK 0x00f00000 #define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_WIDTH 4 #define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_FIELD_SHIFT 20 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_MASK 0x01000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_FIELD_SHIFT 24 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_MASK 0x02000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_FIELD_SHIFT 25 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_MASK 0x04000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_FIELD_SHIFT 26 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_MASK 0x08000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED2_FIELD_SHIFT 27 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_MASK 0x30000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_WIDTH 2 #define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_FIELD_SHIFT 28 extern const ru_field_rec HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD; #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_MASK 0xc0000000 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_WIDTH 2 #define HASH_LKUP_TBL_CFG_TBL_CFG_RESERVED3_FIELD_SHIFT 30 extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD; #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_MASK 0x0fffffff #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_WIDTH 28 #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_FIELD_SHIFT 0 extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD; #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_MASK 0xf0000000 #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_WIDTH 4 #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD; #define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_MASK 0xffffffff #define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_WIDTH 32 #define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_FIELD_SHIFT 0 extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_MASK 0x00000fff #define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_WIDTH 12 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_MASK 0x01fff000 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_WIDTH 13 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_FIELD_SHIFT 12 extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_MASK 0x0e000000 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_WIDTH 3 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED0_FIELD_SHIFT 25 extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_MASK 0x70000000 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_WIDTH 3 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_FIELD_SHIFT 28 extern const ru_field_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_MASK 0x80000000 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_WIDTH 1 #define HASH_LKUP_TBL_CFG_CNTXT_CFG_RESERVED1_FIELD_SHIFT 31 extern const ru_field_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD; #define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_MASK 0x00000fff #define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_WIDTH 12 #define HASH_CAM_CONFIGURATION_CNTXT_CFG_BASE_ADDRESS_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD; #define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_MASK 0xfffff000 #define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_WIDTH 20 #define HASH_CAM_CONFIGURATION_CNTXT_CFG_RESERVED0_FIELD_SHIFT 12 extern const ru_field_rec HASH_CAM_INDIRECT_OP_CMD_FIELD; #define HASH_CAM_INDIRECT_OP_CMD_FIELD_MASK 0x0000000f #define HASH_CAM_INDIRECT_OP_CMD_FIELD_WIDTH 4 #define HASH_CAM_INDIRECT_OP_CMD_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_OP_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_MASK 0xfffffff0 #define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_WIDTH 28 #define HASH_CAM_INDIRECT_OP_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD; #define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_MASK 0x00000001 #define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_WIDTH 1 #define HASH_CAM_INDIRECT_OP_DONE_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_INDIRECT_OP_DONE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD; #define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_MASK 0x00000001 #define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_WIDTH 1 #define HASH_CAM_INDIRECT_ADDR_KEY1_IND_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD; #define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_MASK 0x0000007e #define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_WIDTH 6 #define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_MASK 0xffffff80 #define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_WIDTH 25 #define HASH_CAM_INDIRECT_ADDR_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD; #define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_MASK 0x00000001 #define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_WIDTH 1 #define HASH_CAM_INDIRECT_VLID_IN_VALID_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_INDIRECT_VLID_IN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD; #define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_MASK 0x00000001 #define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_WIDTH 1 #define HASH_CAM_INDIRECT_VLID_OUT_VALID_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_INDIRECT_VLID_OUT_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_MATCH_FIELD; #define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_MASK 0x00000001 #define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_WIDTH 1 #define HASH_CAM_INDIRECT_RSLT_MATCH_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD; #define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_MASK 0x0000000e #define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_WIDTH 3 #define HASH_CAM_INDIRECT_RSLT_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_INDEX_FIELD; #define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_MASK 0x000003f0 #define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_WIDTH 6 #define HASH_CAM_INDIRECT_RSLT_INDEX_FIELD_SHIFT 4 extern const ru_field_rec HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD; #define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_MASK 0xfffffc00 #define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_WIDTH 22 #define HASH_CAM_INDIRECT_RSLT_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD; #define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_MASK 0xffffffff #define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_WIDTH 32 #define HASH_CAM_INDIRECT_KEY_IN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD; #define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_MASK 0xffffffff #define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_WIDTH 32 #define HASH_CAM_INDIRECT_KEY_OUT_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD; #define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_MASK 0xffffffff #define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_WIDTH 32 #define HASH_CAM_BIST_BIST_STATUS_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD; #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_MASK 0x00000001 #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_WIDTH 1 #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD; #define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_MASK 0xffffffff #define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_WIDTH 32 #define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD; #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_MASK 0x000000ff #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_WIDTH 8 #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_MASK 0xffffff00 #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_WIDTH 24 #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD; #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_MASK 0x00000001 #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_WIDTH 1 #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_BIST_BIST_EN_VALUE_FIELD; #define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_MASK 0x000000ff #define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_WIDTH 8 #define HASH_CAM_BIST_BIST_EN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_MASK 0xffffff00 #define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_WIDTH 24 #define HASH_CAM_BIST_BIST_EN_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec HASH_CAM_BIST_BIST_MODE_VALUE_FIELD; #define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_MASK 0x00000003 #define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_WIDTH 2 #define HASH_CAM_BIST_BIST_MODE_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_MASK 0xfffffffc #define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_WIDTH 30 #define HASH_CAM_BIST_BIST_MODE_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD; #define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_MASK 0x00000001 #define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_WIDTH 1 #define HASH_CAM_BIST_BIST_RST_L_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_BIST_BIST_RST_L_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD; #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_MASK 0x000000ff #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_WIDTH 8 #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_MASK 0xffffff00 #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_WIDTH 24 #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec HASH_CAM_BIST_DBG_EN_VALUE_FIELD; #define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_MASK 0x000000ff #define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_WIDTH 8 #define HASH_CAM_BIST_DBG_EN_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD; #define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_MASK 0xffffff00 #define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_WIDTH 24 #define HASH_CAM_BIST_DBG_EN_RESERVED0_FIELD_SHIFT 8 extern const ru_field_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD; #define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_MASK 0x00000007 #define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_WIDTH 3 #define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_MASK 0xfffffff8 #define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_WIDTH 29 #define HASH_CAM_BIST_BIST_CASCADE_SELECT_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD; #define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_MASK 0x0000000f #define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_WIDTH 4 #define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_MASK 0xfffffff0 #define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_WIDTH 28 #define HASH_CAM_BIST_BIST_BLOCK_SELECT_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD; #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_MASK 0x00000001 #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_WIDTH 1 #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_FIELD_SHIFT 0 extern const ru_field_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD; #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_MASK 0xfffffffe #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_WIDTH 31 #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD; #define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_MASK 0x00000001 #define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_INVLD_CMD_FIELD_SHIFT 0 extern const ru_field_rec HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD; #define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_MASK 0x00000002 #define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_MULT_MATCH_FIELD_SHIFT 1 extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD; #define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_MASK 0x00000004 #define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_FIELD_SHIFT 2 extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD; #define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_MASK 0x00000008 #define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_FIELD_SHIFT 3 extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD; #define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_MASK 0x00000010 #define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_FIELD_SHIFT 4 extern const ru_field_rec HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD; #define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_MASK 0x00000020 #define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_FIELD_SHIFT 5 extern const ru_field_rec HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD; #define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_MASK 0x00000040 #define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_WIDTH 1 #define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_FIELD_SHIFT 6 extern const ru_field_rec HASH_INTR_CTRL_ISR_RESERVED0_FIELD; #define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_MASK 0xffffff80 #define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_WIDTH 25 #define HASH_INTR_CTRL_ISR_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec HASH_INTR_CTRL_ISM_ISM_FIELD; #define HASH_INTR_CTRL_ISM_ISM_FIELD_MASK 0xffffffff #define HASH_INTR_CTRL_ISM_ISM_FIELD_WIDTH 32 #define HASH_INTR_CTRL_ISM_ISM_FIELD_SHIFT 0 extern const ru_field_rec HASH_INTR_CTRL_IER_IEM_FIELD; #define HASH_INTR_CTRL_IER_IEM_FIELD_MASK 0xffffffff #define HASH_INTR_CTRL_IER_IEM_FIELD_WIDTH 32 #define HASH_INTR_CTRL_IER_IEM_FIELD_SHIFT 0 extern const ru_field_rec HASH_INTR_CTRL_ITR_IST_FIELD; #define HASH_INTR_CTRL_ITR_IST_FIELD_MASK 0xffffffff #define HASH_INTR_CTRL_ITR_IST_FIELD_WIDTH 32 #define HASH_INTR_CTRL_ITR_IST_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG0_VAL_FIELD; #define HASH_DEBUG_DBG0_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG0_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG0_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG1_VAL_FIELD; #define HASH_DEBUG_DBG1_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG1_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG1_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG2_VAL_FIELD; #define HASH_DEBUG_DBG2_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG2_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG2_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG3_VAL_FIELD; #define HASH_DEBUG_DBG3_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG3_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG3_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG4_VAL_FIELD; #define HASH_DEBUG_DBG4_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG4_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG4_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG5_VAL_FIELD; #define HASH_DEBUG_DBG5_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG5_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG5_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG6_VAL_FIELD; #define HASH_DEBUG_DBG6_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG6_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG6_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG7_VAL_FIELD; #define HASH_DEBUG_DBG7_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG7_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG7_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG8_VAL_FIELD; #define HASH_DEBUG_DBG8_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG8_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG8_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG9_VAL_FIELD; #define HASH_DEBUG_DBG9_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG9_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG9_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG10_VAL_FIELD; #define HASH_DEBUG_DBG10_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG10_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG10_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG11_VAL_FIELD; #define HASH_DEBUG_DBG11_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG11_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG11_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG12_VAL_FIELD; #define HASH_DEBUG_DBG12_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG12_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG12_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG13_VAL_FIELD; #define HASH_DEBUG_DBG13_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG13_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG13_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG14_VAL_FIELD; #define HASH_DEBUG_DBG14_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG14_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG14_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG15_VAL_FIELD; #define HASH_DEBUG_DBG15_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG15_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG15_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG16_VAL_FIELD; #define HASH_DEBUG_DBG16_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG16_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG16_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG17_VAL_FIELD; #define HASH_DEBUG_DBG17_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG17_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG17_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG18_VAL_FIELD; #define HASH_DEBUG_DBG18_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG18_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG18_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG19_VAL_FIELD; #define HASH_DEBUG_DBG19_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG19_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG19_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG20_VAL_FIELD; #define HASH_DEBUG_DBG20_VAL_FIELD_MASK 0xffffffff #define HASH_DEBUG_DBG20_VAL_FIELD_WIDTH 32 #define HASH_DEBUG_DBG20_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG_SEL_VAL_FIELD; #define HASH_DEBUG_DBG_SEL_VAL_FIELD_MASK 0x0000001f #define HASH_DEBUG_DBG_SEL_VAL_FIELD_WIDTH 5 #define HASH_DEBUG_DBG_SEL_VAL_FIELD_SHIFT 0 extern const ru_field_rec HASH_DEBUG_DBG_SEL_RESERVED0_FIELD; #define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_MASK 0xffffffe0 #define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_WIDTH 27 #define HASH_DEBUG_DBG_SEL_RESERVED0_FIELD_SHIFT 5 extern const ru_field_rec HASH_AGING_RAM_AGING_DATA_FIELD; #define HASH_AGING_RAM_AGING_DATA_FIELD_MASK 0xffffffff #define HASH_AGING_RAM_AGING_DATA_FIELD_WIDTH 32 #define HASH_AGING_RAM_AGING_DATA_FIELD_SHIFT 0 extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD; #define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_MASK 0x00ffffff #define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_WIDTH 24 #define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_FIELD_SHIFT 0 extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD; #define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_MASK 0xff000000 #define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_WIDTH 8 #define HASH_CONTEXT_RAM_CONTEXT_47_24_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD; #define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_MASK 0x00ffffff #define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_WIDTH 24 #define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_FIELD_SHIFT 0 extern const ru_field_rec HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD; #define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_MASK 0xff000000 #define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_WIDTH 8 #define HASH_CONTEXT_RAM_CONTEXT_23_0_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD; #define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_MASK 0xffffffff #define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_WIDTH 32 #define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_FIELD_SHIFT 0 extern const ru_field_rec HASH_RAM_ENG_LOW_SKP_FIELD; #define HASH_RAM_ENG_LOW_SKP_FIELD_MASK 0x00000001 #define HASH_RAM_ENG_LOW_SKP_FIELD_WIDTH 1 #define HASH_RAM_ENG_LOW_SKP_FIELD_SHIFT 0 extern const ru_field_rec HASH_RAM_ENG_LOW_CFG_FIELD; #define HASH_RAM_ENG_LOW_CFG_FIELD_MASK 0x0000000e #define HASH_RAM_ENG_LOW_CFG_FIELD_WIDTH 3 #define HASH_RAM_ENG_LOW_CFG_FIELD_SHIFT 1 extern const ru_field_rec HASH_RAM_ENG_LOW_KEY_11_0_FIELD; #define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_MASK 0x0000fff0 #define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_WIDTH 12 #define HASH_RAM_ENG_LOW_KEY_11_0_FIELD_SHIFT 4 extern const ru_field_rec HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD; #define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_MASK 0xffff0000 #define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_WIDTH 16 #define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_FIELD_SHIFT 16 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_MASK 0x0000000f #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_WIDTH 4 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_THR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_MASK 0xfffffff0 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_WIDTH 28 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_RESERVED0_FIELD_SHIFT 4 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_MASK 0x00000001 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_EN_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_MASK 0x0000000e #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_WIDTH 3 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_MASK 0x000003f0 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_WIDTH 6 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ID_FIELD_SHIFT 4 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_MASK 0x0000fc00 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_WIDTH 6 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED1_FIELD_SHIFT 10 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_MASK 0x03ff0000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_WIDTH 10 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_ADDR_FIELD_SHIFT 16 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_MASK 0xfc000000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_WIDTH 6 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_RESERVED2_FIELD_SHIFT 26 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_MASK 0x00000001 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_MASK 0x000000fe #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_WIDTH 7 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED0_FIELD_SHIFT 1 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_MASK 0x0000ff00 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_WIDTH 8 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_TIMER_VAL_FIELD_SHIFT 8 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_MASK 0x00010000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_FIELD_SHIFT 16 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_MASK 0x000e0000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_WIDTH 3 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED1_FIELD_SHIFT 17 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_MASK 0x00700000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_WIDTH 3 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_FIELD_SHIFT 20 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_MASK 0x00800000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_RESERVED2_FIELD_SHIFT 23 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_MASK 0xff000000 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_WIDTH 8 #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_FIELD_SHIFT 24 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_MASK 0x7fffffff #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_WIDTH 31 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_MASK 0x80000000 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_FIELD_SHIFT 31 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_MASK 0x7fffffff #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_WIDTH 31 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_MASK 0x80000000 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_FIELD_SHIFT 31 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_MASK 0x7fffffff #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_WIDTH 31 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_MASK 0x80000000 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_FIELD_SHIFT 31 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_MASK 0x7fffffff #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_WIDTH 31 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_MASK 0x80000000 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_FIELD_SHIFT 31 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_MASK 0x7fffffff #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_WIDTH 31 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_MASK 0x80000000 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_FIELD_SHIFT 31 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_MASK 0xffffffff #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_WIDTH 32 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_MASK 0x00000001 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_SHIFT 0 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_MASK 0x00000002 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_WIDTH 1 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_FIELD_SHIFT 1 extern const ru_field_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_MASK 0xfffffffc #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_WIDTH 30 #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec CNPL_MEMORY_DATA_DATA_FIELD; #define CNPL_MEMORY_DATA_DATA_FIELD_MASK 0xffffffff #define CNPL_MEMORY_DATA_DATA_FIELD_WIDTH 32 #define CNPL_MEMORY_DATA_DATA_FIELD_SHIFT 0 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_MASK 0x000007ff #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_WIDTH 11 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_BA_FIELD_SHIFT 0 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_MASK 0x00001800 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_WIDTH 2 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CN0_BYTS_FIELD_SHIFT 11 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_MASK 0x00002000 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_WIDTH 1 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_DOUBLLE_FIELD_SHIFT 13 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_MASK 0x00004000 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_WIDTH 1 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_WRAP_FIELD_SHIFT 14 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_MASK 0x00008000 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_WIDTH 1 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_CLR_FIELD_SHIFT 15 extern const ru_field_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_MASK 0xffff0000 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_WIDTH 16 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_MASK 0x000007ff #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_WIDTH 11 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_BK_BA_FIELD_SHIFT 0 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_MASK 0x003ff800 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_WIDTH 11 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_PA_BA_FIELD_SHIFT 11 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_MASK 0x00400000 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_WIDTH 1 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_DOUBLLE_FIELD_SHIFT 22 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_RESERVED0_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_RESERVED0_FIELD_MASK 0xff800000 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_RESERVED0_FIELD_WIDTH 9 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_RESERVED0_FIELD_SHIFT 23 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_MASK 0x000000ff #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_WIDTH 8 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_ST_FIELD_SHIFT 0 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_MASK 0x0000ff00 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_WIDTH 8 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_PL_END_FIELD_SHIFT 8 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_MASK 0xffff0000 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_WIDTH 16 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_MASK 0xffffffff #define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_WIDTH 32 #define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_VEC_FIELD_SHIFT 0 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_N_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_N_FIELD_MASK 0x000000ff #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_N_FIELD_WIDTH 8 #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_N_FIELD_SHIFT 0 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_MASK 0x00000100 #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_WIDTH 1 #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_EN_FIELD_SHIFT 8 extern const ru_field_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD; #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_MASK 0xfffffe00 #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_WIDTH 23 #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_RESERVED0_FIELD_SHIFT 9 extern const ru_field_rec CNPL_MISC_ARB_PRM_SW_PRIO_FIELD; #define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_MASK 0x00000003 #define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_WIDTH 2 #define CNPL_MISC_ARB_PRM_SW_PRIO_FIELD_SHIFT 0 extern const ru_field_rec CNPL_MISC_ARB_PRM_RESERVED0_FIELD; #define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_MASK 0xfffffffc #define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_WIDTH 30 #define CNPL_MISC_ARB_PRM_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec CNPL_SW_IF_SW_CMD_VAL_FIELD; #define CNPL_SW_IF_SW_CMD_VAL_FIELD_MASK 0xffffffff #define CNPL_SW_IF_SW_CMD_VAL_FIELD_WIDTH 32 #define CNPL_SW_IF_SW_CMD_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD; #define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_MASK 0x00000001 #define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_WIDTH 1 #define CNPL_SW_IF_SW_STAT_CN_RD_ST_FIELD_SHIFT 0 extern const ru_field_rec CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD; #define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_MASK 0x00000002 #define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_WIDTH 1 #define CNPL_SW_IF_SW_STAT_PL_PLC_ST_FIELD_SHIFT 1 extern const ru_field_rec CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD; #define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_MASK 0x00000004 #define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_WIDTH 1 #define CNPL_SW_IF_SW_STAT_PL_RD_ST_FIELD_SHIFT 2 extern const ru_field_rec CNPL_SW_IF_SW_STAT_RESERVED0_FIELD; #define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_MASK 0xfffffff8 #define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_WIDTH 29 #define CNPL_SW_IF_SW_STAT_RESERVED0_FIELD_SHIFT 3 extern const ru_field_rec CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD; #define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_MASK 0x3fffffff #define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_WIDTH 30 #define CNPL_SW_IF_SW_PL_RSLT_RESERVED0_FIELD_SHIFT 0 extern const ru_field_rec CNPL_SW_IF_SW_PL_RSLT_COL_FIELD; #define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_MASK 0xc0000000 #define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_WIDTH 2 #define CNPL_SW_IF_SW_PL_RSLT_COL_FIELD_SHIFT 30 extern const ru_field_rec CNPL_SW_IF_SW_PL_RD_RD_FIELD; #define CNPL_SW_IF_SW_PL_RD_RD_FIELD_MASK 0xffffffff #define CNPL_SW_IF_SW_PL_RD_RD_FIELD_WIDTH 32 #define CNPL_SW_IF_SW_PL_RD_RD_FIELD_SHIFT 0 extern const ru_field_rec CNPL_SW_IF_SW_CNT_RD_RD_FIELD; #define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_MASK 0xffffffff #define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_WIDTH 32 #define CNPL_SW_IF_SW_CNT_RD_RD_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD; #define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_ENG_CMDS_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD; #define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_CMD_WAIT_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD; #define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_TOT_CYC_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD; #define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_GNT_CYC_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD; #define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_ARB_CYC_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD; #define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_MASK 0xffffffff #define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_WIDTH 32 #define CNPL_PM_COUNTERS_PL_UP_ERR_VAL_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD; #define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_MASK 0x00000001 #define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_WIDTH 1 #define CNPL_PM_COUNTERS_GEN_CFG_RD_CLR_FIELD_SHIFT 0 extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD; #define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_MASK 0x00000002 #define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_WIDTH 1 #define CNPL_PM_COUNTERS_GEN_CFG_WRAP_FIELD_SHIFT 1 extern const ru_field_rec CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD; #define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_MASK 0xfffffffc #define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_WIDTH 30 #define CNPL_PM_COUNTERS_GEN_CFG_RESERVED0_FIELD_SHIFT 2 extern const ru_field_rec CNPL_DEBUG_DBGSEL_VS_FIELD; #define CNPL_DEBUG_DBGSEL_VS_FIELD_MASK 0x0000007f #define CNPL_DEBUG_DBGSEL_VS_FIELD_WIDTH 7 #define CNPL_DEBUG_DBGSEL_VS_FIELD_SHIFT 0 extern const ru_field_rec CNPL_DEBUG_DBGSEL_RESERVED0_FIELD; #define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_MASK 0xffffff80 #define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_WIDTH 25 #define CNPL_DEBUG_DBGSEL_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec CNPL_DEBUG_DBGBUS_VB_FIELD; #define CNPL_DEBUG_DBGBUS_VB_FIELD_MASK 0x001fffff #define CNPL_DEBUG_DBGBUS_VB_FIELD_WIDTH 21 #define CNPL_DEBUG_DBGBUS_VB_FIELD_SHIFT 0 extern const ru_field_rec CNPL_DEBUG_DBGBUS_RESERVED0_FIELD; #define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_MASK 0xffe00000 #define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_WIDTH 11 #define CNPL_DEBUG_DBGBUS_RESERVED0_FIELD_SHIFT 21 extern const ru_field_rec CNPL_DEBUG_REQ_VEC_REQ_FIELD; #define CNPL_DEBUG_REQ_VEC_REQ_FIELD_MASK 0x0000007f #define CNPL_DEBUG_REQ_VEC_REQ_FIELD_WIDTH 7 #define CNPL_DEBUG_REQ_VEC_REQ_FIELD_SHIFT 0 extern const ru_field_rec CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD; #define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_MASK 0xffffff80 #define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_WIDTH 25 #define CNPL_DEBUG_REQ_VEC_RESERVED0_FIELD_SHIFT 7 extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD; #define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_MASK 0x000000ff #define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_WIDTH 8 #define CNPL_DEBUG_POL_UP_ST_ITR_NUM_FIELD_SHIFT 0 extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD; #define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_MASK 0x0000ff00 #define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_WIDTH 8 #define CNPL_DEBUG_POL_UP_ST_POL_NUM_FIELD_SHIFT 8 extern const ru_field_rec CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD; #define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_MASK 0xffff0000 #define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_WIDTH 16 #define CNPL_DEBUG_POL_UP_ST_RESERVED0_FIELD_SHIFT 16 extern const ru_field_rec NATC_CONTROL_STATUS_DDR_ENABLE_FIELD; #define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_MASK 0x80000000 #define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DDR_ENABLE_FIELD_SHIFT 31 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD; #define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_MASK 0x40000000 #define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_FIELD_SHIFT 30 extern const ru_field_rec NATC_CONTROL_STATUS_UNUSED4_FIELD; #define NATC_CONTROL_STATUS_UNUSED4_FIELD_MASK 0x30000000 #define NATC_CONTROL_STATUS_UNUSED4_FIELD_WIDTH 2 #define NATC_CONTROL_STATUS_UNUSED4_FIELD_SHIFT 28 extern const ru_field_rec NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_MASK 0x08000000 #define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_FIELD_SHIFT 27 extern const ru_field_rec NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK 0x04000000 #define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 26 extern const ru_field_rec NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK 0x02000000 #define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 25 extern const ru_field_rec NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD; #define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_MASK 0x01000000 #define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_FIELD_SHIFT 24 extern const ru_field_rec NATC_CONTROL_STATUS_UNUSED3_FIELD; #define NATC_CONTROL_STATUS_UNUSED3_FIELD_MASK 0x00800000 #define NATC_CONTROL_STATUS_UNUSED3_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_UNUSED3_FIELD_SHIFT 23 extern const ru_field_rec NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK 0x00400000 #define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 22 extern const ru_field_rec NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK 0x00200000 #define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 21 extern const ru_field_rec NATC_CONTROL_STATUS_UNUSED7_FIELD; #define NATC_CONTROL_STATUS_UNUSED7_FIELD_MASK 0x001f0000 #define NATC_CONTROL_STATUS_UNUSED7_FIELD_WIDTH 5 #define NATC_CONTROL_STATUS_UNUSED7_FIELD_SHIFT 16 extern const ru_field_rec NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD; #define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_MASK 0x00008000 #define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_FIELD_SHIFT 15 extern const ru_field_rec NATC_CONTROL_STATUS_DDR_OUTSTANDING_REQUEST_FIFO_SIZE_FIELD; #define NATC_CONTROL_STATUS_DDR_OUTSTANDING_REQUEST_FIFO_SIZE_FIELD_MASK 0x00004000 #define NATC_CONTROL_STATUS_DDR_OUTSTANDING_REQUEST_FIFO_SIZE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DDR_OUTSTANDING_REQUEST_FIFO_SIZE_FIELD_SHIFT 14 extern const ru_field_rec NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD; #define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_MASK 0x00003000 #define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_WIDTH 2 #define NATC_CONTROL_STATUS_NAT_HASH_MODE_FIELD_SHIFT 12 extern const ru_field_rec NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD; #define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_MASK 0x00000f00 #define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_WIDTH 4 #define NATC_CONTROL_STATUS_MULTI_HASH_LIMIT_FIELD_SHIFT 8 extern const ru_field_rec NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD; #define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_MASK 0x00000080 #define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_FIELD_SHIFT 7 extern const ru_field_rec NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD; #define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_MASK 0x00000060 #define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_WIDTH 2 #define NATC_CONTROL_STATUS_NAT_ARB_ST_FIELD_SHIFT 5 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD; #define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_MASK 0x00000010 #define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_FIELD_SHIFT 4 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD; #define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_MASK 0x00000008 #define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_FIELD_SHIFT 3 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_SMEM_DISABLE_FIELD; #define NATC_CONTROL_STATUS_NATC_SMEM_DISABLE_FIELD_MASK 0x00000004 #define NATC_CONTROL_STATUS_NATC_SMEM_DISABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_SMEM_DISABLE_FIELD_SHIFT 2 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_ENABLE_FIELD; #define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_MASK 0x00000002 #define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_ENABLE_FIELD_SHIFT 1 extern const ru_field_rec NATC_CONTROL_STATUS_NATC_RESET_FIELD; #define NATC_CONTROL_STATUS_NATC_RESET_FIELD_MASK 0x00000001 #define NATC_CONTROL_STATUS_NATC_RESET_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS_NATC_RESET_FIELD_SHIFT 0 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD; #define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_MASK 0x80000000 #define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_HASH_SWAP_FIELD_SHIFT 31 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD; #define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_MASK 0x60000000 #define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_WIDTH 2 #define NATC_CONTROL_STATUS2_DDR_HASH_MODE_FIELD_SHIFT 29 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_MASK 0x10000000 #define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_FIELD_SHIFT 28 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK 0x08000000 #define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 27 extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD; #define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_MASK 0x04000000 #define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_FIELD_SHIFT 26 extern const ru_field_rec NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD; #define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_MASK 0x02000000 #define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_AGE_TIMER_TICK_FIELD_SHIFT 25 extern const ru_field_rec NATC_CONTROL_STATUS2_AGE_TIMER_FIELD; #define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_MASK 0x01f00000 #define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_WIDTH 5 #define NATC_CONTROL_STATUS2_AGE_TIMER_FIELD_SHIFT 20 extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD; #define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_MASK 0x000f0000 #define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_WIDTH 4 #define NATC_CONTROL_STATUS2_CACHE_ALGO_FIELD_SHIFT 16 extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED1_FIELD; #define NATC_CONTROL_STATUS2_UNUSED1_FIELD_MASK 0x0000ff00 #define NATC_CONTROL_STATUS2_UNUSED1_FIELD_WIDTH 8 #define NATC_CONTROL_STATUS2_UNUSED1_FIELD_SHIFT 8 extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED0_FIELD; #define NATC_CONTROL_STATUS2_UNUSED0_FIELD_MASK 0x000000c0 #define NATC_CONTROL_STATUS2_UNUSED0_FIELD_WIDTH 2 #define NATC_CONTROL_STATUS2_UNUSED0_FIELD_SHIFT 6 extern const ru_field_rec NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD; #define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_MASK 0x00000020 #define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_FIELD_SHIFT 5 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD; #define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_MASK 0x00000010 #define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_FIELD_SHIFT 4 extern const ru_field_rec NATC_CONTROL_STATUS2_UNUSED2_FIELD; #define NATC_CONTROL_STATUS2_UNUSED2_FIELD_MASK 0x00000008 #define NATC_CONTROL_STATUS2_UNUSED2_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_UNUSED2_FIELD_SHIFT 3 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD; #define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_MASK 0x00000004 #define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_FIELD_SHIFT 2 extern const ru_field_rec NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD; #define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_MASK 0x00000002 #define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_FIELD_SHIFT 1 extern const ru_field_rec NATC_CONTROL_STATUS2_EVICTION_DISABLE_FIELD; #define NATC_CONTROL_STATUS2_EVICTION_DISABLE_FIELD_MASK 0x00000001 #define NATC_CONTROL_STATUS2_EVICTION_DISABLE_FIELD_WIDTH 1 #define NATC_CONTROL_STATUS2_EVICTION_DISABLE_FIELD_SHIFT 0 extern const ru_field_rec NATC_TABLE_CONTROL_RESERVED0_FIELD; #define NATC_TABLE_CONTROL_RESERVED0_FIELD_MASK 0xff000000 #define NATC_TABLE_CONTROL_RESERVED0_FIELD_WIDTH 8 #define NATC_TABLE_CONTROL_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_MASK 0x00800000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_FIELD_SHIFT 23 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_MASK 0x00400000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_FIELD_SHIFT 22 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_MASK 0x00200000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_FIELD_SHIFT 21 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_MASK 0x00100000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_FIELD_SHIFT 20 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_MASK 0x00080000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_FIELD_SHIFT 19 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_MASK 0x00040000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_FIELD_SHIFT 18 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_MASK 0x00020000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_FIELD_SHIFT 17 extern const ru_field_rec NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD; #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_MASK 0x00010000 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_FIELD_SHIFT 16 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_MASK 0x00008000 #define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL7_FIELD_SHIFT 15 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_MASK 0x00004000 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL7_FIELD_SHIFT 14 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_MASK 0x00002000 #define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL6_FIELD_SHIFT 13 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_MASK 0x00001000 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL6_FIELD_SHIFT 12 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_MASK 0x00000800 #define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL5_FIELD_SHIFT 11 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_MASK 0x00000400 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL5_FIELD_SHIFT 10 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_MASK 0x00000200 #define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL4_FIELD_SHIFT 9 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_MASK 0x00000100 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL4_FIELD_SHIFT 8 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_MASK 0x00000080 #define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL3_FIELD_SHIFT 7 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_MASK 0x00000040 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL3_FIELD_SHIFT 6 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_MASK 0x00000020 #define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL2_FIELD_SHIFT 5 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_MASK 0x00000010 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL2_FIELD_SHIFT 4 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_MASK 0x00000008 #define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL1_FIELD_SHIFT 3 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_MASK 0x00000004 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL1_FIELD_SHIFT 2 extern const ru_field_rec NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD; #define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_MASK 0x00000002 #define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_KEY_LEN_TBL0_FIELD_SHIFT 1 extern const ru_field_rec NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD; #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_MASK 0x00000001 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_WIDTH 1 #define NATC_TABLE_CONTROL_NON_CACHEABLE_TBL0_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD; #define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_MASK 0xf0000000 #define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_WIDTH 4 #define NATC_ENG_COMMAND_STATUS_RESERVED0_FIELD_SHIFT 28 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD; #define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_MASK 0x0ff00000 #define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_WIDTH 8 #define NATC_ENG_COMMAND_STATUS_DEL_CMD_DDR_BIN_FIELD_SHIFT 20 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_RESERVED1_FIELD; #define NATC_ENG_COMMAND_STATUS_RESERVED1_FIELD_MASK 0x000c0000 #define NATC_ENG_COMMAND_STATUS_RESERVED1_FIELD_WIDTH 2 #define NATC_ENG_COMMAND_STATUS_RESERVED1_FIELD_SHIFT 18 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD; #define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_MASK 0x00020000 #define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_DEL_CMD_MODE_FIELD_SHIFT 17 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD; #define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_MASK 0x00010000 #define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_CACHE_FLUSH_FIELD_SHIFT 16 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD; #define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_MASK 0x00008000 #define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_DECR_COUNT_FIELD_SHIFT 15 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD; #define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_MASK 0x00007000 #define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_WIDTH 3 #define NATC_ENG_COMMAND_STATUS_NAT_TBL_FIELD_SHIFT 12 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD; #define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_MASK 0x00000f00 #define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_WIDTH 4 #define NATC_ENG_COMMAND_STATUS_MULTIHASH_COUNT_FIELD_SHIFT 8 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD; #define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_MASK 0x00000080 #define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_CACHE_HIT_FIELD_SHIFT 7 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_MISS_FIELD; #define NATC_ENG_COMMAND_STATUS_MISS_FIELD_MASK 0x00000040 #define NATC_ENG_COMMAND_STATUS_MISS_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_MISS_FIELD_SHIFT 6 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_ERROR_FIELD; #define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_MASK 0x00000020 #define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_ERROR_FIELD_SHIFT 5 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_BUSY_FIELD; #define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_MASK 0x00000010 #define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_BUSY_FIELD_SHIFT 4 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD; #define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_MASK 0x00000008 #define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_WIDTH 1 #define NATC_ENG_COMMAND_STATUS_UNUSED0_FIELD_SHIFT 3 extern const ru_field_rec NATC_ENG_COMMAND_STATUS_COMMAND_FIELD; #define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_MASK 0x00000007 #define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_WIDTH 3 #define NATC_ENG_COMMAND_STATUS_COMMAND_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_HASH_HASH_FIELD; #define NATC_ENG_HASH_HASH_FIELD_MASK 0xffffffff #define NATC_ENG_HASH_HASH_FIELD_WIDTH 32 #define NATC_ENG_HASH_HASH_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD; #define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_MASK 0xffffffff #define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_WIDTH 32 #define NATC_ENG_HIT_COUNT_HIT_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD; #define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_MASK 0xffffffff #define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_WIDTH 32 #define NATC_ENG_BYTE_COUNT_BYTE_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_PKT_LEN_UNUSED_FIELD; #define NATC_ENG_PKT_LEN_UNUSED_FIELD_MASK 0xffff0000 #define NATC_ENG_PKT_LEN_UNUSED_FIELD_WIDTH 16 #define NATC_ENG_PKT_LEN_UNUSED_FIELD_SHIFT 16 extern const ru_field_rec NATC_ENG_PKT_LEN_PKT_LEN_FIELD; #define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_MASK 0x0000ffff #define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_WIDTH 16 #define NATC_ENG_PKT_LEN_PKT_LEN_FIELD_SHIFT 0 extern const ru_field_rec NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD; #define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_MASK 0xffffffff #define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_WIDTH 32 #define NATC_ENG_KEY_RESULT_NAT_KEY_RESULT_FIELD_SHIFT 0 extern const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_MASK 0xfffffff8 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH 29 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT 3 extern const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK 0x00000007 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH 3 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT 0 extern const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK 0xffffff00 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH 24 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT 8 extern const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_MASK 0x000000ff #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH 8 #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT 0 extern const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_MASK 0xfffffff8 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH 29 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT 3 extern const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK 0x00000007 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH 3 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT 0 extern const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK 0xffffff00 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH 24 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT 8 extern const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_MASK 0x000000ff #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH 8 #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT 0 extern const ru_field_rec NATC_CTRS_TBL_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD; #define NATC_CTRS_TBL_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_MASK 0xffffffff #define NATC_CTRS_TBL_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_WIDTH 32 #define NATC_CTRS_TBL_CACHE_HIT_COUNT_CACHE_HIT_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_CTRS_TBL_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD; #define NATC_CTRS_TBL_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_MASK 0xffffffff #define NATC_CTRS_TBL_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_WIDTH 32 #define NATC_CTRS_TBL_CACHE_MISS_COUNT_CACHE_MISS_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_CTRS_TBL_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD; #define NATC_CTRS_TBL_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_MASK 0xffffffff #define NATC_CTRS_TBL_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_WIDTH 32 #define NATC_CTRS_TBL_DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_CTRS_TBL_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD; #define NATC_CTRS_TBL_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_MASK 0xffffffff #define NATC_CTRS_TBL_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_WIDTH 32 #define NATC_CTRS_TBL_DDR_EVICT_COUNT_DDR_EVICT_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_CTRS_TBL_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD; #define NATC_CTRS_TBL_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_MASK 0xffffffff #define NATC_CTRS_TBL_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_WIDTH 32 #define NATC_CTRS_TBL_DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_FIELD_SHIFT 0 extern const ru_field_rec NATC_KEY_MASK_TBL_KEY_MASK_KEY_MASK_FIELD; #define NATC_KEY_MASK_TBL_KEY_MASK_KEY_MASK_FIELD_MASK 0xffffffff #define NATC_KEY_MASK_TBL_KEY_MASK_KEY_MASK_FIELD_WIDTH 32 #define NATC_KEY_MASK_TBL_KEY_MASK_KEY_MASK_FIELD_SHIFT 0 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_RESERVED0_FIELD; #define NATC_DDR_CFG__DDR_SIZE_RESERVED0_FIELD_MASK 0xff000000 #define NATC_DDR_CFG__DDR_SIZE_RESERVED0_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_SIZE_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL7_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL7_FIELD_MASK 0x00e00000 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL7_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL7_FIELD_SHIFT 21 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL6_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL6_FIELD_MASK 0x001c0000 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL6_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL6_FIELD_SHIFT 18 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL5_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL5_FIELD_MASK 0x00038000 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL5_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL5_FIELD_SHIFT 15 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL4_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL4_FIELD_MASK 0x00007000 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL4_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL4_FIELD_SHIFT 12 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL3_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL3_FIELD_MASK 0x00000e00 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL3_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL3_FIELD_SHIFT 9 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL2_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL2_FIELD_MASK 0x000001c0 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL2_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL2_FIELD_SHIFT 6 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL1_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL1_FIELD_MASK 0x00000038 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL1_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL1_FIELD_SHIFT 3 extern const ru_field_rec NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL0_FIELD; #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL0_FIELD_MASK 0x00000007 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL0_FIELD_WIDTH 3 #define NATC_DDR_CFG__DDR_SIZE_DDR_SIZE_TBL0_FIELD_SHIFT 0 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_MASK 0xff000000 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_FIELD_SHIFT 24 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_MASK 0x00ff0000 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_FIELD_SHIFT 16 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_MASK 0x0000ff00 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_FIELD_SHIFT 8 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_MASK 0x000000ff #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_FIELD_SHIFT 0 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_MASK 0xff000000 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_FIELD_SHIFT 24 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_MASK 0x00ff0000 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_FIELD_SHIFT 16 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_MASK 0x0000ff00 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_FIELD_SHIFT 8 extern const ru_field_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_MASK 0x000000ff #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_WIDTH 8 #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_FIELD_SHIFT 0 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_RESERVED0_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_RESERVED0_FIELD_MASK 0xff000000 #define NATC_DDR_CFG__TOTAL_LEN_RESERVED0_FIELD_WIDTH 8 #define NATC_DDR_CFG__TOTAL_LEN_RESERVED0_FIELD_SHIFT 24 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL7_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_MASK 0x00e00000 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL7_FIELD_SHIFT 21 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL6_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_MASK 0x001c0000 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL6_FIELD_SHIFT 18 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL5_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_MASK 0x00038000 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL5_FIELD_SHIFT 15 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL4_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_MASK 0x00007000 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL4_FIELD_SHIFT 12 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL3_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_MASK 0x00000e00 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL3_FIELD_SHIFT 9 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL2_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_MASK 0x000001c0 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL2_FIELD_SHIFT 6 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL1_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_MASK 0x00000038 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL1_FIELD_SHIFT 3 extern const ru_field_rec NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL0_FIELD; #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_MASK 0x00000007 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_WIDTH 3 #define NATC_DDR_CFG__TOTAL_LEN_TOTAL_LEN_TBL0_FIELD_SHIFT 0 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_RESERVED0_FIELD; #define NATC_DDR_CFG__SM_STATUS_RESERVED0_FIELD_MASK 0xffc00000 #define NATC_DDR_CFG__SM_STATUS_RESERVED0_FIELD_WIDTH 10 #define NATC_DDR_CFG__SM_STATUS_RESERVED0_FIELD_SHIFT 22 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_DEBUG_SEL_FIELD; #define NATC_DDR_CFG__SM_STATUS_DEBUG_SEL_FIELD_MASK 0x00300000 #define NATC_DDR_CFG__SM_STATUS_DEBUG_SEL_FIELD_WIDTH 2 #define NATC_DDR_CFG__SM_STATUS_DEBUG_SEL_FIELD_SHIFT 20 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_APB_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_APB_STATE_FIELD_MASK 0x000c0000 #define NATC_DDR_CFG__SM_STATUS_APB_STATE_FIELD_WIDTH 2 #define NATC_DDR_CFG__SM_STATUS_APB_STATE_FIELD_SHIFT 18 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_DDR_REQ_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_DDR_REQ_STATE_FIELD_MASK 0x00030000 #define NATC_DDR_CFG__SM_STATUS_DDR_REQ_STATE_FIELD_WIDTH 2 #define NATC_DDR_CFG__SM_STATUS_DDR_REQ_STATE_FIELD_SHIFT 16 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_DDR_REP_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_DDR_REP_STATE_FIELD_MASK 0x0000e000 #define NATC_DDR_CFG__SM_STATUS_DDR_REP_STATE_FIELD_WIDTH 3 #define NATC_DDR_CFG__SM_STATUS_DDR_REP_STATE_FIELD_SHIFT 13 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_RUNNER_CMD_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_RUNNER_CMD_STATE_FIELD_MASK 0x00001000 #define NATC_DDR_CFG__SM_STATUS_RUNNER_CMD_STATE_FIELD_WIDTH 1 #define NATC_DDR_CFG__SM_STATUS_RUNNER_CMD_STATE_FIELD_SHIFT 12 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_WB_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_WB_STATE_FIELD_MASK 0x00000800 #define NATC_DDR_CFG__SM_STATUS_WB_STATE_FIELD_WIDTH 1 #define NATC_DDR_CFG__SM_STATUS_WB_STATE_FIELD_SHIFT 11 extern const ru_field_rec NATC_DDR_CFG__SM_STATUS_NAT_STATE_FIELD; #define NATC_DDR_CFG__SM_STATUS_NAT_STATE_FIELD_MASK 0x000007ff #define NATC_DDR_CFG__SM_STATUS_NAT_STATE_FIELD_WIDTH 11 #define NATC_DDR_CFG__SM_STATUS_NAT_STATE_FIELD_SHIFT 0 extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD; #define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_MASK 0xfffff800 #define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_WIDTH 21 #define NATC_INDIR_C_INDIR_ADDR_REG_RESERVED0_FIELD_SHIFT 11 extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD; #define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_MASK 0x00000400 #define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_WIDTH 1 #define NATC_INDIR_C_INDIR_ADDR_REG_W_R_FIELD_SHIFT 10 extern const ru_field_rec NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD; #define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_MASK 0x000003ff #define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_WIDTH 10 #define NATC_INDIR_C_INDIR_ADDR_REG_NATC_ENTRY_FIELD_SHIFT 0 extern const ru_field_rec NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD; #define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_MASK 0xffffffff #define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_WIDTH 32 #define NATC_INDIR_C_INDIR_DATA_REG_DATA_FIELD_SHIFT 0 /****************************************************************************** * XRDP_ Registers ******************************************************************************/ extern const ru_reg_rec QM_GLOBAL_CFG_QM_ENABLE_CTRL_REG; #define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec QM_GLOBAL_CFG_QM_SW_RST_CTRL_REG; #define QM_GLOBAL_CFG_QM_SW_RST_CTRL_REG_OFFSET 0x00000004 extern const ru_reg_rec QM_GLOBAL_CFG_QM_GENERAL_CTRL_REG; #define QM_GLOBAL_CFG_QM_GENERAL_CTRL_REG_OFFSET 0x00000008 extern const ru_reg_rec QM_GLOBAL_CFG_FPM_CONTROL_REG; #define QM_GLOBAL_CFG_FPM_CONTROL_REG_OFFSET 0x0000000c extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_REG; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_REG_OFFSET 0x00000010 extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_REG; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LOWER_THR_REG_OFFSET 0x00000014 extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_REG; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_REG_OFFSET 0x00000018 extern const ru_reg_rec QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_REG; #define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_REG_OFFSET 0x0000001c extern const ru_reg_rec QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_REG; #define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_REG_OFFSET 0x00000020 extern const ru_reg_rec QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_REG; #define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_REG_OFFSET 0x00000024 extern const ru_reg_rec QM_GLOBAL_CFG_ABS_DROP_QUEUE_REG; #define QM_GLOBAL_CFG_ABS_DROP_QUEUE_REG_OFFSET 0x00000028 extern const ru_reg_rec QM_GLOBAL_CFG_AGGREGATION_CTRL_REG; #define QM_GLOBAL_CFG_AGGREGATION_CTRL_REG_OFFSET 0x0000002c extern const ru_reg_rec QM_GLOBAL_CFG_FPM_BASE_ADDR_REG; #define QM_GLOBAL_CFG_FPM_BASE_ADDR_REG_OFFSET 0x00000030 extern const ru_reg_rec QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_REG; #define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_REG_OFFSET 0x00000034 extern const ru_reg_rec QM_GLOBAL_CFG_DDR_SOP_OFFSET_REG; #define QM_GLOBAL_CFG_DDR_SOP_OFFSET_REG_OFFSET 0x00000038 extern const ru_reg_rec QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_REG; #define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_REG_OFFSET 0x0000003c extern const ru_reg_rec QM_GLOBAL_CFG_DQM_FULL_REG; #define QM_GLOBAL_CFG_DQM_FULL_REG_OFFSET 0x00000040 #define QM_GLOBAL_CFG_DQM_FULL_REG_RAM_CNT 0x00000008 extern const ru_reg_rec QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG; #define QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG_OFFSET 0x00000070 #define QM_GLOBAL_CFG_DQM_NOT_EMPTY_REG_RAM_CNT 0x00000008 extern const ru_reg_rec QM_GLOBAL_CFG_DQM_POP_READY_REG; #define QM_GLOBAL_CFG_DQM_POP_READY_REG_OFFSET 0x000000a0 #define QM_GLOBAL_CFG_DQM_POP_READY_REG_RAM_CNT 0x00000008 extern const ru_reg_rec QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG; #define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG_OFFSET 0x000000d0 #define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_REG_RAM_CNT 0x00000008 extern const ru_reg_rec QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_REG; #define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_REG_OFFSET 0x00000100 extern const ru_reg_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_REG; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_REG_OFFSET 0x00000104 #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GRP_RES_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_REG; #define QM_GLOBAL_CFG_QM_FPM_BUFFER_GBL_THR_REG_OFFSET 0x0000010c extern const ru_reg_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_REG; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_RNR_CFG_REG_OFFSET 0x00000110 extern const ru_reg_rec QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_REG; #define QM_GLOBAL_CFG_QM_FLOW_CTRL_INTR_REG_OFFSET 0x00000114 extern const ru_reg_rec QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_REG; #define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_REG_OFFSET 0x00000118 extern const ru_reg_rec QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_REG; #define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_REG_OFFSET 0x0000011c extern const ru_reg_rec QM_FPM_POOLS_THR_REG; #define QM_FPM_POOLS_THR_REG_OFFSET 0x00000200 #define QM_FPM_POOLS_THR_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_0_REG; #define QM_FPM_POOLS_R_0_REG_OFFSET 0x00000204 #define QM_FPM_POOLS_R_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_1_REG; #define QM_FPM_POOLS_R_1_REG_OFFSET 0x00000208 #define QM_FPM_POOLS_R_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_2_REG; #define QM_FPM_POOLS_R_2_REG_OFFSET 0x0000020c #define QM_FPM_POOLS_R_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_3_REG; #define QM_FPM_POOLS_R_3_REG_OFFSET 0x00000210 #define QM_FPM_POOLS_R_3_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_4_REG; #define QM_FPM_POOLS_R_4_REG_OFFSET 0x00000214 #define QM_FPM_POOLS_R_4_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_5_REG; #define QM_FPM_POOLS_R_5_REG_OFFSET 0x00000218 #define QM_FPM_POOLS_R_5_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOLS_R_6_REG; #define QM_FPM_POOLS_R_6_REG_OFFSET 0x0000021c #define QM_FPM_POOLS_R_6_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_LOWER_THR_REG; #define QM_FPM_USR_GRP_LOWER_THR_REG_OFFSET 0x00000280 #define QM_FPM_USR_GRP_LOWER_THR_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_MID_THR_REG; #define QM_FPM_USR_GRP_MID_THR_REG_OFFSET 0x00000284 #define QM_FPM_USR_GRP_MID_THR_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_HIGHER_THR_REG; #define QM_FPM_USR_GRP_HIGHER_THR_REG_OFFSET 0x00000288 #define QM_FPM_USR_GRP_HIGHER_THR_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_CNT_REG; #define QM_FPM_USR_GRP_CNT_REG_OFFSET 0x0000028c #define QM_FPM_USR_GRP_CNT_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_R_0_REG; #define QM_FPM_USR_GRP_R_0_REG_OFFSET 0x00000290 #define QM_FPM_USR_GRP_R_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_R_1_REG; #define QM_FPM_USR_GRP_R_1_REG_OFFSET 0x00000294 #define QM_FPM_USR_GRP_R_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_R_2_REG; #define QM_FPM_USR_GRP_R_2_REG_OFFSET 0x00000298 #define QM_FPM_USR_GRP_R_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_USR_GRP_R_3_REG; #define QM_FPM_USR_GRP_R_3_REG_OFFSET 0x0000029c #define QM_FPM_USR_GRP_R_3_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_RUNNER_GRP_RNR_CONFIG_REG; #define QM_RUNNER_GRP_RNR_CONFIG_REG_OFFSET 0x00000300 #define QM_RUNNER_GRP_RNR_CONFIG_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_QUEUE_CONFIG_REG; #define QM_RUNNER_GRP_QUEUE_CONFIG_REG_OFFSET 0x00000304 #define QM_RUNNER_GRP_QUEUE_CONFIG_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_PDFIFO_CONFIG_REG; #define QM_RUNNER_GRP_PDFIFO_CONFIG_REG_OFFSET 0x00000308 #define QM_RUNNER_GRP_PDFIFO_CONFIG_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG; #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG_OFFSET 0x0000030c #define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_R_0_REG; #define QM_RUNNER_GRP_R_0_REG_OFFSET 0x00000310 #define QM_RUNNER_GRP_R_0_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_R_1_REG; #define QM_RUNNER_GRP_R_1_REG_OFFSET 0x00000314 #define QM_RUNNER_GRP_R_1_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_R_2_REG; #define QM_RUNNER_GRP_R_2_REG_OFFSET 0x00000318 #define QM_RUNNER_GRP_R_2_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RUNNER_GRP_R_3_REG; #define QM_RUNNER_GRP_R_3_REG_OFFSET 0x0000031c #define QM_RUNNER_GRP_R_3_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_INTR_CTRL_ISR_REG; #define QM_INTR_CTRL_ISR_REG_OFFSET 0x00000400 extern const ru_reg_rec QM_INTR_CTRL_ISM_REG; #define QM_INTR_CTRL_ISM_REG_OFFSET 0x00000404 extern const ru_reg_rec QM_INTR_CTRL_IER_REG; #define QM_INTR_CTRL_IER_REG_OFFSET 0x00000408 extern const ru_reg_rec QM_INTR_CTRL_ITR_REG; #define QM_INTR_CTRL_ITR_REG_OFFSET 0x0000040c extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG_OFFSET 0x00000600 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R2_0_REG; #define QM_CPU_INDR_PORT_R2_0_REG_OFFSET 0x00000604 #define QM_CPU_INDR_PORT_R2_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R2_1_REG; #define QM_CPU_INDR_PORT_R2_1_REG_OFFSET 0x00000608 #define QM_CPU_INDR_PORT_R2_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R2_2_REG; #define QM_CPU_INDR_PORT_R2_2_REG_OFFSET 0x0000060c #define QM_CPU_INDR_PORT_R2_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG_OFFSET 0x00000610 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG_OFFSET 0x00000614 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG_OFFSET 0x00000618 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG_OFFSET 0x0000061c #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG_OFFSET 0x00000620 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG_OFFSET 0x00000624 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG_OFFSET 0x00000628 #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG; #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG_OFFSET 0x0000062c #define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R_0_REG; #define QM_CPU_INDR_PORT_R_0_REG_OFFSET 0x00000630 #define QM_CPU_INDR_PORT_R_0_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R_1_REG; #define QM_CPU_INDR_PORT_R_1_REG_OFFSET 0x00000634 #define QM_CPU_INDR_PORT_R_1_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R_2_REG; #define QM_CPU_INDR_PORT_R_2_REG_OFFSET 0x00000638 #define QM_CPU_INDR_PORT_R_2_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_CPU_INDR_PORT_R_3_REG; #define QM_CPU_INDR_PORT_R_3_REG_OFFSET 0x0000063c #define QM_CPU_INDR_PORT_R_3_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_QUEUE_CONTEXT_CONTEXT_REG; #define QM_QUEUE_CONTEXT_CONTEXT_REG_OFFSET 0x00000800 #define QM_QUEUE_CONTEXT_CONTEXT_REG_RAM_CNT 0x0000009f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MIN_THR_0_REG; #define QM_WRED_PROFILE_COLOR_MIN_THR_0_REG_OFFSET 0x00001000 #define QM_WRED_PROFILE_COLOR_MIN_THR_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MIN_THR_1_REG; #define QM_WRED_PROFILE_COLOR_MIN_THR_1_REG_OFFSET 0x00001004 #define QM_WRED_PROFILE_COLOR_MIN_THR_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R0_0_REG; #define QM_WRED_PROFILE_R0_0_REG_OFFSET 0x00001008 #define QM_WRED_PROFILE_R0_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R0_1_REG; #define QM_WRED_PROFILE_R0_1_REG_OFFSET 0x0000100c #define QM_WRED_PROFILE_R0_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MAX_THR_0_REG; #define QM_WRED_PROFILE_COLOR_MAX_THR_0_REG_OFFSET 0x00001010 #define QM_WRED_PROFILE_COLOR_MAX_THR_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_MAX_THR_1_REG; #define QM_WRED_PROFILE_COLOR_MAX_THR_1_REG_OFFSET 0x00001014 #define QM_WRED_PROFILE_COLOR_MAX_THR_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R1_0_REG; #define QM_WRED_PROFILE_R1_0_REG_OFFSET 0x00001018 #define QM_WRED_PROFILE_R1_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R1_1_REG; #define QM_WRED_PROFILE_R1_1_REG_OFFSET 0x0000101c #define QM_WRED_PROFILE_R1_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_SLOPE_0_REG; #define QM_WRED_PROFILE_COLOR_SLOPE_0_REG_OFFSET 0x00001020 #define QM_WRED_PROFILE_COLOR_SLOPE_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_COLOR_SLOPE_1_REG; #define QM_WRED_PROFILE_COLOR_SLOPE_1_REG_OFFSET 0x00001024 #define QM_WRED_PROFILE_COLOR_SLOPE_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R2_0_REG; #define QM_WRED_PROFILE_R2_0_REG_OFFSET 0x00001028 #define QM_WRED_PROFILE_R2_0_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_WRED_PROFILE_R2_1_REG; #define QM_WRED_PROFILE_R2_1_REG_OFFSET 0x0000102c #define QM_WRED_PROFILE_R2_1_REG_RAM_CNT 0x0000000f extern const ru_reg_rec QM_COPY_DECISION_PROFILE_THR_REG; #define QM_COPY_DECISION_PROFILE_THR_REG_OFFSET 0x00001800 #define QM_COPY_DECISION_PROFILE_THR_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_0_REG; #define QM_COPY_DECISION_PROFILE_R_0_REG_OFFSET 0x00001804 #define QM_COPY_DECISION_PROFILE_R_0_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_1_REG; #define QM_COPY_DECISION_PROFILE_R_1_REG_OFFSET 0x00001808 #define QM_COPY_DECISION_PROFILE_R_1_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_2_REG; #define QM_COPY_DECISION_PROFILE_R_2_REG_OFFSET 0x0000180c #define QM_COPY_DECISION_PROFILE_R_2_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_3_REG; #define QM_COPY_DECISION_PROFILE_R_3_REG_OFFSET 0x00001810 #define QM_COPY_DECISION_PROFILE_R_3_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_4_REG; #define QM_COPY_DECISION_PROFILE_R_4_REG_OFFSET 0x00001814 #define QM_COPY_DECISION_PROFILE_R_4_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_5_REG; #define QM_COPY_DECISION_PROFILE_R_5_REG_OFFSET 0x00001818 #define QM_COPY_DECISION_PROFILE_R_5_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_COPY_DECISION_PROFILE_R_6_REG; #define QM_COPY_DECISION_PROFILE_R_6_REG_OFFSET 0x0000181c #define QM_COPY_DECISION_PROFILE_R_6_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_TOTAL_VALID_COUNTER_COUNTER_REG; #define QM_TOTAL_VALID_COUNTER_COUNTER_REG_OFFSET 0x00002000 #define QM_TOTAL_VALID_COUNTER_COUNTER_REG_RAM_CNT 0x0000013f extern const ru_reg_rec QM_DQM_VALID_COUNTER_COUNTER_REG; #define QM_DQM_VALID_COUNTER_COUNTER_REG_OFFSET 0x00003000 #define QM_DQM_VALID_COUNTER_COUNTER_REG_RAM_CNT 0x0000013f extern const ru_reg_rec QM_DROP_COUNTER_COUNTER_REG; #define QM_DROP_COUNTER_COUNTER_REG_OFFSET 0x00004000 #define QM_DROP_COUNTER_COUNTER_REG_RAM_CNT 0x0000013f extern const ru_reg_rec QM_EPON_RPT_CNT_COUNTER_REG; #define QM_EPON_RPT_CNT_COUNTER_REG_OFFSET 0x00005000 #define QM_EPON_RPT_CNT_COUNTER_REG_RAM_CNT 0x000000ff extern const ru_reg_rec QM_EPON_RPT_CNT_QUEUE_STATUS_REG; #define QM_EPON_RPT_CNT_QUEUE_STATUS_REG_OFFSET 0x00005400 #define QM_EPON_RPT_CNT_QUEUE_STATUS_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_RD_DATA_POOL0_REG; #define QM_RD_DATA_POOL0_REG_OFFSET 0x00005800 extern const ru_reg_rec QM_RD_DATA_POOL1_REG; #define QM_RD_DATA_POOL1_REG_OFFSET 0x00005804 extern const ru_reg_rec QM_RD_DATA_POOL2_REG; #define QM_RD_DATA_POOL2_REG_OFFSET 0x00005808 extern const ru_reg_rec QM_RD_DATA_POOL3_REG; #define QM_RD_DATA_POOL3_REG_OFFSET 0x0000580c extern const ru_reg_rec QM_PDFIFO_PTR_REG; #define QM_PDFIFO_PTR_REG_OFFSET 0x00006000 #define QM_PDFIFO_PTR_REG_RAM_CNT 0x0000009f extern const ru_reg_rec QM_UPDATE_FIFO_PTR_REG; #define QM_UPDATE_FIFO_PTR_REG_OFFSET 0x00006500 #define QM_UPDATE_FIFO_PTR_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_RD_DATA_REG; #define QM_RD_DATA_REG_OFFSET 0x00008800 #define QM_RD_DATA_REG_RAM_CNT 0x00000004 extern const ru_reg_rec QM_POP_REG; #define QM_POP_REG_OFFSET 0x00008820 extern const ru_reg_rec QM_CM_COMMON_INPUT_FIFO_DATA_REG; #define QM_CM_COMMON_INPUT_FIFO_DATA_REG_OFFSET 0x00009000 #define QM_CM_COMMON_INPUT_FIFO_DATA_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_NORMAL_RMT_FIFO_DATA_REG; #define QM_NORMAL_RMT_FIFO_DATA_REG_OFFSET 0x00009100 #define QM_NORMAL_RMT_FIFO_DATA_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_NON_DELAYED_RMT_FIFO_DATA_REG; #define QM_NON_DELAYED_RMT_FIFO_DATA_REG_OFFSET 0x00009200 #define QM_NON_DELAYED_RMT_FIFO_DATA_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_EGRESS_DATA_FIFO_DATA_REG; #define QM_EGRESS_DATA_FIFO_DATA_REG_OFFSET 0x00009300 #define QM_EGRESS_DATA_FIFO_DATA_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_EGRESS_RR_FIFO_DATA_REG; #define QM_EGRESS_RR_FIFO_DATA_REG_OFFSET 0x00009400 #define QM_EGRESS_RR_FIFO_DATA_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_EGRESS_BB_INPUT_FIFO_DATA_REG; #define QM_EGRESS_BB_INPUT_FIFO_DATA_REG_OFFSET 0x00009500 #define QM_EGRESS_BB_INPUT_FIFO_DATA_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG; #define QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG_OFFSET 0x00009600 #define QM_EGRESS_BB_OUTPUT_FIFO_DATA_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_BB_OUTPUT_FIFO_DATA_REG; #define QM_BB_OUTPUT_FIFO_DATA_REG_OFFSET 0x00009700 #define QM_BB_OUTPUT_FIFO_DATA_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_NON_DELAYED_OUT_FIFO_DATA_REG; #define QM_NON_DELAYED_OUT_FIFO_DATA_REG_OFFSET 0x00009800 #define QM_NON_DELAYED_OUT_FIFO_DATA_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_CONTEXT_DATA_REG; #define QM_CONTEXT_DATA_REG_OFFSET 0x0000a000 #define QM_CONTEXT_DATA_REG_RAM_CNT 0x0000027f extern const ru_reg_rec QM_DEBUG_SEL_REG; #define QM_DEBUG_SEL_REG_OFFSET 0x00016000 extern const ru_reg_rec QM_DEBUG_BUS_LSB_REG; #define QM_DEBUG_BUS_LSB_REG_OFFSET 0x00016004 extern const ru_reg_rec QM_DEBUG_BUS_MSB_REG; #define QM_DEBUG_BUS_MSB_REG_OFFSET 0x00016008 extern const ru_reg_rec QM_QM_SPARE_CONFIG_REG; #define QM_QM_SPARE_CONFIG_REG_OFFSET 0x0001600c extern const ru_reg_rec QM_GOOD_LVL1_PKTS_CNT_REG; #define QM_GOOD_LVL1_PKTS_CNT_REG_OFFSET 0x00016010 extern const ru_reg_rec QM_GOOD_LVL1_BYTES_CNT_REG; #define QM_GOOD_LVL1_BYTES_CNT_REG_OFFSET 0x00016014 extern const ru_reg_rec QM_GOOD_LVL2_PKTS_CNT_REG; #define QM_GOOD_LVL2_PKTS_CNT_REG_OFFSET 0x00016018 extern const ru_reg_rec QM_GOOD_LVL2_BYTES_CNT_REG; #define QM_GOOD_LVL2_BYTES_CNT_REG_OFFSET 0x0001601c extern const ru_reg_rec QM_COPIED_PKTS_CNT_REG; #define QM_COPIED_PKTS_CNT_REG_OFFSET 0x00016020 extern const ru_reg_rec QM_COPIED_BYTES_CNT_REG; #define QM_COPIED_BYTES_CNT_REG_OFFSET 0x00016024 extern const ru_reg_rec QM_AGG_PKTS_CNT_REG; #define QM_AGG_PKTS_CNT_REG_OFFSET 0x00016028 extern const ru_reg_rec QM_AGG_BYTES_CNT_REG; #define QM_AGG_BYTES_CNT_REG_OFFSET 0x0001602c extern const ru_reg_rec QM_AGG_1_PKTS_CNT_REG; #define QM_AGG_1_PKTS_CNT_REG_OFFSET 0x00016030 extern const ru_reg_rec QM_AGG_2_PKTS_CNT_REG; #define QM_AGG_2_PKTS_CNT_REG_OFFSET 0x00016034 extern const ru_reg_rec QM_AGG_3_PKTS_CNT_REG; #define QM_AGG_3_PKTS_CNT_REG_OFFSET 0x00016038 extern const ru_reg_rec QM_AGG_4_PKTS_CNT_REG; #define QM_AGG_4_PKTS_CNT_REG_OFFSET 0x0001603c extern const ru_reg_rec QM_WRED_DROP_CNT_REG; #define QM_WRED_DROP_CNT_REG_OFFSET 0x00016040 extern const ru_reg_rec QM_FPM_CONGESTION_DROP_CNT_REG; #define QM_FPM_CONGESTION_DROP_CNT_REG_OFFSET 0x00016048 extern const ru_reg_rec QM_DDR_PD_CONGESTION_DROP_CNT_REG; #define QM_DDR_PD_CONGESTION_DROP_CNT_REG_OFFSET 0x00016050 extern const ru_reg_rec QM_DDR_BYTE_CONGESTION_DROP_CNT_REG; #define QM_DDR_BYTE_CONGESTION_DROP_CNT_REG_OFFSET 0x00016054 extern const ru_reg_rec QM_QM_PD_CONGESTION_DROP_CNT_REG; #define QM_QM_PD_CONGESTION_DROP_CNT_REG_OFFSET 0x00016058 extern const ru_reg_rec QM_QM_ABS_REQUEUE_CNT_REG; #define QM_QM_ABS_REQUEUE_CNT_REG_OFFSET 0x0001605c extern const ru_reg_rec QM_FPM_PREFETCH_FIFO0_STATUS_REG; #define QM_FPM_PREFETCH_FIFO0_STATUS_REG_OFFSET 0x00016060 extern const ru_reg_rec QM_FPM_PREFETCH_FIFO1_STATUS_REG; #define QM_FPM_PREFETCH_FIFO1_STATUS_REG_OFFSET 0x00016064 extern const ru_reg_rec QM_FPM_PREFETCH_FIFO2_STATUS_REG; #define QM_FPM_PREFETCH_FIFO2_STATUS_REG_OFFSET 0x00016068 extern const ru_reg_rec QM_FPM_PREFETCH_FIFO3_STATUS_REG; #define QM_FPM_PREFETCH_FIFO3_STATUS_REG_OFFSET 0x0001606c extern const ru_reg_rec QM_NORMAL_RMT_FIFO_STATUS_REG; #define QM_NORMAL_RMT_FIFO_STATUS_REG_OFFSET 0x00016070 extern const ru_reg_rec QM_NON_DELAYED_RMT_FIFO_STATUS_REG; #define QM_NON_DELAYED_RMT_FIFO_STATUS_REG_OFFSET 0x00016074 extern const ru_reg_rec QM_NON_DELAYED_OUT_FIFO_STATUS_REG; #define QM_NON_DELAYED_OUT_FIFO_STATUS_REG_OFFSET 0x00016078 extern const ru_reg_rec QM_PRE_CM_FIFO_STATUS_REG; #define QM_PRE_CM_FIFO_STATUS_REG_OFFSET 0x0001607c extern const ru_reg_rec QM_CM_RD_PD_FIFO_STATUS_REG; #define QM_CM_RD_PD_FIFO_STATUS_REG_OFFSET 0x00016080 extern const ru_reg_rec QM_CM_WR_PD_FIFO_STATUS_REG; #define QM_CM_WR_PD_FIFO_STATUS_REG_OFFSET 0x00016084 extern const ru_reg_rec QM_CM_COMMON_INPUT_FIFO_STATUS_REG; #define QM_CM_COMMON_INPUT_FIFO_STATUS_REG_OFFSET 0x00016088 extern const ru_reg_rec QM_BB0_OUTPUT_FIFO_STATUS_REG; #define QM_BB0_OUTPUT_FIFO_STATUS_REG_OFFSET 0x0001608c extern const ru_reg_rec QM_BB1_OUTPUT_FIFO_STATUS_REG; #define QM_BB1_OUTPUT_FIFO_STATUS_REG_OFFSET 0x00016090 extern const ru_reg_rec QM_BB1_INPUT_FIFO_STATUS_REG; #define QM_BB1_INPUT_FIFO_STATUS_REG_OFFSET 0x00016094 extern const ru_reg_rec QM_EGRESS_DATA_FIFO_STATUS_REG; #define QM_EGRESS_DATA_FIFO_STATUS_REG_OFFSET 0x00016098 extern const ru_reg_rec QM_EGRESS_RR_FIFO_STATUS_REG; #define QM_EGRESS_RR_FIFO_STATUS_REG_OFFSET 0x0001609c extern const ru_reg_rec QM_BB_ROUTE_OVR_REG; #define QM_BB_ROUTE_OVR_REG_OFFSET 0x000160a0 #define QM_BB_ROUTE_OVR_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_QM_INGRESS_STAT_REG; #define QM_QM_INGRESS_STAT_REG_OFFSET 0x000160b0 extern const ru_reg_rec QM_QM_EGRESS_STAT_REG; #define QM_QM_EGRESS_STAT_REG_OFFSET 0x000160b4 extern const ru_reg_rec QM_QM_CM_STAT_REG; #define QM_QM_CM_STAT_REG_OFFSET 0x000160b8 extern const ru_reg_rec QM_QM_FPM_PREFETCH_STAT_REG; #define QM_QM_FPM_PREFETCH_STAT_REG_OFFSET 0x000160bc extern const ru_reg_rec QM_QM_CONNECT_ACK_COUNTER_REG; #define QM_QM_CONNECT_ACK_COUNTER_REG_OFFSET 0x000160c0 extern const ru_reg_rec QM_QM_DDR_WR_REPLY_COUNTER_REG; #define QM_QM_DDR_WR_REPLY_COUNTER_REG_OFFSET 0x000160c4 extern const ru_reg_rec QM_QM_DDR_PIPE_BYTE_COUNTER_REG; #define QM_QM_DDR_PIPE_BYTE_COUNTER_REG_OFFSET 0x000160c8 extern const ru_reg_rec QM_QM_ABS_REQUEUE_VALID_COUNTER_REG; #define QM_QM_ABS_REQUEUE_VALID_COUNTER_REG_OFFSET 0x000160cc extern const ru_reg_rec QM_QM_ILLEGAL_PD_CAPTURE_REG; #define QM_QM_ILLEGAL_PD_CAPTURE_REG_OFFSET 0x000160d0 #define QM_QM_ILLEGAL_PD_CAPTURE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG; #define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG_OFFSET 0x000160e0 #define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_QM_CM_PROCESSED_PD_CAPTURE_REG; #define QM_QM_CM_PROCESSED_PD_CAPTURE_REG_OFFSET 0x000160f0 #define QM_QM_CM_PROCESSED_PD_CAPTURE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_POOL_DROP_CNT_REG; #define QM_FPM_POOL_DROP_CNT_REG_OFFSET 0x00016100 #define QM_FPM_POOL_DROP_CNT_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_GRP_DROP_CNT_REG; #define QM_FPM_GRP_DROP_CNT_REG_OFFSET 0x00016110 #define QM_FPM_GRP_DROP_CNT_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_FPM_BUFFER_RES_DROP_CNT_REG; #define QM_FPM_BUFFER_RES_DROP_CNT_REG_OFFSET 0x00016120 extern const ru_reg_rec QM_DATA_REG; #define QM_DATA_REG_OFFSET 0x00020000 #define QM_DATA_REG_RAM_CNT 0x000009ff extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_RESERVED_REG_OFFSET 0x00040000 extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_REG_OFFSET 0x00040004 extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_REG_OFFSET 0x00040008 extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_REG_OFFSET 0x0004000c extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_REG_OFFSET 0x00040010 extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_REG_OFFSET 0x00040014 extern const ru_reg_rec QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_REG; #define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_REG_OFFSET 0x00040018 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_MACTYPE_REG_OFFSET 0x00050000 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG_OFFSET 0x00050004 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG_OFFSET 0x00050008 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG_OFFSET 0x0005000c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_OFFSET 0x00050010 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_OFFSET 0x00050018 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DMACFG_TX_REG_OFFSET 0x00050020 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG_OFFSET 0x00050024 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_SBPMCFG_REG_OFFSET 0x00050028 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_OFFSET 0x0005002c #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_OFFSET 0x00050034 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_RAM_CNT 0x00000001 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG_OFFSET 0x0005003c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_ARB_CFG_REG_OFFSET 0x00050040 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_BBROUTE_REG_OFFSET 0x00050044 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_REG_OFFSET 0x00050048 #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_Q2RNR_REG_RAM_CNT 0x00000013 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_TXRSTCMD_REG_OFFSET 0x000500a0 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_REG; #define QM_BBH_TX_QM_BBHTX_COMMON_CONFIGURATIONS_DBGSEL_REG_OFFSET 0x000500a4 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDBASE_REG_OFFSET 0x00050400 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x00050450 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x00050500 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x00050550 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00050600 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00050604 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TXTHRESH_REG_OFFSET 0x00050608 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_EEE_REG_OFFSET 0x0005060c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_REG; #define QM_BBH_TX_QM_BBHTX_LAN_CONFIGURATIONS_TS_REG_OFFSET 0x00050610 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_REG_OFFSET 0x00050a00 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_REG_OFFSET 0x00050a04 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_REG_OFFSET 0x00050a08 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_REG_OFFSET 0x00050a10 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_REG_OFFSET 0x00050a14 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_REG_OFFSET 0x00050a18 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_REG_OFFSET 0x00050a1c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_REG_OFFSET 0x00050a20 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_REG_OFFSET 0x00050a24 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_REG_OFFSET 0x00050a28 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_REG_OFFSET 0x00050a2c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_REG_OFFSET 0x00050a30 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_REG_OFFSET 0x00050a34 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_REG_OFFSET 0x00050a38 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_REG_OFFSET 0x00050a3c extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REG_OFFSET 0x00050a40 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_REG_OFFSET 0x00050a44 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_REG_OFFSET 0x00050a48 extern const ru_reg_rec QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_REG; #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_REG_OFFSET 0x00050a50 #define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_REG_RAM_CNT 0x0000001f extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_REG; #define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_REG_OFFSET 0x00060000 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_REG; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_REG_OFFSET 0x00060004 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_REG; #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_REG_OFFSET 0x00060024 #define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_U_THRESH_REG; #define QM_DMA_QM_DMA_CONFIG_U_THRESH_REG_OFFSET 0x00060044 #define QM_DMA_QM_DMA_CONFIG_U_THRESH_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_PRI_REG; #define QM_DMA_QM_DMA_CONFIG_PRI_REG_OFFSET 0x00060064 #define QM_DMA_QM_DMA_CONFIG_PRI_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_REG; #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_REG_OFFSET 0x00060084 #define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_WEIGHT_REG; #define QM_DMA_QM_DMA_CONFIG_WEIGHT_REG_OFFSET 0x000600a4 #define QM_DMA_QM_DMA_CONFIG_WEIGHT_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_PTRRST_REG; #define QM_DMA_QM_DMA_CONFIG_PTRRST_REG_OFFSET 0x000600d0 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_MAX_OTF_REG; #define QM_DMA_QM_DMA_CONFIG_MAX_OTF_REG_OFFSET 0x000600d4 extern const ru_reg_rec QM_DMA_QM_DMA_CONFIG_DBG_SEL_REG; #define QM_DMA_QM_DMA_CONFIG_DBG_SEL_REG_OFFSET 0x000600e0 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_NEMPTY_REG; #define QM_DMA_QM_DMA_DEBUG_NEMPTY_REG_OFFSET 0x00060100 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_URGNT_REG; #define QM_DMA_QM_DMA_DEBUG_URGNT_REG_OFFSET 0x00060104 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_SELSRC_REG; #define QM_DMA_QM_DMA_DEBUG_SELSRC_REG_OFFSET 0x00060108 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REG; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REG_OFFSET 0x00060110 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REG; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REG_OFFSET 0x00060130 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REG; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REG_OFFSET 0x00060150 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REG; #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REG_OFFSET 0x00060170 #define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REG_RAM_CNT 0x00000007 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_RDADD_REG; #define QM_DMA_QM_DMA_DEBUG_RDADD_REG_OFFSET 0x00060200 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_RDVALID_REG; #define QM_DMA_QM_DMA_DEBUG_RDVALID_REG_OFFSET 0x00060204 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_RDDATA_REG; #define QM_DMA_QM_DMA_DEBUG_RDDATA_REG_OFFSET 0x00060208 #define QM_DMA_QM_DMA_DEBUG_RDDATA_REG_RAM_CNT 0x00000003 extern const ru_reg_rec QM_DMA_QM_DMA_DEBUG_RDDATARDY_REG; #define QM_DMA_QM_DMA_DEBUG_RDDATARDY_REG_OFFSET 0x00060218 extern const ru_reg_rec DQM_FPM_ADDR_REG; #define DQM_FPM_ADDR_REG_OFFSET 0x00000000 extern const ru_reg_rec DQM_IRQ_STS_REG; #define DQM_IRQ_STS_REG_OFFSET 0x00000004 extern const ru_reg_rec DQM_IRQ_MSK_REG; #define DQM_IRQ_MSK_REG_OFFSET 0x00000008 extern const ru_reg_rec DQM_BUF_SIZE_REG; #define DQM_BUF_SIZE_REG_OFFSET 0x0000000c extern const ru_reg_rec DQM_BUF_BASE_REG; #define DQM_BUF_BASE_REG_OFFSET 0x00000010 extern const ru_reg_rec DQM_TOKENS_USED_REG; #define DQM_TOKENS_USED_REG_OFFSET 0x00000018 extern const ru_reg_rec DQM_NUM_PUSHED_REG; #define DQM_NUM_PUSHED_REG_OFFSET 0x0000001c extern const ru_reg_rec DQM_NUM_POPPED_REG; #define DQM_NUM_POPPED_REG_OFFSET 0x00000020 extern const ru_reg_rec DQM_DIAG_SEL_REG; #define DQM_DIAG_SEL_REG_OFFSET 0x00000024 extern const ru_reg_rec DQM_DIAG_DATA_REG; #define DQM_DIAG_DATA_REG_OFFSET 0x00000028 extern const ru_reg_rec DQM_IRQ_TST_REG; #define DQM_IRQ_TST_REG_OFFSET 0x0000002c extern const ru_reg_rec DQM_TOKEN_FIFO_REG; #define DQM_TOKEN_FIFO_REG_OFFSET 0x00000034 #define DQM_TOKEN_FIFO_REG_RAM_CNT 0x0000000f extern const ru_reg_rec DQM_STATUS_REG; #define DQM_STATUS_REG_OFFSET 0x000007b4 #define DQM_STATUS_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_HEAD_PTR_REG; #define DQM_HEAD_PTR_REG_OFFSET 0x00000fb4 #define DQM_HEAD_PTR_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DQM_TAIL_PTR_REG; #define DQM_TAIL_PTR_REG_OFFSET 0x00000fb8 #define DQM_TAIL_PTR_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DQM_DQMOL_SIZE_REG; #define DQM_DQMOL_SIZE_REG_OFFSET 0x00001fb4 #define DQM_DQMOL_SIZE_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_CFGA_REG; #define DQM_DQMOL_CFGA_REG_OFFSET 0x00001fb8 #define DQM_DQMOL_CFGA_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_CFGB_REG; #define DQM_DQMOL_CFGB_REG_OFFSET 0x00001fbc #define DQM_DQMOL_CFGB_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_CFGC_REG; #define DQM_DQMOL_CFGC_REG_OFFSET 0x00001fc0 #define DQM_DQMOL_CFGC_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_PUSHTOKEN_REG; #define DQM_DQMOL_PUSHTOKEN_REG_OFFSET 0x00001fc4 #define DQM_DQMOL_PUSHTOKEN_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_PUSHTOKENNEXT_REG; #define DQM_DQMOL_PUSHTOKENNEXT_REG_OFFSET 0x00001fc8 #define DQM_DQMOL_PUSHTOKENNEXT_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_POPTOKEN_REG; #define DQM_DQMOL_POPTOKEN_REG_OFFSET 0x00001fcc #define DQM_DQMOL_POPTOKEN_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_DQMOL_POPTOKENNEXT_REG; #define DQM_DQMOL_POPTOKENNEXT_REG_OFFSET 0x00001fd0 #define DQM_DQMOL_POPTOKENNEXT_REG_RAM_CNT 0x0000011f extern const ru_reg_rec DQM_QSM_DATA_REG; #define DQM_QSM_DATA_REG_OFFSET 0x0001ffb4 #define DQM_QSM_DATA_REG_RAM_CNT 0x00008fff extern const ru_reg_rec FPM_FPM_CTL_REG; #define FPM_FPM_CTL_REG_OFFSET 0x00000000 extern const ru_reg_rec FPM_FPM_CFG1_REG; #define FPM_FPM_CFG1_REG_OFFSET 0x00000004 extern const ru_reg_rec FPM_FPM_WEIGHT_REG; #define FPM_FPM_WEIGHT_REG_OFFSET 0x00000008 extern const ru_reg_rec FPM_FPM_BB_CFG_REG; #define FPM_FPM_BB_CFG_REG_OFFSET 0x0000000c extern const ru_reg_rec FPM_POOL1_INTR_MSK_REG; #define FPM_POOL1_INTR_MSK_REG_OFFSET 0x00000010 extern const ru_reg_rec FPM_POOL1_INTR_STS_REG; #define FPM_POOL1_INTR_STS_REG_OFFSET 0x00000014 extern const ru_reg_rec FPM_POOL1_STALL_MSK_REG; #define FPM_POOL1_STALL_MSK_REG_OFFSET 0x00000018 extern const ru_reg_rec FPM_POOL2_INTR_MSK_REG; #define FPM_POOL2_INTR_MSK_REG_OFFSET 0x0000001c extern const ru_reg_rec FPM_POOL2_INTR_STS_REG; #define FPM_POOL2_INTR_STS_REG_OFFSET 0x00000020 extern const ru_reg_rec FPM_POOL2_STALL_MSK_REG; #define FPM_POOL2_STALL_MSK_REG_OFFSET 0x00000024 extern const ru_reg_rec FPM_POOL1_CFG1_REG; #define FPM_POOL1_CFG1_REG_OFFSET 0x00000040 extern const ru_reg_rec FPM_POOL1_CFG2_REG; #define FPM_POOL1_CFG2_REG_OFFSET 0x00000044 extern const ru_reg_rec FPM_POOL1_CFG3_REG; #define FPM_POOL1_CFG3_REG_OFFSET 0x00000048 extern const ru_reg_rec FPM_POOL1_STAT1_REG; #define FPM_POOL1_STAT1_REG_OFFSET 0x00000050 extern const ru_reg_rec FPM_POOL1_STAT2_REG; #define FPM_POOL1_STAT2_REG_OFFSET 0x00000054 extern const ru_reg_rec FPM_POOL1_STAT3_REG; #define FPM_POOL1_STAT3_REG_OFFSET 0x00000058 extern const ru_reg_rec FPM_POOL1_STAT4_REG; #define FPM_POOL1_STAT4_REG_OFFSET 0x0000005c extern const ru_reg_rec FPM_POOL1_STAT5_REG; #define FPM_POOL1_STAT5_REG_OFFSET 0x00000060 extern const ru_reg_rec FPM_POOL1_STAT6_REG; #define FPM_POOL1_STAT6_REG_OFFSET 0x00000064 extern const ru_reg_rec FPM_POOL1_STAT7_REG; #define FPM_POOL1_STAT7_REG_OFFSET 0x00000068 extern const ru_reg_rec FPM_POOL1_STAT8_REG; #define FPM_POOL1_STAT8_REG_OFFSET 0x0000006c extern const ru_reg_rec FPM_POOL2_STAT1_REG; #define FPM_POOL2_STAT1_REG_OFFSET 0x00000070 extern const ru_reg_rec FPM_POOL2_STAT2_REG; #define FPM_POOL2_STAT2_REG_OFFSET 0x00000074 extern const ru_reg_rec FPM_POOL2_STAT3_REG; #define FPM_POOL2_STAT3_REG_OFFSET 0x00000078 extern const ru_reg_rec FPM_POOL2_STAT4_REG; #define FPM_POOL2_STAT4_REG_OFFSET 0x0000007c extern const ru_reg_rec FPM_POOL2_STAT5_REG; #define FPM_POOL2_STAT5_REG_OFFSET 0x00000080 extern const ru_reg_rec FPM_POOL2_STAT6_REG; #define FPM_POOL2_STAT6_REG_OFFSET 0x00000084 extern const ru_reg_rec FPM_POOL2_STAT7_REG; #define FPM_POOL2_STAT7_REG_OFFSET 0x00000088 extern const ru_reg_rec FPM_POOL2_STAT8_REG; #define FPM_POOL2_STAT8_REG_OFFSET 0x0000008c extern const ru_reg_rec FPM_POOL1_XON_XOFF_CFG_REG; #define FPM_POOL1_XON_XOFF_CFG_REG_OFFSET 0x000000c0 extern const ru_reg_rec FPM_FPM_NOT_EMPTY_CFG_REG; #define FPM_FPM_NOT_EMPTY_CFG_REG_OFFSET 0x000000d0 extern const ru_reg_rec FPM_MEM_CTL_REG; #define FPM_MEM_CTL_REG_OFFSET 0x00000100 extern const ru_reg_rec FPM_MEM_DATA1_REG; #define FPM_MEM_DATA1_REG_OFFSET 0x00000104 extern const ru_reg_rec FPM_MEM_DATA2_REG; #define FPM_MEM_DATA2_REG_OFFSET 0x00000108 extern const ru_reg_rec FPM_TOKEN_RECOVER_CTL_REG; #define FPM_TOKEN_RECOVER_CTL_REG_OFFSET 0x00000130 extern const ru_reg_rec FPM_SHORT_AGING_TIMER_REG; #define FPM_SHORT_AGING_TIMER_REG_OFFSET 0x00000134 extern const ru_reg_rec FPM_LONG_AGING_TIMER_REG; #define FPM_LONG_AGING_TIMER_REG_OFFSET 0x00000138 extern const ru_reg_rec FPM_CACHE_RECYCLE_TIMER_REG; #define FPM_CACHE_RECYCLE_TIMER_REG_OFFSET 0x0000013c extern const ru_reg_rec FPM_EXPIRED_TOKEN_COUNT_POOL1_REG; #define FPM_EXPIRED_TOKEN_COUNT_POOL1_REG_OFFSET 0x00000140 extern const ru_reg_rec FPM_RECOVERED_TOKEN_COUNT_POOL1_REG; #define FPM_RECOVERED_TOKEN_COUNT_POOL1_REG_OFFSET 0x00000144 extern const ru_reg_rec FPM_EXPIRED_TOKEN_COUNT_POOL2_REG; #define FPM_EXPIRED_TOKEN_COUNT_POOL2_REG_OFFSET 0x00000148 extern const ru_reg_rec FPM_RECOVERED_TOKEN_COUNT_POOL2_REG; #define FPM_RECOVERED_TOKEN_COUNT_POOL2_REG_OFFSET 0x0000014c extern const ru_reg_rec FPM_TOKEN_RECOVER_START_END_POOL1_REG; #define FPM_TOKEN_RECOVER_START_END_POOL1_REG_OFFSET 0x00000150 extern const ru_reg_rec FPM_TOKEN_RECOVER_START_END_POOL2_REG; #define FPM_TOKEN_RECOVER_START_END_POOL2_REG_OFFSET 0x00000154 extern const ru_reg_rec FPM_POOL1_ALLOC_DEALLOC_REG; #define FPM_POOL1_ALLOC_DEALLOC_REG_OFFSET 0x00000200 extern const ru_reg_rec FPM_POOL2_ALLOC_DEALLOC_REG; #define FPM_POOL2_ALLOC_DEALLOC_REG_OFFSET 0x00000208 extern const ru_reg_rec FPM_POOL3_ALLOC_DEALLOC_REG; #define FPM_POOL3_ALLOC_DEALLOC_REG_OFFSET 0x00000210 extern const ru_reg_rec FPM_POOL4_ALLOC_DEALLOC_REG; #define FPM_POOL4_ALLOC_DEALLOC_REG_OFFSET 0x00000218 extern const ru_reg_rec FPM_SPARE_REG; #define FPM_SPARE_REG_OFFSET 0x00000220 extern const ru_reg_rec FPM_POOL_MULTI_REG; #define FPM_POOL_MULTI_REG_OFFSET 0x00000224 extern const ru_reg_rec FPM_SEARCH_MEMORY_HIGH_REG; #define FPM_SEARCH_MEMORY_HIGH_REG_OFFSET 0x00004000 #define FPM_SEARCH_MEMORY_HIGH_REG_RAM_CNT 0x00000117 extern const ru_reg_rec FPM_SEARCH_MEMORY_LOW_REG; #define FPM_SEARCH_MEMORY_LOW_REG_OFFSET 0x00004004 #define FPM_SEARCH_MEMORY_LOW_REG_RAM_CNT 0x00000117 extern const ru_reg_rec FPM_MCAST_MEMORY_HIGH_REG; #define FPM_MCAST_MEMORY_HIGH_REG_OFFSET 0x00010000 #define FPM_MCAST_MEMORY_HIGH_REG_RAM_CNT 0x000007ff extern const ru_reg_rec FPM_MCAST_MEMORY_LOW_REG; #define FPM_MCAST_MEMORY_LOW_REG_OFFSET 0x00010004 #define FPM_MCAST_MEMORY_LOW_REG_RAM_CNT 0x000007ff extern const ru_reg_rec FPM_FPM_BB_FORCE_REG; #define FPM_FPM_BB_FORCE_REG_OFFSET 0x00030000 extern const ru_reg_rec FPM_FPM_BB_FORCED_CTRL_REG; #define FPM_FPM_BB_FORCED_CTRL_REG_OFFSET 0x00030004 extern const ru_reg_rec FPM_FPM_BB_FORCED_ADDR_REG; #define FPM_FPM_BB_FORCED_ADDR_REG_OFFSET 0x00030008 extern const ru_reg_rec FPM_FPM_BB_FORCED_DATA_REG; #define FPM_FPM_BB_FORCED_DATA_REG_OFFSET 0x0003000c extern const ru_reg_rec FPM_FPM_BB_DECODE_CFG_REG; #define FPM_FPM_BB_DECODE_CFG_REG_OFFSET 0x00030010 extern const ru_reg_rec FPM_FPM_BB_DBG_CFG_REG; #define FPM_FPM_BB_DBG_CFG_REG_OFFSET 0x00030014 extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_STS_REG; #define FPM_FPM_BB_DBG_RXFIFO_STS_REG_OFFSET 0x00030018 extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_STS_REG; #define FPM_FPM_BB_DBG_TXFIFO_STS_REG_OFFSET 0x0003001c extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_DATA1_REG; #define FPM_FPM_BB_DBG_RXFIFO_DATA1_REG_OFFSET 0x00030020 extern const ru_reg_rec FPM_FPM_BB_DBG_RXFIFO_DATA2_REG; #define FPM_FPM_BB_DBG_RXFIFO_DATA2_REG_OFFSET 0x00030024 extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA1_REG; #define FPM_FPM_BB_DBG_TXFIFO_DATA1_REG_OFFSET 0x00030028 extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA2_REG; #define FPM_FPM_BB_DBG_TXFIFO_DATA2_REG_OFFSET 0x0003002c extern const ru_reg_rec FPM_FPM_BB_DBG_TXFIFO_DATA3_REG; #define FPM_FPM_BB_DBG_TXFIFO_DATA3_REG_OFFSET 0x00030030 extern const ru_reg_rec RNR_MEM_HIGH_REG; #define RNR_MEM_HIGH_REG_OFFSET 0x00000000 #define RNR_MEM_HIGH_REG_RAM_CNT 0x000007ff extern const ru_reg_rec RNR_MEM_LOW_REG; #define RNR_MEM_LOW_REG_OFFSET 0x00000004 #define RNR_MEM_LOW_REG_RAM_CNT 0x000007ff extern const ru_reg_rec RNR_INST_MEM_ENTRY_REG; #define RNR_INST_MEM_ENTRY_REG_OFFSET 0x00000000 #define RNR_INST_MEM_ENTRY_REG_RAM_CNT 0x00001fff extern const ru_reg_rec RNR_CNTXT_MEM_ENTRY_REG; #define RNR_CNTXT_MEM_ENTRY_REG_OFFSET 0x00000000 #define RNR_CNTXT_MEM_ENTRY_REG_RAM_CNT 0x000001ff extern const ru_reg_rec RNR_PRED_MEM_ENTRY_REG; #define RNR_PRED_MEM_ENTRY_REG_OFFSET 0x00000000 #define RNR_PRED_MEM_ENTRY_REG_RAM_CNT 0x000001ff extern const ru_reg_rec RNR_REGS_CFG_GLOBAL_CTRL_REG; #define RNR_REGS_CFG_GLOBAL_CTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec RNR_REGS_CFG_CPU_WAKEUP_REG; #define RNR_REGS_CFG_CPU_WAKEUP_REG_OFFSET 0x00000004 extern const ru_reg_rec RNR_REGS_CFG_INT_CTRL_REG; #define RNR_REGS_CFG_INT_CTRL_REG_OFFSET 0x00000008 extern const ru_reg_rec RNR_REGS_CFG_INT_MASK_REG; #define RNR_REGS_CFG_INT_MASK_REG_OFFSET 0x0000000c extern const ru_reg_rec RNR_REGS_CFG_GEN_CFG_REG; #define RNR_REGS_CFG_GEN_CFG_REG_OFFSET 0x00000030 extern const ru_reg_rec RNR_REGS_CFG_CAM_CFG_REG; #define RNR_REGS_CFG_CAM_CFG_REG_OFFSET 0x00000034 extern const ru_reg_rec RNR_REGS_CFG_DDR_CFG_REG; #define RNR_REGS_CFG_DDR_CFG_REG_OFFSET 0x00000040 extern const ru_reg_rec RNR_REGS_CFG_PSRAM_CFG_REG; #define RNR_REGS_CFG_PSRAM_CFG_REG_OFFSET 0x00000044 extern const ru_reg_rec RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_REG; #define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG_REG_OFFSET 0x00000048 extern const ru_reg_rec RNR_REGS_CFG_SCH_CFG_REG; #define RNR_REGS_CFG_SCH_CFG_REG_OFFSET 0x0000004c extern const ru_reg_rec RNR_REGS_CFG_BKPT_CFG_REG; #define RNR_REGS_CFG_BKPT_CFG_REG_OFFSET 0x00000050 extern const ru_reg_rec RNR_REGS_CFG_BKPT_IMM_REG; #define RNR_REGS_CFG_BKPT_IMM_REG_OFFSET 0x00000054 extern const ru_reg_rec RNR_REGS_CFG_BKPT_STS_REG; #define RNR_REGS_CFG_BKPT_STS_REG_OFFSET 0x00000058 extern const ru_reg_rec RNR_REGS_CFG_PC_STS_REG; #define RNR_REGS_CFG_PC_STS_REG_OFFSET 0x0000005c extern const ru_reg_rec RNR_REGS_CFG_PROFILING_STS_REG; #define RNR_REGS_CFG_PROFILING_STS_REG_OFFSET 0x000000b0 extern const ru_reg_rec RNR_REGS_CFG_PROFILING_CFG_0_REG; #define RNR_REGS_CFG_PROFILING_CFG_0_REG_OFFSET 0x000000b4 extern const ru_reg_rec RNR_REGS_CFG_PROFILING_CFG_1_REG; #define RNR_REGS_CFG_PROFILING_CFG_1_REG_OFFSET 0x000000b8 extern const ru_reg_rec RNR_REGS_CFG_PROFILING_COUNTER_REG; #define RNR_REGS_CFG_PROFILING_COUNTER_REG_OFFSET 0x000000bc extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT1_REG; #define RNR_REGS_CFG_STALL_CNT1_REG_OFFSET 0x000000c0 extern const ru_reg_rec RNR_REGS_CFG_STALL_CNT2_REG; #define RNR_REGS_CFG_STALL_CNT2_REG_OFFSET 0x000000c4 extern const ru_reg_rec RNR_REGS_CFG_IDLE_CNT1_REG; #define RNR_REGS_CFG_IDLE_CNT1_REG_OFFSET 0x000000c8 extern const ru_reg_rec RNR_REGS_CFG_JMP_CNT_REG; #define RNR_REGS_CFG_JMP_CNT_REG_OFFSET 0x000000cc extern const ru_reg_rec RNR_REGS_CFG_METAL_FIX_REG_REG; #define RNR_REGS_CFG_METAL_FIX_REG_REG_OFFSET 0x000000f0 extern const ru_reg_rec RNR_REGS_DBG_DESIGN_DBG_CTRL_REG; #define RNR_REGS_DBG_DESIGN_DBG_CTRL_REG_OFFSET 0x000002b4 extern const ru_reg_rec RNR_REGS_DBG_DESIGN_DBG_DATA_REG; #define RNR_REGS_DBG_DESIGN_DBG_DATA_REG_OFFSET 0x000002b8 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_RES_CNTRL_REG; #define RNR_QUAD_UBUS_SLV_RES_CNTRL_REG_OFFSET 0x00000000 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_VPB_BASE_REG; #define RNR_QUAD_UBUS_SLV_VPB_BASE_REG_OFFSET 0x00000004 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_VPB_MASK_REG; #define RNR_QUAD_UBUS_SLV_VPB_MASK_REG_OFFSET 0x00000008 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_APB_BASE_REG; #define RNR_QUAD_UBUS_SLV_APB_BASE_REG_OFFSET 0x0000000c extern const ru_reg_rec RNR_QUAD_UBUS_SLV_APB_MASK_REG; #define RNR_QUAD_UBUS_SLV_APB_MASK_REG_OFFSET 0x00000010 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_DQM_BASE_REG; #define RNR_QUAD_UBUS_SLV_DQM_BASE_REG_OFFSET 0x00000014 extern const ru_reg_rec RNR_QUAD_UBUS_SLV_DQM_MASK_REG; #define RNR_QUAD_UBUS_SLV_DQM_MASK_REG_OFFSET 0x00000018 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_ENG_REG_OFFSET 0x00000400 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PARSER_MISC_CFG_REG_OFFSET 0x00000404 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_0_1_REG_OFFSET 0x00000408 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_2_3_REG_OFFSET 0x0000040c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_4_5_REG_OFFSET 0x00000410 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_VID_6_7_REG_OFFSET 0x00000414 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_REG_OFFSET 0x00000418 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_REG_OFFSET 0x0000041c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_REG_OFFSET 0x00000428 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_REG_OFFSET 0x0000042c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_REG_OFFSET 0x00000438 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_REG_OFFSET 0x0000043c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_REG_OFFSET 0x00000440 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_REG_OFFSET 0x00000444 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_REG_OFFSET 0x00000448 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_REG_OFFSET 0x0000044c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_REG_OFFSET 0x00000450 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_REG_OFFSET 0x00000454 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_NEST_REG_OFFSET 0x00000458 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_0_REG_OFFSET 0x0000045c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_1_REG_OFFSET 0x00000460 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_QTAG_HARD_NEST_2_REG_OFFSET 0x00000464 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_USER_IP_PROT_REG_OFFSET 0x00000468 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_REG_OFFSET 0x00000470 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_H_REG_OFFSET 0x00000474 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_REG_OFFSET 0x00000478 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_H_REG_OFFSET 0x0000047c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_REG_OFFSET 0x00000480 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_REG_OFFSET 0x00000484 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_REG_OFFSET 0x00000488 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_REG_OFFSET 0x0000048c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_REG_OFFSET 0x00000490 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_REG_OFFSET 0x00000494 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_REG_OFFSET 0x00000498 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_REG_OFFSET 0x0000049c extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_REG_OFFSET 0x000004a0 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_REG_OFFSET 0x000004a4 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_REG_OFFSET 0x000004a8 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_REG_OFFSET 0x000004ac extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_L_REG_OFFSET 0x000004b0 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT8_VAL_H_REG_OFFSET 0x000004b4 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_REG_OFFSET 0x000004c8 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_H_REG_OFFSET 0x000004cc extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_REG_OFFSET 0x000004d0 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_H_REG_OFFSET 0x000004d4 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_0_REG_OFFSET 0x000004d8 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_1_REG_OFFSET 0x000004dc extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_2_REG_OFFSET 0x000004e0 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_REG_OFFSET 0x000004e4 extern const ru_reg_rec RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_REG; #define RNR_QUAD_PARSER_CORE_CONFIGURATION_PROP_TAG_CFG_REG_OFFSET 0x000004e8 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG_REG_OFFSET 0x00000500 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE_REG_OFFSET 0x00000504 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE_REG_OFFSET 0x00000508 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE_REG_OFFSET 0x0000050c extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE_REG_OFFSET 0x00000510 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE_REG_OFFSET 0x00000514 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_REG; #define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE_REG_OFFSET 0x00000518 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK_REG_OFFSET 0x0000051c extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK_REG_OFFSET 0x00000520 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK_REG_OFFSET 0x00000524 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK_REG_OFFSET 0x00000528 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK_REG_OFFSET 0x0000052c extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_REG; #define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK_REG_OFFSET 0x00000530 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_REG; #define RNR_QUAD_GENERAL_CONFIG_PROFILING_CONFIG_REG_OFFSET 0x00000534 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG_REG_OFFSET 0x00000540 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG_REG_OFFSET 0x00000544 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG_REG_OFFSET 0x00000548 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG_REG_OFFSET 0x0000054c extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG_REG_OFFSET 0x00000550 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG_REG_OFFSET 0x00000554 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG_REG_OFFSET 0x00000558 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG_REG_OFFSET 0x0000055c extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_REG; #define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG_REG_OFFSET 0x00000560 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_REG; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG_REG_OFFSET 0x00000570 extern const ru_reg_rec RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_REG; #define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS_REG_OFFSET 0x00000574 extern const ru_reg_rec RNR_QUAD_DEBUG_FIFO_CONFIG_REG; #define RNR_QUAD_DEBUG_FIFO_CONFIG_REG_OFFSET 0x00000600 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_REG; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS_REG_OFFSET 0x00000604 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_REG; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS_REG_OFFSET 0x00000608 extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_REG; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS_REG_OFFSET 0x0000060c extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_REG; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS_REG_OFFSET 0x00000610 extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_REG; #define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2_REG_OFFSET 0x00000614 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_REG; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1_REG_OFFSET 0x00000620 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_REG; #define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2_REG_OFFSET 0x00000624 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_REG; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1_REG_OFFSET 0x00000628 extern const ru_reg_rec RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_REG; #define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2_REG_OFFSET 0x0000062c extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_REG; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1_REG_OFFSET 0x00000630 extern const ru_reg_rec RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_REG; #define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2_REG_OFFSET 0x00000634 extern const ru_reg_rec RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG; #define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG_OFFSET 0x00000800 #define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL_REG_RAM_CNT 0x00000023 extern const ru_reg_rec RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG; #define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG_OFFSET 0x00000a00 #define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_REG_RAM_CNT 0x0000000f extern const ru_reg_rec RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG; #define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG_OFFSET 0x00000a40 #define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE_REG_RAM_CNT 0x0000000f extern const ru_reg_rec DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REG; #define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG_REG_OFFSET 0x00000000 extern const ru_reg_rec DSPTCHR_REORDER_CFG_VQ_EN_REG; #define DSPTCHR_REORDER_CFG_VQ_EN_REG_OFFSET 0x00000004 extern const ru_reg_rec DSPTCHR_REORDER_CFG_BB_CFG_REG; #define DSPTCHR_REORDER_CFG_BB_CFG_REG_OFFSET 0x00000008 extern const ru_reg_rec DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_REG; #define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL_REG_OFFSET 0x0000000c extern const ru_reg_rec DSPTCHR_CONGESTION_INGRS_CONGSTN_REG; #define DSPTCHR_CONGESTION_INGRS_CONGSTN_REG_OFFSET 0x00000080 #define DSPTCHR_CONGESTION_INGRS_CONGSTN_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_CONGESTION_EGRS_CONGSTN_REG; #define DSPTCHR_CONGESTION_EGRS_CONGSTN_REG_OFFSET 0x00000100 #define DSPTCHR_CONGESTION_EGRS_CONGSTN_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_REG; #define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN_REG_OFFSET 0x00000180 extern const ru_reg_rec DSPTCHR_CONGESTION_GLBL_CONGSTN_REG; #define DSPTCHR_CONGESTION_GLBL_CONGSTN_REG_OFFSET 0x00000184 extern const ru_reg_rec DSPTCHR_CONGESTION_CONGSTN_STATUS_REG; #define DSPTCHR_CONGESTION_CONGSTN_STATUS_REG_OFFSET 0x00000188 extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_REG; #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW_REG_OFFSET 0x0000018c extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_REG; #define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_REG_OFFSET 0x00000190 extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_REG; #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW_REG_OFFSET 0x00000194 extern const ru_reg_rec DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_REG; #define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_REG_OFFSET 0x00000198 extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG_OFFSET 0x00000280 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG_OFFSET 0x00000300 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG; #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG_OFFSET 0x00000380 #define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG; #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG_OFFSET 0x00000400 #define DSPTCHR_QUEUE_MAPPING_CRDT_CFG_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG; #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG_OFFSET 0x00000480 #define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD_REG_RAM_CNT 0x0000000f extern const ru_reg_rec DSPTCHR_QUEUE_MAPPING_Q_DEST_REG; #define DSPTCHR_QUEUE_MAPPING_Q_DEST_REG_OFFSET 0x000004c0 extern const ru_reg_rec DSPTCHR_POOL_SIZES_CMN_POOL_LMT_REG; #define DSPTCHR_POOL_SIZES_CMN_POOL_LMT_REG_OFFSET 0x000004d0 extern const ru_reg_rec DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_REG; #define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE_REG_OFFSET 0x000004d4 extern const ru_reg_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_REG; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT_REG_OFFSET 0x000004d8 extern const ru_reg_rec DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_REG; #define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE_REG_OFFSET 0x000004dc extern const ru_reg_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_REG; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT_REG_OFFSET 0x000004e0 extern const ru_reg_rec DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_REG; #define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE_REG_OFFSET 0x000004e4 extern const ru_reg_rec DSPTCHR_POOL_SIZES_RNR_POOL_LMT_REG; #define DSPTCHR_POOL_SIZES_RNR_POOL_LMT_REG_OFFSET 0x000004e8 extern const ru_reg_rec DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_REG; #define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE_REG_OFFSET 0x000004ec extern const ru_reg_rec DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_REG; #define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE_REG_OFFSET 0x000004f0 extern const ru_reg_rec DSPTCHR_MASK_MSK_TSK_255_0_REG; #define DSPTCHR_MASK_MSK_TSK_255_0_REG_OFFSET 0x00000500 #define DSPTCHR_MASK_MSK_TSK_255_0_REG_RAM_CNT 0x0000003f extern const ru_reg_rec DSPTCHR_MASK_MSK_Q_REG; #define DSPTCHR_MASK_MSK_Q_REG_OFFSET 0x00000600 #define DSPTCHR_MASK_MSK_Q_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DSPTCHR_MASK_DLY_Q_REG; #define DSPTCHR_MASK_DLY_Q_REG_OFFSET 0x00000620 extern const ru_reg_rec DSPTCHR_MASK_NON_DLY_Q_REG; #define DSPTCHR_MASK_NON_DLY_Q_REG_OFFSET 0x00000624 extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_REG; #define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT_REG_OFFSET 0x00000630 extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_REG; #define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_REG_OFFSET 0x00000634 extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_REG; #define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_REG_OFFSET 0x00000638 extern const ru_reg_rec DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG; #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG_OFFSET 0x00000680 #define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_REG; #define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ_REG_OFFSET 0x00000770 extern const ru_reg_rec DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_REG; #define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD_REG_OFFSET 0x00000774 extern const ru_reg_rec DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG; #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG_OFFSET 0x00000780 #define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_REG; #define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT_REG_OFFSET 0x00000800 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_LB_CFG_REG; #define DSPTCHR_LOAD_BALANCING_LB_CFG_REG_OFFSET 0x00000850 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1_REG_OFFSET 0x00000860 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3_REG_OFFSET 0x00000864 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5_REG_OFFSET 0x00000868 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7_REG_OFFSET 0x0000086c extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9_REG_OFFSET 0x00000870 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11_REG_OFFSET 0x00000874 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13_REG_OFFSET 0x00000878 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_REG; #define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15_REG_OFFSET 0x0000087c extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG; #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG_OFFSET 0x00000900 #define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_REG; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3_REG_OFFSET 0x00000980 extern const ru_reg_rec DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_REG; #define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7_REG_OFFSET 0x00000984 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_REG_OFFSET 0x00000990 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_REG_OFFSET 0x00000994 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_REG_OFFSET 0x00000998 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_REG_OFFSET 0x0000099c extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_REG_OFFSET 0x000009a0 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_REG_OFFSET 0x000009a4 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_REG_OFFSET 0x000009a8 extern const ru_reg_rec DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_REG; #define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_REG_OFFSET 0x000009ac extern const ru_reg_rec DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_REG; #define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL_REG_OFFSET 0x000009b0 extern const ru_reg_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_REG; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7_REG_OFFSET 0x000009b4 extern const ru_reg_rec DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_REG; #define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15_REG_OFFSET 0x000009b8 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_BUS_CNTRL_REG; #define DSPTCHR_DEBUG_DBG_BUS_CNTRL_REG_OFFSET 0x000009bc extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_0_REG; #define DSPTCHR_DEBUG_DBG_VEC_0_REG_OFFSET 0x000009c0 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_1_REG; #define DSPTCHR_DEBUG_DBG_VEC_1_REG_OFFSET 0x000009c4 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_2_REG; #define DSPTCHR_DEBUG_DBG_VEC_2_REG_OFFSET 0x000009c8 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_3_REG; #define DSPTCHR_DEBUG_DBG_VEC_3_REG_OFFSET 0x000009cc extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_4_REG; #define DSPTCHR_DEBUG_DBG_VEC_4_REG_OFFSET 0x000009d0 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_5_REG; #define DSPTCHR_DEBUG_DBG_VEC_5_REG_OFFSET 0x000009d4 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_6_REG; #define DSPTCHR_DEBUG_DBG_VEC_6_REG_OFFSET 0x000009d8 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_7_REG; #define DSPTCHR_DEBUG_DBG_VEC_7_REG_OFFSET 0x000009dc extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_8_REG; #define DSPTCHR_DEBUG_DBG_VEC_8_REG_OFFSET 0x000009e0 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_9_REG; #define DSPTCHR_DEBUG_DBG_VEC_9_REG_OFFSET 0x000009e4 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_10_REG; #define DSPTCHR_DEBUG_DBG_VEC_10_REG_OFFSET 0x000009e8 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_11_REG; #define DSPTCHR_DEBUG_DBG_VEC_11_REG_OFFSET 0x000009ec extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_12_REG; #define DSPTCHR_DEBUG_DBG_VEC_12_REG_OFFSET 0x000009f0 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_13_REG; #define DSPTCHR_DEBUG_DBG_VEC_13_REG_OFFSET 0x000009f4 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_14_REG; #define DSPTCHR_DEBUG_DBG_VEC_14_REG_OFFSET 0x000009f8 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_15_REG; #define DSPTCHR_DEBUG_DBG_VEC_15_REG_OFFSET 0x000009fc extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_16_REG; #define DSPTCHR_DEBUG_DBG_VEC_16_REG_OFFSET 0x00000a00 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_17_REG; #define DSPTCHR_DEBUG_DBG_VEC_17_REG_OFFSET 0x00000a04 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_18_REG; #define DSPTCHR_DEBUG_DBG_VEC_18_REG_OFFSET 0x00000a08 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_19_REG; #define DSPTCHR_DEBUG_DBG_VEC_19_REG_OFFSET 0x00000a0c extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_20_REG; #define DSPTCHR_DEBUG_DBG_VEC_20_REG_OFFSET 0x00000a10 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_21_REG; #define DSPTCHR_DEBUG_DBG_VEC_21_REG_OFFSET 0x00000a14 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_22_REG; #define DSPTCHR_DEBUG_DBG_VEC_22_REG_OFFSET 0x00000a18 extern const ru_reg_rec DSPTCHR_DEBUG_DBG_VEC_23_REG; #define DSPTCHR_DEBUG_DBG_VEC_23_REG_OFFSET 0x00000a1c extern const ru_reg_rec DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_REG; #define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL_REG_OFFSET 0x00000a70 extern const ru_reg_rec DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG; #define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG_OFFSET 0x00000a80 #define DSPTCHR_DEBUG_STATISTICS_DBG_CNT_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_HEAD_REG; #define DSPTCHR_QDES_HEAD_REG_OFFSET 0x00002000 #define DSPTCHR_QDES_HEAD_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_BFOUT_REG; #define DSPTCHR_QDES_BFOUT_REG_OFFSET 0x00002004 #define DSPTCHR_QDES_BFOUT_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_BUFIN_REG; #define DSPTCHR_QDES_BUFIN_REG_OFFSET 0x00002008 #define DSPTCHR_QDES_BUFIN_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_TAIL_REG; #define DSPTCHR_QDES_TAIL_REG_OFFSET 0x0000200c #define DSPTCHR_QDES_TAIL_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_FBDNULL_REG; #define DSPTCHR_QDES_FBDNULL_REG_OFFSET 0x00002010 #define DSPTCHR_QDES_FBDNULL_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_NULLBD_REG; #define DSPTCHR_QDES_NULLBD_REG_OFFSET 0x00002014 #define DSPTCHR_QDES_NULLBD_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_BUFAVAIL_REG; #define DSPTCHR_QDES_BUFAVAIL_REG_OFFSET 0x00002018 #define DSPTCHR_QDES_BUFAVAIL_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_RESERVED_REG; #define DSPTCHR_QDES_RESERVED_REG_OFFSET 0x0000201c #define DSPTCHR_QDES_RESERVED_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_REG_Q_HEAD_REG; #define DSPTCHR_QDES_REG_Q_HEAD_REG_OFFSET 0x00002600 #define DSPTCHR_QDES_REG_Q_HEAD_REG_RAM_CNT 0x0000001f extern const ru_reg_rec DSPTCHR_QDES_REG_VIQ_HEAD_VLD_REG; #define DSPTCHR_QDES_REG_VIQ_HEAD_VLD_REG_OFFSET 0x00002680 extern const ru_reg_rec DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_REG; #define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD_REG_OFFSET 0x00002684 extern const ru_reg_rec DSPTCHR_QDES_REG_VEQ_HEAD_VLD_REG; #define DSPTCHR_QDES_REG_VEQ_HEAD_VLD_REG_OFFSET 0x00002688 extern const ru_reg_rec DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_REG; #define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL_REG_OFFSET 0x0000268c extern const ru_reg_rec DSPTCHR_FLLDES_HEAD_REG; #define DSPTCHR_FLLDES_HEAD_REG_OFFSET 0x00002700 extern const ru_reg_rec DSPTCHR_FLLDES_BFOUT_REG; #define DSPTCHR_FLLDES_BFOUT_REG_OFFSET 0x00002704 extern const ru_reg_rec DSPTCHR_FLLDES_BFIN_REG; #define DSPTCHR_FLLDES_BFIN_REG_OFFSET 0x00002708 extern const ru_reg_rec DSPTCHR_FLLDES_TAIL_REG; #define DSPTCHR_FLLDES_TAIL_REG_OFFSET 0x0000270c extern const ru_reg_rec DSPTCHR_FLLDES_FLLDROP_REG; #define DSPTCHR_FLLDES_FLLDROP_REG_OFFSET 0x00002710 extern const ru_reg_rec DSPTCHR_FLLDES_LTINT_REG; #define DSPTCHR_FLLDES_LTINT_REG_OFFSET 0x00002714 extern const ru_reg_rec DSPTCHR_FLLDES_BUFAVAIL_REG; #define DSPTCHR_FLLDES_BUFAVAIL_REG_OFFSET 0x00002720 extern const ru_reg_rec DSPTCHR_FLLDES_FREEMIN_REG; #define DSPTCHR_FLLDES_FREEMIN_REG_OFFSET 0x00002724 extern const ru_reg_rec DSPTCHR_BDRAM_DATA_REG; #define DSPTCHR_BDRAM_DATA_REG_OFFSET 0x00003000 #define DSPTCHR_BDRAM_DATA_REG_RAM_CNT 0x000003ff extern const ru_reg_rec DSPTCHR_PDRAM_DATA_REG; #define DSPTCHR_PDRAM_DATA_REG_OFFSET 0x00004000 #define DSPTCHR_PDRAM_DATA_REG_RAM_CNT 0x00000fff extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_REG; #define BBH_TX_COMMON_CONFIGURATIONS_MACTYPE_REG_OFFSET 0x00000000 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_1_TX_REG_OFFSET 0x00000004 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG; #define BBH_TX_COMMON_CONFIGURATIONS_BBCFG_2_TX_REG_OFFSET 0x00000008 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DDRCFG_TX_REG_OFFSET 0x0000000c extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_OFFSET 0x00000010 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_1_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG; #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_OFFSET 0x00000018 #define BBH_TX_COMMON_CONFIGURATIONS_RNRCFG_2_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DMACFG_TX_REG_OFFSET 0x00000020 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG; #define BBH_TX_COMMON_CONFIGURATIONS_SDMACFG_TX_REG_OFFSET 0x00000024 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_REG; #define BBH_TX_COMMON_CONFIGURATIONS_SBPMCFG_REG_OFFSET 0x00000028 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_OFFSET 0x0000002c #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEL_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_OFFSET 0x00000034 #define BBH_TX_COMMON_CONFIGURATIONS_DDRTMBASEH_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DFIFOCTRL_REG_OFFSET 0x0000003c extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_REG; #define BBH_TX_COMMON_CONFIGURATIONS_ARB_CFG_REG_OFFSET 0x00000040 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_REG; #define BBH_TX_COMMON_CONFIGURATIONS_BBROUTE_REG_OFFSET 0x00000044 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_REG; #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_REG_OFFSET 0x00000048 #define BBH_TX_COMMON_CONFIGURATIONS_Q2RNR_REG_RAM_CNT 0x00000013 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_REG; #define BBH_TX_COMMON_CONFIGURATIONS_PERQTASK_REG_OFFSET 0x000000a0 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REG; #define BBH_TX_COMMON_CONFIGURATIONS_TXRSTCMD_REG_OFFSET 0x000000b0 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_REG; #define BBH_TX_COMMON_CONFIGURATIONS_DBGSEL_REG_OFFSET 0x000000b4 extern const ru_reg_rec BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_REG; #define BBH_TX_COMMON_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x000000b8 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDBASE_REG; #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_REG_OFFSET 0x00000100 #define BBH_TX_WAN_CONFIGURATIONS_PDBASE_REG_RAM_CNT 0x00000013 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDSIZE_REG; #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x00000150 #define BBH_TX_WAN_CONFIGURATIONS_PDSIZE_REG_RAM_CNT 0x00000013 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_REG; #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x00000200 #define BBH_TX_WAN_CONFIGURATIONS_PDWKUPH_REG_RAM_CNT 0x00000013 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_REG; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x00000250 #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_REG_RAM_CNT 0x00000013 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG; #define BBH_TX_WAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000300 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_REG; #define BBH_TX_WAN_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000304 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG_OFFSET 0x00000310 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_1_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG; #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG_OFFSET 0x00000320 #define BBH_TX_WAN_CONFIGURATIONS_STSRNRCFG_2_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG_OFFSET 0x00000330 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_1_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG; #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG_OFFSET 0x00000340 #define BBH_TX_WAN_CONFIGURATIONS_MSGRNRCFG_2_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REG; #define BBH_TX_WAN_CONFIGURATIONS_EPNCFG_REG_OFFSET 0x00000350 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_REG; #define BBH_TX_WAN_CONFIGURATIONS_FLOW2PORT_REG_OFFSET 0x00000354 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_TS_REG; #define BBH_TX_WAN_CONFIGURATIONS_TS_REG_OFFSET 0x00000358 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_REG; #define BBH_TX_WAN_CONFIGURATIONS_MAXWLEN_REG_OFFSET 0x00000360 extern const ru_reg_rec BBH_TX_WAN_CONFIGURATIONS_FLUSH_REG; #define BBH_TX_WAN_CONFIGURATIONS_FLUSH_REG_OFFSET 0x00000364 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDBASE_REG; #define BBH_TX_LAN_CONFIGURATIONS_PDBASE_REG_OFFSET 0x00000400 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDSIZE_REG; #define BBH_TX_LAN_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x00000450 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_REG; #define BBH_TX_LAN_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x00000500 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x00000550 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG; #define BBH_TX_LAN_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000600 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_REG; #define BBH_TX_LAN_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000604 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_REG; #define BBH_TX_LAN_CONFIGURATIONS_TXTHRESH_REG_OFFSET 0x00000608 extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_EEE_REG; #define BBH_TX_LAN_CONFIGURATIONS_EEE_REG_OFFSET 0x0000060c extern const ru_reg_rec BBH_TX_LAN_CONFIGURATIONS_TS_REG; #define BBH_TX_LAN_CONFIGURATIONS_TS_REG_OFFSET 0x00000610 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_REG_OFFSET 0x00000700 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDBASE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_REG_OFFSET 0x00000750 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDSIZE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_REG_OFFSET 0x00000800 #define BBH_TX_UNIFIED_CONFIGURATIONS_PDWKUPH_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_REG_OFFSET 0x00000850 #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PD_BYTE_TH_EN_REG_OFFSET 0x00000900 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_PDEMPTY_REG_OFFSET 0x00000904 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_GTXTHRESH_REG_OFFSET 0x00000908 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_EEE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_EEE_REG_OFFSET 0x0000090c extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TS_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_TS_REG_OFFSET 0x00000910 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG_OFFSET 0x00000920 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEBASE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG_OFFSET 0x00000940 #define BBH_TX_UNIFIED_CONFIGURATIONS_FESIZE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG_OFFSET 0x00000960 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDBASE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG_OFFSET 0x00000980 #define BBH_TX_UNIFIED_CONFIGURATIONS_FEPDSIZE_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG_OFFSET 0x000009a0 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXWRR_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG; #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG_OFFSET 0x000009e0 #define BBH_TX_UNIFIED_CONFIGURATIONS_TXTHRESH_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMPD_REG; #define BBH_TX_DEBUG_COUNTERS_SRAMPD_REG_OFFSET 0x00000a00 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRPD_REG; #define BBH_TX_DEBUG_COUNTERS_DDRPD_REG_OFFSET 0x00000a04 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_PDDROP_REG; #define BBH_TX_DEBUG_COUNTERS_PDDROP_REG_OFFSET 0x00000a08 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_STSCNT_REG; #define BBH_TX_DEBUG_COUNTERS_STSCNT_REG_OFFSET 0x00000a10 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_STSDROP_REG; #define BBH_TX_DEBUG_COUNTERS_STSDROP_REG_OFFSET 0x00000a14 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_MSGCNT_REG; #define BBH_TX_DEBUG_COUNTERS_MSGCNT_REG_OFFSET 0x00000a18 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_MSGDROP_REG; #define BBH_TX_DEBUG_COUNTERS_MSGDROP_REG_OFFSET 0x00000a1c extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_REG; #define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL_REG_OFFSET 0x00000a20 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_REG; #define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS_REG_OFFSET 0x00000a24 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_LENERR_REG; #define BBH_TX_DEBUG_COUNTERS_LENERR_REG_OFFSET 0x00000a28 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_AGGRLENERR_REG; #define BBH_TX_DEBUG_COUNTERS_AGGRLENERR_REG_OFFSET 0x00000a2c extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMPKT_REG; #define BBH_TX_DEBUG_COUNTERS_SRAMPKT_REG_OFFSET 0x00000a30 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRPKT_REG; #define BBH_TX_DEBUG_COUNTERS_DDRPKT_REG_OFFSET 0x00000a34 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SRAMBYTE_REG; #define BBH_TX_DEBUG_COUNTERS_SRAMBYTE_REG_OFFSET 0x00000a38 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DDRBYTE_REG; #define BBH_TX_DEBUG_COUNTERS_DDRBYTE_REG_OFFSET 0x00000a3c extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDEN_REG; #define BBH_TX_DEBUG_COUNTERS_SWRDEN_REG_OFFSET 0x00000a40 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDADDR_REG; #define BBH_TX_DEBUG_COUNTERS_SWRDADDR_REG_OFFSET 0x00000a44 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_SWRDDATA_REG; #define BBH_TX_DEBUG_COUNTERS_SWRDDATA_REG_OFFSET 0x00000a48 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG; #define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG_OFFSET 0x00000a50 #define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT_REG_RAM_CNT 0x00000007 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG; #define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG_OFFSET 0x00000a70 #define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE_REG_RAM_CNT 0x00000007 extern const ru_reg_rec BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG; #define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG_OFFSET 0x00000a90 #define BBH_TX_DEBUG_COUNTERS_DBGOUTREG_REG_RAM_CNT 0x0000001f extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_BBCFG_REG; #define BBH_RX_GENERAL_CONFIGURATION_BBCFG_REG_OFFSET 0x00000000 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_REG; #define BBH_RX_GENERAL_CONFIGURATION_DISPVIQ_REG_OFFSET 0x00000004 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_REG; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATALSB_REG_OFFSET 0x00000008 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_REG; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNDATAMSB_REG_OFFSET 0x0000000c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_REG; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKLSB_REG_OFFSET 0x00000010 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_REG; #define BBH_RX_GENERAL_CONFIGURATION_PATTERNMASKMSB_REG_OFFSET 0x00000014 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_REG; #define BBH_RX_GENERAL_CONFIGURATION_EXCLQCFG_REG_OFFSET 0x00000018 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_REG; #define BBH_RX_GENERAL_CONFIGURATION_SDMAADDR_REG_OFFSET 0x0000001c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SDMACFG_REG; #define BBH_RX_GENERAL_CONFIGURATION_SDMACFG_REG_OFFSET 0x00000020 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKT0_REG; #define BBH_RX_GENERAL_CONFIGURATION_MINPKT0_REG_OFFSET 0x00000024 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_REG; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT0_REG_OFFSET 0x00000028 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_REG; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKT1_REG_OFFSET 0x0000002c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_REG; #define BBH_RX_GENERAL_CONFIGURATION_SOPOFFSET_REG_OFFSET 0x00000030 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_REG; #define BBH_RX_GENERAL_CONFIGURATION_FLOWCTRL_REG_OFFSET 0x00000034 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_REG; #define BBH_RX_GENERAL_CONFIGURATION_CRCOMITDIS_REG_OFFSET 0x00000038 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_ENABLE_REG; #define BBH_RX_GENERAL_CONFIGURATION_ENABLE_REG_OFFSET 0x0000003c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_G9991EN_REG; #define BBH_RX_GENERAL_CONFIGURATION_G9991EN_REG_OFFSET 0x00000040 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_REG; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWTH_REG_OFFSET 0x00000044 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_REG; #define BBH_RX_GENERAL_CONFIGURATION_PERFLOWSETS_REG_OFFSET 0x00000048 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_REG; #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL0_REG_OFFSET 0x00000050 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_REG; #define BBH_RX_GENERAL_CONFIGURATION_MINPKTSEL1_REG_OFFSET 0x00000054 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_REG; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL0_REG_OFFSET 0x00000058 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_REG; #define BBH_RX_GENERAL_CONFIGURATION_MAXPKTSEL1_REG_OFFSET 0x0000005c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_MACMODE_REG; #define BBH_RX_GENERAL_CONFIGURATION_MACMODE_REG_OFFSET 0x00000060 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_REG; #define BBH_RX_GENERAL_CONFIGURATION_SBPMCFG_REG_OFFSET 0x00000064 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REG; #define BBH_RX_GENERAL_CONFIGURATION_RXRSTRST_REG_OFFSET 0x00000068 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_REG; #define BBH_RX_GENERAL_CONFIGURATION_RXDBGSEL_REG_OFFSET 0x0000006c extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_REG; #define BBH_RX_GENERAL_CONFIGURATION_BBHRX_RADDR_DECODER_REG_OFFSET 0x00000070 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_NONETH_REG; #define BBH_RX_GENERAL_CONFIGURATION_NONETH_REG_OFFSET 0x00000074 extern const ru_reg_rec BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_REG; #define BBH_RX_GENERAL_CONFIGURATION_CLK_GATE_CNTRL_REG_OFFSET 0x00000078 extern const ru_reg_rec BBH_RX_PM_COUNTERS_INPKT_REG; #define BBH_RX_PM_COUNTERS_INPKT_REG_OFFSET 0x00000100 extern const ru_reg_rec BBH_RX_PM_COUNTERS_THIRDFLOW_REG; #define BBH_RX_PM_COUNTERS_THIRDFLOW_REG_OFFSET 0x00000104 extern const ru_reg_rec BBH_RX_PM_COUNTERS_SOPASOP_REG; #define BBH_RX_PM_COUNTERS_SOPASOP_REG_OFFSET 0x00000108 extern const ru_reg_rec BBH_RX_PM_COUNTERS_TOOSHORT_REG; #define BBH_RX_PM_COUNTERS_TOOSHORT_REG_OFFSET 0x0000010c extern const ru_reg_rec BBH_RX_PM_COUNTERS_TOOLONG_REG; #define BBH_RX_PM_COUNTERS_TOOLONG_REG_OFFSET 0x00000110 extern const ru_reg_rec BBH_RX_PM_COUNTERS_CRCERROR_REG; #define BBH_RX_PM_COUNTERS_CRCERROR_REG_OFFSET 0x00000114 extern const ru_reg_rec BBH_RX_PM_COUNTERS_ENCRYPTERROR_REG; #define BBH_RX_PM_COUNTERS_ENCRYPTERROR_REG_OFFSET 0x00000118 extern const ru_reg_rec BBH_RX_PM_COUNTERS_DISPCONG_REG; #define BBH_RX_PM_COUNTERS_DISPCONG_REG_OFFSET 0x0000011c extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSBPMSBN_REG; #define BBH_RX_PM_COUNTERS_NOSBPMSBN_REG_OFFSET 0x00000124 extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSDMACD_REG; #define BBH_RX_PM_COUNTERS_NOSDMACD_REG_OFFSET 0x0000012c extern const ru_reg_rec BBH_RX_PM_COUNTERS_INPLOAM_REG; #define BBH_RX_PM_COUNTERS_INPLOAM_REG_OFFSET 0x00000130 extern const ru_reg_rec BBH_RX_PM_COUNTERS_CRCERRORPLOAM_REG; #define BBH_RX_PM_COUNTERS_CRCERRORPLOAM_REG_OFFSET 0x00000134 extern const ru_reg_rec BBH_RX_PM_COUNTERS_DISPCONGPLOAM_REG; #define BBH_RX_PM_COUNTERS_DISPCONGPLOAM_REG_OFFSET 0x00000138 extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_REG; #define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM_REG_OFFSET 0x0000013c extern const ru_reg_rec BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_REG; #define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM_REG_OFFSET 0x00000140 extern const ru_reg_rec BBH_RX_PM_COUNTERS_EPONTYPERROR_REG; #define BBH_RX_PM_COUNTERS_EPONTYPERROR_REG_OFFSET 0x00000144 extern const ru_reg_rec BBH_RX_PM_COUNTERS_RUNTERROR_REG; #define BBH_RX_PM_COUNTERS_RUNTERROR_REG_OFFSET 0x00000148 extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0LSB_REG; #define BBH_RX_DEBUG_CNTXTX0LSB_REG_OFFSET 0x00000200 extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0MSB_REG; #define BBH_RX_DEBUG_CNTXTX0MSB_REG_OFFSET 0x00000204 extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1LSB_REG; #define BBH_RX_DEBUG_CNTXTX1LSB_REG_OFFSET 0x00000208 extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1MSB_REG; #define BBH_RX_DEBUG_CNTXTX1MSB_REG_OFFSET 0x0000020c extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX0INGRESS_REG; #define BBH_RX_DEBUG_CNTXTX0INGRESS_REG_OFFSET 0x00000210 extern const ru_reg_rec BBH_RX_DEBUG_CNTXTX1INGRESS_REG; #define BBH_RX_DEBUG_CNTXTX1INGRESS_REG_OFFSET 0x00000214 extern const ru_reg_rec BBH_RX_DEBUG_IBUW_REG; #define BBH_RX_DEBUG_IBUW_REG_OFFSET 0x00000218 extern const ru_reg_rec BBH_RX_DEBUG_BBUW_REG; #define BBH_RX_DEBUG_BBUW_REG_OFFSET 0x0000021c extern const ru_reg_rec BBH_RX_DEBUG_CFUW_REG; #define BBH_RX_DEBUG_CFUW_REG_OFFSET 0x00000220 extern const ru_reg_rec BBH_RX_DEBUG_ACKCNT_REG; #define BBH_RX_DEBUG_ACKCNT_REG_OFFSET 0x00000224 extern const ru_reg_rec BBH_RX_DEBUG_COHERENCYCNT_REG; #define BBH_RX_DEBUG_COHERENCYCNT_REG_OFFSET 0x00000228 extern const ru_reg_rec BBH_RX_DEBUG_DBGVEC_REG; #define BBH_RX_DEBUG_DBGVEC_REG_OFFSET 0x0000022c extern const ru_reg_rec BBH_RX_DEBUG_UFUW_REG; #define BBH_RX_DEBUG_UFUW_REG_OFFSET 0x00000230 extern const ru_reg_rec BBH_RX_DEBUG_CREDITCNT_REG; #define BBH_RX_DEBUG_CREDITCNT_REG_OFFSET 0x00000234 extern const ru_reg_rec BBH_RX_DEBUG_SDMACNT_REG; #define BBH_RX_DEBUG_SDMACNT_REG_OFFSET 0x00000238 extern const ru_reg_rec BBH_RX_DEBUG_CMFUW_REG; #define BBH_RX_DEBUG_CMFUW_REG_OFFSET 0x0000023c extern const ru_reg_rec BBH_RX_DEBUG_SBNFIFO_REG; #define BBH_RX_DEBUG_SBNFIFO_REG_OFFSET 0x00000240 #define BBH_RX_DEBUG_SBNFIFO_REG_RAM_CNT 0x0000000f extern const ru_reg_rec BBH_RX_DEBUG_CMDFIFO_REG; #define BBH_RX_DEBUG_CMDFIFO_REG_OFFSET 0x00000280 #define BBH_RX_DEBUG_CMDFIFO_REG_RAM_CNT 0x00000003 extern const ru_reg_rec BBH_RX_DEBUG_SBNRECYCLEFIFO_REG; #define BBH_RX_DEBUG_SBNRECYCLEFIFO_REG_OFFSET 0x00000290 #define BBH_RX_DEBUG_SBNRECYCLEFIFO_REG_RAM_CNT 0x00000001 extern const ru_reg_rec BBH_RX_DEBUG_COHERENCYCNT2_REG; #define BBH_RX_DEBUG_COHERENCYCNT2_REG_OFFSET 0x000002a0 extern const ru_reg_rec BBH_RX_DEBUG_DROPSTATUS_REG; #define BBH_RX_DEBUG_DROPSTATUS_REG_OFFSET 0x000002a4 extern const ru_reg_rec UBUS_MSTR_EN_REG; #define UBUS_MSTR_EN_REG_OFFSET 0x00000000 extern const ru_reg_rec UBUS_MSTR_REQ_CNTRL_REG; #define UBUS_MSTR_REQ_CNTRL_REG_OFFSET 0x00000004 extern const ru_reg_rec UBUS_MSTR_HYST_CTRL_REG; #define UBUS_MSTR_HYST_CTRL_REG_OFFSET 0x00000008 extern const ru_reg_rec UBUS_MSTR_HP_REG; #define UBUS_MSTR_HP_REG_OFFSET 0x0000000c extern const ru_reg_rec UBUS_MSTR_REPLY_ADD_REG; #define UBUS_MSTR_REPLY_ADD_REG_OFFSET 0x00000010 extern const ru_reg_rec UBUS_MSTR_REPLY_DATA_REG; #define UBUS_MSTR_REPLY_DATA_REG_OFFSET 0x00000014 extern const ru_reg_rec UBUS_SLV_RESERVED_REG; #define UBUS_SLV_RESERVED_REG_OFFSET 0x00000000 extern const ru_reg_rec UBUS_SLV_VPB_BASE_REG; #define UBUS_SLV_VPB_BASE_REG_OFFSET 0x00000004 extern const ru_reg_rec UBUS_SLV_VPB_MASK_REG; #define UBUS_SLV_VPB_MASK_REG_OFFSET 0x00000008 extern const ru_reg_rec UBUS_SLV_APB_BASE_REG; #define UBUS_SLV_APB_BASE_REG_OFFSET 0x0000000c extern const ru_reg_rec UBUS_SLV_APB_MASK_REG; #define UBUS_SLV_APB_MASK_REG_OFFSET 0x00000010 extern const ru_reg_rec UBUS_SLV_DQM_BASE_REG; #define UBUS_SLV_DQM_BASE_REG_OFFSET 0x00000014 extern const ru_reg_rec UBUS_SLV_DQM_MASK_REG; #define UBUS_SLV_DQM_MASK_REG_OFFSET 0x00000018 extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ISR_REG; #define UBUS_SLV_RNR_INTR_CTRL_ISR_REG_OFFSET 0x00000080 extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ISM_REG; #define UBUS_SLV_RNR_INTR_CTRL_ISM_REG_OFFSET 0x00000084 extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_IER_REG; #define UBUS_SLV_RNR_INTR_CTRL_IER_REG_OFFSET 0x00000088 extern const ru_reg_rec UBUS_SLV_RNR_INTR_CTRL_ITR_REG; #define UBUS_SLV_RNR_INTR_CTRL_ITR_REG_OFFSET 0x0000008c extern const ru_reg_rec UBUS_SLV_PROFILING_CFG_REG; #define UBUS_SLV_PROFILING_CFG_REG_OFFSET 0x00000100 extern const ru_reg_rec UBUS_SLV_PROFILING_STATUS_REG; #define UBUS_SLV_PROFILING_STATUS_REG_OFFSET 0x00000104 extern const ru_reg_rec UBUS_SLV_PROFILING_COUNTER_REG; #define UBUS_SLV_PROFILING_COUNTER_REG_OFFSET 0x00000108 extern const ru_reg_rec UBUS_SLV_PROFILING_START_VALUE_REG; #define UBUS_SLV_PROFILING_START_VALUE_REG_OFFSET 0x0000010c extern const ru_reg_rec UBUS_SLV_PROFILING_STOP_VALUE_REG; #define UBUS_SLV_PROFILING_STOP_VALUE_REG_OFFSET 0x00000110 extern const ru_reg_rec UBUS_SLV_PROFILING_CYCLE_NUM_REG; #define UBUS_SLV_PROFILING_CYCLE_NUM_REG_OFFSET 0x00000114 extern const ru_reg_rec UBUS_SLV__CNTRL_REG; #define UBUS_SLV__CNTRL_REG_OFFSET 0x00000300 extern const ru_reg_rec UBUS_SLV__IB_STATUS_REG; #define UBUS_SLV__IB_STATUS_REG_OFFSET 0x00000304 extern const ru_reg_rec UBUS_SLV__RX_CLOCK_DELAY_CNTRL_REG; #define UBUS_SLV__RX_CLOCK_DELAY_CNTRL_REG_OFFSET 0x00000308 extern const ru_reg_rec UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_REG; #define UBUS_SLV__ATE_RX_CNTRL_EXP_DATA_REG_OFFSET 0x0000030c extern const ru_reg_rec UBUS_SLV__ATE_RX_EXP_DATA_1_REG; #define UBUS_SLV__ATE_RX_EXP_DATA_1_REG_OFFSET 0x00000310 extern const ru_reg_rec UBUS_SLV__ATE_RX_STATUS_0_REG; #define UBUS_SLV__ATE_RX_STATUS_0_REG_OFFSET 0x00000314 extern const ru_reg_rec UBUS_SLV__ATE_RX_STATUS_1_REG; #define UBUS_SLV__ATE_RX_STATUS_1_REG_OFFSET 0x00000318 extern const ru_reg_rec UBUS_SLV__ATE_TX_CNTRL_REG; #define UBUS_SLV__ATE_TX_CNTRL_REG_OFFSET 0x0000031c extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_0_REG; #define UBUS_SLV__ATE_TX_DATA_0_REG_OFFSET 0x00000320 extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_1_REG; #define UBUS_SLV__ATE_TX_DATA_1_REG_OFFSET 0x00000324 extern const ru_reg_rec UBUS_SLV__ATE_TX_DATA_2_REG; #define UBUS_SLV__ATE_TX_DATA_2_REG_OFFSET 0x00000328 extern const ru_reg_rec UBUS_SLV__TX_DELAY_CNTRL_0_REG; #define UBUS_SLV__TX_DELAY_CNTRL_0_REG_OFFSET 0x0000032c extern const ru_reg_rec UBUS_SLV__TX_DELAY_CNTRL_1_REG; #define UBUS_SLV__TX_DELAY_CNTRL_1_REG_OFFSET 0x00000330 extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_0_REG; #define UBUS_SLV__RX_DELAY_CNTRL_0_REG_OFFSET 0x00000334 extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_1_REG; #define UBUS_SLV__RX_DELAY_CNTRL_1_REG_OFFSET 0x00000338 extern const ru_reg_rec UBUS_SLV__RX_DELAY_CNTRL_2_REG; #define UBUS_SLV__RX_DELAY_CNTRL_2_REG_OFFSET 0x0000033c extern const ru_reg_rec UBUS_SLV__CLK_RST_CTRL_REG; #define UBUS_SLV__CLK_RST_CTRL_REG_OFFSET 0x00000340 extern const ru_reg_rec SBPM_REGS_INIT_FREE_LIST_REG; #define SBPM_REGS_INIT_FREE_LIST_REG_OFFSET 0x00000000 extern const ru_reg_rec SBPM_REGS_BN_ALLOC_REG; #define SBPM_REGS_BN_ALLOC_REG_OFFSET 0x00000004 extern const ru_reg_rec SBPM_REGS_BN_ALLOC_RPLY_REG; #define SBPM_REGS_BN_ALLOC_RPLY_REG_OFFSET 0x00000008 extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_REG; #define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW_REG_OFFSET 0x0000000c extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_REG; #define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH_REG_OFFSET 0x00000010 extern const ru_reg_rec SBPM_REGS_MCST_INC_REG; #define SBPM_REGS_MCST_INC_REG_OFFSET 0x00000014 extern const ru_reg_rec SBPM_REGS_MCST_INC_RPLY_REG; #define SBPM_REGS_MCST_INC_RPLY_REG_OFFSET 0x00000018 extern const ru_reg_rec SBPM_REGS_BN_CONNECT_REG; #define SBPM_REGS_BN_CONNECT_REG_OFFSET 0x0000001c extern const ru_reg_rec SBPM_REGS_BN_CONNECT_RPLY_REG; #define SBPM_REGS_BN_CONNECT_RPLY_REG_OFFSET 0x00000020 extern const ru_reg_rec SBPM_REGS_GET_NEXT_REG; #define SBPM_REGS_GET_NEXT_REG_OFFSET 0x00000024 extern const ru_reg_rec SBPM_REGS_GET_NEXT_RPLY_REG; #define SBPM_REGS_GET_NEXT_RPLY_REG_OFFSET 0x00000028 extern const ru_reg_rec SBPM_REGS_SBPM_CLK_GATE_CNTRL_REG; #define SBPM_REGS_SBPM_CLK_GATE_CNTRL_REG_OFFSET 0x0000002c extern const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_REG_OFFSET 0x00000038 extern const ru_reg_rec SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG; #define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY_REG_OFFSET 0x0000003c extern const ru_reg_rec SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_REG; #define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY_REG_OFFSET 0x00000040 extern const ru_reg_rec SBPM_REGS_SBPM_GL_TRSH_REG; #define SBPM_REGS_SBPM_GL_TRSH_REG_OFFSET 0x0000004c extern const ru_reg_rec SBPM_REGS_SBPM_UG0_TRSH_REG; #define SBPM_REGS_SBPM_UG0_TRSH_REG_OFFSET 0x00000050 extern const ru_reg_rec SBPM_REGS_SBPM_UG1_TRSH_REG; #define SBPM_REGS_SBPM_UG1_TRSH_REG_OFFSET 0x00000054 extern const ru_reg_rec SBPM_REGS_SBPM_DBG_REG; #define SBPM_REGS_SBPM_DBG_REG_OFFSET 0x00000074 extern const ru_reg_rec SBPM_REGS_SBPM_UG0_BAC_REG; #define SBPM_REGS_SBPM_UG0_BAC_REG_OFFSET 0x00000078 extern const ru_reg_rec SBPM_REGS_SBPM_UG1_BAC_REG; #define SBPM_REGS_SBPM_UG1_BAC_REG_OFFSET 0x0000007c extern const ru_reg_rec SBPM_REGS_SBPM_GL_BAC_REG; #define SBPM_REGS_SBPM_GL_BAC_REG_OFFSET 0x00000098 extern const ru_reg_rec SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_REG; #define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH_REG_OFFSET 0x0000009c extern const ru_reg_rec SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_REG; #define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH_REG_OFFSET 0x00000100 extern const ru_reg_rec SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_REG; #define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH_REG_OFFSET 0x00000104 extern const ru_reg_rec SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_REG; #define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH_REG_OFFSET 0x00000108 extern const ru_reg_rec SBPM_REGS_SBPM_UG_STATUS_REG; #define SBPM_REGS_SBPM_UG_STATUS_REG_OFFSET 0x0000011c extern const ru_reg_rec SBPM_REGS_ERROR_HANDLING_PARAMS_REG; #define SBPM_REGS_ERROR_HANDLING_PARAMS_REG_OFFSET 0x00000138 extern const ru_reg_rec SBPM_REGS_SBPM_IIR_LOW_REG; #define SBPM_REGS_SBPM_IIR_LOW_REG_OFFSET 0x00000148 extern const ru_reg_rec SBPM_REGS_SBPM_IIR_HIGH_REG; #define SBPM_REGS_SBPM_IIR_HIGH_REG_OFFSET 0x0000014c extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC0_REG; #define SBPM_REGS_SBPM_DBG_VEC0_REG_OFFSET 0x00000150 extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC1_REG; #define SBPM_REGS_SBPM_DBG_VEC1_REG_OFFSET 0x00000154 extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC2_REG; #define SBPM_REGS_SBPM_DBG_VEC2_REG_OFFSET 0x00000174 extern const ru_reg_rec SBPM_REGS_SBPM_DBG_VEC3_REG; #define SBPM_REGS_SBPM_DBG_VEC3_REG_OFFSET 0x00000178 extern const ru_reg_rec SBPM_REGS_SBPM_SP_BBH_LOW_REG; #define SBPM_REGS_SBPM_SP_BBH_LOW_REG_OFFSET 0x0000017c extern const ru_reg_rec SBPM_REGS_SBPM_SP_BBH_HIGH_REG; #define SBPM_REGS_SBPM_SP_BBH_HIGH_REG_OFFSET 0x00000180 extern const ru_reg_rec SBPM_REGS_SBPM_SP_RNR_LOW_REG; #define SBPM_REGS_SBPM_SP_RNR_LOW_REG_OFFSET 0x00000184 extern const ru_reg_rec SBPM_REGS_SBPM_SP_RNR_HIGH_REG; #define SBPM_REGS_SBPM_SP_RNR_HIGH_REG_OFFSET 0x00000188 extern const ru_reg_rec SBPM_REGS_SBPM_UG_MAP_LOW_REG; #define SBPM_REGS_SBPM_UG_MAP_LOW_REG_OFFSET 0x0000018c extern const ru_reg_rec SBPM_REGS_SBPM_UG_MAP_HIGH_REG; #define SBPM_REGS_SBPM_UG_MAP_HIGH_REG_OFFSET 0x00000190 extern const ru_reg_rec SBPM_REGS_SBPM_NACK_MASK_LOW_REG; #define SBPM_REGS_SBPM_NACK_MASK_LOW_REG_OFFSET 0x00000194 extern const ru_reg_rec SBPM_REGS_SBPM_NACK_MASK_HIGH_REG; #define SBPM_REGS_SBPM_NACK_MASK_HIGH_REG_OFFSET 0x00000198 extern const ru_reg_rec SBPM_REGS_SBPM_EXCL_MASK_LOW_REG; #define SBPM_REGS_SBPM_EXCL_MASK_LOW_REG_OFFSET 0x0000019c extern const ru_reg_rec SBPM_REGS_SBPM_EXCL_MASK_HIGH_REG; #define SBPM_REGS_SBPM_EXCL_MASK_HIGH_REG_OFFSET 0x000001a0 extern const ru_reg_rec SBPM_REGS_SBPM_RADDR_DECODER_REG; #define SBPM_REGS_SBPM_RADDR_DECODER_REG_OFFSET 0x000001a4 extern const ru_reg_rec SBPM_REGS_SBPM_WR_DATA_REG; #define SBPM_REGS_SBPM_WR_DATA_REG_OFFSET 0x000001a8 extern const ru_reg_rec SBPM_REGS_SBPM_UG_BAC_MAX_REG; #define SBPM_REGS_SBPM_UG_BAC_MAX_REG_OFFSET 0x000001ac extern const ru_reg_rec SBPM_REGS_SBPM_SPARE_REG; #define SBPM_REGS_SBPM_SPARE_REG_OFFSET 0x000001b0 extern const ru_reg_rec SBPM_INTR_CTRL_ISR_REG; #define SBPM_INTR_CTRL_ISR_REG_OFFSET 0x00000200 extern const ru_reg_rec SBPM_INTR_CTRL_ISM_REG; #define SBPM_INTR_CTRL_ISM_REG_OFFSET 0x00000204 extern const ru_reg_rec SBPM_INTR_CTRL_IER_REG; #define SBPM_INTR_CTRL_IER_REG_OFFSET 0x00000208 extern const ru_reg_rec SBPM_INTR_CTRL_ITR_REG; #define SBPM_INTR_CTRL_ITR_REG_OFFSET 0x0000020c extern const ru_reg_rec DMA_CONFIG_BBROUTEOVRD_REG; #define DMA_CONFIG_BBROUTEOVRD_REG_OFFSET 0x00000000 extern const ru_reg_rec DMA_CONFIG_NUM_OF_WRITES_REG; #define DMA_CONFIG_NUM_OF_WRITES_REG_OFFSET 0x00000004 #define DMA_CONFIG_NUM_OF_WRITES_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_NUM_OF_READS_REG; #define DMA_CONFIG_NUM_OF_READS_REG_OFFSET 0x00000024 #define DMA_CONFIG_NUM_OF_READS_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_U_THRESH_REG; #define DMA_CONFIG_U_THRESH_REG_OFFSET 0x00000044 #define DMA_CONFIG_U_THRESH_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_PRI_REG; #define DMA_CONFIG_PRI_REG_OFFSET 0x00000064 #define DMA_CONFIG_PRI_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_PERIPH_SOURCE_REG; #define DMA_CONFIG_PERIPH_SOURCE_REG_OFFSET 0x00000084 #define DMA_CONFIG_PERIPH_SOURCE_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_WEIGHT_REG; #define DMA_CONFIG_WEIGHT_REG_OFFSET 0x000000a4 #define DMA_CONFIG_WEIGHT_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_CONFIG_PTRRST_REG; #define DMA_CONFIG_PTRRST_REG_OFFSET 0x000000d0 extern const ru_reg_rec DMA_CONFIG_MAX_OTF_REG; #define DMA_CONFIG_MAX_OTF_REG_OFFSET 0x000000d4 extern const ru_reg_rec DMA_CONFIG_CLK_GATE_CNTRL_REG; #define DMA_CONFIG_CLK_GATE_CNTRL_REG_OFFSET 0x000000d8 extern const ru_reg_rec DMA_CONFIG_DBG_SEL_REG; #define DMA_CONFIG_DBG_SEL_REG_OFFSET 0x000000e0 extern const ru_reg_rec DMA_DEBUG_NEMPTY_REG; #define DMA_DEBUG_NEMPTY_REG_OFFSET 0x00000100 extern const ru_reg_rec DMA_DEBUG_URGNT_REG; #define DMA_DEBUG_URGNT_REG_OFFSET 0x00000104 extern const ru_reg_rec DMA_DEBUG_SELSRC_REG; #define DMA_DEBUG_SELSRC_REG_OFFSET 0x00000108 extern const ru_reg_rec DMA_DEBUG_REQ_CNT_RX_REG; #define DMA_DEBUG_REQ_CNT_RX_REG_OFFSET 0x00000110 #define DMA_DEBUG_REQ_CNT_RX_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_DEBUG_REQ_CNT_TX_REG; #define DMA_DEBUG_REQ_CNT_TX_REG_OFFSET 0x00000130 #define DMA_DEBUG_REQ_CNT_TX_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_DEBUG_REQ_CNT_RX_ACC_REG; #define DMA_DEBUG_REQ_CNT_RX_ACC_REG_OFFSET 0x00000150 #define DMA_DEBUG_REQ_CNT_RX_ACC_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_DEBUG_REQ_CNT_TX_ACC_REG; #define DMA_DEBUG_REQ_CNT_TX_ACC_REG_OFFSET 0x00000170 #define DMA_DEBUG_REQ_CNT_TX_ACC_REG_RAM_CNT 0x00000007 extern const ru_reg_rec DMA_DEBUG_RDADD_REG; #define DMA_DEBUG_RDADD_REG_OFFSET 0x00000200 extern const ru_reg_rec DMA_DEBUG_RDVALID_REG; #define DMA_DEBUG_RDVALID_REG_OFFSET 0x00000204 extern const ru_reg_rec DMA_DEBUG_RDDATA_REG; #define DMA_DEBUG_RDDATA_REG_OFFSET 0x00000208 #define DMA_DEBUG_RDDATA_REG_RAM_CNT 0x00000003 extern const ru_reg_rec DMA_DEBUG_RDDATARDY_REG; #define DMA_DEBUG_RDDATARDY_REG_OFFSET 0x00000218 extern const ru_reg_rec PSRAM_MEMORY_DATA_REG; #define PSRAM_MEMORY_DATA_REG_OFFSET 0x00000000 #define PSRAM_MEMORY_DATA_REG_RAM_CNT 0x0000bfff extern const ru_reg_rec PSRAM_CONFIGURATIONS_CTRL_REG; #define PSRAM_CONFIGURATIONS_CTRL_REG_OFFSET 0x00799000 extern const ru_reg_rec PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_REG; #define PSRAM_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x0079900c extern const ru_reg_rec PSRAM_PM_COUNTERS_MUEN_REG; #define PSRAM_PM_COUNTERS_MUEN_REG_OFFSET 0x00799100 extern const ru_reg_rec PSRAM_PM_COUNTERS_BWCL_REG; #define PSRAM_PM_COUNTERS_BWCL_REG_OFFSET 0x00799104 extern const ru_reg_rec PSRAM_PM_COUNTERS_BWEN_REG; #define PSRAM_PM_COUNTERS_BWEN_REG_OFFSET 0x00799108 extern const ru_reg_rec PSRAM_PM_COUNTERS_MAX_TIME_REG; #define PSRAM_PM_COUNTERS_MAX_TIME_REG_OFFSET 0x00799110 #define PSRAM_PM_COUNTERS_MAX_TIME_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_ACC_TIME_REG; #define PSRAM_PM_COUNTERS_ACC_TIME_REG_OFFSET 0x00799130 #define PSRAM_PM_COUNTERS_ACC_TIME_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_ACC_REQ_REG; #define PSRAM_PM_COUNTERS_ACC_REQ_REG_OFFSET 0x00799150 #define PSRAM_PM_COUNTERS_ACC_REQ_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG; #define PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG_OFFSET 0x00799170 #define PSRAM_PM_COUNTERS_LAST_ACC_TIME_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG; #define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG_OFFSET 0x00799190 #define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_REG; #define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_REG_OFFSET 0x007991b0 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_REG; #define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_REG_OFFSET 0x007991b4 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_REG; #define PSRAM_PM_COUNTERS_BW_WR_CNT_REG_OFFSET 0x007991b8 #define PSRAM_PM_COUNTERS_BW_WR_CNT_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_REG; #define PSRAM_PM_COUNTERS_BW_RD_CNT_REG_OFFSET 0x007991d8 #define PSRAM_PM_COUNTERS_BW_RD_CNT_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_REG; #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_REG_OFFSET 0x007991f8 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_REG; #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_REG_OFFSET 0x007991fc extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG; #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG_OFFSET 0x00799200 #define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG; #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG_OFFSET 0x00799220 #define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_REG_RAM_CNT 0x00000006 extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_REQ_REG; #define PSRAM_PM_COUNTERS_ARB_REQ_REG_OFFSET 0x00799240 extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_ARB_REG; #define PSRAM_PM_COUNTERS_ARB_ARB_REG_OFFSET 0x00799244 extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_REG; #define PSRAM_PM_COUNTERS_ARB_COMB_REG_OFFSET 0x00799248 extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_4_REG; #define PSRAM_PM_COUNTERS_ARB_COMB_4_REG_OFFSET 0x0079924c extern const ru_reg_rec PSRAM_PM_COUNTERS_ARB_COMB_BANKS_REG; #define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_REG_OFFSET 0x00799250 extern const ru_reg_rec PSRAM_DEBUG_DBGSEL_REG; #define PSRAM_DEBUG_DBGSEL_REG_OFFSET 0x00799300 extern const ru_reg_rec PSRAM_DEBUG_DBGBUS_REG; #define PSRAM_DEBUG_DBGBUS_REG_OFFSET 0x00799304 extern const ru_reg_rec PSRAM_DEBUG_REQ_VEC_REG; #define PSRAM_DEBUG_REQ_VEC_REG_OFFSET 0x00799308 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_CFG1_REG; #define PSRAM_DEBUG_DBG_CAP_CFG1_REG_OFFSET 0x00799380 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_CFG2_REG; #define PSRAM_DEBUG_DBG_CAP_CFG2_REG_OFFSET 0x00799384 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_ST_REG; #define PSRAM_DEBUG_DBG_CAP_ST_REG_OFFSET 0x00799388 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W0_REG; #define PSRAM_DEBUG_DBG_CAP_W0_REG_OFFSET 0x00799390 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W1_REG; #define PSRAM_DEBUG_DBG_CAP_W1_REG_OFFSET 0x00799394 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W2_REG; #define PSRAM_DEBUG_DBG_CAP_W2_REG_OFFSET 0x00799398 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_W3_REG; #define PSRAM_DEBUG_DBG_CAP_W3_REG_OFFSET 0x0079939c extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_WMSK_REG; #define PSRAM_DEBUG_DBG_CAP_WMSK_REG_OFFSET 0x007993a0 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R0_REG; #define PSRAM_DEBUG_DBG_CAP_R0_REG_OFFSET 0x007993b0 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R1_REG; #define PSRAM_DEBUG_DBG_CAP_R1_REG_OFFSET 0x007993b4 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R2_REG; #define PSRAM_DEBUG_DBG_CAP_R2_REG_OFFSET 0x007993b8 extern const ru_reg_rec PSRAM_DEBUG_DBG_CAP_R3_REG; #define PSRAM_DEBUG_DBG_CAP_R3_REG_OFFSET 0x007993bc extern const ru_reg_rec UNIMAC_RDP_UMAC_DUMMY_REG; #define UNIMAC_RDP_UMAC_DUMMY_REG_OFFSET 0x00000000 extern const ru_reg_rec UNIMAC_RDP_HD_BKP_CNTL_REG; #define UNIMAC_RDP_HD_BKP_CNTL_REG_OFFSET 0x00000004 extern const ru_reg_rec UNIMAC_RDP_CMD_REG; #define UNIMAC_RDP_CMD_REG_OFFSET 0x00000008 extern const ru_reg_rec UNIMAC_RDP_MAC0_REG; #define UNIMAC_RDP_MAC0_REG_OFFSET 0x0000000c extern const ru_reg_rec UNIMAC_RDP_MAC1_REG; #define UNIMAC_RDP_MAC1_REG_OFFSET 0x00000010 extern const ru_reg_rec UNIMAC_RDP_FRM_LEN_REG; #define UNIMAC_RDP_FRM_LEN_REG_OFFSET 0x00000014 extern const ru_reg_rec UNIMAC_RDP_PAUSE_QUNAT_REG; #define UNIMAC_RDP_PAUSE_QUNAT_REG_OFFSET 0x00000018 extern const ru_reg_rec UNIMAC_RDP_SFD_OFFSET_REG; #define UNIMAC_RDP_SFD_OFFSET_REG_OFFSET 0x00000040 extern const ru_reg_rec UNIMAC_RDP_MODE_REG; #define UNIMAC_RDP_MODE_REG_OFFSET 0x00000044 extern const ru_reg_rec UNIMAC_RDP_FRM_TAG0_REG; #define UNIMAC_RDP_FRM_TAG0_REG_OFFSET 0x00000048 extern const ru_reg_rec UNIMAC_RDP_FRM_TAG1_REG; #define UNIMAC_RDP_FRM_TAG1_REG_OFFSET 0x0000004c extern const ru_reg_rec UNIMAC_RDP_TX_IPG_LEN_REG; #define UNIMAC_RDP_TX_IPG_LEN_REG_OFFSET 0x0000005c extern const ru_reg_rec UNIMAC_RDP_EEE_CTRL_REG; #define UNIMAC_RDP_EEE_CTRL_REG_OFFSET 0x00000064 extern const ru_reg_rec UNIMAC_RDP_EEE_LPI_TIMER_REG; #define UNIMAC_RDP_EEE_LPI_TIMER_REG_OFFSET 0x00000068 extern const ru_reg_rec UNIMAC_RDP_EEE_WAKE_TIMER_REG; #define UNIMAC_RDP_EEE_WAKE_TIMER_REG_OFFSET 0x0000006c extern const ru_reg_rec UNIMAC_RDP_EEE_REF_COUNT_REG; #define UNIMAC_RDP_EEE_REF_COUNT_REG_OFFSET 0x00000070 extern const ru_reg_rec UNIMAC_RDP_RX_PKT_DROP_STATUS_REG; #define UNIMAC_RDP_RX_PKT_DROP_STATUS_REG_OFFSET 0x00000078 extern const ru_reg_rec UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_REG; #define UNIMAC_RDP_SYMMETRIC_IDLE_THRESHOLD_REG_OFFSET 0x0000007c extern const ru_reg_rec UNIMAC_RDP_MACSEC_PROG_TX_CRC_REG; #define UNIMAC_RDP_MACSEC_PROG_TX_CRC_REG_OFFSET 0x00000310 extern const ru_reg_rec UNIMAC_RDP_MACSEC_CNTRL_REG; #define UNIMAC_RDP_MACSEC_CNTRL_REG_OFFSET 0x00000314 extern const ru_reg_rec UNIMAC_RDP_TS_STATUS_CNTRL_REG; #define UNIMAC_RDP_TS_STATUS_CNTRL_REG_OFFSET 0x00000318 extern const ru_reg_rec UNIMAC_RDP_TX_TS_DATA_REG; #define UNIMAC_RDP_TX_TS_DATA_REG_OFFSET 0x0000031c extern const ru_reg_rec UNIMAC_RDP_PAUSE_CNTRL_REG; #define UNIMAC_RDP_PAUSE_CNTRL_REG_OFFSET 0x00000330 extern const ru_reg_rec UNIMAC_RDP_TXFIFO_FLUSH_REG; #define UNIMAC_RDP_TXFIFO_FLUSH_REG_OFFSET 0x00000334 extern const ru_reg_rec UNIMAC_RDP_RXFIFO_STAT_REG; #define UNIMAC_RDP_RXFIFO_STAT_REG_OFFSET 0x00000338 extern const ru_reg_rec UNIMAC_RDP_TXFIFO_STAT_REG; #define UNIMAC_RDP_TXFIFO_STAT_REG_OFFSET 0x0000033c extern const ru_reg_rec UNIMAC_RDP_PPP_CNTRL_REG; #define UNIMAC_RDP_PPP_CNTRL_REG_OFFSET 0x00000340 extern const ru_reg_rec UNIMAC_RDP_PPP_REFRESH_CNTRL_REG; #define UNIMAC_RDP_PPP_REFRESH_CNTRL_REG_OFFSET 0x00000344 extern const ru_reg_rec UNIMAC_RDP_TX_PAUSE_PREL0_REG; #define UNIMAC_RDP_TX_PAUSE_PREL0_REG_OFFSET 0x00000348 extern const ru_reg_rec UNIMAC_RDP_TX_PAUSE_PREL1_REG; #define UNIMAC_RDP_TX_PAUSE_PREL1_REG_OFFSET 0x0000034c extern const ru_reg_rec UNIMAC_RDP_TX_PAUSE_PREL2_REG; #define UNIMAC_RDP_TX_PAUSE_PREL2_REG_OFFSET 0x00000350 extern const ru_reg_rec UNIMAC_RDP_TX_PAUSE_PREL3_REG; #define UNIMAC_RDP_TX_PAUSE_PREL3_REG_OFFSET 0x00000354 extern const ru_reg_rec UNIMAC_RDP_RX_PAUSE_PREL0_REG; #define UNIMAC_RDP_RX_PAUSE_PREL0_REG_OFFSET 0x00000358 extern const ru_reg_rec UNIMAC_RDP_RX_PAUSE_PREL1_REG; #define UNIMAC_RDP_RX_PAUSE_PREL1_REG_OFFSET 0x0000035c extern const ru_reg_rec UNIMAC_RDP_RX_PAUSE_PREL2_REG; #define UNIMAC_RDP_RX_PAUSE_PREL2_REG_OFFSET 0x00000360 extern const ru_reg_rec UNIMAC_RDP_RX_PAUSE_PREL3_REG; #define UNIMAC_RDP_RX_PAUSE_PREL3_REG_OFFSET 0x00000364 extern const ru_reg_rec UNIMAC_RDP_RXERR_MASK_REG; #define UNIMAC_RDP_RXERR_MASK_REG_OFFSET 0x00000604 extern const ru_reg_rec UNIMAC_RDP_RX_MAX_PKT_SIZE_REG; #define UNIMAC_RDP_RX_MAX_PKT_SIZE_REG_OFFSET 0x00000608 extern const ru_reg_rec UNIMAC_RDP_MDIO_CMD_REG; #define UNIMAC_RDP_MDIO_CMD_REG_OFFSET 0x00000614 extern const ru_reg_rec UNIMAC_RDP_MDIO_CFG_REG; #define UNIMAC_RDP_MDIO_CFG_REG_OFFSET 0x00000618 extern const ru_reg_rec UNIMAC_RDP_MDF_CNT_REG; #define UNIMAC_RDP_MDF_CNT_REG_OFFSET 0x00000638 extern const ru_reg_rec UNIMAC_RDP_DIAG_SEL_REG; #define UNIMAC_RDP_DIAG_SEL_REG_OFFSET 0x0000064c extern const ru_reg_rec UNIMAC_MIB_GR64_REG; #define UNIMAC_MIB_GR64_REG_OFFSET 0x00000000 extern const ru_reg_rec UNIMAC_MIB_GR127_REG; #define UNIMAC_MIB_GR127_REG_OFFSET 0x00000004 extern const ru_reg_rec UNIMAC_MIB_GR255_REG; #define UNIMAC_MIB_GR255_REG_OFFSET 0x00000008 extern const ru_reg_rec UNIMAC_MIB_GR511_REG; #define UNIMAC_MIB_GR511_REG_OFFSET 0x0000000c extern const ru_reg_rec UNIMAC_MIB_GR1023_REG; #define UNIMAC_MIB_GR1023_REG_OFFSET 0x00000010 extern const ru_reg_rec UNIMAC_MIB_GR1518_REG; #define UNIMAC_MIB_GR1518_REG_OFFSET 0x00000014 extern const ru_reg_rec UNIMAC_MIB_GRMGV_REG; #define UNIMAC_MIB_GRMGV_REG_OFFSET 0x00000018 extern const ru_reg_rec UNIMAC_MIB_GR2047_REG; #define UNIMAC_MIB_GR2047_REG_OFFSET 0x0000001c extern const ru_reg_rec UNIMAC_MIB_GR4095_REG; #define UNIMAC_MIB_GR4095_REG_OFFSET 0x00000020 extern const ru_reg_rec UNIMAC_MIB_GR9216_REG; #define UNIMAC_MIB_GR9216_REG_OFFSET 0x00000024 extern const ru_reg_rec UNIMAC_MIB_GRPKT_REG; #define UNIMAC_MIB_GRPKT_REG_OFFSET 0x00000028 extern const ru_reg_rec UNIMAC_MIB_GRBYT_REG; #define UNIMAC_MIB_GRBYT_REG_OFFSET 0x0000002c extern const ru_reg_rec UNIMAC_MIB_GRMCA_REG; #define UNIMAC_MIB_GRMCA_REG_OFFSET 0x00000030 extern const ru_reg_rec UNIMAC_MIB_GRBCA_REG; #define UNIMAC_MIB_GRBCA_REG_OFFSET 0x00000034 extern const ru_reg_rec UNIMAC_MIB_GRFCS_REG; #define UNIMAC_MIB_GRFCS_REG_OFFSET 0x00000038 extern const ru_reg_rec UNIMAC_MIB_GRXCF_REG; #define UNIMAC_MIB_GRXCF_REG_OFFSET 0x0000003c extern const ru_reg_rec UNIMAC_MIB_GRXPF_REG; #define UNIMAC_MIB_GRXPF_REG_OFFSET 0x00000040 extern const ru_reg_rec UNIMAC_MIB_GRXUO_REG; #define UNIMAC_MIB_GRXUO_REG_OFFSET 0x00000044 extern const ru_reg_rec UNIMAC_MIB_GRALN_REG; #define UNIMAC_MIB_GRALN_REG_OFFSET 0x00000048 extern const ru_reg_rec UNIMAC_MIB_GRFLR_REG; #define UNIMAC_MIB_GRFLR_REG_OFFSET 0x0000004c extern const ru_reg_rec UNIMAC_MIB_GRCDE_REG; #define UNIMAC_MIB_GRCDE_REG_OFFSET 0x00000050 extern const ru_reg_rec UNIMAC_MIB_GRFCR_REG; #define UNIMAC_MIB_GRFCR_REG_OFFSET 0x00000054 extern const ru_reg_rec UNIMAC_MIB_GROVR_REG; #define UNIMAC_MIB_GROVR_REG_OFFSET 0x00000058 extern const ru_reg_rec UNIMAC_MIB_GRJBR_REG; #define UNIMAC_MIB_GRJBR_REG_OFFSET 0x0000005c extern const ru_reg_rec UNIMAC_MIB_GRMTUE_REG; #define UNIMAC_MIB_GRMTUE_REG_OFFSET 0x00000060 extern const ru_reg_rec UNIMAC_MIB_GRPOK_REG; #define UNIMAC_MIB_GRPOK_REG_OFFSET 0x00000064 extern const ru_reg_rec UNIMAC_MIB_GRUC_REG; #define UNIMAC_MIB_GRUC_REG_OFFSET 0x00000068 extern const ru_reg_rec UNIMAC_MIB_GRPPP_REG; #define UNIMAC_MIB_GRPPP_REG_OFFSET 0x0000006c extern const ru_reg_rec UNIMAC_MIB_GRCRC_REG; #define UNIMAC_MIB_GRCRC_REG_OFFSET 0x00000070 extern const ru_reg_rec UNIMAC_MIB_TR64_REG; #define UNIMAC_MIB_TR64_REG_OFFSET 0x00000080 extern const ru_reg_rec UNIMAC_MIB_TR127_REG; #define UNIMAC_MIB_TR127_REG_OFFSET 0x00000084 extern const ru_reg_rec UNIMAC_MIB_TR255_REG; #define UNIMAC_MIB_TR255_REG_OFFSET 0x00000088 extern const ru_reg_rec UNIMAC_MIB_TR511_REG; #define UNIMAC_MIB_TR511_REG_OFFSET 0x0000008c extern const ru_reg_rec UNIMAC_MIB_TR1023_REG; #define UNIMAC_MIB_TR1023_REG_OFFSET 0x00000090 extern const ru_reg_rec UNIMAC_MIB_TR1518_REG; #define UNIMAC_MIB_TR1518_REG_OFFSET 0x00000094 extern const ru_reg_rec UNIMAC_MIB_TRMGV_REG; #define UNIMAC_MIB_TRMGV_REG_OFFSET 0x00000098 extern const ru_reg_rec UNIMAC_MIB_TR2047_REG; #define UNIMAC_MIB_TR2047_REG_OFFSET 0x0000009c extern const ru_reg_rec UNIMAC_MIB_RRPKT_REG; #define UNIMAC_MIB_RRPKT_REG_OFFSET 0x00000100 extern const ru_reg_rec UNIMAC_MIB_RRUND_REG; #define UNIMAC_MIB_RRUND_REG_OFFSET 0x00000104 extern const ru_reg_rec UNIMAC_MIB_RRFRG_REG; #define UNIMAC_MIB_RRFRG_REG_OFFSET 0x00000108 extern const ru_reg_rec UNIMAC_MIB_RRBYT_REG; #define UNIMAC_MIB_RRBYT_REG_OFFSET 0x0000010c extern const ru_reg_rec UNIMAC_MIB_MIB_CNTRL_REG; #define UNIMAC_MIB_MIB_CNTRL_REG_OFFSET 0x00000180 extern const ru_reg_rec UNIMAC_MIB_TR4095_REG; #define UNIMAC_MIB_TR4095_REG_OFFSET 0x000000a0 extern const ru_reg_rec UNIMAC_MIB_TR9216_REG; #define UNIMAC_MIB_TR9216_REG_OFFSET 0x000000a4 extern const ru_reg_rec UNIMAC_MIB_GTPKT_REG; #define UNIMAC_MIB_GTPKT_REG_OFFSET 0x000000a8 extern const ru_reg_rec UNIMAC_MIB_GTMCA_REG; #define UNIMAC_MIB_GTMCA_REG_OFFSET 0x000000ac extern const ru_reg_rec UNIMAC_MIB_GTBCA_REG; #define UNIMAC_MIB_GTBCA_REG_OFFSET 0x000000b0 extern const ru_reg_rec UNIMAC_MIB_GTXPF_REG; #define UNIMAC_MIB_GTXPF_REG_OFFSET 0x000000b4 extern const ru_reg_rec UNIMAC_MIB_GTXCF_REG; #define UNIMAC_MIB_GTXCF_REG_OFFSET 0x000000b8 extern const ru_reg_rec UNIMAC_MIB_GTFCS_REG; #define UNIMAC_MIB_GTFCS_REG_OFFSET 0x000000bc extern const ru_reg_rec UNIMAC_MIB_GTOVR_REG; #define UNIMAC_MIB_GTOVR_REG_OFFSET 0x000000c0 extern const ru_reg_rec UNIMAC_MIB_GTDRF_REG; #define UNIMAC_MIB_GTDRF_REG_OFFSET 0x000000c4 extern const ru_reg_rec UNIMAC_MIB_GTEDF_REG; #define UNIMAC_MIB_GTEDF_REG_OFFSET 0x000000c8 extern const ru_reg_rec UNIMAC_MIB_GTSCL_REG; #define UNIMAC_MIB_GTSCL_REG_OFFSET 0x000000cc extern const ru_reg_rec UNIMAC_MIB_GTMCL_REG; #define UNIMAC_MIB_GTMCL_REG_OFFSET 0x000000d0 extern const ru_reg_rec UNIMAC_MIB_GTLCL_REG; #define UNIMAC_MIB_GTLCL_REG_OFFSET 0x000000d4 extern const ru_reg_rec UNIMAC_MIB_GTXCL_REG; #define UNIMAC_MIB_GTXCL_REG_OFFSET 0x000000d8 extern const ru_reg_rec UNIMAC_MIB_GTFRG_REG; #define UNIMAC_MIB_GTFRG_REG_OFFSET 0x000000dc extern const ru_reg_rec UNIMAC_MIB_GTNCL_REG; #define UNIMAC_MIB_GTNCL_REG_OFFSET 0x000000e0 extern const ru_reg_rec UNIMAC_MIB_GTJBR_REG; #define UNIMAC_MIB_GTJBR_REG_OFFSET 0x000000e4 extern const ru_reg_rec UNIMAC_MIB_GTBYT_REG; #define UNIMAC_MIB_GTBYT_REG_OFFSET 0x000000e8 extern const ru_reg_rec UNIMAC_MIB_GTPOK_REG; #define UNIMAC_MIB_GTPOK_REG_OFFSET 0x000000ec extern const ru_reg_rec UNIMAC_MIB_GTUC_REG; #define UNIMAC_MIB_GTUC_REG_OFFSET 0x000000f0 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_CFG_REG_OFFSET 0x00000000 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG1_REG_OFFSET 0x00000004 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_EXT_CFG2_REG_OFFSET 0x00000008 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_UPDATE_MASK_REG_OFFSET 0x0000000c extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_STAT_REG_OFFSET 0x00000010 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_DEBUG_REG_OFFSET 0x00000014 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RST_REG_OFFSET 0x00000018 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_RSV_MASK_REG_OFFSET 0x0000001c extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_OVERRUN_COUNTER_REG_OFFSET 0x00000020 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_MISC_UNIMAC_1588_REG_OFFSET 0x00000024 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISR_REG_OFFSET 0x00000040 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_IER_REG_OFFSET 0x00000044 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ITR_REG_OFFSET 0x00000048 extern const ru_reg_rec UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_REG; #define UNIMAC_MISC_UNIMAC_TOP_UNIMAC_INTS_ISM_REG_OFFSET 0x0000004c extern const ru_reg_rec TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG; #define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG_OFFSET 0x00000000 #define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_REG_RAM_CNT 0x000007ff extern const ru_reg_rec TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_REG; #define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN_REG_OFFSET 0x00002000 extern const ru_reg_rec TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG; #define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG_OFFSET 0x00002010 #define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK_REG_RAM_CNT 0x00000007 extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_REG; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_REG_OFFSET 0x00002100 extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_REG; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_REG_OFFSET 0x00002104 extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_REG; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_REG_OFFSET 0x00002108 extern const ru_reg_rec TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_REG; #define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_REG_OFFSET 0x0000210c extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_REG_OFFSET 0x00002200 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_REG_OFFSET 0x00002204 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR_REG_OFFSET 0x00002208 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_REG_OFFSET 0x0000220c extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_REG_OFFSET 0x00002214 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT_REG_OFFSET 0x00002218 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG_OFFSET 0x00002220 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_REG_RAM_CNT 0x00000007 extern const ru_reg_rec TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG; #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG_OFFSET 0x00002240 #define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_REG_RAM_CNT 0x00000007 extern const ru_reg_rec TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_REG; #define TCAM_DEBUG_BUS_TCAM_DEBUG_BUS_SELECT_REG_OFFSET 0x00002500 extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_REG; #define HASH_GENERAL_CONFIGURATION_PWR_SAV_EN_REG_OFFSET 0x00000000 extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PAD_HIGH_REG; #define HASH_GENERAL_CONFIGURATION_PAD_HIGH_REG_OFFSET 0x00000004 extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_PAD_LOW_REG; #define HASH_GENERAL_CONFIGURATION_PAD_LOW_REG_OFFSET 0x00000008 extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_REG; #define HASH_GENERAL_CONFIGURATION_MULT_HIT_ERR_REG_OFFSET 0x0000000c extern const ru_reg_rec HASH_GENERAL_CONFIGURATION_UNDO_FIX_REG; #define HASH_GENERAL_CONFIGURATION_UNDO_FIX_REG_OFFSET 0x00000010 extern const ru_reg_rec HASH_PM_COUNTERS_HITS_REG; #define HASH_PM_COUNTERS_HITS_REG_OFFSET 0x00000100 extern const ru_reg_rec HASH_PM_COUNTERS_SRCHS_REG; #define HASH_PM_COUNTERS_SRCHS_REG_OFFSET 0x00000104 extern const ru_reg_rec HASH_PM_COUNTERS_MISS_REG; #define HASH_PM_COUNTERS_MISS_REG_OFFSET 0x00000108 extern const ru_reg_rec HASH_PM_COUNTERS_HIT_1ST_ACS_REG; #define HASH_PM_COUNTERS_HIT_1ST_ACS_REG_OFFSET 0x0000010c extern const ru_reg_rec HASH_PM_COUNTERS_HIT_2ND_ACS_REG; #define HASH_PM_COUNTERS_HIT_2ND_ACS_REG_OFFSET 0x00000110 extern const ru_reg_rec HASH_PM_COUNTERS_HIT_3RD_ACS_REG; #define HASH_PM_COUNTERS_HIT_3RD_ACS_REG_OFFSET 0x00000114 extern const ru_reg_rec HASH_PM_COUNTERS_HIT_4TH_ACS_REG; #define HASH_PM_COUNTERS_HIT_4TH_ACS_REG_OFFSET 0x00000118 extern const ru_reg_rec HASH_PM_COUNTERS_FRZ_CNT_REG; #define HASH_PM_COUNTERS_FRZ_CNT_REG_OFFSET 0x00000150 extern const ru_reg_rec HASH_LKUP_TBL_CFG_TBL_CFG_REG; #define HASH_LKUP_TBL_CFG_TBL_CFG_REG_OFFSET 0x00000200 #define HASH_LKUP_TBL_CFG_TBL_CFG_REG_RAM_CNT 0x00000006 extern const ru_reg_rec HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG; #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG_OFFSET 0x00000204 #define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_REG_RAM_CNT 0x00000006 extern const ru_reg_rec HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG; #define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG_OFFSET 0x00000208 #define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_REG_RAM_CNT 0x00000006 extern const ru_reg_rec HASH_LKUP_TBL_CFG_CNTXT_CFG_REG; #define HASH_LKUP_TBL_CFG_CNTXT_CFG_REG_OFFSET 0x0000020c #define HASH_LKUP_TBL_CFG_CNTXT_CFG_REG_RAM_CNT 0x00000006 extern const ru_reg_rec HASH_CAM_CONFIGURATION_CNTXT_CFG_REG; #define HASH_CAM_CONFIGURATION_CNTXT_CFG_REG_OFFSET 0x00000400 extern const ru_reg_rec HASH_CAM_INDIRECT_OP_REG; #define HASH_CAM_INDIRECT_OP_REG_OFFSET 0x00000800 extern const ru_reg_rec HASH_CAM_INDIRECT_OP_DONE_REG; #define HASH_CAM_INDIRECT_OP_DONE_REG_OFFSET 0x00000804 extern const ru_reg_rec HASH_CAM_INDIRECT_ADDR_REG; #define HASH_CAM_INDIRECT_ADDR_REG_OFFSET 0x00000808 extern const ru_reg_rec HASH_CAM_INDIRECT_VLID_IN_REG; #define HASH_CAM_INDIRECT_VLID_IN_REG_OFFSET 0x0000080c extern const ru_reg_rec HASH_CAM_INDIRECT_VLID_OUT_REG; #define HASH_CAM_INDIRECT_VLID_OUT_REG_OFFSET 0x00000814 extern const ru_reg_rec HASH_CAM_INDIRECT_RSLT_REG; #define HASH_CAM_INDIRECT_RSLT_REG_OFFSET 0x00000818 extern const ru_reg_rec HASH_CAM_INDIRECT_KEY_IN_REG; #define HASH_CAM_INDIRECT_KEY_IN_REG_OFFSET 0x00000820 #define HASH_CAM_INDIRECT_KEY_IN_REG_RAM_CNT 0x00000001 extern const ru_reg_rec HASH_CAM_INDIRECT_KEY_OUT_REG; #define HASH_CAM_INDIRECT_KEY_OUT_REG_OFFSET 0x00000840 #define HASH_CAM_INDIRECT_KEY_OUT_REG_RAM_CNT 0x00000001 extern const ru_reg_rec HASH_CAM_BIST_BIST_STATUS_REG; #define HASH_CAM_BIST_BIST_STATUS_REG_OFFSET 0x00000900 extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_COMPARE_EN_REG; #define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_REG_OFFSET 0x00000904 extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_REG; #define HASH_CAM_BIST_BIST_DBG_DATA_REG_OFFSET 0x00000908 extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_REG; #define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_REG_OFFSET 0x0000090c extern const ru_reg_rec HASH_CAM_BIST_BIST_DBG_DATA_VALID_REG; #define HASH_CAM_BIST_BIST_DBG_DATA_VALID_REG_OFFSET 0x00000910 extern const ru_reg_rec HASH_CAM_BIST_BIST_EN_REG; #define HASH_CAM_BIST_BIST_EN_REG_OFFSET 0x00000914 extern const ru_reg_rec HASH_CAM_BIST_BIST_MODE_REG; #define HASH_CAM_BIST_BIST_MODE_REG_OFFSET 0x00000918 extern const ru_reg_rec HASH_CAM_BIST_BIST_RST_L_REG; #define HASH_CAM_BIST_BIST_RST_L_REG_OFFSET 0x0000091c extern const ru_reg_rec HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_REG; #define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_REG_OFFSET 0x00000920 extern const ru_reg_rec HASH_CAM_BIST_DBG_EN_REG; #define HASH_CAM_BIST_DBG_EN_REG_OFFSET 0x00000924 extern const ru_reg_rec HASH_CAM_BIST_BIST_CASCADE_SELECT_REG; #define HASH_CAM_BIST_BIST_CASCADE_SELECT_REG_OFFSET 0x00000928 extern const ru_reg_rec HASH_CAM_BIST_BIST_BLOCK_SELECT_REG; #define HASH_CAM_BIST_BIST_BLOCK_SELECT_REG_OFFSET 0x0000092c extern const ru_reg_rec HASH_CAM_BIST_BIST_REPAIR_ENABLE_REG; #define HASH_CAM_BIST_BIST_REPAIR_ENABLE_REG_OFFSET 0x00000930 extern const ru_reg_rec HASH_INTR_CTRL_ISR_REG; #define HASH_INTR_CTRL_ISR_REG_OFFSET 0x00000a00 extern const ru_reg_rec HASH_INTR_CTRL_ISM_REG; #define HASH_INTR_CTRL_ISM_REG_OFFSET 0x00000a04 extern const ru_reg_rec HASH_INTR_CTRL_IER_REG; #define HASH_INTR_CTRL_IER_REG_OFFSET 0x00000a08 extern const ru_reg_rec HASH_INTR_CTRL_ITR_REG; #define HASH_INTR_CTRL_ITR_REG_OFFSET 0x00000a0c extern const ru_reg_rec HASH_DEBUG_DBG0_REG; #define HASH_DEBUG_DBG0_REG_OFFSET 0x00000a30 extern const ru_reg_rec HASH_DEBUG_DBG1_REG; #define HASH_DEBUG_DBG1_REG_OFFSET 0x00000a34 extern const ru_reg_rec HASH_DEBUG_DBG2_REG; #define HASH_DEBUG_DBG2_REG_OFFSET 0x00000a38 extern const ru_reg_rec HASH_DEBUG_DBG3_REG; #define HASH_DEBUG_DBG3_REG_OFFSET 0x00000a3c extern const ru_reg_rec HASH_DEBUG_DBG4_REG; #define HASH_DEBUG_DBG4_REG_OFFSET 0x00000a40 extern const ru_reg_rec HASH_DEBUG_DBG5_REG; #define HASH_DEBUG_DBG5_REG_OFFSET 0x00000a44 extern const ru_reg_rec HASH_DEBUG_DBG6_REG; #define HASH_DEBUG_DBG6_REG_OFFSET 0x00000a48 extern const ru_reg_rec HASH_DEBUG_DBG7_REG; #define HASH_DEBUG_DBG7_REG_OFFSET 0x00000a4c extern const ru_reg_rec HASH_DEBUG_DBG8_REG; #define HASH_DEBUG_DBG8_REG_OFFSET 0x00000a50 extern const ru_reg_rec HASH_DEBUG_DBG9_REG; #define HASH_DEBUG_DBG9_REG_OFFSET 0x00000a54 extern const ru_reg_rec HASH_DEBUG_DBG10_REG; #define HASH_DEBUG_DBG10_REG_OFFSET 0x00000a58 extern const ru_reg_rec HASH_DEBUG_DBG11_REG; #define HASH_DEBUG_DBG11_REG_OFFSET 0x00000a5c extern const ru_reg_rec HASH_DEBUG_DBG12_REG; #define HASH_DEBUG_DBG12_REG_OFFSET 0x00000a60 extern const ru_reg_rec HASH_DEBUG_DBG13_REG; #define HASH_DEBUG_DBG13_REG_OFFSET 0x00000a64 extern const ru_reg_rec HASH_DEBUG_DBG14_REG; #define HASH_DEBUG_DBG14_REG_OFFSET 0x00000a68 extern const ru_reg_rec HASH_DEBUG_DBG15_REG; #define HASH_DEBUG_DBG15_REG_OFFSET 0x00000a6c extern const ru_reg_rec HASH_DEBUG_DBG16_REG; #define HASH_DEBUG_DBG16_REG_OFFSET 0x00000a70 extern const ru_reg_rec HASH_DEBUG_DBG17_REG; #define HASH_DEBUG_DBG17_REG_OFFSET 0x00000a74 extern const ru_reg_rec HASH_DEBUG_DBG18_REG; #define HASH_DEBUG_DBG18_REG_OFFSET 0x00000a78 extern const ru_reg_rec HASH_DEBUG_DBG19_REG; #define HASH_DEBUG_DBG19_REG_OFFSET 0x00000a7c extern const ru_reg_rec HASH_DEBUG_DBG20_REG; #define HASH_DEBUG_DBG20_REG_OFFSET 0x00000a80 extern const ru_reg_rec HASH_DEBUG_DBG_SEL_REG; #define HASH_DEBUG_DBG_SEL_REG_OFFSET 0x00000a84 extern const ru_reg_rec HASH_AGING_RAM_AGING_REG; #define HASH_AGING_RAM_AGING_REG_OFFSET 0x00007000 #define HASH_AGING_RAM_AGING_REG_RAM_CNT 0x00000041 extern const ru_reg_rec HASH_CONTEXT_RAM_CONTEXT_47_24_REG; #define HASH_CONTEXT_RAM_CONTEXT_47_24_REG_OFFSET 0x00008000 #define HASH_CONTEXT_RAM_CONTEXT_47_24_REG_RAM_CNT 0x000004bf extern const ru_reg_rec HASH_CONTEXT_RAM_CONTEXT_23_0_REG; #define HASH_CONTEXT_RAM_CONTEXT_23_0_REG_OFFSET 0x00008004 #define HASH_CONTEXT_RAM_CONTEXT_23_0_REG_RAM_CNT 0x000004bf extern const ru_reg_rec HASH_RAM_ENG_HIGH_REG; #define HASH_RAM_ENG_HIGH_REG_OFFSET 0x00010000 #define HASH_RAM_ENG_HIGH_REG_RAM_CNT 0x000007ff extern const ru_reg_rec HASH_RAM_ENG_LOW_REG; #define HASH_RAM_ENG_LOW_REG_OFFSET 0x00010004 #define HASH_RAM_ENG_LOW_REG_RAM_CNT 0x000007ff extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_REG; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_RSLT_F_FULL_THR_REG_OFFSET 0x00000000 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_REG; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_DEC_ROUT_OVRIDE_REG_OFFSET 0x00000004 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_REG; #define BAC_IF_BACIF_BLOCK_BACIF_CONFIGURATIONS_CLK_GATE_CNTRL_REG_OFFSET 0x0000000c extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG_OFFSET 0x00000100 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_REG_RAM_CNT 0x0000007f extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG_OFFSET 0x00000500 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_REG_RAM_CNT 0x0000001f extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG_OFFSET 0x00000600 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_REG_RAM_CNT 0x0000001f extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG_OFFSET 0x00000700 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_REG_RAM_CNT 0x00000007 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG; #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG_OFFSET 0x00000800 #define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_REG_RAM_CNT 0x00000007 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_REG_OFFSET 0x00000c00 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_REG_OFFSET 0x00000c04 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_REG_OFFSET 0x00000c08 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_REG_OFFSET 0x00000c10 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_REG_OFFSET 0x00000c14 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_REG_OFFSET 0x00000c18 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_REG_OFFSET 0x00000c30 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_REG_OFFSET 0x00000c34 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_REG_OFFSET 0x00000c38 extern const ru_reg_rec BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_REG; #define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_REG_OFFSET 0x00000cfc extern const ru_reg_rec CNPL_MEMORY_DATA_REG; #define CNPL_MEMORY_DATA_REG_OFFSET 0x00000000 #define CNPL_MEMORY_DATA_REG_RAM_CNT 0x00000bff extern const ru_reg_rec CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG; #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG_OFFSET 0x00004000 #define CNPL_COUNTERS_CONFIGURATIONS_CN_LOC_PROF_REG_RAM_CNT 0x0000000f extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG_OFFSET 0x00004100 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF0_REG_RAM_CNT 0x00000001 extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG; #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG_OFFSET 0x00004108 #define CNPL_POLICERS_CONFIGURATIONS_PL_LOC_PROF1_REG_RAM_CNT 0x00000001 extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG; #define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG_OFFSET 0x00004110 #define CNPL_POLICERS_CONFIGURATIONS_PL_CALC_TYPE_REG_RAM_CNT 0x00000002 extern const ru_reg_rec CNPL_POLICERS_CONFIGURATIONS_PER_UP_REG; #define CNPL_POLICERS_CONFIGURATIONS_PER_UP_REG_OFFSET 0x00004120 extern const ru_reg_rec CNPL_MISC_ARB_PRM_REG; #define CNPL_MISC_ARB_PRM_REG_OFFSET 0x00004200 extern const ru_reg_rec CNPL_SW_IF_SW_CMD_REG; #define CNPL_SW_IF_SW_CMD_REG_OFFSET 0x00004300 extern const ru_reg_rec CNPL_SW_IF_SW_STAT_REG; #define CNPL_SW_IF_SW_STAT_REG_OFFSET 0x00004304 extern const ru_reg_rec CNPL_SW_IF_SW_PL_RSLT_REG; #define CNPL_SW_IF_SW_PL_RSLT_REG_OFFSET 0x00004310 extern const ru_reg_rec CNPL_SW_IF_SW_PL_RD_REG; #define CNPL_SW_IF_SW_PL_RD_REG_OFFSET 0x00004314 #define CNPL_SW_IF_SW_PL_RD_REG_RAM_CNT 0x00000001 extern const ru_reg_rec CNPL_SW_IF_SW_CNT_RD_REG; #define CNPL_SW_IF_SW_CNT_RD_REG_OFFSET 0x00004320 #define CNPL_SW_IF_SW_CNT_RD_REG_RAM_CNT 0x00000007 extern const ru_reg_rec CNPL_PM_COUNTERS_ENG_CMDS_REG; #define CNPL_PM_COUNTERS_ENG_CMDS_REG_OFFSET 0x00004400 #define CNPL_PM_COUNTERS_ENG_CMDS_REG_RAM_CNT 0x0000000a extern const ru_reg_rec CNPL_PM_COUNTERS_CMD_WAIT_REG; #define CNPL_PM_COUNTERS_CMD_WAIT_REG_OFFSET 0x00004440 #define CNPL_PM_COUNTERS_CMD_WAIT_REG_RAM_CNT 0x00000001 extern const ru_reg_rec CNPL_PM_COUNTERS_TOT_CYC_REG; #define CNPL_PM_COUNTERS_TOT_CYC_REG_OFFSET 0x00004450 extern const ru_reg_rec CNPL_PM_COUNTERS_GNT_CYC_REG; #define CNPL_PM_COUNTERS_GNT_CYC_REG_OFFSET 0x00004454 extern const ru_reg_rec CNPL_PM_COUNTERS_ARB_CYC_REG; #define CNPL_PM_COUNTERS_ARB_CYC_REG_OFFSET 0x00004458 extern const ru_reg_rec CNPL_PM_COUNTERS_PL_UP_ERR_REG; #define CNPL_PM_COUNTERS_PL_UP_ERR_REG_OFFSET 0x00004460 extern const ru_reg_rec CNPL_PM_COUNTERS_GEN_CFG_REG; #define CNPL_PM_COUNTERS_GEN_CFG_REG_OFFSET 0x000044fc extern const ru_reg_rec CNPL_DEBUG_DBGSEL_REG; #define CNPL_DEBUG_DBGSEL_REG_OFFSET 0x00004500 extern const ru_reg_rec CNPL_DEBUG_DBGBUS_REG; #define CNPL_DEBUG_DBGBUS_REG_OFFSET 0x00004504 extern const ru_reg_rec CNPL_DEBUG_REQ_VEC_REG; #define CNPL_DEBUG_REQ_VEC_REG_OFFSET 0x00004508 extern const ru_reg_rec CNPL_DEBUG_POL_UP_ST_REG; #define CNPL_DEBUG_POL_UP_ST_REG_OFFSET 0x00004510 extern const ru_reg_rec NATC_CONTROL_STATUS_REG; #define NATC_CONTROL_STATUS_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_CONTROL_STATUS2_REG; #define NATC_CONTROL_STATUS2_REG_OFFSET 0x00000004 extern const ru_reg_rec NATC_TABLE_CONTROL_REG; #define NATC_TABLE_CONTROL_REG_OFFSET 0x00000008 extern const ru_reg_rec NATC_ENG_COMMAND_STATUS_REG; #define NATC_ENG_COMMAND_STATUS_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_ENG_HASH_REG; #define NATC_ENG_HASH_REG_OFFSET 0x00000008 extern const ru_reg_rec NATC_ENG_HIT_COUNT_REG; #define NATC_ENG_HIT_COUNT_REG_OFFSET 0x0000000c extern const ru_reg_rec NATC_ENG_BYTE_COUNT_REG; #define NATC_ENG_BYTE_COUNT_REG_OFFSET 0x00000010 extern const ru_reg_rec NATC_ENG_PKT_LEN_REG; #define NATC_ENG_PKT_LEN_REG_OFFSET 0x00000014 extern const ru_reg_rec NATC_ENG_KEY_RESULT_REG; #define NATC_ENG_KEY_RESULT_REG_OFFSET 0x00000020 #define NATC_ENG_KEY_RESULT_REG_RAM_CNT 0x00000011 extern const ru_reg_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG; #define NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG_OFFSET 0x00000004 extern const ru_reg_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG_OFFSET 0x00000008 extern const ru_reg_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG; #define NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG_OFFSET 0x0000000c extern const ru_reg_rec NATC_CTRS_TBL_CACHE_HIT_COUNT_REG; #define NATC_CTRS_TBL_CACHE_HIT_COUNT_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_CTRS_TBL_CACHE_MISS_COUNT_REG; #define NATC_CTRS_TBL_CACHE_MISS_COUNT_REG_OFFSET 0x00000004 extern const ru_reg_rec NATC_CTRS_TBL_DDR_REQUEST_COUNT_REG; #define NATC_CTRS_TBL_DDR_REQUEST_COUNT_REG_OFFSET 0x00000008 extern const ru_reg_rec NATC_CTRS_TBL_DDR_EVICT_COUNT_REG; #define NATC_CTRS_TBL_DDR_EVICT_COUNT_REG_OFFSET 0x0000000c extern const ru_reg_rec NATC_CTRS_TBL_DDR_BLOCK_COUNT_REG; #define NATC_CTRS_TBL_DDR_BLOCK_COUNT_REG_OFFSET 0x00000010 extern const ru_reg_rec NATC_KEY_MASK_TBL_KEY_MASK_REG; #define NATC_KEY_MASK_TBL_KEY_MASK_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_DDR_CFG__DDR_SIZE_REG; #define NATC_DDR_CFG__DDR_SIZE_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_REG; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_0_REG_OFFSET 0x00000004 extern const ru_reg_rec NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_REG; #define NATC_DDR_CFG__DDR_BINS_PER_BUCKET_1_REG_OFFSET 0x00000008 extern const ru_reg_rec NATC_DDR_CFG__TOTAL_LEN_REG; #define NATC_DDR_CFG__TOTAL_LEN_REG_OFFSET 0x0000000c extern const ru_reg_rec NATC_DDR_CFG__SM_STATUS_REG; #define NATC_DDR_CFG__SM_STATUS_REG_OFFSET 0x00000020 extern const ru_reg_rec NATC_INDIR_C_INDIR_ADDR_REG_REG; #define NATC_INDIR_C_INDIR_ADDR_REG_REG_OFFSET 0x00000000 extern const ru_reg_rec NATC_INDIR_C_INDIR_DATA_REG_REG; #define NATC_INDIR_C_INDIR_DATA_REG_REG_OFFSET 0x00000010 #define NATC_INDIR_C_INDIR_DATA_REG_REG_RAM_CNT 0x00000014 /****************************************************************************** * XRDP_ Blocks ******************************************************************************/ extern const ru_block_rec QM_BLOCK; extern const ru_block_rec DQM_BLOCK; extern const ru_block_rec FPM_BLOCK; extern const ru_block_rec RNR_MEM_BLOCK; extern const ru_block_rec RNR_INST_BLOCK; extern const ru_block_rec RNR_CNTXT_BLOCK; extern const ru_block_rec RNR_PRED_BLOCK; extern const ru_block_rec RNR_REGS_BLOCK; extern const ru_block_rec RNR_QUAD_BLOCK; extern const ru_block_rec DSPTCHR_BLOCK; extern const ru_block_rec BBH_TX_BLOCK; extern const ru_block_rec BBH_RX_BLOCK; extern const ru_block_rec UBUS_MSTR_BLOCK; extern const ru_block_rec UBUS_SLV_BLOCK; extern const ru_block_rec SBPM_BLOCK; extern const ru_block_rec DMA_BLOCK; extern const ru_block_rec PSRAM_BLOCK; extern const ru_block_rec UNIMAC_RDP_BLOCK; extern const ru_block_rec UNIMAC_MIB_BLOCK; extern const ru_block_rec UNIMAC_MISC_BLOCK; extern const ru_block_rec TCAM_BLOCK; extern const ru_block_rec HASH_BLOCK; extern const ru_block_rec BAC_IF_BLOCK; extern const ru_block_rec CNPL_BLOCK; extern const ru_block_rec NATC_BLOCK; extern const ru_block_rec NATC_ENG_BLOCK; extern const ru_block_rec NATC_CFG_BLOCK; extern const ru_block_rec NATC_CTRS_BLOCK; extern const ru_block_rec NATC_KEY_MASK_BLOCK; extern const ru_block_rec NATC_DDR_CFG_BLOCK; extern const ru_block_rec NATC_INDIR_BLOCK; extern const ru_block_rec *RU_ALL_BLOCKS[]; #define RU_BLK_COUNT 31 #define RU_REG_COUNT 1145 #define RU_FLD_COUNT 3368 #endif /* End of file XRDP_.h */