/*
   Copyright (c) 2015 Broadcom
   All Rights Reserved

    <:label-BRCM:2015:DUAL/GPL:standard

    Unless you and Broadcom execute a separate written software license
    agreement governing use of this software, this software is licensed
    to you under the terms of the GNU General Public License version 2
    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
    with the following added to such license:

       As a special exception, the copyright holders of this software give
       you permission to link this software with independent modules, and
       to copy and distribute the resulting executable under terms of your
       choice, provided that you also meet, for each linked independent
       module, the terms and conditions of the license of that module.
       An independent module is a module which is not derived from this
       software.  The special exception does not apply to any modifications
       of the software.

    Not withstanding the above, under no circumstances may you combine
    this software in any way with any other Broadcom software provided
    under a license other than the GPL, without Broadcom's express prior
    written consent.

:>
*/

#include "ru.h"

#if RU_INCLUDE_FIELD_DB
/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD =
{
    "BAR",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD =
{
    "ZEROS",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD =
{
    "ZEROS",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD =
{
    "BAR",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD =
{
    "BAR",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD =
{
    "ZEROS",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD =
{
    "ZEROS",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

/******************************************************************************
 * Field: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR
 ******************************************************************************/
const ru_field_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD =
{
    "BAR",
#if RU_INCLUDE_DESC
    "",
    "",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_MASK,
    0,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_WIDTH,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD_SHIFT,
#if RU_INCLUDE_ACCESS
    ru_access_rw
#endif
};

#endif /* RU_INCLUDE_FIELD_DB */

/******************************************************************************
 * Register: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_FIELDS[] =
{
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_BAR_FIELD,
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_ZEROS_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG = 
{
    "TBL_DDR_KEY_BASE_ADDRESS_LOWER",
#if RU_INCLUDE_DESC
    "Lower 32-bit of NAT table  key base address NAT table in DDR",
    "Lower 32-bit of the base address of DDR key table"
    "Address must be 64-bit aligned (bit 2 through 0 are zero's)"
    "In order maximum number of key fetches,"
    "for 16-byte key, bit 3 should be 0 to align at 16 byte boundary"
    "for 32-byte key, bit 3 and 4 should be 0 to align at 32 bytes boundary",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG_OFFSET,
    0,
    0,
    1128,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    2,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_FIELDS
#endif /* RU_INCLUDE_FIELD_DB */
};

/******************************************************************************
 * Register: NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_FIELDS[] =
{
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_ZEROS_FIELD,
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_BAR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG = 
{
    "TBL_DDR_KEY_BASE_ADDRESS_UPPER",
#if RU_INCLUDE_DESC
    "Upper 32-bit of NAT table  key base address NAT table in DDR",
    "Upper 8-bit of the base address of DDR key table"
    "For 32-bit system this field should be left as 0",
#endif
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG_OFFSET,
    0,
    0,
    1129,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    2,
    NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_FIELDS
#endif /* RU_INCLUDE_FIELD_DB */
};

/******************************************************************************
 * Register: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_FIELDS[] =
{
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_BAR_FIELD,
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_ZEROS_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG = 
{
    "TBL_DDR_RESULT_BASE_ADDRESS_LOWER",
#if RU_INCLUDE_DESC
    "Lower 32-bit of NAT table result base address NAT table in DDR",
    "Lower 32-bit of the base address of DDR context table"
    "Address must be 64-bit aligned (bit 2 through 0 are zero's)",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG_OFFSET,
    0,
    0,
    1130,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    2,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_FIELDS
#endif /* RU_INCLUDE_FIELD_DB */
};

/******************************************************************************
 * Register: NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER
 ******************************************************************************/
#if RU_INCLUDE_FIELD_DB
static const ru_field_rec *NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_FIELDS[] =
{
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_ZEROS_FIELD,
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_BAR_FIELD,
};

#endif /* RU_INCLUDE_FIELD_DB */

const ru_reg_rec NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG = 
{
    "TBL_DDR_RESULT_BASE_ADDRESS_UPPER",
#if RU_INCLUDE_DESC
    "Upper 32-bit of NAT table result base address NAT table in DDR",
    "Upper 8-bit of the base address of DDR context table"
    "For 32-bit system this field should be left as 0",
#endif
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG_OFFSET,
    0,
    0,
    1131,
#if RU_INCLUDE_ACCESS
    ru_access_rw,
#endif
#if RU_INCLUDE_FIELD_DB
    2,
    NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_FIELDS
#endif /* RU_INCLUDE_FIELD_DB */
};

/******************************************************************************
 * Block: NATC_CFG
 ******************************************************************************/
static const ru_reg_rec *NATC_CFG_REGS[] =
{
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_LOWER_REG,
    &NATC_CFG_TBL_DDR_KEY_BASE_ADDRESS_UPPER_REG,
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_LOWER_REG,
    &NATC_CFG_TBL_DDR_RESULT_BASE_ADDRESS_UPPER_REG,
};

unsigned long NATC_CFG_ADDRS[] =
{
    0x82e50290,
    0x82e502a0,
    0x82e502b0,
    0x82e502c0,
    0x82e502d0,
    0x82e502e0,
    0x82e502f0,
    0x82e50300,
};

const ru_block_rec NATC_CFG_BLOCK = 
{
    "NATC_CFG",
    NATC_CFG_ADDRS,
    8,
    4,
    NATC_CFG_REGS
};

/* End of file XRDP_NATC_CFG.c */