#ifndef IMAGE_3_CODE_ADDRESSES #define IMAGE_3_CODE_ADDRESSES #define image_3_start_task_initialization_task (0x18) #define image_3_initialization_task (0x18) #define image_3_start_task_update_fifo_read_1st_wakeup_request (0x11E4) #define image_3_update_fifo_read_1st_wakeup_request (0x11E4) #define image_3_start_task_ghost_reporting_1st_wakeup_request (0xD10) #define image_3_ghost_reporting_1st_wakeup_request (0xD10) #define image_3_start_task_tx_task_1st_wakeup_request (0x178) #define image_3_tx_task_1st_wakeup_request (0x178) #define image_3_start_task_epon_update_fifo_read_1st_wakeup_request (0x144C) #define image_3_epon_update_fifo_read_1st_wakeup_request (0x144C) #define image_3_start_task_epon_tx_task_wakeup_request (0x4EC) #define image_3_epon_tx_task_wakeup_request (0x4EC) #define image_3_start_task_budget_allocator_1st_wakeup_request (0x78C) #define image_3_budget_allocator_1st_wakeup_request (0x78C) #define image_3_start_task_debug_routine (0x4C) #define image_3_debug_routine (0x4C) #define image_3_start_task_ovl_budget_allocator_1st_wakeup_request (0xA80) #define image_3_ovl_budget_allocator_1st_wakeup_request (0xA80) #define image_3_start_task_flush_task_1st_wakeup_request (0x10F8) #define image_3_flush_task_1st_wakeup_request (0x10F8) #define image_3_debug_routine_handler (0xC) #define image_3_scheduling_update_status (0x39C) #define image_3_scheduling_action_not_valid (0x480) #define image_3_basic_scheduler_update_dwrr (0x650) #define image_3_complex_scheduler_update_dwrr_basic_schedulers (0x758) #define image_3_complex_scheduler_update_dwrr_queues (0x768) #define image_3_basic_rate_limiter_complex_scheduler (0xB5C) #define image_3_basic_rate_limiter_basic_scheduler_no_cs (0xB88) #define image_3_basic_rate_limiter_queue_with_cs_bs (0xBB4) #define image_3_basic_rate_limiter_queue_with_bs (0xC00) #define image_3_ovl_rate_limiter (0xC30) #define image_3_complex_rate_limiter_queue_sir (0xC40) #define image_3_complex_rate_limiter_queue_pir (0xC74) #define image_3_complex_rate_limiter_basic_scheduler_sir (0xCA8) #define image_3_complex_rate_limiter_basic_scheduler_pir (0xCDC) #endif