/* Copyright (c) 2015 Broadcom All Rights Reserved <:label-BRCM:2015:DUAL/GPL:standard Unless you and Broadcom execute a separate written software license agreement governing use of this software, this software is licensed to you under the terms of the GNU General Public License version 2 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, with the following added to such license: As a special exception, the copyright holders of this software give you permission to link this software with independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from this software. The special exception does not apply to any modifications of the software. Not withstanding the above, under no circumstances may you combine this software in any way with any other Broadcom software provided under a license other than the GPL, without Broadcom's express prior written consent. :> */ /* This is an automated file. Do not edit its contents. */ #ifndef _RDD_RUNNER_DEFS_AUTO_H_ #define _RDD_RUNNER_DEFS_AUTO_H_ #ifdef BCM6858 /* DDR */ #define IPTV_DDR_CONTEXT_TABLE_ADDRESS 0x-001 #define IPTV_DDR_CONTEXT_TABLE_BYTE_SIZE 0x10000 #define IPTV_DDR_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x0010 #define RDD_IPTV_DDR_CONTEXT_TABLE_SIZE 1024 #define RDD_IPTV_DDR_CONTEXT_TABLE_LOG2_SIZE 10 #define WLAN_MCAST_DHD_LIST_TABLE_ADDRESS 0x-001 #define WLAN_MCAST_DHD_LIST_TABLE_BYTE_SIZE 0x1000 #define WLAN_MCAST_DHD_LIST_TABLE_LOG2_BYTE_SIZE 0x000c #define RDD_WLAN_MCAST_DHD_LIST_TABLE_SIZE 64 #define RDD_WLAN_MCAST_DHD_LIST_TABLE_LOG2_SIZE 6 #define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_ADDRESS 0x-001 #define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_BYTE_SIZE 0x0001 #define WLAN_MCAST_DHD_LIST_FORMAT_TABLE_LOG2_BYTE_SIZE 0x0001 /* PSRAM */ /* IMAGE_0 */ #define IMAGE_0_PD_FIFO_TABLE_ADDRESS 0x0000 #define IMAGE_0_PD_FIFO_TABLE_BYTE_SIZE 0x1400 #define IMAGE_0_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x000d #define RDD_IMAGE_0_PD_FIFO_TABLE_SIZE 320 #define RDD_IMAGE_0_PD_FIFO_TABLE_LOG2_SIZE 9 #define IMAGE_0_COMPLEX_SCHEDULER_TABLE_ADDRESS 0x1400 #define IMAGE_0_COMPLEX_SCHEDULER_TABLE_BYTE_SIZE 0x0400 #define IMAGE_0_COMPLEX_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_0_COMPLEX_SCHEDULER_TABLE_SIZE 16 #define RDD_IMAGE_0_COMPLEX_SCHEDULER_TABLE_LOG2_SIZE 4 #define IMAGE_0_SCHEDULING_QUEUE_TABLE_ADDRESS 0x1800 #define IMAGE_0_SCHEDULING_QUEUE_TABLE_BYTE_SIZE 0x0500 #define IMAGE_0_SCHEDULING_QUEUE_TABLE_LOG2_BYTE_SIZE 0x000b #define RDD_IMAGE_0_SCHEDULING_QUEUE_TABLE_SIZE 160 #define RDD_IMAGE_0_SCHEDULING_QUEUE_TABLE_LOG2_SIZE 8 #define IMAGE_0_TM_FLOW_CNTR_TABLE_ADDRESS 0x1d00 #define IMAGE_0_TM_FLOW_CNTR_TABLE_BYTE_SIZE 0x0080 #define IMAGE_0_TM_FLOW_CNTR_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_0_TM_FLOW_CNTR_TABLE_SIZE 128 #define RDD_IMAGE_0_TM_FLOW_CNTR_TABLE_LOG2_SIZE 7 #define IMAGE_0_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS 0x1d80 #define IMAGE_0_BBH_TX_EGRESS_COUNTER_TABLE_BYTE_SIZE 0x0040 #define IMAGE_0_BBH_TX_EGRESS_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_0_BBH_TX_EGRESS_COUNTER_TABLE_SIZE 8 #define RDD_IMAGE_0_BBH_TX_EGRESS_COUNTER_TABLE_LOG2_SIZE 3 #define IMAGE_0_TM_ACTION_PTR_TABLE_ADDRESS 0x1dc0 #define IMAGE_0_TM_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_0_TM_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_0_TM_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_0_TM_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_0_BUDGET_ALLOCATION_TIMER_VALUE_ADDRESS 0x1de2 #define IMAGE_0_BUDGET_ALLOCATION_TIMER_VALUE_BYTE_SIZE 0x0002 #define IMAGE_0_BUDGET_ALLOCATION_TIMER_VALUE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_BB_DESTINATION_TABLE_ADDRESS 0x1de4 #define IMAGE_0_BB_DESTINATION_TABLE_BYTE_SIZE 0x0002 #define IMAGE_0_BB_DESTINATION_TABLE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_SCHEDULING_GLOBAL_FLUSH_CFG_ADDRESS 0x1de6 #define IMAGE_0_SCHEDULING_GLOBAL_FLUSH_CFG_BYTE_SIZE 0x0001 #define IMAGE_0_SCHEDULING_GLOBAL_FLUSH_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_SCHEDULING_FLUSH_GLOBAL_CFG_ADDRESS 0x1de7 #define IMAGE_0_SCHEDULING_FLUSH_GLOBAL_CFG_BYTE_SIZE 0x0001 #define IMAGE_0_SCHEDULING_FLUSH_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_BBH_TX_QUEUE_ID_TABLE_ADDRESS 0x1de8 #define IMAGE_0_BBH_TX_QUEUE_ID_TABLE_BYTE_SIZE 0x0008 #define IMAGE_0_BBH_TX_QUEUE_ID_TABLE_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_0_BBH_TX_QUEUE_ID_TABLE_SIZE 2 #define RDD_IMAGE_0_BBH_TX_QUEUE_ID_TABLE_LOG2_SIZE 1 #define IMAGE_0_FLUSH_DISPATCHER_CREDIT_TABLE_ADDRESS 0x1df0 #define IMAGE_0_FLUSH_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_0_FLUSH_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_0_FLUSH_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_0_FLUSH_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_0_TASK_IDX_ADDRESS 0x1dfc #define IMAGE_0_TASK_IDX_BYTE_SIZE 0x0004 #define IMAGE_0_TASK_IDX_LOG2_BYTE_SIZE 0x0002 #define IMAGE_0_BASIC_SCHEDULER_TABLE_ADDRESS 0x1e00 #define IMAGE_0_BASIC_SCHEDULER_TABLE_BYTE_SIZE 0x0200 #define IMAGE_0_BASIC_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_0_BASIC_SCHEDULER_TABLE_SIZE 32 #define RDD_IMAGE_0_BASIC_SCHEDULER_TABLE_LOG2_SIZE 5 #define IMAGE_0_BASIC_RATE_LIMITER_TABLE_ADDRESS 0x2000 #define IMAGE_0_BASIC_RATE_LIMITER_TABLE_BYTE_SIZE 0x0800 #define IMAGE_0_BASIC_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000b #define RDD_IMAGE_0_BASIC_RATE_LIMITER_TABLE_SIZE 128 #define RDD_IMAGE_0_BASIC_RATE_LIMITER_TABLE_LOG2_SIZE 7 #define IMAGE_0_RUNNER_PROFILING_TRACE_BUFFER_ADDRESS 0x2800 #define IMAGE_0_RUNNER_PROFILING_TRACE_BUFFER_BYTE_SIZE 0x0200 #define IMAGE_0_RUNNER_PROFILING_TRACE_BUFFER_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_0_RUNNER_PROFILING_TRACE_BUFFER_SIZE 128 #define RDD_IMAGE_0_RUNNER_PROFILING_TRACE_BUFFER_LOG2_SIZE 7 #define IMAGE_0_BBH_QUEUE_TABLE_ADDRESS 0x2a00 #define IMAGE_0_BBH_QUEUE_TABLE_BYTE_SIZE 0x00a0 #define IMAGE_0_BBH_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_0_BBH_QUEUE_TABLE_SIZE 40 #define RDD_IMAGE_0_BBH_QUEUE_TABLE_LOG2_SIZE 6 #define IMAGE_0_REGISTERS_BUFFER_ADDRESS 0x2aa0 #define IMAGE_0_REGISTERS_BUFFER_BYTE_SIZE 0x0080 #define IMAGE_0_REGISTERS_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_0_REGISTERS_BUFFER_SIZE 32 #define RDD_IMAGE_0_REGISTERS_BUFFER_LOG2_SIZE 5 #define IMAGE_0_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x2b20 #define IMAGE_0_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020 #define IMAGE_0_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_0_RUNNER_GLOBAL_REGISTERS_INIT_SIZE 8 #define RDD_IMAGE_0_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE 3 #define IMAGE_0_UPDATE_FIFO_TABLE_ADDRESS 0x2b40 #define IMAGE_0_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_0_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_0_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_0_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_0_SCHEDULING_FLUSH_VECTOR_ADDRESS 0x2b60 #define IMAGE_0_SCHEDULING_FLUSH_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_0_SCHEDULING_FLUSH_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_0_SCHEDULING_FLUSH_VECTOR_SIZE 5 #define RDD_IMAGE_0_SCHEDULING_FLUSH_VECTOR_LOG2_SIZE 3 #define IMAGE_0_TX_MIRRORING_CONFIGURATION_ADDRESS 0x2b74 #define IMAGE_0_TX_MIRRORING_CONFIGURATION_BYTE_SIZE 0x0002 #define IMAGE_0_TX_MIRRORING_CONFIGURATION_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_SRAM_DUMMY_STORE_ADDRESS 0x2b76 #define IMAGE_0_SRAM_DUMMY_STORE_BYTE_SIZE 0x0001 #define IMAGE_0_SRAM_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_BBH_TX_FIFO_SIZE_ADDRESS 0x2b77 #define IMAGE_0_BBH_TX_FIFO_SIZE_BYTE_SIZE 0x0001 #define IMAGE_0_BBH_TX_FIFO_SIZE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_MIRRORING_SCRATCH_ADDRESS 0x2b78 #define IMAGE_0_MIRRORING_SCRATCH_BYTE_SIZE 0x0008 #define IMAGE_0_MIRRORING_SCRATCH_LOG2_BYTE_SIZE 0x0003 #define IMAGE_0_SCHEDULING_QUEUE_AGING_VECTOR_ADDRESS 0x2b80 #define IMAGE_0_SCHEDULING_QUEUE_AGING_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_0_SCHEDULING_QUEUE_AGING_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_0_SCHEDULING_QUEUE_AGING_VECTOR_SIZE 5 #define RDD_IMAGE_0_SCHEDULING_QUEUE_AGING_VECTOR_LOG2_SIZE 3 #define IMAGE_0_FIRST_QUEUE_MAPPING_ADDRESS 0x2b94 #define IMAGE_0_FIRST_QUEUE_MAPPING_BYTE_SIZE 0x0001 #define IMAGE_0_FIRST_QUEUE_MAPPING_LOG2_BYTE_SIZE 0x0001 #define IMAGE_0_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_ADDRESS 0x2ba0 #define IMAGE_0_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_0_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_0_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_SIZE 5 #define RDD_IMAGE_0_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_LOG2_SIZE 3 #define IMAGE_0_RATE_LIMITER_VALID_TABLE_ADDRESS 0x2bc0 #define IMAGE_0_RATE_LIMITER_VALID_TABLE_BYTE_SIZE 0x0010 #define IMAGE_0_RATE_LIMITER_VALID_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_0_RATE_LIMITER_VALID_TABLE_SIZE 4 #define RDD_IMAGE_0_RATE_LIMITER_VALID_TABLE_LOG2_SIZE 2 #define IMAGE_0_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_ADDRESS 0x2bd0 #define IMAGE_0_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_0_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_0_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_0_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_0_FPM_GLOBAL_CFG_ADDRESS 0x2be0 #define IMAGE_0_FPM_GLOBAL_CFG_BYTE_SIZE 0x000c #define IMAGE_0_FPM_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_0_NATC_TBL_CFG_ADDRESS 0x2c00 #define IMAGE_0_NATC_TBL_CFG_BYTE_SIZE 0x0030 #define IMAGE_0_NATC_TBL_CFG_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_0_NATC_TBL_CFG_SIZE 2 #define RDD_IMAGE_0_NATC_TBL_CFG_LOG2_SIZE 1 /* IMAGE_1 */ #define IMAGE_1_DHD_FLOW_RING_CACHE_CTX_TABLE_ADDRESS 0x0000 #define IMAGE_1_DHD_FLOW_RING_CACHE_CTX_TABLE_BYTE_SIZE 0x0300 #define IMAGE_1_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_1_DHD_FLOW_RING_CACHE_CTX_TABLE_SIZE 48 #define RDD_IMAGE_1_DHD_FLOW_RING_CACHE_CTX_TABLE_LOG2_SIZE 6 #define IMAGE_1_DHD_POST_COMMON_RADIO_DATA_ADDRESS 0x0300 #define IMAGE_1_DHD_POST_COMMON_RADIO_DATA_BYTE_SIZE 0x00c0 #define IMAGE_1_DHD_POST_COMMON_RADIO_DATA_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_DHD_POST_COMMON_RADIO_DATA_SIZE 3 #define RDD_IMAGE_1_DHD_POST_COMMON_RADIO_DATA_LOG2_SIZE 2 #define IMAGE_1_DS_CPU_REASON_TO_METER_TABLE_ADDRESS 0x03c0 #define IMAGE_1_DS_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040 #define IMAGE_1_DS_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_DS_CPU_REASON_TO_METER_TABLE_SIZE 64 #define RDD_IMAGE_1_DS_CPU_REASON_TO_METER_TABLE_LOG2_SIZE 6 #define IMAGE_1_CPU_RX_SCRATCHPAD_ADDRESS 0x0400 #define IMAGE_1_CPU_RX_SCRATCHPAD_BYTE_SIZE 0x0200 #define IMAGE_1_CPU_RX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_1_CPU_RX_SCRATCHPAD_SIZE 64 #define RDD_IMAGE_1_CPU_RX_SCRATCHPAD_LOG2_SIZE 6 #define IMAGE_1_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_ADDRESS 0x0600 #define IMAGE_1_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_BYTE_SIZE 0x0180 #define IMAGE_1_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_1_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_SIZE 48 #define RDD_IMAGE_1_WLAN_MCAST_SSID_MAC_ADDRESS_TABLE_LOG2_SIZE 6 #define IMAGE_1_DS_CPU_RX_METER_TABLE_ADDRESS 0x0780 #define IMAGE_1_DS_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080 #define IMAGE_1_DS_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_DS_CPU_RX_METER_TABLE_SIZE 16 #define RDD_IMAGE_1_DS_CPU_RX_METER_TABLE_LOG2_SIZE 4 #define IMAGE_1_RX_FLOW_TABLE_ADDRESS 0x0800 #define IMAGE_1_RX_FLOW_TABLE_BYTE_SIZE 0x0280 #define IMAGE_1_RX_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_1_RX_FLOW_TABLE_SIZE 320 #define RDD_IMAGE_1_RX_FLOW_TABLE_LOG2_SIZE 9 #define IMAGE_1_US_CPU_RX_METER_TABLE_ADDRESS 0x0a80 #define IMAGE_1_US_CPU_RX_METER_TABLE_BYTE_SIZE 0x0080 #define IMAGE_1_US_CPU_RX_METER_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_US_CPU_RX_METER_TABLE_SIZE 16 #define RDD_IMAGE_1_US_CPU_RX_METER_TABLE_LOG2_SIZE 4 #define IMAGE_1_CPU_RING_INTERRUPT_COUNTER_TABLE_ADDRESS 0x0b00 #define IMAGE_1_CPU_RING_INTERRUPT_COUNTER_TABLE_BYTE_SIZE 0x0090 #define IMAGE_1_CPU_RING_INTERRUPT_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_CPU_RING_INTERRUPT_COUNTER_TABLE_SIZE 18 #define RDD_IMAGE_1_CPU_RING_INTERRUPT_COUNTER_TABLE_LOG2_SIZE 5 #define IMAGE_1_DHD_FPM_POOL_NUMBER_MAPPING_TABLE_ADDRESS 0x0b90 #define IMAGE_1_DHD_FPM_POOL_NUMBER_MAPPING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_DHD_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_DHD_FPM_POOL_NUMBER_MAPPING_TABLE_SIZE 16 #define RDD_IMAGE_1_DHD_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_SIZE 4 #define IMAGE_1_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x0ba0 #define IMAGE_1_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020 #define IMAGE_1_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_RUNNER_GLOBAL_REGISTERS_INIT_SIZE 8 #define RDD_IMAGE_1_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE 3 #define IMAGE_1_US_CPU_REASON_TO_METER_TABLE_ADDRESS 0x0bc0 #define IMAGE_1_US_CPU_REASON_TO_METER_TABLE_BYTE_SIZE 0x0040 #define IMAGE_1_US_CPU_REASON_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_US_CPU_REASON_TO_METER_TABLE_SIZE 64 #define RDD_IMAGE_1_US_CPU_REASON_TO_METER_TABLE_LOG2_SIZE 6 #define IMAGE_1_RUNNER_PROFILING_TRACE_BUFFER_ADDRESS 0x0c00 #define IMAGE_1_RUNNER_PROFILING_TRACE_BUFFER_BYTE_SIZE 0x0200 #define IMAGE_1_RUNNER_PROFILING_TRACE_BUFFER_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_1_RUNNER_PROFILING_TRACE_BUFFER_SIZE 128 #define RDD_IMAGE_1_RUNNER_PROFILING_TRACE_BUFFER_LOG2_SIZE 7 #define IMAGE_1_CPU_RECYCLE_SRAM_PD_FIFO_ADDRESS 0x0e00 #define IMAGE_1_CPU_RECYCLE_SRAM_PD_FIFO_BYTE_SIZE 0x0100 #define IMAGE_1_CPU_RECYCLE_SRAM_PD_FIFO_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_CPU_RECYCLE_SRAM_PD_FIFO_SIZE 16 #define RDD_IMAGE_1_CPU_RECYCLE_SRAM_PD_FIFO_LOG2_SIZE 4 #define IMAGE_1_DHD_TX_POST_FLOW_RING_BUFFER_ADDRESS 0x0f00 #define IMAGE_1_DHD_TX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0090 #define IMAGE_1_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_DHD_TX_POST_FLOW_RING_BUFFER_SIZE 3 #define RDD_IMAGE_1_DHD_TX_POST_FLOW_RING_BUFFER_LOG2_SIZE 2 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_ADDRESS 0x0f90 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_DIRECT_PROCESSING_PD_TABLE_ADDRESS 0x0fa0 #define IMAGE_1_DIRECT_PROCESSING_PD_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_DIRECT_PROCESSING_PD_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_DIRECT_PROCESSING_PD_TABLE_SIZE 2 #define RDD_IMAGE_1_DIRECT_PROCESSING_PD_TABLE_LOG2_SIZE 1 #define IMAGE_1_WLAN_MCAST_DFT_LIST_ENTRY_SCRATCH_ADDRESS 0x0fc0 #define IMAGE_1_WLAN_MCAST_DFT_LIST_ENTRY_SCRATCH_BYTE_SIZE 0x0040 #define IMAGE_1_WLAN_MCAST_DFT_LIST_ENTRY_SCRATCH_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_WLAN_MCAST_DFT_LIST_ENTRY_SCRATCH_SIZE 64 #define RDD_IMAGE_1_WLAN_MCAST_DFT_LIST_ENTRY_SCRATCH_LOG2_SIZE 6 #define IMAGE_1_WLAN_MCAST_DHD_STATION_TABLE_ADDRESS 0x1000 #define IMAGE_1_WLAN_MCAST_DHD_STATION_TABLE_BYTE_SIZE 0x0200 #define IMAGE_1_WLAN_MCAST_DHD_STATION_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_1_WLAN_MCAST_DHD_STATION_TABLE_SIZE 64 #define RDD_IMAGE_1_WLAN_MCAST_DHD_STATION_TABLE_LOG2_SIZE 6 #define IMAGE_1_DHD_TX_POST_PD_FIFO_TABLE_ADDRESS 0x1200 #define IMAGE_1_DHD_TX_POST_PD_FIFO_TABLE_BYTE_SIZE 0x00c0 #define IMAGE_1_DHD_TX_POST_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_DHD_TX_POST_PD_FIFO_TABLE_SIZE 12 #define RDD_IMAGE_1_DHD_TX_POST_PD_FIFO_TABLE_LOG2_SIZE 4 #define IMAGE_1_UPDATE_FIFO_TABLE_ADDRESS 0x12c0 #define IMAGE_1_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_1_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_1_SCRATCH_ADDRESS 0x12e0 #define IMAGE_1_SCRATCH_BYTE_SIZE 0x0020 #define IMAGE_1_SCRATCH_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_SCRATCH_SIZE 8 #define RDD_IMAGE_1_SCRATCH_LOG2_SIZE 3 #define IMAGE_1_CPU_REASON_AND_VPORT_TO_METER_TABLE_ADDRESS 0x1300 #define IMAGE_1_CPU_REASON_AND_VPORT_TO_METER_TABLE_BYTE_SIZE 0x0078 #define IMAGE_1_CPU_REASON_AND_VPORT_TO_METER_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_CPU_REASON_AND_VPORT_TO_METER_TABLE_SIZE 120 #define RDD_IMAGE_1_CPU_REASON_AND_VPORT_TO_METER_TABLE_LOG2_SIZE 7 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x1378 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_DHD_L2_HEADER_ADDRESS 0x1380 #define IMAGE_1_DHD_L2_HEADER_BYTE_SIZE 0x0048 #define IMAGE_1_DHD_L2_HEADER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_DHD_L2_HEADER_SIZE 72 #define RDD_IMAGE_1_DHD_L2_HEADER_LOG2_SIZE 7 #define IMAGE_1_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x13c8 #define IMAGE_1_CPU_RX_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_1_CPU_RX_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_CPU_RX_PSRAM_GET_NEXT_SCRATCHPAD_ADDRESS 0x13d0 #define IMAGE_1_CPU_RX_PSRAM_GET_NEXT_SCRATCHPAD_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_RX_PSRAM_GET_NEXT_SCRATCHPAD_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_CPU_RX_PSRAM_GET_NEXT_SCRATCHPAD_SIZE 4 #define RDD_IMAGE_1_CPU_RX_PSRAM_GET_NEXT_SCRATCHPAD_LOG2_SIZE 2 #define IMAGE_1_DHD_MCAST_DISPATCHER_CREDIT_TABLE_ADDRESS 0x13e0 #define IMAGE_1_DHD_MCAST_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_1_DHD_MCAST_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_DHD_MCAST_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_1_DHD_MCAST_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_1_CPU_RX_INTERRUPT_SCRATCH_ADDRESS 0x13ec #define IMAGE_1_CPU_RX_INTERRUPT_SCRATCH_BYTE_SIZE 0x0004 #define IMAGE_1_CPU_RX_INTERRUPT_SCRATCH_LOG2_BYTE_SIZE 0x0002 #define IMAGE_1_CPU_RX_COPY_DISPATCHER_CREDIT_TABLE_ADDRESS 0x13f0 #define IMAGE_1_CPU_RX_COPY_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_1_CPU_RX_COPY_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_CPU_RX_COPY_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_1_CPU_RX_COPY_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_1_TASK_IDX_ADDRESS 0x13fc #define IMAGE_1_TASK_IDX_BYTE_SIZE 0x0004 #define IMAGE_1_TASK_IDX_LOG2_BYTE_SIZE 0x0002 #define IMAGE_1_DHD_FLOW_RING_CACHE_LKP_TABLE_ADDRESS 0x1400 #define IMAGE_1_DHD_FLOW_RING_CACHE_LKP_TABLE_BYTE_SIZE 0x0060 #define IMAGE_1_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_DHD_FLOW_RING_CACHE_LKP_TABLE_SIZE 48 #define RDD_IMAGE_1_DHD_FLOW_RING_CACHE_LKP_TABLE_LOG2_SIZE 6 #define IMAGE_1_DHD_DOORBELL_VALUE_ADDRESS 0x1460 #define IMAGE_1_DHD_DOORBELL_VALUE_BYTE_SIZE 0x000c #define IMAGE_1_DHD_DOORBELL_VALUE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_DHD_DOORBELL_VALUE_SIZE 3 #define RDD_IMAGE_1_DHD_DOORBELL_VALUE_LOG2_SIZE 2 #define IMAGE_1_CPU_FEED_RING_INTERRUPT_THRESHOLD_ADDRESS 0x146c #define IMAGE_1_CPU_FEED_RING_INTERRUPT_THRESHOLD_BYTE_SIZE 0x0002 #define IMAGE_1_CPU_FEED_RING_INTERRUPT_THRESHOLD_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_CPU_FEED_RING_INTERRUPT_COUNTER_ADDRESS 0x146e #define IMAGE_1_CPU_FEED_RING_INTERRUPT_COUNTER_BYTE_SIZE 0x0002 #define IMAGE_1_CPU_FEED_RING_INTERRUPT_COUNTER_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_ADDRESS 0x1470 #define IMAGE_1_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_CPU_RX_COPY_PD_FIFO_TABLE_ADDRESS 0x1480 #define IMAGE_1_CPU_RX_COPY_PD_FIFO_TABLE_BYTE_SIZE 0x0040 #define IMAGE_1_CPU_RX_COPY_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_CPU_RX_COPY_PD_FIFO_TABLE_SIZE 4 #define RDD_IMAGE_1_CPU_RX_COPY_PD_FIFO_TABLE_LOG2_SIZE 2 #define IMAGE_1_REGISTERS_BUFFER_ADDRESS 0x14c0 #define IMAGE_1_REGISTERS_BUFFER_BYTE_SIZE 0x0080 #define IMAGE_1_REGISTERS_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_1_REGISTERS_BUFFER_SIZE 32 #define RDD_IMAGE_1_REGISTERS_BUFFER_LOG2_SIZE 5 #define IMAGE_1_DHD_TX_POST_UPDATE_FIFO_TABLE_ADDRESS 0x1540 #define IMAGE_1_DHD_TX_POST_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_DHD_TX_POST_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_DHD_TX_POST_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_1_DHD_TX_POST_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_1_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_ADDRESS 0x1560 #define IMAGE_1_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_SIZE 2 #define RDD_IMAGE_1_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_LOG2_SIZE 1 #define IMAGE_1_CPU_INTERRUPT_COALESCING_TABLE_ADDRESS 0x1570 #define IMAGE_1_CPU_INTERRUPT_COALESCING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_INTERRUPT_COALESCING_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_WLAN_MCAST_DFT_LIST_SIZE_ADDRESS 0x1580 #define IMAGE_1_WLAN_MCAST_DFT_LIST_SIZE_BYTE_SIZE 0x0040 #define IMAGE_1_WLAN_MCAST_DFT_LIST_SIZE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_WLAN_MCAST_DFT_LIST_SIZE_SIZE 64 #define RDD_IMAGE_1_WLAN_MCAST_DFT_LIST_SIZE_LOG2_SIZE 6 #define IMAGE_1_DHD_MCAST_UPDATE_FIFO_TABLE_ADDRESS 0x15c0 #define IMAGE_1_DHD_MCAST_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_DHD_MCAST_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_DHD_MCAST_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_1_DHD_MCAST_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_1_CPU_FEED_RING_DESCRIPTOR_TABLE_ADDRESS 0x15e0 #define IMAGE_1_CPU_FEED_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_FEED_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_CPU_RX_LOCAL_SCRATCH_ADDRESS 0x15f0 #define IMAGE_1_CPU_RX_LOCAL_SCRATCH_BYTE_SIZE 0x0010 #define IMAGE_1_CPU_RX_LOCAL_SCRATCH_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_1_CPU_RX_LOCAL_SCRATCH_SIZE 2 #define RDD_IMAGE_1_CPU_RX_LOCAL_SCRATCH_LOG2_SIZE 1 #define IMAGE_1_NATC_TBL_CFG_ADDRESS 0x1600 #define IMAGE_1_NATC_TBL_CFG_BYTE_SIZE 0x0030 #define IMAGE_1_NATC_TBL_CFG_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_NATC_TBL_CFG_SIZE 2 #define RDD_IMAGE_1_NATC_TBL_CFG_LOG2_SIZE 1 #define IMAGE_1_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x1630 #define IMAGE_1_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_1_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_WLAN_MCAST_DFT_ADDR_ADDRESS 0x1638 #define IMAGE_1_WLAN_MCAST_DFT_ADDR_BYTE_SIZE 0x0008 #define IMAGE_1_WLAN_MCAST_DFT_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_CPU_RX_COPY_UPDATE_FIFO_TABLE_ADDRESS 0x1640 #define IMAGE_1_CPU_RX_COPY_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_CPU_RX_COPY_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_CPU_RX_COPY_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_1_CPU_RX_COPY_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_1_FPM_GLOBAL_CFG_ADDRESS 0x1660 #define IMAGE_1_FPM_GLOBAL_CFG_BYTE_SIZE 0x000c #define IMAGE_1_FPM_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_SRAM_DUMMY_STORE_ADDRESS 0x166c #define IMAGE_1_SRAM_DUMMY_STORE_BYTE_SIZE 0x0001 #define IMAGE_1_SRAM_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_MAC_TYPE_ADDRESS 0x166d #define IMAGE_1_MAC_TYPE_BYTE_SIZE 0x0001 #define IMAGE_1_MAC_TYPE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_ADDRESS 0x1670 #define IMAGE_1_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_BYTE_SIZE 0x0008 #define IMAGE_1_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_CPU_RX_COPY_LOCAL_SCRATCH_ADDRESS 0x1678 #define IMAGE_1_CPU_RX_COPY_LOCAL_SCRATCH_BYTE_SIZE 0x0008 #define IMAGE_1_CPU_RX_COPY_LOCAL_SCRATCH_LOG2_BYTE_SIZE 0x0003 #define IMAGE_1_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_ADDRESS 0x1680 #define IMAGE_1_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0030 #define IMAGE_1_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_SIZE 3 #define RDD_IMAGE_1_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_SIZE 2 #define IMAGE_1_WLAN_MCAST_SCRATCHPAD_ADDRESS 0x16b0 #define IMAGE_1_WLAN_MCAST_SCRATCHPAD_BYTE_SIZE 0x0004 #define IMAGE_1_WLAN_MCAST_SCRATCHPAD_LOG2_BYTE_SIZE 0x0002 #define IMAGE_1_DIRECT_PROCESSING_EPON_CONTROL_SCRATCH_ADDRESS 0x16b8 #define IMAGE_1_DIRECT_PROCESSING_EPON_CONTROL_SCRATCH_BYTE_SIZE 0x0001 #define IMAGE_1_DIRECT_PROCESSING_EPON_CONTROL_SCRATCH_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_PD_FIFO_TABLE_ADDRESS 0x16c0 #define IMAGE_1_PD_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_PD_FIFO_TABLE_SIZE 2 #define RDD_IMAGE_1_PD_FIFO_TABLE_LOG2_SIZE 1 #define IMAGE_1_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_ADDRESS 0x1700 #define IMAGE_1_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_BYTE_SIZE 0x0030 #define IMAGE_1_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_SIZE 3 #define RDD_IMAGE_1_DHD_TX_POST_FLOW_RING_MGMT_DESCRIPTOR_BUFFER_LOG2_SIZE 2 #define IMAGE_1_DHD_MCAST_PD_FIFO_TABLE_ADDRESS 0x1740 #define IMAGE_1_DHD_MCAST_PD_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_1_DHD_MCAST_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_1_DHD_MCAST_PD_FIFO_TABLE_SIZE 2 #define RDD_IMAGE_1_DHD_MCAST_PD_FIFO_TABLE_LOG2_SIZE 1 #define IMAGE_1_CPU_REASON_TO_TC_ADDRESS 0x1760 #define IMAGE_1_CPU_REASON_TO_TC_BYTE_SIZE 0x0040 #define IMAGE_1_CPU_REASON_TO_TC_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_CPU_REASON_TO_TC_SIZE 64 #define RDD_IMAGE_1_CPU_REASON_TO_TC_LOG2_SIZE 6 #define IMAGE_1_TC_TO_CPU_RXQ_ADDRESS 0x17a0 #define IMAGE_1_TC_TO_CPU_RXQ_BYTE_SIZE 0x0040 #define IMAGE_1_TC_TO_CPU_RXQ_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_TC_TO_CPU_RXQ_SIZE 64 #define RDD_IMAGE_1_TC_TO_CPU_RXQ_LOG2_SIZE 6 #define IMAGE_1_WLAN_MCAST_DHD_STATION_CTX_TABLE_ADDRESS 0x1800 #define IMAGE_1_WLAN_MCAST_DHD_STATION_CTX_TABLE_BYTE_SIZE 0x0040 #define IMAGE_1_WLAN_MCAST_DHD_STATION_CTX_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_WLAN_MCAST_DHD_STATION_CTX_TABLE_SIZE 64 #define RDD_IMAGE_1_WLAN_MCAST_DHD_STATION_CTX_TABLE_LOG2_SIZE 6 #define IMAGE_1_EXC_TC_TO_CPU_RXQ_ADDRESS 0x1840 #define IMAGE_1_EXC_TC_TO_CPU_RXQ_BYTE_SIZE 0x0040 #define IMAGE_1_EXC_TC_TO_CPU_RXQ_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_EXC_TC_TO_CPU_RXQ_SIZE 64 #define RDD_IMAGE_1_EXC_TC_TO_CPU_RXQ_LOG2_SIZE 6 #define IMAGE_1_VPORT_TO_CPU_OBJ_ADDRESS 0x1880 #define IMAGE_1_VPORT_TO_CPU_OBJ_BYTE_SIZE 0x0028 #define IMAGE_1_VPORT_TO_CPU_OBJ_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_1_VPORT_TO_CPU_OBJ_SIZE 40 #define RDD_IMAGE_1_VPORT_TO_CPU_OBJ_LOG2_SIZE 6 #define IMAGE_1_DHD_HW_CFG_ADDRESS 0x1900 #define IMAGE_1_DHD_HW_CFG_BYTE_SIZE 0x000c #define IMAGE_1_DHD_HW_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_SCRATCH_ADDRESS 0x1980 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_SCRATCH_BYTE_SIZE 0x0008 #define IMAGE_1_CPU_RECYCLE_INTERRUPT_SCRATCH_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_1_CPU_RECYCLE_INTERRUPT_SCRATCH_SIZE 2 #define RDD_IMAGE_1_CPU_RECYCLE_INTERRUPT_SCRATCH_LOG2_SIZE 1 #define IMAGE_1_CPU_RECYCLE_SHADOW_RD_IDX_ADDRESS 0x1a00 #define IMAGE_1_CPU_RECYCLE_SHADOW_RD_IDX_BYTE_SIZE 0x0002 #define IMAGE_1_CPU_RECYCLE_SHADOW_RD_IDX_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_CPU_RECYCLE_SHADOW_WR_IDX_ADDRESS 0x1a80 #define IMAGE_1_CPU_RECYCLE_SHADOW_WR_IDX_BYTE_SIZE 0x0002 #define IMAGE_1_CPU_RECYCLE_SHADOW_WR_IDX_LOG2_BYTE_SIZE 0x0001 #define IMAGE_1_CPU_RING_DESCRIPTORS_TABLE_ADDRESS 0x3000 #define IMAGE_1_CPU_RING_DESCRIPTORS_TABLE_BYTE_SIZE 0x0100 #define IMAGE_1_CPU_RING_DESCRIPTORS_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_1_CPU_RING_DESCRIPTORS_TABLE_SIZE 16 #define RDD_IMAGE_1_CPU_RING_DESCRIPTORS_TABLE_LOG2_SIZE 4 /* IMAGE_2 */ #define IMAGE_2_REPORTING_QUEUE_DESCRIPTOR_TABLE_ADDRESS 0x0000 #define IMAGE_2_REPORTING_QUEUE_DESCRIPTOR_TABLE_BYTE_SIZE 0x0a00 #define IMAGE_2_REPORTING_QUEUE_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x000c #define RDD_IMAGE_2_REPORTING_QUEUE_DESCRIPTOR_TABLE_SIZE 160 #define RDD_IMAGE_2_REPORTING_QUEUE_DESCRIPTOR_TABLE_LOG2_SIZE 8 #define IMAGE_2_TX_FLOW_TABLE_ADDRESS 0x0a00 #define IMAGE_2_TX_FLOW_TABLE_BYTE_SIZE 0x0140 #define IMAGE_2_TX_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_2_TX_FLOW_TABLE_SIZE 320 #define RDD_IMAGE_2_TX_FLOW_TABLE_LOG2_SIZE 9 #define IMAGE_2_DHD_TX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x0b40 #define IMAGE_2_DHD_TX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0030 #define IMAGE_2_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_2_DHD_TX_COMPLETE_FLOW_RING_BUFFER_SIZE 3 #define RDD_IMAGE_2_DHD_TX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE 2 #define IMAGE_2_CPU_TX_FPM_POOL_NUMBER_MAPPING_TABLE_ADDRESS 0x0b70 #define IMAGE_2_CPU_TX_FPM_POOL_NUMBER_MAPPING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_2_CPU_TX_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_CPU_TX_FPM_POOL_NUMBER_MAPPING_TABLE_SIZE 16 #define RDD_IMAGE_2_CPU_TX_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_SIZE 4 #define IMAGE_2_REPORTING_QUEUE_ACCUMULATED_TABLE_ADDRESS 0x0b80 #define IMAGE_2_REPORTING_QUEUE_ACCUMULATED_TABLE_BYTE_SIZE 0x0080 #define IMAGE_2_REPORTING_QUEUE_ACCUMULATED_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_2_REPORTING_QUEUE_ACCUMULATED_TABLE_SIZE 16 #define RDD_IMAGE_2_REPORTING_QUEUE_ACCUMULATED_TABLE_LOG2_SIZE 4 #define IMAGE_2_CPU_TX_SCRATCHPAD_ADDRESS 0x0c00 #define IMAGE_2_CPU_TX_SCRATCHPAD_BYTE_SIZE 0x0400 #define IMAGE_2_CPU_TX_SCRATCHPAD_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_2_CPU_TX_SCRATCHPAD_SIZE 128 #define RDD_IMAGE_2_CPU_TX_SCRATCHPAD_LOG2_SIZE 7 #define IMAGE_2_RUNNER_PROFILING_TRACE_BUFFER_ADDRESS 0x1000 #define IMAGE_2_RUNNER_PROFILING_TRACE_BUFFER_BYTE_SIZE 0x0200 #define IMAGE_2_RUNNER_PROFILING_TRACE_BUFFER_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_2_RUNNER_PROFILING_TRACE_BUFFER_SIZE 128 #define RDD_IMAGE_2_RUNNER_PROFILING_TRACE_BUFFER_LOG2_SIZE 7 #define IMAGE_2_DHD_COMPLETE_COMMON_RADIO_DATA_ADDRESS 0x1200 #define IMAGE_2_DHD_COMPLETE_COMMON_RADIO_DATA_BYTE_SIZE 0x0138 #define IMAGE_2_DHD_COMPLETE_COMMON_RADIO_DATA_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_2_DHD_COMPLETE_COMMON_RADIO_DATA_SIZE 3 #define RDD_IMAGE_2_DHD_COMPLETE_COMMON_RADIO_DATA_LOG2_SIZE 2 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x1338 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_2_QUEUE_THRESHOLD_VECTOR_ADDRESS 0x1340 #define IMAGE_2_QUEUE_THRESHOLD_VECTOR_BYTE_SIZE 0x0024 #define IMAGE_2_QUEUE_THRESHOLD_VECTOR_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_2_QUEUE_THRESHOLD_VECTOR_SIZE 9 #define RDD_IMAGE_2_QUEUE_THRESHOLD_VECTOR_LOG2_SIZE 4 #define IMAGE_2_GHOST_REPORTING_GLOBAL_CFG_ADDRESS 0x1364 #define IMAGE_2_GHOST_REPORTING_GLOBAL_CFG_BYTE_SIZE 0x0004 #define IMAGE_2_GHOST_REPORTING_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0002 #define IMAGE_2_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x1368 #define IMAGE_2_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_2_DHD_CPU_RECYCLE_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_2_FPM_REPLY_ADDRESS 0x1370 #define IMAGE_2_FPM_REPLY_BYTE_SIZE 0x0010 #define IMAGE_2_FPM_REPLY_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_FPM_REPLY_SIZE 2 #define RDD_IMAGE_2_FPM_REPLY_LOG2_SIZE 1 #define IMAGE_2_DHD_RX_COMPLETE_FLOW_RING_BUFFER_ADDRESS 0x1380 #define IMAGE_2_DHD_RX_COMPLETE_FLOW_RING_BUFFER_BYTE_SIZE 0x0060 #define IMAGE_2_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_2_DHD_RX_COMPLETE_FLOW_RING_BUFFER_SIZE 3 #define RDD_IMAGE_2_DHD_RX_COMPLETE_FLOW_RING_BUFFER_LOG2_SIZE 2 #define IMAGE_2_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x13e0 #define IMAGE_2_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020 #define IMAGE_2_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_RUNNER_GLOBAL_REGISTERS_INIT_SIZE 8 #define RDD_IMAGE_2_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE 3 #define IMAGE_2_CPU_RECYCLE_SRAM_PD_FIFO_ADDRESS 0x1400 #define IMAGE_2_CPU_RECYCLE_SRAM_PD_FIFO_BYTE_SIZE 0x0100 #define IMAGE_2_CPU_RECYCLE_SRAM_PD_FIFO_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_2_CPU_RECYCLE_SRAM_PD_FIFO_SIZE 16 #define RDD_IMAGE_2_CPU_RECYCLE_SRAM_PD_FIFO_LOG2_SIZE 4 #define IMAGE_2_REPORTING_COUNTER_TABLE_ADDRESS 0x1500 #define IMAGE_2_REPORTING_COUNTER_TABLE_BYTE_SIZE 0x00a0 #define IMAGE_2_REPORTING_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_2_REPORTING_COUNTER_TABLE_SIZE 40 #define RDD_IMAGE_2_REPORTING_COUNTER_TABLE_LOG2_SIZE 6 #define IMAGE_2_GHOST_REPORTING_QUEUE_STATUS_BIT_VECTOR_TABLE_ADDRESS 0x15a0 #define IMAGE_2_GHOST_REPORTING_QUEUE_STATUS_BIT_VECTOR_TABLE_BYTE_SIZE 0x0014 #define IMAGE_2_GHOST_REPORTING_QUEUE_STATUS_BIT_VECTOR_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_GHOST_REPORTING_QUEUE_STATUS_BIT_VECTOR_TABLE_SIZE 5 #define RDD_IMAGE_2_GHOST_REPORTING_QUEUE_STATUS_BIT_VECTOR_TABLE_LOG2_SIZE 3 #define IMAGE_2_TASK_IDX_ADDRESS 0x15b4 #define IMAGE_2_TASK_IDX_BYTE_SIZE 0x0004 #define IMAGE_2_TASK_IDX_LOG2_BYTE_SIZE 0x0002 #define IMAGE_2_REPORT_BBH_TX_QUEUE_ID_TABLE_ADDRESS 0x15b8 #define IMAGE_2_REPORT_BBH_TX_QUEUE_ID_TABLE_BYTE_SIZE 0x0008 #define IMAGE_2_REPORT_BBH_TX_QUEUE_ID_TABLE_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_2_REPORT_BBH_TX_QUEUE_ID_TABLE_SIZE 2 #define RDD_IMAGE_2_REPORT_BBH_TX_QUEUE_ID_TABLE_LOG2_SIZE 1 #define IMAGE_2_CPU_TX_EGRESS_UPDATE_FIFO_TABLE_ADDRESS 0x15c0 #define IMAGE_2_CPU_TX_EGRESS_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_2_CPU_TX_EGRESS_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_CPU_TX_EGRESS_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_2_CPU_TX_EGRESS_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_ADDRESS 0x15e0 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_COALESCING_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_2_XGPON_REPORT_TABLE_ADDRESS 0x15f0 #define IMAGE_2_XGPON_REPORT_TABLE_BYTE_SIZE 0x0010 #define IMAGE_2_XGPON_REPORT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_XGPON_REPORT_TABLE_SIZE 4 #define RDD_IMAGE_2_XGPON_REPORT_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_RX_POST_FLOW_RING_BUFFER_ADDRESS 0x1600 #define IMAGE_2_DHD_RX_POST_FLOW_RING_BUFFER_BYTE_SIZE 0x0060 #define IMAGE_2_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_2_DHD_RX_POST_FLOW_RING_BUFFER_SIZE 3 #define RDD_IMAGE_2_DHD_RX_POST_FLOW_RING_BUFFER_LOG2_SIZE 2 #define IMAGE_2_REGISTERS_BUFFER_ADDRESS 0x1660 #define IMAGE_2_REGISTERS_BUFFER_BYTE_SIZE 0x0080 #define IMAGE_2_REGISTERS_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_2_REGISTERS_BUFFER_SIZE 32 #define RDD_IMAGE_2_REGISTERS_BUFFER_LOG2_SIZE 5 #define IMAGE_2_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS 0x16e0 #define IMAGE_2_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_2_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_2_CPU_TX_EGRESS_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_RX_POST_RING_SIZE_ADDRESS 0x16ec #define IMAGE_2_DHD_RX_POST_RING_SIZE_BYTE_SIZE 0x0002 #define IMAGE_2_DHD_RX_POST_RING_SIZE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_DHD_RX_COMPLETE_RING_SIZE_ADDRESS 0x16ee #define IMAGE_2_DHD_RX_COMPLETE_RING_SIZE_BYTE_SIZE 0x0002 #define IMAGE_2_DHD_RX_COMPLETE_RING_SIZE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_ADDRESS 0x16f0 #define IMAGE_2_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_2_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_2_CPU_TX_INGRESS_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_TX_COMPLETE_RING_SIZE_ADDRESS 0x16fc #define IMAGE_2_DHD_TX_COMPLETE_RING_SIZE_BYTE_SIZE 0x0002 #define IMAGE_2_DHD_TX_COMPLETE_RING_SIZE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_SRAM_DUMMY_STORE_ADDRESS 0x16fe #define IMAGE_2_SRAM_DUMMY_STORE_BYTE_SIZE 0x0001 #define IMAGE_2_SRAM_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_BBH_TX_INGRESS_COUNTER_TABLE_ADDRESS 0x16ff #define IMAGE_2_BBH_TX_INGRESS_COUNTER_TABLE_BYTE_SIZE 0x0001 #define IMAGE_2_BBH_TX_INGRESS_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_NATC_TBL_CFG_ADDRESS 0x1700 #define IMAGE_2_NATC_TBL_CFG_BYTE_SIZE 0x0030 #define IMAGE_2_NATC_TBL_CFG_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_2_NATC_TBL_CFG_SIZE 2 #define RDD_IMAGE_2_NATC_TBL_CFG_LOG2_SIZE 1 #define IMAGE_2_DHD_RX_COMPLETE_0_DISPATCHER_CREDIT_TABLE_ADDRESS 0x1730 #define IMAGE_2_DHD_RX_COMPLETE_0_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_2_DHD_RX_COMPLETE_0_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_DHD_RX_COMPLETE_0_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_2_DHD_RX_COMPLETE_0_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_2_CPU_TX_INGRESS_UPDATE_FIFO_TABLE_ADDRESS 0x1740 #define IMAGE_2_CPU_TX_INGRESS_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_2_CPU_TX_INGRESS_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_CPU_TX_INGRESS_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_2_CPU_TX_INGRESS_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_2_DHD_RX_COMPLETE_1_DISPATCHER_CREDIT_TABLE_ADDRESS 0x1760 #define IMAGE_2_DHD_RX_COMPLETE_1_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_2_DHD_RX_COMPLETE_1_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_DHD_RX_COMPLETE_1_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_2_DHD_RX_COMPLETE_1_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_RX_COMPLETE_2_DISPATCHER_CREDIT_TABLE_ADDRESS 0x1770 #define IMAGE_2_DHD_RX_COMPLETE_2_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_2_DHD_RX_COMPLETE_2_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_DHD_RX_COMPLETE_2_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_2_DHD_RX_COMPLETE_2_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_ADDRESS 0x1780 #define IMAGE_2_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0030 #define IMAGE_2_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_2_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_SIZE 3 #define RDD_IMAGE_2_DHD_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_SIZE 2 #define IMAGE_2_DHD_DOORBELL_VALUE_ADDRESS 0x17b0 #define IMAGE_2_DHD_DOORBELL_VALUE_BYTE_SIZE 0x000c #define IMAGE_2_DHD_DOORBELL_VALUE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_DHD_DOORBELL_VALUE_SIZE 3 #define RDD_IMAGE_2_DHD_DOORBELL_VALUE_LOG2_SIZE 2 #define IMAGE_2_CPU_TX_EGRESS_PD_FIFO_TABLE_ADDRESS 0x17c0 #define IMAGE_2_CPU_TX_EGRESS_PD_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_2_CPU_TX_EGRESS_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_CPU_TX_EGRESS_PD_FIFO_TABLE_SIZE 2 #define RDD_IMAGE_2_CPU_TX_EGRESS_PD_FIFO_TABLE_LOG2_SIZE 1 #define IMAGE_2_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_ADDRESS 0x17e0 #define IMAGE_2_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_2_CPU_RECYCLE_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_2_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_ADDRESS 0x17f0 #define IMAGE_2_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_2_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_SIZE 2 #define RDD_IMAGE_2_CPU_RECYCLE_RING_INDEX_DDR_ADDR_TABLE_LOG2_SIZE 1 #define IMAGE_2_CPU_TX_INGRESS_PD_FIFO_TABLE_ADDRESS 0x1800 #define IMAGE_2_CPU_TX_INGRESS_PD_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_2_CPU_TX_INGRESS_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_CPU_TX_INGRESS_PD_FIFO_TABLE_SIZE 2 #define RDD_IMAGE_2_CPU_TX_INGRESS_PD_FIFO_TABLE_LOG2_SIZE 1 #define IMAGE_2_FPM_GLOBAL_CFG_ADDRESS 0x1820 #define IMAGE_2_FPM_GLOBAL_CFG_BYTE_SIZE 0x000c #define IMAGE_2_FPM_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_2_XGPON_REPORT_ZERO_SENT_TABLE_ADDRESS 0x1830 #define IMAGE_2_XGPON_REPORT_ZERO_SENT_TABLE_BYTE_SIZE 0x000a #define IMAGE_2_XGPON_REPORT_ZERO_SENT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_2_XGPON_REPORT_ZERO_SENT_TABLE_SIZE 10 #define RDD_IMAGE_2_XGPON_REPORT_ZERO_SENT_TABLE_LOG2_SIZE 4 #define IMAGE_2_DHD_FPM_REPLY_ADDRESS 0x1840 #define IMAGE_2_DHD_FPM_REPLY_BYTE_SIZE 0x0018 #define IMAGE_2_DHD_FPM_REPLY_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_2_DHD_FPM_REPLY_SIZE 24 #define RDD_IMAGE_2_DHD_FPM_REPLY_LOG2_SIZE 5 #define IMAGE_2_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_ADDRESS 0x1858 #define IMAGE_2_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_BYTE_SIZE 0x0008 #define IMAGE_2_CPU_RECYCLE_RING_INTERRUPT_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0003 #define IMAGE_2_BBH_TX_EGRESS_REPORT_COUNTER_TABLE_ADDRESS 0x1860 #define IMAGE_2_BBH_TX_EGRESS_REPORT_COUNTER_TABLE_BYTE_SIZE 0x0008 #define IMAGE_2_BBH_TX_EGRESS_REPORT_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0003 #define IMAGE_2_DHD_HW_CFG_ADDRESS 0x1880 #define IMAGE_2_DHD_HW_CFG_BYTE_SIZE 0x000c #define IMAGE_2_DHD_HW_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_SCRATCH_ADDRESS 0x1900 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_SCRATCH_BYTE_SIZE 0x0008 #define IMAGE_2_CPU_RECYCLE_INTERRUPT_SCRATCH_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_2_CPU_RECYCLE_INTERRUPT_SCRATCH_SIZE 2 #define RDD_IMAGE_2_CPU_RECYCLE_INTERRUPT_SCRATCH_LOG2_SIZE 1 #define IMAGE_2_CPU_RECYCLE_SHADOW_RD_IDX_ADDRESS 0x1980 #define IMAGE_2_CPU_RECYCLE_SHADOW_RD_IDX_BYTE_SIZE 0x0002 #define IMAGE_2_CPU_RECYCLE_SHADOW_RD_IDX_LOG2_BYTE_SIZE 0x0001 #define IMAGE_2_CPU_RECYCLE_SHADOW_WR_IDX_ADDRESS 0x1a00 #define IMAGE_2_CPU_RECYCLE_SHADOW_WR_IDX_BYTE_SIZE 0x0002 #define IMAGE_2_CPU_RECYCLE_SHADOW_WR_IDX_LOG2_BYTE_SIZE 0x0001 /* IMAGE_3 */ #define IMAGE_3_PD_FIFO_TABLE_ADDRESS 0x0000 #define IMAGE_3_PD_FIFO_TABLE_BYTE_SIZE 0x1400 #define IMAGE_3_PD_FIFO_TABLE_LOG2_BYTE_SIZE 0x000d #define RDD_IMAGE_3_PD_FIFO_TABLE_SIZE 320 #define RDD_IMAGE_3_PD_FIFO_TABLE_LOG2_SIZE 9 #define IMAGE_3_COMPLEX_SCHEDULER_TABLE_ADDRESS 0x1400 #define IMAGE_3_COMPLEX_SCHEDULER_TABLE_BYTE_SIZE 0x0400 #define IMAGE_3_COMPLEX_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_3_COMPLEX_SCHEDULER_TABLE_SIZE 16 #define RDD_IMAGE_3_COMPLEX_SCHEDULER_TABLE_LOG2_SIZE 4 #define IMAGE_3_SCHEDULING_QUEUE_TABLE_ADDRESS 0x1800 #define IMAGE_3_SCHEDULING_QUEUE_TABLE_BYTE_SIZE 0x0500 #define IMAGE_3_SCHEDULING_QUEUE_TABLE_LOG2_BYTE_SIZE 0x000b #define RDD_IMAGE_3_SCHEDULING_QUEUE_TABLE_SIZE 160 #define RDD_IMAGE_3_SCHEDULING_QUEUE_TABLE_LOG2_SIZE 8 #define IMAGE_3_TM_FLOW_CNTR_TABLE_ADDRESS 0x1d00 #define IMAGE_3_TM_FLOW_CNTR_TABLE_BYTE_SIZE 0x0080 #define IMAGE_3_TM_FLOW_CNTR_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_3_TM_FLOW_CNTR_TABLE_SIZE 128 #define RDD_IMAGE_3_TM_FLOW_CNTR_TABLE_LOG2_SIZE 7 #define IMAGE_3_BBH_TX_EGRESS_COUNTER_TABLE_ADDRESS 0x1d80 #define IMAGE_3_BBH_TX_EGRESS_COUNTER_TABLE_BYTE_SIZE 0x0040 #define IMAGE_3_BBH_TX_EGRESS_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_3_BBH_TX_EGRESS_COUNTER_TABLE_SIZE 8 #define RDD_IMAGE_3_BBH_TX_EGRESS_COUNTER_TABLE_LOG2_SIZE 3 #define IMAGE_3_BBH_TX_EPON_INGRESS_COUNTER_TABLE_ADDRESS 0x1dc0 #define IMAGE_3_BBH_TX_EPON_INGRESS_COUNTER_TABLE_BYTE_SIZE 0x0028 #define IMAGE_3_BBH_TX_EPON_INGRESS_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_3_BBH_TX_EPON_INGRESS_COUNTER_TABLE_SIZE 40 #define RDD_IMAGE_3_BBH_TX_EPON_INGRESS_COUNTER_TABLE_LOG2_SIZE 6 #define IMAGE_3_BBH_TX_QUEUE_ID_TABLE_ADDRESS 0x1de8 #define IMAGE_3_BBH_TX_QUEUE_ID_TABLE_BYTE_SIZE 0x0008 #define IMAGE_3_BBH_TX_QUEUE_ID_TABLE_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_3_BBH_TX_QUEUE_ID_TABLE_SIZE 2 #define RDD_IMAGE_3_BBH_TX_QUEUE_ID_TABLE_LOG2_SIZE 1 #define IMAGE_3_OVERALL_RATE_LIMITER_TABLE_ADDRESS 0x1df0 #define IMAGE_3_OVERALL_RATE_LIMITER_TABLE_BYTE_SIZE 0x0010 #define IMAGE_3_OVERALL_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_3_BASIC_SCHEDULER_TABLE_ADDRESS 0x1e00 #define IMAGE_3_BASIC_SCHEDULER_TABLE_BYTE_SIZE 0x0200 #define IMAGE_3_BASIC_SCHEDULER_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_3_BASIC_SCHEDULER_TABLE_SIZE 32 #define RDD_IMAGE_3_BASIC_SCHEDULER_TABLE_LOG2_SIZE 5 #define IMAGE_3_BASIC_RATE_LIMITER_TABLE_ADDRESS 0x2000 #define IMAGE_3_BASIC_RATE_LIMITER_TABLE_BYTE_SIZE 0x0800 #define IMAGE_3_BASIC_RATE_LIMITER_TABLE_LOG2_BYTE_SIZE 0x000b #define RDD_IMAGE_3_BASIC_RATE_LIMITER_TABLE_SIZE 128 #define RDD_IMAGE_3_BASIC_RATE_LIMITER_TABLE_LOG2_SIZE 7 #define IMAGE_3_RUNNER_PROFILING_TRACE_BUFFER_ADDRESS 0x2800 #define IMAGE_3_RUNNER_PROFILING_TRACE_BUFFER_BYTE_SIZE 0x0200 #define IMAGE_3_RUNNER_PROFILING_TRACE_BUFFER_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_3_RUNNER_PROFILING_TRACE_BUFFER_SIZE 128 #define RDD_IMAGE_3_RUNNER_PROFILING_TRACE_BUFFER_LOG2_SIZE 7 #define IMAGE_3_BBH_QUEUE_TABLE_ADDRESS 0x2a00 #define IMAGE_3_BBH_QUEUE_TABLE_BYTE_SIZE 0x00a0 #define IMAGE_3_BBH_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_3_BBH_QUEUE_TABLE_SIZE 40 #define RDD_IMAGE_3_BBH_QUEUE_TABLE_LOG2_SIZE 6 #define IMAGE_3_REGISTERS_BUFFER_ADDRESS 0x2aa0 #define IMAGE_3_REGISTERS_BUFFER_BYTE_SIZE 0x0080 #define IMAGE_3_REGISTERS_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_3_REGISTERS_BUFFER_SIZE 32 #define RDD_IMAGE_3_REGISTERS_BUFFER_LOG2_SIZE 5 #define IMAGE_3_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x2b20 #define IMAGE_3_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020 #define IMAGE_3_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_RUNNER_GLOBAL_REGISTERS_INIT_SIZE 8 #define RDD_IMAGE_3_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE 3 #define IMAGE_3_BBH_TX_EPON_EGRESS_COUNTER_TABLE_ADDRESS 0x2b40 #define IMAGE_3_BBH_TX_EPON_EGRESS_COUNTER_TABLE_BYTE_SIZE 0x0028 #define IMAGE_3_BBH_TX_EPON_EGRESS_COUNTER_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_3_BBH_TX_EPON_EGRESS_COUNTER_TABLE_SIZE 5 #define RDD_IMAGE_3_BBH_TX_EPON_EGRESS_COUNTER_TABLE_LOG2_SIZE 3 #define IMAGE_3_BBH_TX_EPON_QUEUE_ID_TABLE_ADDRESS 0x2b68 #define IMAGE_3_BBH_TX_EPON_QUEUE_ID_TABLE_BYTE_SIZE 0x0008 #define IMAGE_3_BBH_TX_EPON_QUEUE_ID_TABLE_LOG2_BYTE_SIZE 0x0003 #define RDD_IMAGE_3_BBH_TX_EPON_QUEUE_ID_TABLE_SIZE 2 #define RDD_IMAGE_3_BBH_TX_EPON_QUEUE_ID_TABLE_LOG2_SIZE 1 #define IMAGE_3_FLUSH_DISPATCHER_CREDIT_TABLE_ADDRESS 0x2b70 #define IMAGE_3_FLUSH_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_3_FLUSH_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_3_FLUSH_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_3_FLUSH_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_3_BUDGET_ALLOCATION_TIMER_VALUE_ADDRESS 0x2b7c #define IMAGE_3_BUDGET_ALLOCATION_TIMER_VALUE_BYTE_SIZE 0x0002 #define IMAGE_3_BUDGET_ALLOCATION_TIMER_VALUE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_BB_DESTINATION_TABLE_ADDRESS 0x2b7e #define IMAGE_3_BB_DESTINATION_TABLE_BYTE_SIZE 0x0002 #define IMAGE_3_BB_DESTINATION_TABLE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_TM_ACTION_PTR_TABLE_ADDRESS 0x2b80 #define IMAGE_3_TM_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_3_TM_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_3_TM_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_3_TM_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_3_SCHEDULING_GLOBAL_FLUSH_CFG_ADDRESS 0x2ba2 #define IMAGE_3_SCHEDULING_GLOBAL_FLUSH_CFG_BYTE_SIZE 0x0001 #define IMAGE_3_SCHEDULING_GLOBAL_FLUSH_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_SCHEDULING_FLUSH_GLOBAL_CFG_ADDRESS 0x2ba3 #define IMAGE_3_SCHEDULING_FLUSH_GLOBAL_CFG_BYTE_SIZE 0x0001 #define IMAGE_3_SCHEDULING_FLUSH_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_TASK_IDX_ADDRESS 0x2ba4 #define IMAGE_3_TASK_IDX_BYTE_SIZE 0x0004 #define IMAGE_3_TASK_IDX_LOG2_BYTE_SIZE 0x0002 #define IMAGE_3_MIRRORING_SCRATCH_ADDRESS 0x2ba8 #define IMAGE_3_MIRRORING_SCRATCH_BYTE_SIZE 0x0008 #define IMAGE_3_MIRRORING_SCRATCH_LOG2_BYTE_SIZE 0x0003 #define IMAGE_3_DISPATCHER_CREDIT_TABLE_ADDRESS 0x2bb0 #define IMAGE_3_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_3_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_3_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_3_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_3_TX_MIRRORING_CONFIGURATION_ADDRESS 0x2bbc #define IMAGE_3_TX_MIRRORING_CONFIGURATION_BYTE_SIZE 0x0002 #define IMAGE_3_TX_MIRRORING_CONFIGURATION_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_SRAM_DUMMY_STORE_ADDRESS 0x2bbe #define IMAGE_3_SRAM_DUMMY_STORE_BYTE_SIZE 0x0001 #define IMAGE_3_SRAM_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_BBH_TX_FIFO_SIZE_ADDRESS 0x2bbf #define IMAGE_3_BBH_TX_FIFO_SIZE_BYTE_SIZE 0x0001 #define IMAGE_3_BBH_TX_FIFO_SIZE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_EPON_UPDATE_FIFO_TABLE_ADDRESS 0x2bc0 #define IMAGE_3_EPON_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_3_EPON_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_EPON_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_3_EPON_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_3_SCHEDULING_FLUSH_VECTOR_ADDRESS 0x2be0 #define IMAGE_3_SCHEDULING_FLUSH_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_3_SCHEDULING_FLUSH_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_SCHEDULING_FLUSH_VECTOR_SIZE 5 #define RDD_IMAGE_3_SCHEDULING_FLUSH_VECTOR_LOG2_SIZE 3 #define IMAGE_3_FIRST_QUEUE_MAPPING_ADDRESS 0x2bf4 #define IMAGE_3_FIRST_QUEUE_MAPPING_BYTE_SIZE 0x0001 #define IMAGE_3_FIRST_QUEUE_MAPPING_LOG2_BYTE_SIZE 0x0001 #define IMAGE_3_NATC_TBL_CFG_ADDRESS 0x2c00 #define IMAGE_3_NATC_TBL_CFG_BYTE_SIZE 0x0030 #define IMAGE_3_NATC_TBL_CFG_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_3_NATC_TBL_CFG_SIZE 2 #define RDD_IMAGE_3_NATC_TBL_CFG_LOG2_SIZE 1 #define IMAGE_3_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_ADDRESS 0x2c30 #define IMAGE_3_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_BYTE_SIZE 0x000c #define IMAGE_3_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_3_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_SIZE 3 #define RDD_IMAGE_3_TX_MIRRORING_DISPATCHER_CREDIT_TABLE_LOG2_SIZE 2 #define IMAGE_3_UPDATE_FIFO_TABLE_ADDRESS 0x2c40 #define IMAGE_3_UPDATE_FIFO_TABLE_BYTE_SIZE 0x0020 #define IMAGE_3_UPDATE_FIFO_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_UPDATE_FIFO_TABLE_SIZE 8 #define RDD_IMAGE_3_UPDATE_FIFO_TABLE_LOG2_SIZE 3 #define IMAGE_3_SCHEDULING_QUEUE_AGING_VECTOR_ADDRESS 0x2c60 #define IMAGE_3_SCHEDULING_QUEUE_AGING_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_3_SCHEDULING_QUEUE_AGING_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_SCHEDULING_QUEUE_AGING_VECTOR_SIZE 5 #define RDD_IMAGE_3_SCHEDULING_QUEUE_AGING_VECTOR_LOG2_SIZE 3 #define IMAGE_3_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_ADDRESS 0x2c80 #define IMAGE_3_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_BYTE_SIZE 0x0014 #define IMAGE_3_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_3_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_SIZE 5 #define RDD_IMAGE_3_SCHEDULING_AGGREGATION_CONTEXT_VECTOR_LOG2_SIZE 3 #define IMAGE_3_RATE_LIMITER_VALID_TABLE_ADDRESS 0x2ca0 #define IMAGE_3_RATE_LIMITER_VALID_TABLE_BYTE_SIZE 0x0010 #define IMAGE_3_RATE_LIMITER_VALID_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_3_RATE_LIMITER_VALID_TABLE_SIZE 4 #define RDD_IMAGE_3_RATE_LIMITER_VALID_TABLE_LOG2_SIZE 2 #define IMAGE_3_FPM_GLOBAL_CFG_ADDRESS 0x2cb0 #define IMAGE_3_FPM_GLOBAL_CFG_BYTE_SIZE 0x000c #define IMAGE_3_FPM_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0004 /* IMAGE_4 */ #define IMAGE_4_RX_FLOW_TABLE_ADDRESS 0x0000 #define IMAGE_4_RX_FLOW_TABLE_BYTE_SIZE 0x0280 #define IMAGE_4_RX_FLOW_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_4_RX_FLOW_TABLE_SIZE 320 #define RDD_IMAGE_4_RX_FLOW_TABLE_LOG2_SIZE 9 #define IMAGE_4_LAYER2_HEADER_COPY_MAPPING_TABLE_ADDRESS 0x0280 #define IMAGE_4_LAYER2_HEADER_COPY_MAPPING_TABLE_BYTE_SIZE 0x0078 #define IMAGE_4_LAYER2_HEADER_COPY_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_LAYER2_HEADER_COPY_MAPPING_TABLE_SIZE 30 #define RDD_IMAGE_4_LAYER2_HEADER_COPY_MAPPING_TABLE_LOG2_SIZE 5 #define IMAGE_4_IPTV_CONFIGURATION_TABLE_ADDRESS 0x02f8 #define IMAGE_4_IPTV_CONFIGURATION_TABLE_BYTE_SIZE 0x0008 #define IMAGE_4_IPTV_CONFIGURATION_TABLE_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_ADDRESS 0x0300 #define IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_BYTE_SIZE 0x0100 #define IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_LOG2_BYTE_SIZE 0x0008 #define RDD_IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_SIZE 4 #define RDD_IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_LOG2_SIZE 2 #define RDD_IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_SIZE2 64 #define RDD_IMAGE_4_DSCP_TO_PBITS_MAP_TABLE_LOG2_SIZE2 6 #define IMAGE_4_PROCESSING_CPU_RX_SCRATCHPAD_ADDRESS 0x0400 #define IMAGE_4_PROCESSING_CPU_RX_SCRATCHPAD_BYTE_SIZE 0x0020 #define IMAGE_4_PROCESSING_CPU_RX_SCRATCHPAD_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_4_PROCESSING_CPU_RX_SCRATCHPAD_SIZE 8 #define RDD_IMAGE_4_PROCESSING_CPU_RX_SCRATCHPAD_LOG2_SIZE 3 #define IMAGE_4_RUNNER_GLOBAL_REGISTERS_INIT_ADDRESS 0x0420 #define IMAGE_4_RUNNER_GLOBAL_REGISTERS_INIT_BYTE_SIZE 0x0020 #define IMAGE_4_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_4_RUNNER_GLOBAL_REGISTERS_INIT_SIZE 8 #define RDD_IMAGE_4_RUNNER_GLOBAL_REGISTERS_INIT_LOG2_SIZE 3 #define IMAGE_4_GLOBAL_DSCP_TO_PBITS_TABLE_ADDRESS 0x0440 #define IMAGE_4_GLOBAL_DSCP_TO_PBITS_TABLE_BYTE_SIZE 0x0040 #define IMAGE_4_GLOBAL_DSCP_TO_PBITS_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_GLOBAL_DSCP_TO_PBITS_TABLE_SIZE2 64 #define RDD_IMAGE_4_GLOBAL_DSCP_TO_PBITS_TABLE_LOG2_SIZE2 6 #define IMAGE_4_VPORT_CFG_TABLE_ADDRESS 0x0480 #define IMAGE_4_VPORT_CFG_TABLE_BYTE_SIZE 0x0050 #define IMAGE_4_VPORT_CFG_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_VPORT_CFG_TABLE_SIZE 40 #define RDD_IMAGE_4_VPORT_CFG_TABLE_LOG2_SIZE 6 #define IMAGE_4_FPM_POOL_NUMBER_MAPPING_TABLE_ADDRESS 0x04d0 #define IMAGE_4_FPM_POOL_NUMBER_MAPPING_TABLE_BYTE_SIZE 0x0010 #define IMAGE_4_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_4_FPM_POOL_NUMBER_MAPPING_TABLE_SIZE 16 #define RDD_IMAGE_4_FPM_POOL_NUMBER_MAPPING_TABLE_LOG2_SIZE 4 #define IMAGE_4_VPORT_TO_DSCP_TO_PBITS_TABLE_ADDRESS 0x04e0 #define IMAGE_4_VPORT_TO_DSCP_TO_PBITS_TABLE_BYTE_SIZE 0x0020 #define IMAGE_4_VPORT_TO_DSCP_TO_PBITS_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_4_VPORT_TO_DSCP_TO_PBITS_TABLE_SIZE 32 #define RDD_IMAGE_4_VPORT_TO_DSCP_TO_PBITS_TABLE_LOG2_SIZE 5 #define IMAGE_4_INGRESS_FILTER_PROFILE_TABLE_ADDRESS 0x0500 #define IMAGE_4_INGRESS_FILTER_PROFILE_TABLE_BYTE_SIZE 0x0080 #define IMAGE_4_INGRESS_FILTER_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_INGRESS_FILTER_PROFILE_TABLE_SIZE 16 #define RDD_IMAGE_4_INGRESS_FILTER_PROFILE_TABLE_LOG2_SIZE 4 #define IMAGE_4_POLICER_PARAMS_TABLE_ADDRESS 0x0580 #define IMAGE_4_POLICER_PARAMS_TABLE_BYTE_SIZE 0x0050 #define IMAGE_4_POLICER_PARAMS_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_POLICER_PARAMS_TABLE_SIZE 80 #define RDD_IMAGE_4_POLICER_PARAMS_TABLE_LOG2_SIZE 7 #define IMAGE_4_INGRESS_FILTER_L2_REASON_TABLE_ADDRESS 0x05d0 #define IMAGE_4_INGRESS_FILTER_L2_REASON_TABLE_BYTE_SIZE 0x0010 #define IMAGE_4_INGRESS_FILTER_L2_REASON_TABLE_LOG2_BYTE_SIZE 0x0004 #define RDD_IMAGE_4_INGRESS_FILTER_L2_REASON_TABLE_SIZE 16 #define RDD_IMAGE_4_INGRESS_FILTER_L2_REASON_TABLE_LOG2_SIZE 4 #define IMAGE_4_TCAM_IC_HANDLER_TABLE_ADDRESS 0x05e0 #define IMAGE_4_TCAM_IC_HANDLER_TABLE_BYTE_SIZE 0x0020 #define IMAGE_4_TCAM_IC_HANDLER_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_4_TCAM_IC_HANDLER_TABLE_SIZE 16 #define RDD_IMAGE_4_TCAM_IC_HANDLER_TABLE_LOG2_SIZE 4 #define IMAGE_4_LAYER2_GRE_TUNNEL_TABLE_ADDRESS 0x0600 #define IMAGE_4_LAYER2_GRE_TUNNEL_TABLE_BYTE_SIZE 0x0180 #define IMAGE_4_LAYER2_GRE_TUNNEL_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_4_LAYER2_GRE_TUNNEL_TABLE_SIZE 12 #define RDD_IMAGE_4_LAYER2_GRE_TUNNEL_TABLE_LOG2_SIZE 4 #define IMAGE_4_PBIT_TO_GEM_TABLE_ADDRESS 0x0780 #define IMAGE_4_PBIT_TO_GEM_TABLE_BYTE_SIZE 0x0040 #define IMAGE_4_PBIT_TO_GEM_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_PBIT_TO_GEM_TABLE_SIZE 8 #define RDD_IMAGE_4_PBIT_TO_GEM_TABLE_LOG2_SIZE 3 #define RDD_IMAGE_4_PBIT_TO_GEM_TABLE_SIZE2 8 #define RDD_IMAGE_4_PBIT_TO_GEM_TABLE_LOG2_SIZE2 3 #define IMAGE_4_DUAL_STACK_LITE_TABLE_ADDRESS 0x07c0 #define IMAGE_4_DUAL_STACK_LITE_TABLE_BYTE_SIZE 0x0040 #define IMAGE_4_DUAL_STACK_LITE_TABLE_LOG2_BYTE_SIZE 0x0006 #define IMAGE_4_TC_TO_QUEUE_TABLE_ADDRESS 0x0800 #define IMAGE_4_TC_TO_QUEUE_TABLE_BYTE_SIZE 0x0208 #define IMAGE_4_TC_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_4_TC_TO_QUEUE_TABLE_SIZE 65 #define RDD_IMAGE_4_TC_TO_QUEUE_TABLE_LOG2_SIZE 7 #define IMAGE_4_REGISTERS_BUFFER_ADDRESS 0x0a08 #define IMAGE_4_REGISTERS_BUFFER_BYTE_SIZE 0x0080 #define IMAGE_4_REGISTERS_BUFFER_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_REGISTERS_BUFFER_SIZE 32 #define RDD_IMAGE_4_REGISTERS_BUFFER_LOG2_SIZE 5 #define IMAGE_4_RX_FLOW_CONTEXT_DDR_ADDR_ADDRESS 0x0a88 #define IMAGE_4_RX_FLOW_CONTEXT_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_4_RX_FLOW_CONTEXT_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_NULL_BUFFER_ADDRESS 0x0a90 #define IMAGE_4_NULL_BUFFER_BYTE_SIZE 0x0008 #define IMAGE_4_NULL_BUFFER_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_CPU_RX_INTERRUPT_ID_DDR_ADDR_ADDRESS 0x0a98 #define IMAGE_4_CPU_RX_INTERRUPT_ID_DDR_ADDR_BYTE_SIZE 0x0008 #define IMAGE_4_CPU_RX_INTERRUPT_ID_DDR_ADDR_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_BRIDGE_CFG_TABLE_ADDRESS 0x0aa0 #define IMAGE_4_BRIDGE_CFG_TABLE_BYTE_SIZE 0x0018 #define IMAGE_4_BRIDGE_CFG_TABLE_LOG2_BYTE_SIZE 0x0005 #define RDD_IMAGE_4_BRIDGE_CFG_TABLE_SIZE 3 #define RDD_IMAGE_4_BRIDGE_CFG_TABLE_LOG2_SIZE 2 #define IMAGE_4_DEFAULT_BRIDGE_CFG_ADDRESS 0x0ab8 #define IMAGE_4_DEFAULT_BRIDGE_CFG_BYTE_SIZE 0x0008 #define IMAGE_4_DEFAULT_BRIDGE_CFG_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_LOOPBACK_QUEUE_TABLE_ADDRESS 0x0ac0 #define IMAGE_4_LOOPBACK_QUEUE_TABLE_BYTE_SIZE 0x0028 #define IMAGE_4_LOOPBACK_QUEUE_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_LOOPBACK_QUEUE_TABLE_SIZE 40 #define RDD_IMAGE_4_LOOPBACK_QUEUE_TABLE_LOG2_SIZE 6 #define IMAGE_4_SYSTEM_CONFIGURATION_ADDRESS 0x0ae8 #define IMAGE_4_SYSTEM_CONFIGURATION_BYTE_SIZE 0x0005 #define IMAGE_4_SYSTEM_CONFIGURATION_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_FORCE_DSCP_ADDRESS 0x0aed #define IMAGE_4_FORCE_DSCP_BYTE_SIZE 0x0001 #define IMAGE_4_FORCE_DSCP_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_CORE_ID_TABLE_ADDRESS 0x0aee #define IMAGE_4_CORE_ID_TABLE_BYTE_SIZE 0x0001 #define IMAGE_4_CORE_ID_TABLE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_SRAM_DUMMY_STORE_ADDRESS 0x0aef #define IMAGE_4_SRAM_DUMMY_STORE_BYTE_SIZE 0x0001 #define IMAGE_4_SRAM_DUMMY_STORE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_CPU_FEED_RING_DESCRIPTOR_TABLE_ADDRESS 0x0af0 #define IMAGE_4_CPU_FEED_RING_DESCRIPTOR_TABLE_BYTE_SIZE 0x0010 #define IMAGE_4_CPU_FEED_RING_DESCRIPTOR_TABLE_LOG2_BYTE_SIZE 0x0004 #define IMAGE_4_INGRESS_FILTER_VPORT_TO_PROFILE_TABLE_ADDRESS 0x0b00 #define IMAGE_4_INGRESS_FILTER_VPORT_TO_PROFILE_TABLE_BYTE_SIZE 0x0040 #define IMAGE_4_INGRESS_FILTER_VPORT_TO_PROFILE_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_INGRESS_FILTER_VPORT_TO_PROFILE_TABLE_SIZE 64 #define RDD_IMAGE_4_INGRESS_FILTER_VPORT_TO_PROFILE_TABLE_LOG2_SIZE 6 #define IMAGE_4_TCAM_IC_CFG_TABLE_ADDRESS 0x0b40 #define IMAGE_4_TCAM_IC_CFG_TABLE_BYTE_SIZE 0x0050 #define IMAGE_4_TCAM_IC_CFG_TABLE_LOG2_BYTE_SIZE 0x0007 #define RDD_IMAGE_4_TCAM_IC_CFG_TABLE_SIZE 5 #define RDD_IMAGE_4_TCAM_IC_CFG_TABLE_LOG2_SIZE 3 #define IMAGE_4_FPM_GLOBAL_CFG_ADDRESS 0x0b90 #define IMAGE_4_FPM_GLOBAL_CFG_BYTE_SIZE 0x000c #define IMAGE_4_FPM_GLOBAL_CFG_LOG2_BYTE_SIZE 0x0004 #define IMAGE_4_TASK_IDX_ADDRESS 0x0b9c #define IMAGE_4_TASK_IDX_BYTE_SIZE 0x0004 #define IMAGE_4_TASK_IDX_LOG2_BYTE_SIZE 0x0002 #define IMAGE_4_TUNNELS_PARSING_CFG_ADDRESS 0x0ba0 #define IMAGE_4_TUNNELS_PARSING_CFG_BYTE_SIZE 0x0008 #define IMAGE_4_TUNNELS_PARSING_CFG_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_IPTV_CFG_TABLE_ADDRESS 0x0ba8 #define IMAGE_4_IPTV_CFG_TABLE_BYTE_SIZE 0x0008 #define IMAGE_4_IPTV_CFG_TABLE_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_IPTV_DDR_CTX_TABLE_ADDRESS_ADDRESS 0x0bb0 #define IMAGE_4_IPTV_DDR_CTX_TABLE_ADDRESS_BYTE_SIZE 0x0008 #define IMAGE_4_IPTV_DDR_CTX_TABLE_ADDRESS_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_NAT_CACHE_CFG_ADDRESS 0x0bb8 #define IMAGE_4_NAT_CACHE_CFG_BYTE_SIZE 0x0007 #define IMAGE_4_NAT_CACHE_CFG_LOG2_BYTE_SIZE 0x0003 #define IMAGE_4_IC_DEBUG_COUNTER_MODE_ADDRESS 0x0bbf #define IMAGE_4_IC_DEBUG_COUNTER_MODE_BYTE_SIZE 0x0001 #define IMAGE_4_IC_DEBUG_COUNTER_MODE_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_QUEUE_THRESHOLD_VECTOR_ADDRESS 0x0bc0 #define IMAGE_4_QUEUE_THRESHOLD_VECTOR_BYTE_SIZE 0x0024 #define IMAGE_4_QUEUE_THRESHOLD_VECTOR_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_QUEUE_THRESHOLD_VECTOR_SIZE 9 #define RDD_IMAGE_4_QUEUE_THRESHOLD_VECTOR_LOG2_SIZE 4 #define IMAGE_4_CPU_FEED_RING_INTERRUPT_THRESHOLD_ADDRESS 0x0be4 #define IMAGE_4_CPU_FEED_RING_INTERRUPT_THRESHOLD_BYTE_SIZE 0x0002 #define IMAGE_4_CPU_FEED_RING_INTERRUPT_THRESHOLD_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_DHD_FPM_LOW_THRESHOLD_ADDRESS 0x0be6 #define IMAGE_4_DHD_FPM_LOW_THRESHOLD_BYTE_SIZE 0x0002 #define IMAGE_4_DHD_FPM_LOW_THRESHOLD_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_DHD_FPM_HIGH_THRESHOLD_ADDRESS 0x0be8 #define IMAGE_4_DHD_FPM_HIGH_THRESHOLD_BYTE_SIZE 0x0002 #define IMAGE_4_DHD_FPM_HIGH_THRESHOLD_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_RX_MIRRORING_CONFIGURATION_ADDRESS 0x0bea #define IMAGE_4_RX_MIRRORING_CONFIGURATION_BYTE_SIZE 0x0002 #define IMAGE_4_RX_MIRRORING_CONFIGURATION_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_INGRESS_FILTER_1588_CFG_ADDRESS 0x0bec #define IMAGE_4_INGRESS_FILTER_1588_CFG_BYTE_SIZE 0x0001 #define IMAGE_4_INGRESS_FILTER_1588_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_INGRESS_FILTER_CFG_ADDRESS 0x0bf0 #define IMAGE_4_INGRESS_FILTER_CFG_BYTE_SIZE 0x0002 #define IMAGE_4_INGRESS_FILTER_CFG_LOG2_BYTE_SIZE 0x0001 #define IMAGE_4_PBIT_TO_QUEUE_TABLE_ADDRESS 0x0c00 #define IMAGE_4_PBIT_TO_QUEUE_TABLE_BYTE_SIZE 0x0208 #define IMAGE_4_PBIT_TO_QUEUE_TABLE_LOG2_BYTE_SIZE 0x000a #define RDD_IMAGE_4_PBIT_TO_QUEUE_TABLE_SIZE 65 #define RDD_IMAGE_4_PBIT_TO_QUEUE_TABLE_LOG2_SIZE 7 #define IMAGE_4_FLOW_BASED_ACTION_PTR_TABLE_ADDRESS 0x0e40 #define IMAGE_4_FLOW_BASED_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_4_FLOW_BASED_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_FLOW_BASED_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_4_FLOW_BASED_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_4_RULE_BASED_ACTION_PTR_TABLE_ADDRESS 0x0e80 #define IMAGE_4_RULE_BASED_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_4_RULE_BASED_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_RULE_BASED_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_4_RULE_BASED_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_4_RULE_BASED_CONTEXT_ACTION_PTR_TABLE_ADDRESS 0x0ec0 #define IMAGE_4_RULE_BASED_CONTEXT_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_4_RULE_BASED_CONTEXT_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_RULE_BASED_CONTEXT_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_4_RULE_BASED_CONTEXT_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_4_NATC_TBL_CFG_ADDRESS 0x0f00 #define IMAGE_4_NATC_TBL_CFG_BYTE_SIZE 0x0030 #define IMAGE_4_NATC_TBL_CFG_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_NATC_TBL_CFG_SIZE 2 #define RDD_IMAGE_4_NATC_TBL_CFG_LOG2_SIZE 1 #define IMAGE_4_IPTV_ACTION_PTR_TABLE_ADDRESS 0x0f40 #define IMAGE_4_IPTV_ACTION_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_4_IPTV_ACTION_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_IPTV_ACTION_PTR_TABLE_SIZE 17 #define RDD_IMAGE_4_IPTV_ACTION_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_4_VLAN_ACTION_GPE_HANDLER_PTR_TABLE_ADDRESS 0x0f80 #define IMAGE_4_VLAN_ACTION_GPE_HANDLER_PTR_TABLE_BYTE_SIZE 0x0022 #define IMAGE_4_VLAN_ACTION_GPE_HANDLER_PTR_TABLE_LOG2_BYTE_SIZE 0x0006 #define RDD_IMAGE_4_VLAN_ACTION_GPE_HANDLER_PTR_TABLE_SIZE 17 #define RDD_IMAGE_4_VLAN_ACTION_GPE_HANDLER_PTR_TABLE_LOG2_SIZE 5 #define IMAGE_4_DS_PACKET_BUFFER_ADDRESS 0x1000 #define IMAGE_4_DS_PACKET_BUFFER_BYTE_SIZE 0x1000 #define IMAGE_4_DS_PACKET_BUFFER_LOG2_BYTE_SIZE 0x000c #define RDD_IMAGE_4_DS_PACKET_BUFFER_SIZE 8 #define RDD_IMAGE_4_DS_PACKET_BUFFER_LOG2_SIZE 3 #define IMAGE_4_IC_EXT_CONTEXT_TABLE_ADDRESS 0x2000 #define IMAGE_4_IC_EXT_CONTEXT_TABLE_BYTE_SIZE 0x1000 #define IMAGE_4_IC_EXT_CONTEXT_TABLE_LOG2_BYTE_SIZE 0x000c #define RDD_IMAGE_4_IC_EXT_CONTEXT_TABLE_SIZE 1024 #define RDD_IMAGE_4_IC_EXT_CONTEXT_TABLE_LOG2_SIZE 10 #define IMAGE_4_RUNNER_PROFILING_TRACE_BUFFER_ADDRESS 0x3000 #define IMAGE_4_RUNNER_PROFILING_TRACE_BUFFER_BYTE_SIZE 0x0200 #define IMAGE_4_RUNNER_PROFILING_TRACE_BUFFER_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_4_RUNNER_PROFILING_TRACE_BUFFER_SIZE 128 #define RDD_IMAGE_4_RUNNER_PROFILING_TRACE_BUFFER_LOG2_SIZE 7 #define IMAGE_4_TCAM_IC_CMD_TABLE_ADDRESS 0x3200 #define IMAGE_4_TCAM_IC_CMD_TABLE_BYTE_SIZE 0x0180 #define IMAGE_4_TCAM_IC_CMD_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_4_TCAM_IC_CMD_TABLE_SIZE 6 #define RDD_IMAGE_4_TCAM_IC_CMD_TABLE_LOG2_SIZE 3 #define RDD_IMAGE_4_TCAM_IC_CMD_TABLE_SIZE2 16 #define RDD_IMAGE_4_TCAM_IC_CMD_TABLE_LOG2_SIZE2 4 #define IMAGE_4_TX_FLOW_TABLE_ADDRESS 0x3400 #define IMAGE_4_TX_FLOW_TABLE_BYTE_SIZE 0x0140 #define IMAGE_4_TX_FLOW_TABLE_LOG2_BYTE_SIZE 0x0009 #define RDD_IMAGE_4_TX_FLOW_TABLE_SIZE 320 #define RDD_IMAGE_4_TX_FLOW_TABLE_LOG2_SIZE 9 #endif #endif /* _RDD_RUNNER_DEFS_AUTO_H_ */