/dts-v1/; /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "qcom-ipq6018.dtsi" #include "qcom-ipq6018-rpm-regulator.dtsi" #include "qcom-ipq6018-cpr-regulator.dtsi" #include "qcom-ipq6018-cp-cpu.dtsi" / { #address-cells = <0x2>; #size-cells = <0x2>; model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP02-C1"; compatible = "qcom,ipq6018-cp02", "qcom,ipq6018"; interrupt-parent = <&intc>; qcom,msm-id = <0x192 0x0>, <0x193 0x0>; aliases { serial0 = &blsp1_uart3; serial1 = &blsp1_uart5; sdhc1 = &sdhc_1; /* * Aliases as required by u-boot * to patch MAC addresses */ ethernet0 = "/soc/dp1"; ethernet1 = "/soc/dp2"; }; chosen { bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; #ifdef __IPQ_MEM_PROFILE_256_MB__ bootargs-append = " swiotlb=1"; #else bootargs-append = " swiotlb=1 coherent_pool=2M"; #endif }; /* * +=========+==============+========================+ * | | | | * | Region | Start Offset | Size | * | | | | * +--------+--------------+-------------------------+ * | | | | * | | | | * | | | | * | | | | * | Linux | 0x41000000 | 119MB | * | | | | * | | | | * | | | | * +--------+--------------+-------------------------+ * | | | | * | LPASS | | | * | Q6 | 0x48700000 | 26MB | * | | | | * +--------+--------------+-------------------------+ * * From the available 145 MB for Linux in the first 256 MB, * we are reserving 26 MB for LPASS. * * Refer arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi * for memory layout. */ #if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__) reserved-memory { lpass_q6_region: lpass@48700000 { no-map; reg = <0x0 0x48700000 0x0 0x01a00000>; }; }; #endif }; &tlmm { uart_pins: uart_pins { mux { pins = "gpio44", "gpio45"; function = "blsp2_uart"; drive-strength = <8>; bias-pull-up; }; }; spi_0_pins: spi_0_pins { mux { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "blsp0_spi"; drive-strength = <8>; bias-pull-down; }; }; spi_1_pins: spi_1_pins { mux { pins = "gpio69", "gpio71", "gpio72"; function = "blsp1_spi"; drive-strength = <8>; bias-disable; }; spi_cs { pins = "gpio70"; function = "blsp1_spi"; drive-strength = <8>; bias-disable; }; quartz_interrupt { pins = "gpio73"; function = "gpio"; input; bias-disable; }; quartz_reset { pins = "gpio74"; function = "gpio"; output-low; bias-disable; }; }; qpic_pins: qpic_pins { data_0 { pins = "gpio15"; function = "qpic_pad0"; drive-strength = <8>; bias-pull-down; }; data_1 { pins = "gpio12"; function = "qpic_pad1"; drive-strength = <8>; bias-pull-down; }; data_2 { pins = "gpio13"; function = "qpic_pad2"; drive-strength = <8>; bias-pull-down; }; data_3 { pins = "gpio14"; function = "qpic_pad3"; drive-strength = <8>; bias-pull-down; }; data_4 { pins = "gpio5"; function = "qpic_pad4"; drive-strength = <8>; bias-pull-down; }; data_5 { pins = "gpio6"; function = "qpic_pad5"; drive-strength = <8>; bias-pull-down; }; data_6 { pins = "gpio7"; function = "qpic_pad6"; drive-strength = <8>; bias-pull-down; }; data_7 { pins = "gpio8"; function = "qpic_pad7"; drive-strength = <8>; bias-pull-down; }; qpic_pad { pins = "gpio1", "gpio3", "gpio4", "gpio10", "gpio11", "gpio17"; function = "qpic_pad"; drive-strength = <8>; bias-pull-down; }; }; button_pins: button_pins { wps_button { pins = "gpio9"; function = "gpio"; drive-strength = <8>; bias-pull-down; }; }; mdio_pins: mdio_pinmux { mux_0 { pins = "gpio64"; function = "mdc"; drive-strength = <8>; bias-pull-up; }; mux_1 { pins = "gpio65"; function = "mdio"; drive-strength = <8>; bias-pull-up; }; mux_2 { pins = "gpio77"; function = "gpio"; bias-pull-up; }; }; hsuart_pins: hsuart_pins { mux { pins = "gpio55", "gpio56", "gpio57", "gpio58"; function = "blsp4_uart"; drive-strength = <8>; bias-disable; }; }; }; &soc { mdio: mdio@90000 { #address-cells = <0x1>; #size-cells = <0x0>; pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; phy-reset-gpio = <&tlmm 77 0>; status = "ok"; phy0: ethernet-phy@0 { reg = <0x10>; }; phy1: ethernet-phy@1 { reg = <0x14>; }; }; ess-switch@3a000000 { switch_cpu_bmp = <0x1>; /* cpu port bitmap */ switch_lan_bmp = <0x10>; /* lan port bitmap */ switch_wan_bmp = <0x20>; /* wan port bitmap */ switch_inner_bmp = <0xc0>; /*inner port bitmap*/ switch_mac_mode = <0xf>; /* mac mode for uniphy instance0*/ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ qcom,port_phyinfo { port@4 { port_id = <4>; phy_address = <0x10>; port_mac_sel = "QGMAC_PORT"; }; port@5 { port_id = <5>; phy_address = <0x14>; port_mac_sel = "QGMAC_PORT"; }; }; }; dp1 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <4>; reg = <0x3a001600 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <16>; phy-mode = "sgmii"; }; dp2 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <5>; reg = <0x3a001800 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; qcom,link-poll = <1>; qcom,phy-mdio-addr = <20>; phy-mode = "sgmii"; }; nss-macsec0 { compatible = "qcom,nss-macsec"; phy_addr = <0x10>; phy_access_mode = <0>; mdiobus = <&mdio>; }; nss-macsec1 { compatible = "qcom,nss-macsec"; phy_addr = <0x14>; phy_access_mode = <0>; mdiobus = <&mdio>; }; }; &blsp1_uart3 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; status = "ok"; }; &blsp1_uart5 { pinctrl-0 = <&hsuart_pins>; pinctrl-names = "default"; dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; status = "ok"; }; &spi_0 { pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; cs-select = <0>; status = "ok"; m25p80@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; compatible = "n25q128a11"; linux,modalias = "m25p80", "n25q128a11"; spi-max-frequency = <50000000>; use-default-sizes; }; }; &spi_1 { /* BLSP1 QUP1 */ pinctrl-0 = <&spi_1_pins>; pinctrl-names = "default"; cs-select = <0>; quartz-reset-gpio = <&tlmm 74 1>; status = "ok"; spidev1: spi@1 { compatible = "qca,spidev"; reg = <0>; spi-max-frequency = <24000000>; }; }; &sdhc_1 { status = "ok"; }; &qpic_bam { status = "ok"; }; &nand { pinctrl-0 = <&qpic_pins>; pinctrl-names = "default"; status = "ok"; }; &ssphy_0 { status = "ok"; }; &qusb_phy_0 { status = "ok"; }; &usb3 { status = "ok"; }; &nss_crypto { status = "ok"; }; &pcie_phy { status = "ok"; }; &pcie0 { status = "ok"; };