--- zzzz-none-000/linux-2.6.19.2/arch/arm/mach-omap2/board-h4.c 2007-01-10 19:10:37.000000000 +0000 +++ davinci-8020-5505/linux-2.6.19.2/arch/arm/mach-omap2/board-h4.c 2007-01-11 07:38:19.000000000 +0000 @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include @@ -36,11 +38,15 @@ #include #include #include +#include #include "prcm-regs.h" #include #include +#define H4_FLASH_CS 0 +#define H4_SMC91X_CS 1 + static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; @@ -117,8 +123,6 @@ }; static struct resource h4_flash_resource = { - .start = H4_CS0_BASE, - .end = H4_CS0_BASE + SZ_64M - 1, .flags = IORESOURCE_MEM, }; @@ -134,8 +138,6 @@ static struct resource h4_smc91x_resources[] = { [0] = { - .start = OMAP24XX_ETHR_START, /* Physical */ - .end = OMAP24XX_ETHR_START + 0xf, .flags = IORESOURCE_MEM, }, [1] = { @@ -154,6 +156,7 @@ /* Select between the IrDA and aGPS module */ +#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE) static int h4_select_irda(struct device *dev, int state) { unsigned char expa; @@ -210,6 +213,10 @@ return 0; } +#else +static int h4_select_irda(struct device *dev, int state) { return 0; } +static int h4_transceiver_mode(struct device *dev, int mode) { return 0; } +#endif static struct omap_irda_config h4_irda_data = { .transceiver_cap = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE, @@ -272,25 +279,104 @@ &h4_lcd_device, }; +/* 2420 Sysboot setup (2430 is different) */ +static u32 get_sysboot_value(void) +{ + return (omap_readl(OMAP242X_CONTROL_STATUS) & 0xFFF); +} + +/* FIXME: This function should be moved to some other file, gpmc.c? */ + +/* H4-2420's always used muxed mode, H4-2422's always use non-muxed + * + * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423 + * correctly. The macro needs to look at production_id not just hawkeye. + */ +static u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & 0xF) == 0xd) + return 1; /* NAND config (could be either) */ + if (mux & 0x2) /* if mux'ed */ + return 1; + else + return 0; +} + static inline void __init h4_init_smc91x(void) { + int eth_cs; + unsigned long cs_mem_base; + unsigned int muxed, rate; + struct clk *l3ck; + + eth_cs = H4_SMC91X_CS; + + l3ck = clk_get(NULL, "core_l3_ck"); + if (IS_ERR(l3ck)) + rate = 100000000; + else + rate = clk_get_rate(l3ck); + + if (is_gpmc_muxed()) + muxed = 0x200; + else + muxed = 0; + /* Make sure CS1 timings are correct */ - GPMC_CONFIG1_1 = 0x00011200; - GPMC_CONFIG2_1 = 0x001f1f01; - GPMC_CONFIG3_1 = 0x00080803; - GPMC_CONFIG4_1 = 0x1c091c09; - GPMC_CONFIG5_1 = 0x041f1f1f; - GPMC_CONFIG6_1 = 0x000004c4; - GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, + 0x00011000 | muxed); + + if (rate >= 160000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else if (rate >= 130000000) { + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); + } else {/* rate = 100000000 */ + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); + gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); + } + + if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { + printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); + return; + } + h4_smc91x_resources[0].start = cs_mem_base + 0x300; + h4_smc91x_resources[0].end = cs_mem_base + 0x30f; udelay(100); omap_cfg_reg(M15_24XX_GPIO92); if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", OMAP24XX_ETHR_GPIO_IRQ); + gpmc_cs_free(eth_cs); return; } omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); + +} + +static void __init h4_init_flash(void) +{ + unsigned long base; + + if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) { + printk("Can't request GPMC CS for flash\n"); + return; + } + h4_flash_resource.start = base; + h4_flash_resource.end = base + SZ_64M - 1; } static void __init omap_h4_init_irq(void) @@ -299,6 +385,7 @@ omap_init_irq(); omap_gpio_init(); h4_init_smc91x(); + h4_init_flash(); } static struct omap_uart_config h4_uart_config __initdata = { @@ -325,6 +412,72 @@ { OMAP_TAG_LCD, &h4_lcd_config }, }; +#ifdef CONFIG_MACH_OMAP_H4_TUSB + +#include + +static struct musb_hdrc_platform_data tusb_data = { + .mode = MUSB_OTG, + .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */ + + /* 1.8V supplied by Menelaus, other voltages supplied by VBAT; + * so no switching. + */ +}; + +static void __init tusb_evm_setup(void) +{ + static char announce[] __initdata = + KERN_INFO "TUSB 6010 EVM\n"; + int irq; + unsigned dmachan = 0; + + /* There are at least 32 different combinations of boards that + * are loosely called "H4", with a 2420 ... different OMAP chip + * revisions (with pin mux changes for DMAREQ, GPMC errata, etc), + * modifications of the CPU board, mainboard, EVM, TUSB etc. + * Plus omap2422, omap2423, etc. + * + * So you might need to tweak this setup to make the TUSB EVM + * behave on your particular setup ... + */ + + /* Already set up: GPMC AD[0..15], CLK, nOE, nWE, nADV_ALE */ + omap_cfg_reg(E2_GPMC_NCS2); + omap_cfg_reg(L2_GPMC_NCS7); + omap_cfg_reg(M1_GPMC_WAIT2); + + switch ((system_rev >> 8) & 0x0f) { + case 0: /* ES 1.0 */ + case 1: /* ES 2.0 */ + /* Assume early board revision without optional ES2.0 + * rework to swap J15 & AA10 so DMAREQ0 works + */ + omap_cfg_reg(AA10_242X_GPIO13); + irq = 13; + // omap_cfg_reg(J15_24XX_DMAREQ0); + break; + default: + /* Later Menelaus boards can support all 6 DMA request + * lines, at the price of boot flash A23-A26. + */ + omap_cfg_reg(J15_24XX_GPIO99); + irq = 99; + omap_cfg_reg(AA10_242X_DMAREQ0); + omap_cfg_reg(AA6_242X_DMAREQ1); + dmachan = (1 << 1) | (1 << 0); + break; + } + + if (tusb6010_setup_interface(&tusb_data, + TUSB6010_REFCLK_24, /* waitpin */ 2, + /* async cs */ 2, /* sync cs */ 7, + irq, dmachan) == 0) + printk(announce); +} + +#endif + static void __init omap_h4_init(void) { /* @@ -349,6 +502,11 @@ omap_board_config = h4_config; omap_board_config_size = ARRAY_SIZE(h4_config); omap_serial_init(); + +#ifdef CONFIG_MACH_OMAP_H4_TUSB + tusb_evm_setup(); +#endif + } static void __init omap_h4_map_io(void)