--- zzzz-none-000/linux-2.6.19.2/arch/mips/kernel/traps.c	2007-01-10 19:10:37.000000000 +0000
+++ davinci-8020-5505/linux-2.6.19.2/arch/mips/kernel/traps.c	2008-02-25 14:14:47.000000000 +0000
@@ -112,12 +112,12 @@
 		show_raw_backtrace(sp);
 		return;
 	}
-	printk("Call Trace:\n");
+	__printk(KERN_ERR "Call Trace:\n");
 	do {
 		print_ip_sym(pc);
 		pc = unwind_stack(task, &sp, pc, &ra);
 	} while (pc);
-	printk("\n");
+	__printk(KERN_ERR "\n");
 }
 
 /*
@@ -1081,12 +1081,17 @@
 {
 	unsigned long handler = (unsigned long) addr;
 	unsigned long old_handler = exception_handlers[n];
+    extern char except_vec4_lui, except_vec4_ori, except_vec4;      /* genex.S */
 
 	exception_handlers[n] = handler;
 	if (n == 0 && cpu_has_divec) {
-		*(volatile u32 *)(ebase + 0x200) = 0x08000000 |
-		                                 (0x03ffffff & (handler >> 2));
-		flush_icache_range(ebase + 0x200, ebase + 0x204);
+		*(volatile u32 *)(&except_vec4_lui - &except_vec4 + ebase + 0x200) = 
+            (*(volatile u32 *)(&except_vec4_lui - &except_vec4 + ebase + 0x200) & 0xffff0000) |
+            ((handler >> 16) & 0xffff);
+		*(volatile u32 *)(&except_vec4_ori - &except_vec4 + ebase + 0x200) = 
+            (*(volatile u32 *)(&except_vec4_ori - &except_vec4 + ebase + 0x200) & 0xffff0000) |
+            (handler & 0xffff);
+		flush_icache_range(ebase + 0x200, ebase + 0x210);
 	}
 	return (void *)old_handler;
 }
@@ -1111,7 +1116,7 @@
 static void mips_srs_init(void)
 {
 	shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
-	printk(KERN_INFO "%ld MIPSR2 register sets available\n",
+	printk(KERN_INFO "%d MIPSR2 register sets available\n",
 	       shadow_registers.sr_supported);
 	shadow_registers.sr_allocated = 1;	/* Set 0 used by kernel */
 }
@@ -1473,7 +1478,7 @@
 			set_vi_handler(i, NULL);
 	}
 	else if (cpu_has_divec)
-		set_handler(0x200, &except_vec4, 0x8);
+		set_handler(0x200, &except_vec4, 0x10);
 
 	/*
 	 * Some CPUs can enable/disable for cache parity detection, but does