/dts-v1/;
/*
 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
#include "qcom-ipq807x-soc.dtsi"
#include "qcom-ipq807x-spmi-regulator.dtsi"

#include "qcom-ipq807x-coresight.dtsi"
/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ807x-HK01";
	compatible = "qcom,ipq807x-hk01", "qcom,ipq807x";
	qcom,msm-id = <0x125 0x0>;
	interrupt-parent = <&intc>;
	qcom,board-id = <0x10 0x0>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD slot */
	};

	chosen {
		bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw init=/init";
		bootargs-append = " clk_ignore_unused";
	};
};

	&CPU0 {
		operating-points-v2 = <&cpu0_opp_table>;
		voltage-tolerance = <1>;
		cpu0-supply = <&s3>;
	};

	&CPU1 {
		operating-points-v2 = <&cpu0_opp_table>;
		voltage-tolerance = <1>;
		cpu-supply = <&s3>;
	};

	&CPU2 {
		operating-points-v2 = <&cpu0_opp_table>;
		voltage-tolerance = <1>;
		cpu-supply = <&s3>;
	};

	&CPU3 {
		operating-points-v2 = <&cpu0_opp_table>;
		voltage-tolerance = <1>;
		cpu-supply = <&s3>;
	};

	&cpus {
		cpu0_opp_table: opp_table0 {
			compatible = "operating-points-v2";
			opp-shared;

			opp00 {
				opp-hz = /bits/ 64 <1036800000>;
				opp-microvolt = <670000>;
				clock-latency-ns = <200000>;
			};
			opp01 {
				opp-hz = /bits/ 64 <1689600000>;
				opp-microvolt = <735000>;
				clock-latency-ns = <200000>;
			};
			opp02 {
				opp-hz = /bits/ 64 <1843200000>;
				opp-microvolt = <800000>;
				clock-latency-ns = <200000>;
			};
			opp03 {
				opp-hz = /bits/ 64 <1958400000>;
				opp-microvolt = <850000>;
				clock-latency-ns = <200000>;
			};
			opp04 {
				opp-hz = /bits/ 64 <2016000000>;
				opp-microvolt = <905000>;
				clock-latency-ns = <200000>;
			};
			opp05 {
				opp-hz = /bits/ 64 <2208000000>;
				opp-microvolt = <990000>;
				clock-latency-ns = <200000>;
			};
		};
	};


&soc {
	dp1 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <1>;
		reg = <0x3a001000 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
	};

	dp2 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <2>;
		reg = <0x3a001200 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
	};

	dp3 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <3>;
		reg = <0x3a001400 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
	};

	dp4 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <4>;
		reg = <0x3a001600 0x200>;
		qcom,mactype = <0>;
		local-mac-address = [000000000000];
	};

	dp5 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <5>;
		reg = <0x3a003000 0x3fff>;
		qcom,mactype = <1>;
		local-mac-address = [000000000000];
	};

	dp6 {
		device_type = "network";
		compatible = "qcom,nss-dp";
		qcom,id = <6>;
		reg = <0x3a007000 0x3fff>;
		qcom,mactype = <1>;
		local-mac-address = [000000000000];
	};

	serial_blsp2: serial@78B1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78B1000 0x200>;
			interrupts = <0x0 306 0x0>;
			clocks = <&gcc GCC_DUMMY_CLK>,
				 <&gcc GCC_DUMMY_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 4>,
				 <&blsp_dma 5>;
			dma-names = "tx", "rx";

			pinctrl-0 = <&hsuart_pins>;
			pinctrl-names = "default";
			status = "disabled";
	};

	spi_2: spi@78b8000 { /* BLSP1 QUP3 */
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x78b8000 0x600>;
			interrupts = <0 98 0>;
			spi-max-frequency = <24000000>;
			clocks = <&gcc GCC_DUMMY_CLK>,
				<&gcc GCC_DUMMY_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 18>, <&blsp_dma 19>;
			dma-names = "tx", "rx";
			pinctrl-0 = <&spi_2_pins>;
			pinctrl-names = "default";
			status = "disabled";
	};

	edma@3ab00000 {
		compatible = "qcom,edma";
		reg = <0x3ab00000 0x76900>;
		reg-names = "edma-reg-base";
		qcom,txdesc-ring-start = <23>;
		qcom,txdesc-rings = <1>;
		qcom,txcmpl-ring-start = <7>;
		qcom,txcmpl-rings = <1>;
		qcom,rxfill-ring-start = <7>;
		qcom,rxfill-rings = <1>;
		qcom,rxdesc-ring-start = <15>;
		qcom,rxdesc-rings = <1>;
		interrupts = <0 345 4>,
			   <0 353 4>,
			   <0 361 4>,
			   <0 344 4>;
	};

	mdio@90000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "qcom,ipq40xx-mdio";
		reg = <0x90000 0x64>;
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
		phy1: ethernet-phy@1 {
			reg = <1>;
		};
		phy2: ethernet-phy@2 {
			reg = <2>;
		};
		phy3: ethernet-phy@3 {
			reg = <3>;
		};
		phy4: ethernet-phy@4 {
			reg = <4>;
		};
		phy5: ethernet-phy@5 {
			compatible ="ethernet-phy-ieee802.3-c45";
			reg = <7>;
		};
	};

	ess-switch@3a000000 {
		compatible = "qcom,ess-switch";
		reg = <0x3a000000 0x1000000>;
		switch_access_mode = "local bus";
		switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
		switch_lan_bmp = <0x3e>; /* lan port bitmap */
		switch_wan_bmp = <0x40>; /* wan port bitmap */
		switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
		switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
		switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
		bm_tick_mode = <0>; /* bm tick mode */
		tm_tick_mode = <0>; /* tm tick mode */
		port_scheduler_resource {
			port@0 {
				port_id = <0>;
				ucast_queue = <0 143>;
				mcast_queue = <256 271>;
				l0sp = <0 35>;
				l0cdrr = <0 47>;
				l0edrr = <0 47>;
				l1cdrr = <0 7>;
				l1edrr = <0 7>;
			};
			port@1 {
				port_id = <1>;
				ucast_queue = <144 159>;
				mcast_queue = <272 275>;
				l0sp = <36 39>;
				l0cdrr = <48 63>;
				l0edrr = <48 63>;
				l1cdrr = <8 11>;
				l1edrr = <8 11>;
			};
			port@2 {
				port_id = <2>;
				ucast_queue = <160 175>;
				mcast_queue = <276 279>;
				l0sp = <40 43>;
				l0cdrr = <64 79>;
				l0edrr = <64 79>;
				l1cdrr = <12 15>;
				l1edrr = <12 15>;
			};
			port@3 {
				port_id = <3>;
				ucast_queue = <176 191>;
				mcast_queue = <280 283>;
				l0sp = <44 47>;
				l0cdrr = <80 95>;
				l0edrr = <80 95>;
				l1cdrr = <16 19>;
				l1edrr = <16 19>;
			};
			port@4 {
				port_id = <4>;
				ucast_queue = <192 207>;
				mcast_queue = <284 287>;
				l0sp = <48 51>;
				l0cdrr = <96 111>;
				l0edrr = <96 111>;
				l1cdrr = <20 23>;
				l1edrr = <20 23>;
			};
			port@5 {
				port_id = <5>;
				ucast_queue = <208 223>;
				mcast_queue = <288 291>;
				l0sp = <52 55>;
				l0cdrr = <112 127>;
				l0edrr = <112 127>;
				l1cdrr = <24 27>;
				l1edrr = <24 27>;
			};
			port@6 {
				port_id = <6>;
				ucast_queue = <224 239>;
				mcast_queue = <292 295>;
				l0sp = <56 59>;
				l0cdrr = <128 143>;
				l0edrr = <128 143>;
				l1cdrr = <28 31>;
				l1edrr = <28 31>;
			};
			port@7 {
				port_id = <7>;
				ucast_queue = <240 255>;
				mcast_queue = <296 299>;
				l0sp = <60 63>;
				l0cdrr = <144 159>;
				l0edrr = <144 159>;
				l1cdrr = <32 35>;
				l1edrr = <32 35>;
			};
		};
		port_scheduler_config {
			port@0 {
				port_id = <0>;
				l1scheduler {
					group@0 {
						sp = <0 1>; /*L0 SPs*/
						/*cpri cdrr epri edrr*/
						cfg = <0 0 0 0>;
					};
				};
				l0scheduler {
					group@0 {
						/*unicast queues*/
						ucast_queue = <0 4 8>;
						/*multicast queues*/
						mcast_queue = <256 260>;
						/*sp cpri cdrr epri edrr*/
						cfg = <0 0 0 0 0>;
					};
					group@1 {
						ucast_queue = <1 5 9>;
						mcast_queue = <257 261>;
						cfg = <0 1 1 1 1>;
					};
					group@2 {
						ucast_queue = <2 6 10>;
						mcast_queue = <258 262>;
						cfg = <0 2 2 2 2>;
					};
					group@3 {
						ucast_queue = <3 7 11>;
						mcast_queue = <259 263>;
						cfg = <0 3 3 3 3>;
					};
				};
			};
			port@1 {
				port_id = <1>;
				l1scheduler {
					group@0 {
						sp = <36>;
						cfg = <0 8 0 8>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <144>;
						mcast_queue = <272>;
						cfg = <36 0 48 0 48>;
					};
				};
			};
			port@2 {
				port_id = <2>;
				l1scheduler {
					group@0 {
						sp = <40>;
						cfg = <0 12 0 12>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <160>;
						mcast_queue = <276>;
						cfg = <40 0 64 0 64>;
					};
				};
			};
			port@3 {
				port_id = <3>;
				l1scheduler {
					group@0 {
						sp = <44>;
						cfg = <0 16 0 16>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <176>;
						mcast_queue = <280>;
						cfg = <44 0 80 0 80>;
					};
				};
			};
			port@4 {
				port_id = <4>;
				l1scheduler {
					group@0 {
						sp = <48>;
						cfg = <0 20 0 20>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <192>;
						mcast_queue = <284>;
						cfg = <48 0 96 0 96>;
					};
				};
			};
			port@5 {
				port_id = <5>;
				l1scheduler {
					group@0 {
						sp = <52>;
						cfg = <0 24 0 24>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <208>;
						mcast_queue = <288>;
						cfg = <52 0 112 0 112>;
					};
				};
			};
			port@6 {
				port_id = <6>;
				l1scheduler {
					group@0 {
						sp = <56>;
						cfg = <0 28 0 28>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <224>;
						mcast_queue = <292>;
						cfg = <56 0 128 0 128>;
					};
				};
			};
			port@7 {
				port_id = <7>;
				l1scheduler {
					group@0 {
						sp = <60>;
						cfg = <0 32 0 32>;
					};
				};
				l0scheduler {
					group@0 {
						ucast_queue = <240>;
						mcast_queue = <296>;
						cfg = <60 0 144 0 144>;
					};
				};
			};
		};
	};

	ess-uniphy@7a00000 {
		compatible = "qcom,ess-uniphy";
		reg = <0x7a00000 0x30000>;
		uniphy_access_mode = "local bus";
	};

	nss-common {
		compatible = "qcom,nss-common";
		reg = <0x01d00000 0x1000>;
		reg-names = "nss_fpb_base";
		clocks = <&gcc GCC_DUMMY_CLK>, <&gcc GCC_DUMMY_CLK>;
		clock-names = "nss-core-clk", "nss-tcm-clk";
	};

	nss0: nss@40000000 {
		compatible = "qcom,nss";
		interrupts = <0 377 0x1>, <0 378 0x1>, <0 379 0x1>, <0 380 0x1>,
			     <0 381 0x1>, <0 382 0x1>, <0 383 0x1>;
		reg = <0x39000000 0x1000>, <0x38000000 0x30000>,
		      <0x0b111000 0x1000>;
		reg-names = "nphys", "vphys", "qgic-phys";
		clocks = <&gcc GCC_DUMMY_CLK>, <&gcc GCC_DUMMY_CLK>,
			 <&gcc GCC_DUMMY_CLK>;
		clock-names = "nss-core-clk", "nss-tcm-src",
			      "nss-tcm-clk";
		resets = <&gcc GCC_DUMMY_CLK>,
			 <&gcc GCC_DUMMY_CLK>,
			 <&gcc GCC_DUMMY_CLK>,
			 <&gcc GCC_DUMMY_CLK>;
		reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
		qcom,id = <0>;
		qcom,num-queue = <4>;
		qcom,num-irq = <7>;
		qcom,load-addr = <0x40000000>;
		qcom,low-frequency = <748800000>;
		qcom,mid-frequency = <1497600000>;
		qcom,max-frequency = <1689600000>;
		qcom,bridge-enabled;
		qcom,ipv4-enabled;
		qcom,ipv6-enabled;
		qcom,wlanredirect-enabled;
		qcom,tun6rd-enabled;
		qcom,l2tpv2-enabled;
		qcom,gre-enabled;
		qcom,map-t-enabled;
		qcom,portid-enabled;
		qcom,ppe-enabled;
		qcom,pppoe-enabled;
		qcom,pptp-enabled;
		qcom,tunipip6-enabled;
		qcom,shaping-enabled;
		qcom,wlan-dataplane-offload-enabled;
		qcom,vlan-enabled;
	};

	nss1: nss@40800000 {
		compatible = "qcom,nss";
		interrupts = <0 390 0x1>, <0 391 0x1>, <0 392 0x1>, <0 393 0x1>,
				<0 394 0x1>, <0 395 0x1>, <0 396 0x1>;
		reg = <0x39400000 0x1000>, <0x38030000 0x30000>,
			<0x0b111000 0x1000>;
		reg-names = "nphys", "vphys", "qgic-phys";
		clocks = <&gcc GCC_DUMMY_CLK>, <&gcc GCC_DUMMY_CLK>,
			<&gcc GCC_DUMMY_CLK>;
		clock-names = "nss-core-clk", "nss-tcm-src",
				"nss-tcm-clk";
		resets = <&gcc GCC_DUMMY_CLK>,
			<&gcc GCC_DUMMY_CLK>,
			<&gcc GCC_DUMMY_CLK>,
			<&gcc GCC_DUMMY_CLK>;
		reset-names = "clkrst-clamp", "clamp", "ahb", "axi";
		qcom,id = <1>;
		qcom,num-queue = <4>;
		qcom,num-irq = <7>;
		qcom,load-addr = <0x40800000>;
		qcom,capwap-enabled;
		qcom,dtls-enabled;
		qcom,crypto-enabled;
		qcom,ipsec-enabled;
	};

	audio: audio@7700000 {
		status = "ok";
	};

	mbox0: mbox@7708000 {
		status = "ok";
	};

	mbox3: mbox@770e000 {
		status = "ok";
	};

	stereo0: stereo@7709000 {
		status = "ok";
	};

	stereo3: stereo@770f000 {
		status = "ok";
	};

	/* Enable Audio Interfaces */
	i2s: ipq8074-pcm-i2s@0 {
		status = "ok";
	};

	i2splatform: qca-pcm-i2s@7709000 {
		status = "ok";
	};

	tdmplatform: qca-pcm-tdm@7709000 {
		status = "ok";
	};

	tdm: tdm@0 {
		status = "ok";
	};

	sound: sound@0 {
		pinctrl-0 = <&audio_gpio_pins>;
		pinctrl-1 = <&audio_pins>;
		pinctrl-names = "default", "audio";
		status = "ok";
	};

	/* Enable VOIP Interfaces */
	pcm: pcm@7704000 {
		status = "ok";
	};

	pcm_lb: pcm_lb@0 {
		status = "ok";
		pinctrl-0 = <&voip_pins>;
		pinctrl-names = "default";
	};
};

&tlmm {
	hsuart_pins: hsuart_pins {
		mux {
			pins = "gpio46", "gpio47", "gpio48", "gpio49";
			function = "blsp2_uart";
			bias-disable;
		};
	};

	uart_pins: uart_pins {
		mux {
			pins = "gpio23", "gpio24";
			function = "blsp4_uart1";
			bias-disable;
		};
	};

	spi_2_pins: spi_2_pinmux {
				mux {
					pins = "gpio50", "gpio51", "gpio52", "gpio52";
					function = "blsp3_spi";
					bias-disable;
				};
	};

	i2c_0_pins: i2c_0_pinmux {
				mux {
					pins = "gpio42", "gpio43";
					function = "blsp1_i2c";
					bias-disable;
				};
	};

	audio_gpio_pins: audio_gpio_pinmux {
		mux_1 {
			pins = "gpio25";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_2 {
			pins = "gpio26";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_3 {
			pins = "gpio27";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_4 {
			pins = "gpio28";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_5 {
			pins = "gpio29";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_6 {
			pins = "gpio30";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_7 {
			pins = "gpio31";
			function = "gpio";
			bias-pull,up;
			output-high;
		};

		mux_8 {
			pins = "gpio32";
			function = "gpio";
			bias-pull,up;
			output-high;
		};
	};

	audio_pins: audio_pinmux {
		mux_1 {
			pins = "gpio25";
			function = "audio_txmclk";
			bias-pull,up;
		};

		mux_2 {
			pins = "gpio26";
			function = "audio_txbclk";
			bias-pull,up;
		};

		mux_3 {
			pins = "gpio27";
			function = "audio_txfsync";
			bias-pull,up;
		};

		mux_4 {
			pins = "gpio28";
			function = "audio_txd";
			bias-pull,up;
		};

		mux_5 {
			pins = "gpio29";
			function = "audio_rxmclk";
			bias-pull,up;
		};

		mux_6 {
			pins = "gpio30";
			function = "audio_rxbclk";
			bias-pull,up;
		};

		mux_7 {
			pins = "gpio31";
			function = "audio_rxfsync";
			bias-pull,up;
		};

		mux_8 {
			pins = "gpio32";
			function = "audio_rxd";
			bias-pull,up;
		};
	};

	voip_pins: voip_pinmux {
		mux_1 {
			pins = "gpio33";
			function = "pcm_drx";
			bias-pull,up;
		};

		mux_2 {
			pins = "gpio34";
			function = "pcm_dtx";
			bias-pull,up;
		};

		mux_3 {
			pins = "gpio35";
			function = "pcm_fsync";
			bias-pull,up;
		};

		mux_4 {
			pins = "gpio36";
			function = "pcm_pclk";
			bias-pull,up;
		};
	};

	spi_0_pins: spi_0_pins {
		mux {
			pins = "gpio38", "gpio39", "gpio40", "gpio41";
			function = "blsp0_spi";
			bias-disable;
		};
	};
};

&q6v5_wcss {
	qca,emulation = <1>;
};

&serial_blsp4 {
	pinctrl-0 = <&uart_pins>;
	pinctrl-names = "default";
	status = "disabled";
};

&serial_blsp0 {
	status = "ok";
};

&spi_0 { /* BLSP1 QUP1 */
	#pinctrl-0 = <&spi_0_pins>;
	#pinctrl-names = "default";
	status = "ok";

	m25p80@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		compatible = "n25q128a11";
		linux,modalias = "m25p80", "n25q128a11";
		spi-max-frequency = <24000000>;
		use-default-sizes;
	};
};

&i2c_0 {
	pinctrl-0 = <&i2c_0_pins>;
	pinctrl-names = "default";
	status = "disabled";
};

&qpic_bam {
	clocks = <&gcc GCC_DUMMY_CLK>;
	clock-names = "bam_clk";
	status = "ok";
};

&nand {
	clocks = <&gcc GCC_DUMMY_CLK>,
		<&gcc GCC_DUMMY_CLK>;
	clock-names = "core", "aon";
	status = "ok";
};

&qpic_lcd {
	clocks = <&gcc GCC_DUMMY_CLK>,
		<&gcc GCC_DUMMY_CLK>;
	clock-names = "core", "aon";
	status = "ok";
};

&qpic_lcd_panel {
	status = "ok";
};

&ssphy_0 {
	qcom,emulation = <1>;
	status = "ok";
};

&qusb_phy_0 {
	qcom,emulation = <1>;
	status = "ok";
};

&ssphy_1 {
	qcom,emulation = <1>;
	status = "ok";
};

&qusb_phy_1 {
	qcom,emulation = <1>;
	status = "ok";
};

&dwc_0 {
	dr_mode = "peripheral";
};

&usb3_0 {
	status = "ok";
};

&usb3_1 {
	status = "ok";
};

&sdhc_1 {
	qcom,clk-rates = <400000 25000000 50000000 100000000 \
			 192000000 384000000>;
	qcom,bus-speed-mode = "DDR_1p8v";
	qcom,nonremovable;
	qcom,emulation = <1>;
	status = "ok";
};

&sdhc_2 {
	qcom,clk-rates = <400000 25000000 50000000 100000000 \
			 192000000 384000000>;
	qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
	qcom,emulation = <1>;
	status = "disabled";
};