--- zzzz-none-000/linux-4.9.231/include/linux/irqchip/mips-gic.h	2020-07-22 07:10:54.000000000 +0000
+++ falcon-5530-730/linux-4.9.231/include/linux/irqchip/mips-gic.h	2022-08-31 08:19:49.000000000 +0000
@@ -26,6 +26,9 @@
 /* Accessors */
 #define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
 
+#define GIC_REG_ADDR(segment, offset) \
+	(segment##_##SECTION_OFS + offset)
+
 /* GIC Address Space */
 #define SHARED_SECTION_OFS		0x0000
 #define SHARED_SECTION_SIZE		0x8000
@@ -270,6 +273,18 @@
 extern int gic_get_c0_perfcount_int(void);
 extern int gic_get_c0_fdc_int(void);
 extern int gic_get_usm_range(struct resource *gic_usm_res);
+extern unsigned long gic_read_reg(unsigned int reg);
+extern void gic_write_reg(unsigned int reg, unsigned long val);
+extern int gic_yield_setup(unsigned int cpu,
+			   unsigned int pin, unsigned int irq);
+extern int gic_clear_edge(unsigned int irq);
+
+#define GIC_VPE_WD_START    BIT(0)
+#define GIC_VPE_WD_TYPE_SCD BIT(1)
+#define GIC_VPE_WD_NWAIT    BIT(5)
+#define GIC_VPE_WD_WDINTR   BIT(6)
+#define GIC_VPE_WD_WDRESET  BIT(7)
+extern void gic_wd_setup_on(int cpu, u32 config, u32 initcnt);
 
 #else /* CONFIG_MIPS_GIC */
 
@@ -295,4 +310,6 @@
  */
 extern unsigned gic_read_local_vp_id(void);
 
+extern void gic_send_ipi_simple(unsigned int hwirq, unsigned int cpu);
+
 #endif /* __LINUX_IRQCHIP_MIPS_GIC_H */