// SPDX-License-Identifier: GPL-2.0

#ifndef __LTQ_MIPS_CM_H__
#define __LTQ_MIPS_CM_H__

/*
 * GCR custom address range is connected via a 64 bit bus, which seems to use
 * little endian. Endian swapping happens somewhere for 32 bits; hence we don't
 * need to endian swap inside dwords, but still need to address the other
 * dword if we run in big endian mode.
 */
#if IS_ENABLED(CONFIG_SYS_SUPPORTS_BIG_ENDIAN)
# define LTQ_GCR_CUSTOM_ADDR_FIXUP(addr)	((addr) ^ 4)
#else
# define LTQ_GCR_CUSTOM_ADDR_FIXUP(addr)	(addr)
#endif

#define BUILD_CM_CUSTOM_R_(name, off)					\
static inline unsigned long __iomem *addr_gcr_custom_##name(void)	\
{									\
	return (unsigned long __iomem *)(mips_cm_custom_base		\
			+ LTQ_GCR_CUSTOM_ADDR_FIXUP(off));		\
}									\
									\
static inline unsigned long read_gcr_custom_##name(void)		\
{									\
	return __raw_readl(addr_gcr_custom_##name());			\
}

#define BUILD_CM_CUSTOM__W(name, off)					\
static inline void write_gcr_custom_##name(unsigned long value)		\
{									\
	__raw_writel(value, addr_gcr_custom_##name());			\
}

#define BUILD_CM_CUSTOM_RW(name, off)					\
	BUILD_CM_CUSTOM_R_(name, off)					\
	BUILD_CM_CUSTOM__W(name, off)

#define BUILD_CM_CUSTOM_R__VEC(name, off)				\
static inline unsigned long __iomem *addr_gcr_custom_##name(int index)	\
{									\
	return (unsigned long __iomem *)(mips_cm_custom_base		\
			+ LTQ_GCR_CUSTOM_ADDR_FIXUP((off)		\
						    + 4 * index));	\
}									\
									\
static inline unsigned long read_gcr_custom_##name(int index)		\
{									\
	return __raw_readl(addr_gcr_custom_##name(index));		\
}

#define BUILD_CM_CUSTOM__W_VEC(name, off)				\
static inline void write_gcr_custom_##name(int index,			\
		   unsigned long value)					\
{									\
	__raw_writel(value, addr_gcr_custom_##name(index));		\
}

#define BUILD_CM_CUSTOM_RW(name, off)					\
	BUILD_CM_CUSTOM_R_(name, off)					\
	BUILD_CM_CUSTOM__W(name, off)

#define BUILD_CM_CUSTOM_RW_VEC(name, off)					\
	BUILD_CM_CUSTOM_R__VEC(name, off)					\
	BUILD_CM_CUSTOM__W_VEC(name, off)

BUILD_CM_CUSTOM_RW_VEC(CPU_MCONNID_MAP,	0x0)
BUILD_CM_CUSTOM_RW(CCA_OV,		0x10)
BUILD_CM_CUSTOM_RW(CCA_IC_MADDR0,	0x14)
BUILD_CM_CUSTOM_RW_VEC(CCA_IC_MREQ,	0x18)
BUILD_CM_CUSTOM_RW(CCA_IC_MADDR1,	0x114)
BUILD_CM_CUSTOM_RW(CCA_IC_MREQ_IOCU2,	0x198)

#define CCA_WT		0 /* write through */
#define CCA_UC		2 /* uncached */
#define CCA_WB		3 /* writeback, cacheable, non-coherent */
#define CCA_CWBE	4 /* coherent writeback exclusive */
#define CCA_CWB		5 /* coherent writeback */
#define CCA_UCA		7 /* uncached accelerated */

#endif /* __LTQ_MIPS_CM_H__ */