// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 Intel Corporation.
 */

#ifndef _SSX1_SSX_H
#define _SSX1_SSX_H

/*! Base Address of SSX1 */
#define SSX1_MODULE_BASE 0x18000000u

/*! offsets for the match and the read and write permission registers */
#define SSX1_OFFSET_ADDR_MATCH 0x00
#define SSX1_OFFSET_READ_PERMISSION 0x10
#define SSX1_OFFSET_WRITE_PERMISSION 0x18
#define SSX1_OFFSET_REGISTER 0x20

#define REG0_TDDR_PM_TDDR_PM_BASE 0x84440
#define REG0_TDDR_PM_TDDR_PM_NREG 8

/*! Permission Offset (relative) */
#define REG0_TREG0_PM_TREG0_PM_READ_PERMISSION_0 0x80050
#define REG0_TREG0_PM_TREG0_PM_WRITE_PERMISSION_0 0x80058
#define REG0_TREG0_PM_TREG0_PM_READ_PERMISSION_1 0x80070
#define REG0_TREG0_PM_TREG0_PM_WRITE_PERMISSION_1 0x80078
#define REG0_TOTP_PM_TOTP_PM_READ_PERMISSION_0 0x80C50
#define REG0_TOTP_PM_TOTP_PM_WRITE_PERMISSION_0 0x80C58
#define REG0_TCBM1_PM_TCBM1_PM_READ_PERMISSION_0 0x81050
#define REG0_TCBM1_PM_TCBM1_PM_WRITE_PERMISSION_0 0x81058
#define REG0_TCBM2_PM_TCBM2_PM_READ_PERMISSION_0 0x81450
#define REG0_TCBM2_PM_TCBM2_PM_WRITE_PERMISSION_0 0x81458
#define REG0_TE123_PM_TE123_PM_READ_PERMISSION_0 0x81C50
#define REG0_TE123_PM_TE123_PM_WRITE_PERMISSION_0 0x81C58
#define REG0_TDMA3_PM_TDM3_PM_READ_PERMISSION_0 0x82050
#define REG0_TDMA3_PM_TDM3_PM_WRITE_PERMISSION_0 0x82058
#define REG0_TDMAT1_PM_TDMAT1_PM_READ_PERMISSION_0 0x82450
#define REG0_TDMAT1_PM_TDMAT1_PM_WRITE_PERMISSION_0 0x82458
#define REG0_TEX04_PM_TEX04_PM_READ_PERMISSION_0 0x84050
#define REG0_TEX04_PM_TEX04_PM_WRITE_PERMISSION_0 0x84058
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_0 0x84450
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_0 0x84458
#define REG0_TDDR_PM_TDDR_PM_ADDR_MATCH_1 0x84460
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_1 0x84470
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_1 0x84478
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_2 0x84490
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_2 0x84498
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_3 0x844B0
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_3 0x844B8
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_4 0x844D0
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_4 0x844D8
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_5 0x844F0
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_5 0x844F8
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_6 0x84510
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_6 0x84518
#define REG0_TDDR_PM_TDDR_PM_READ_PERMISSION_7 0x84530
#define REG0_TDDR_PM_TDDR_PM_WRITE_PERMISSION_7 0x84538
#define REG0_TPCTL_PM_TPCTL_PM_READ_PERMISSION_0 0x84850
#define REG0_TPCTL_PM_TPCTL_PM_WRITE_PERMISSION_0 0x84858
#define REG0_TPUB_PM_TPUB_PM_READ_PERMISSION_0 0x84C50
#define REG0_TPUB_PM_TPUB_PM_WRITE_PERMISSION_0 0x84C58
#define REG0_TPON_PM_TPON_PM_READ_PERMISSION_0 0x85050
#define REG0_TPON_PM_TPON_PM_WRITE_PERMISSION_0 0x85058
#define REG0_TGSWIP_PM_TGSWIP_PM_READ_PERMISSION_0 0x85450
#define REG0_TGSWIP_PM_TGSWIP_PM_WRITE_PERMISSION_0 0x85458
#define REG0_TQSPIC_PM_TQSPIC_PM_READ_PERMISSION_0 0x85850
#define REG0_TQSPIC_PM_TQSPIC_PM_WRITE_PERMISSION_0 0x85858
#define REG0_TMSI_PM_TMSI1_PM_READ_PERMISSION_0 0x85C50
#define REG0_TMSI_PM_TMSI1_PM_WRITE_PERMISSION_0 0x85C58
#define REG0_TDMAT2_PM_TDMAT2_PM_READ_PERMISSION_0 0x86050
#define REG0_TDMAT2_PM_TDMAT2_PM_WRITE_PERMISSION_0 0x86058
#define REG0_TQSPID_PM_TQSPID_PM_READ_PERMISSION_0 0x86450
#define REG0_TQSPID_PM_TQSPID_PM_WRITE_PERMISSION_0 0x86458
#define REG0_TDMAR1_PM_TDMAR1_PM_READ_PERMISSION_0 0x86850
#define REG0_TDMAR1_PM_TDMAR1_PM_WRITE_PERMISSION_0 0x86858
#define REG0_TDMAR2_PM_TDMAR2_PM_READ_PERMISSION_0 0x86C50
#define REG0_TDMAR2_PM_TDMAR2_PM_WRITE_PERMISSION_0 0x86C58
#define REG0_TACA_PM_TACA_PM_READ_PERMISSION_0 0x87050
#define REG0_TACA_PM_TACA_PM_WRITE_PERMISSION_0 0x87058
#define REG0_TPCIE_CR1_PM_TPCIE_CR1_PM_READ_PERMISSION_0 0x87450
#define REG0_TPCIE_CR1_PM_TPCIE_CR1_PM_WRITE_PERMISSION_0 0x87458
#define REG0_TPCI2_PM_TPCI2_PM_READ_PERMISSION_0 0x87850
#define REG0_TPCI2_PM_TPCI2_PM_WRITE_PERMISSION_0 0x87858
#define REG0_TPCI1_PM_TPCI1_PM_READ_PERMISSION_0 0x87C50
#define REG0_TPCI1_PM_TPCI1_PM_WRITE_PERMISSION_0 0x87C58
#define REG0_TMSI2_PM_TMSI2_PM_READ_PERMISSION_0 0x88050
#define REG0_TMSI2_PM_TMSI2_PM_WRITE_PERMISSION_0 0x88058
#define REG0_TPCIE_CR2_PM_TPCIE_CR2_PM_READ_PERMISSION_0 0x88850
#define REG0_TPCIE_CR2_PM_TPCIE_CR2_PM_WRITE_PERMISSION_0 0x88858
#define REG0_TLNPPV4_PM_TLNPPV4_PM_READ_PERMISSION_0 0x92050
#define REG0_TLNPPV4_PM_TLNPPV4_PM_WRITE_PERMISSION_0 0x92058
#define REG0_TXPCS_PM_TXPCS_PM_READ_PERMISSION_0 0x92450
#define REG0_TXPCS_PM_TXPCS_PM_WRITE_PERMISSION_0 0x92458
#define REG0_TPC1DBI_PM_TPCI1DBI_PM_READ_PERMISSION_0 0x92850
#define REG0_TPC1DBI_PM_TPCI1DBI_PM_WRITE_PERMISSION_0 0x92858
#define REG0_TPC2DBI_PM_TPCI2DBI_PM_READ_PERMISSION_0 0x92C50
#define REG0_TPC2DBI_PM_TPCI2DBI_PM_WRITE_PERMISSION_0 0x92C58
#define REG0_TSSB_PM_TSSB_PM_READ_PERMISSION_0 0x93050
#define REG0_TSSB_PM_TSSB_PM_WRITE_PERMISSION_0 0x93058
#define REG0_TROM_PM_TROM_PM_READ_PERMISSION_0 0x93450
#define REG0_TROM_PM_TROM_PM_WRITE_PERMISSION_0 0x93458
#define REG0_TMACS_PM_TMAC_PM_READ_PERMISSION_0 0x95050
#define REG0_TMACS_PM_TMAC_PM_WRITE_PERMISSION_0 0x95058
#define REG0_TIOCU1_PM_TIOCU1_PM_READ_PERMISSION_0 0x95450
#define REG0_TIOCU1_PM_TIOCU1_PM_WRITE_PERMISSION_0 0x95458
#define REG0_TDM4_PM_TDM4_PM_READ_PERMISSION_0 0x95850
#define REG0_TDM4_PM_TDM4_PM_WRITE_PERMISSION_0 0x95858

#endif