//----------------------------------------------------------------------------- // LSD Generator //----------------------------------------------------------------------------- // Perl Package : LSD::generator::targetC (v1.1) // LSD Source : D:/Users/shij/Perforce/l1033.grx500.win.v_shij.priv.dfv.grx500.dfv/ipg_lsd/lsd_sys/source/xml/reg_files/ssx0_ssx.xml // Register File Name : SSX0_SSX // Register File Title : SSX0_ssx // Register Width : 64 // Note : Doxygen compliant comments //----------------------------------------------------------------------------- #ifndef _SSX0_SSX_H #define _SSX0_SSX_H //! \defgroup SSX0_SSX Register File SSX0_SSX - SSX0_ssx //! @{ //! Base Address of SSX0_SSX #define SSX0_SSX_MODULE_BASE 0x1FF00000u //! \defgroup TREG0_RT_COMPONENT Register TREG0_RT_COMPONENT - component //! @{ //! Register Offset (relative) #define TREG0_RT_COMPONENT 0x0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_RT_COMPONENT 0x1FF00000u //! Register Reset Value #define TREG0_RT_COMPONENT_RST 0x0000000062003532u //! Field REV - rev #define TREG0_RT_COMPONENT_REV_POS 0 //! Field REV - rev #define TREG0_RT_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TREG0_RT_COMPONENT_CODE_POS 16 //! Field CODE - code #define TREG0_RT_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TREG0_RT_NETWORK Register TREG0_RT_NETWORK - network //! @{ //! Register Offset (relative) #define TREG0_RT_NETWORK 0x10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_RT_NETWORK 0x1FF00010u //! Register Reset Value #define TREG0_RT_NETWORK_RST 0x0000000000000000u //! Field REV - rev #define TREG0_RT_NETWORK_REV_POS 32 //! Field REV - rev #define TREG0_RT_NETWORK_REV_MASK 0xFFFF00000000u //! Field ID - id #define TREG0_RT_NETWORK_ID_POS 48 //! Field ID - id #define TREG0_RT_NETWORK_ID_MASK 0xFFFF000000000000u //! @} //! \defgroup TREG0_RT_INITID_READBACK Register TREG0_RT_INITID_READBACK - initid_readback //! @{ //! Register Offset (relative) #define TREG0_RT_INITID_READBACK 0x70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_RT_INITID_READBACK 0x1FF00070u //! Register Reset Value #define TREG0_RT_INITID_READBACK_RST 0x0000000000000000u //! Field INITID - initid #define TREG0_RT_INITID_READBACK_INITID_POS 0 //! Field INITID - initid #define TREG0_RT_INITID_READBACK_INITID_MASK 0xFFu //! @} //! \defgroup TREG0_RT_NETWORK_CONTROL Register TREG0_RT_NETWORK_CONTROL - network_control //! @{ //! Register Offset (relative) #define TREG0_RT_NETWORK_CONTROL 0x78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_RT_NETWORK_CONTROL 0x1FF00078u //! Register Reset Value #define TREG0_RT_NETWORK_CONTROL_RST 0x0000000000000000u //! Field TIMEOUT_BASE - timeout_base #define TREG0_RT_NETWORK_CONTROL_TIMEOUT_BASE_POS 8 //! Field TIMEOUT_BASE - timeout_base #define TREG0_RT_NETWORK_CONTROL_TIMEOUT_BASE_MASK 0x700u //! Field CLOCK_GATE_DISABLE - clock_gate_disable #define TREG0_RT_NETWORK_CONTROL_CLOCK_GATE_DISABLE_POS 56 //! Field CLOCK_GATE_DISABLE - clock_gate_disable #define TREG0_RT_NETWORK_CONTROL_CLOCK_GATE_DISABLE_MASK 0x100000000000000u //! @} //! \defgroup TREG0_SI_CONTROL Register TREG0_SI_CONTROL - control //! @{ //! Register Offset (relative) #define TREG0_SI_CONTROL 0x420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_CONTROL 0x1FF00420u //! Register Reset Value #define TREG0_SI_CONTROL_RST 0x0000000000000000u //! Field CLOCK_GATE_DISABLE - clock_gate_disable #define TREG0_SI_CONTROL_CLOCK_GATE_DISABLE_POS 56 //! Field CLOCK_GATE_DISABLE - clock_gate_disable #define TREG0_SI_CONTROL_CLOCK_GATE_DISABLE_MASK 0x100000000000000u //! @} //! \defgroup TREG0_SI_FLAG_STATUS_0 Register TREG0_SI_FLAG_STATUS_0 - flag_status_0 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_0 0x510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_0 0x1FF00510u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_0_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_0_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_0_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_1 Register TREG0_SI_FLAG_STATUS_1 - flag_status_1 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_1 0x530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_1 0x1FF00530u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_1_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_1_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_1_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_2 Register TREG0_SI_FLAG_STATUS_2 - flag_status_2 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_2 0x550 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_2 0x1FF00550u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_2_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_2_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_2_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_3 Register TREG0_SI_FLAG_STATUS_3 - flag_status_3 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_3 0x570 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_3 0x1FF00570u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_3_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_3_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_3_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_4 Register TREG0_SI_FLAG_STATUS_4 - flag_status_4 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_4 0x590 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_4 0x1FF00590u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_4_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_4_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_4_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_5 Register TREG0_SI_FLAG_STATUS_5 - flag_status_5 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_5 0x5B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_5 0x1FF005B0u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_5_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_5_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_5_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_6 Register TREG0_SI_FLAG_STATUS_6 - flag_status_6 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_6 0x5D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_6 0x1FF005D0u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_6_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_6_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_6_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_SI_FLAG_STATUS_7 Register TREG0_SI_FLAG_STATUS_7 - flag_status_7 //! @{ //! Register Offset (relative) #define TREG0_SI_FLAG_STATUS_7 0x5F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_SI_FLAG_STATUS_7 0x1FF005F0u //! Register Reset Value #define TREG0_SI_FLAG_STATUS_7_RST 0x0000000000000000u //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_7_STATUS_POS 0 //! Field STATUS - status #define TREG0_SI_FLAG_STATUS_7_STATUS_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_TA_COMPONENT Register TSSB_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TSSB_TA_COMPONENT 0x1000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_COMPONENT 0x1FF01000u //! Register Reset Value #define TSSB_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TSSB_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TSSB_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TSSB_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TSSB_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TSSB_TA_CORE Register TSSB_TA_CORE - core //! @{ //! Register Offset (relative) #define TSSB_TA_CORE 0x1018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_CORE 0x1FF01018u //! Register Reset Value #define TSSB_TA_CORE_RST 0x000088C3000B0001u //! Field REV_CODE - rev_code #define TSSB_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TSSB_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TSSB_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TSSB_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TSSB_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TSSB_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TSSB_TA_AGENT_CONTROL Register TSSB_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TSSB_TA_AGENT_CONTROL 0x1020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_AGENT_CONTROL 0x1FF01020u //! Register Reset Value #define TSSB_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TSSB_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TSSB_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TSSB_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TSSB_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TSSB_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TSSB_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TSSB_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TSSB_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TSSB_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TSSB_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TSSB_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TSSB_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TSSB_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TSSB_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TSSB_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TSSB_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TSSB_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TSSB_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TSSB_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TSSB_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TSSB_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TSSB_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TSSB_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TSSB_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TSSB_TA_AGENT_STATUS Register TSSB_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TSSB_TA_AGENT_STATUS 0x1028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_AGENT_STATUS 0x1FF01028u //! Register Reset Value #define TSSB_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TSSB_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TSSB_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TSSB_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TSSB_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TSSB_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TSSB_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TSSB_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TSSB_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TSSB_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TSSB_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TSSB_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TSSB_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TSSB_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TSSB_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TSSB_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TSSB_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TSSB_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TSSB_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TSSB_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TSSB_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TSSB_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TSSB_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TSSB_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TSSB_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TSSB_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TSSB_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TSSB_TA_ERROR_LOG Register TSSB_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TSSB_TA_ERROR_LOG 0x1058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ERROR_LOG 0x1FF01058u //! Register Reset Value #define TSSB_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TSSB_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TSSB_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TSSB_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TSSB_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TSSB_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TSSB_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TSSB_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TSSB_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TSSB_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TSSB_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TSSB_TA_ERROR_LOG_ADDR Register TSSB_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TSSB_TA_ERROR_LOG_ADDR 0x1060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ERROR_LOG_ADDR 0x1FF01060u //! Register Reset Value #define TSSB_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TSSB_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TSSB_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_TA_BANDWIDTH_0 Register TSSB_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TSSB_TA_BANDWIDTH_0 0x1100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_BANDWIDTH_0 0x1FF01100u //! Register Reset Value #define TSSB_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TSSB_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TSSB_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TSSB_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TSSB_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TSSB_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TSSB_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TSSB_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TSSB_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_BANDWIDTH_1 Register TSSB_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TSSB_TA_BANDWIDTH_1 0x1108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_BANDWIDTH_1 0x1FF01108u //! Register Reset Value #define TSSB_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TSSB_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TSSB_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TSSB_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TSSB_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TSSB_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TSSB_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TSSB_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TSSB_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_BANDWIDTH_2 Register TSSB_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TSSB_TA_BANDWIDTH_2 0x1110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_BANDWIDTH_2 0x1FF01110u //! Register Reset Value #define TSSB_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TSSB_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TSSB_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TSSB_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TSSB_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TSSB_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TSSB_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TSSB_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TSSB_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_BANDWIDTH_3 Register TSSB_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TSSB_TA_BANDWIDTH_3 0x1118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_BANDWIDTH_3 0x1FF01118u //! Register Reset Value #define TSSB_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TSSB_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TSSB_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TSSB_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TSSB_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TSSB_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TSSB_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TSSB_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TSSB_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_ALLOC_LIMIT_0 Register TSSB_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TSSB_TA_ALLOC_LIMIT_0 0x1200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ALLOC_LIMIT_0 0x1FF01200u //! Register Reset Value #define TSSB_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TSSB_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TSSB_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_ALLOC_LIMIT_1 Register TSSB_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TSSB_TA_ALLOC_LIMIT_1 0x1208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ALLOC_LIMIT_1 0x1FF01208u //! Register Reset Value #define TSSB_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TSSB_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TSSB_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_ALLOC_LIMIT_2 Register TSSB_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TSSB_TA_ALLOC_LIMIT_2 0x1210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ALLOC_LIMIT_2 0x1FF01210u //! Register Reset Value #define TSSB_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TSSB_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TSSB_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TSSB_TA_ALLOC_LIMIT_3 Register TSSB_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TSSB_TA_ALLOC_LIMIT_3 0x1218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_TA_ALLOC_LIMIT_3 0x1FF01218u //! Register Reset Value #define TSSB_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TSSB_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TSSB_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_COMPONENT Register TROM_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TROM_TA_COMPONENT 0x1400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_COMPONENT 0x1FF01400u //! Register Reset Value #define TROM_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TROM_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TROM_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TROM_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TROM_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TROM_TA_CORE Register TROM_TA_CORE - core //! @{ //! Register Offset (relative) #define TROM_TA_CORE 0x1418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_CORE 0x1FF01418u //! Register Reset Value #define TROM_TA_CORE_RST 0x000088C300080001u //! Field REV_CODE - rev_code #define TROM_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TROM_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TROM_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TROM_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TROM_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TROM_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TROM_TA_AGENT_CONTROL Register TROM_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TROM_TA_AGENT_CONTROL 0x1420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_AGENT_CONTROL 0x1FF01420u //! Register Reset Value #define TROM_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TROM_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TROM_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TROM_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TROM_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TROM_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TROM_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TROM_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TROM_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TROM_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TROM_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TROM_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TROM_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TROM_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TROM_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TROM_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TROM_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TROM_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TROM_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TROM_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TROM_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TROM_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TROM_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TROM_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TROM_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TROM_TA_AGENT_STATUS Register TROM_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TROM_TA_AGENT_STATUS 0x1428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_AGENT_STATUS 0x1FF01428u //! Register Reset Value #define TROM_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TROM_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TROM_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TROM_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TROM_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TROM_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TROM_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TROM_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TROM_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TROM_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TROM_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TROM_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TROM_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TROM_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TROM_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TROM_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TROM_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TROM_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TROM_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TROM_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TROM_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TROM_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TROM_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TROM_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TROM_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TROM_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TROM_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TROM_TA_ERROR_LOG Register TROM_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TROM_TA_ERROR_LOG 0x1458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ERROR_LOG 0x1FF01458u //! Register Reset Value #define TROM_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TROM_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TROM_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TROM_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TROM_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TROM_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TROM_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TROM_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TROM_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TROM_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TROM_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TROM_TA_ERROR_LOG_ADDR Register TROM_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TROM_TA_ERROR_LOG_ADDR 0x1460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ERROR_LOG_ADDR 0x1FF01460u //! Register Reset Value #define TROM_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TROM_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TROM_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_TA_BANDWIDTH_0 Register TROM_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TROM_TA_BANDWIDTH_0 0x1500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_BANDWIDTH_0 0x1FF01500u //! Register Reset Value #define TROM_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TROM_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TROM_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TROM_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TROM_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TROM_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TROM_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TROM_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TROM_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_BANDWIDTH_1 Register TROM_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TROM_TA_BANDWIDTH_1 0x1508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_BANDWIDTH_1 0x1FF01508u //! Register Reset Value #define TROM_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TROM_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TROM_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TROM_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TROM_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TROM_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TROM_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TROM_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TROM_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_BANDWIDTH_2 Register TROM_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TROM_TA_BANDWIDTH_2 0x1510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_BANDWIDTH_2 0x1FF01510u //! Register Reset Value #define TROM_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TROM_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TROM_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TROM_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TROM_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TROM_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TROM_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TROM_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TROM_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_BANDWIDTH_3 Register TROM_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TROM_TA_BANDWIDTH_3 0x1518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_BANDWIDTH_3 0x1FF01518u //! Register Reset Value #define TROM_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TROM_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TROM_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TROM_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TROM_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TROM_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TROM_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TROM_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TROM_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_ALLOC_LIMIT_0 Register TROM_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TROM_TA_ALLOC_LIMIT_0 0x1600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ALLOC_LIMIT_0 0x1FF01600u //! Register Reset Value #define TROM_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TROM_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TROM_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_ALLOC_LIMIT_1 Register TROM_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TROM_TA_ALLOC_LIMIT_1 0x1608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ALLOC_LIMIT_1 0x1FF01608u //! Register Reset Value #define TROM_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TROM_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TROM_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_ALLOC_LIMIT_2 Register TROM_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TROM_TA_ALLOC_LIMIT_2 0x1610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ALLOC_LIMIT_2 0x1FF01610u //! Register Reset Value #define TROM_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TROM_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TROM_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TROM_TA_ALLOC_LIMIT_3 Register TROM_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TROM_TA_ALLOC_LIMIT_3 0x1618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_TA_ALLOC_LIMIT_3 0x1FF01618u //! Register Reset Value #define TROM_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TROM_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TROM_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_COMPONENT Register TOTP_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TOTP_TA_COMPONENT 0x1800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_COMPONENT 0x1FF01800u //! Register Reset Value #define TOTP_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TOTP_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TOTP_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TOTP_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TOTP_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TOTP_TA_CORE Register TOTP_TA_CORE - core //! @{ //! Register Offset (relative) #define TOTP_TA_CORE 0x1818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_CORE 0x1FF01818u //! Register Reset Value #define TOTP_TA_CORE_RST 0x000088C300070001u //! Field REV_CODE - rev_code #define TOTP_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TOTP_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TOTP_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TOTP_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TOTP_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TOTP_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TOTP_TA_AGENT_CONTROL Register TOTP_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TOTP_TA_AGENT_CONTROL 0x1820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_AGENT_CONTROL 0x1FF01820u //! Register Reset Value #define TOTP_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TOTP_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TOTP_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TOTP_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TOTP_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TOTP_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TOTP_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TOTP_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TOTP_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TOTP_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TOTP_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TOTP_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TOTP_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TOTP_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TOTP_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TOTP_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TOTP_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TOTP_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TOTP_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TOTP_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TOTP_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TOTP_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TOTP_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TOTP_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TOTP_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TOTP_TA_AGENT_STATUS Register TOTP_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TOTP_TA_AGENT_STATUS 0x1828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_AGENT_STATUS 0x1FF01828u //! Register Reset Value #define TOTP_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TOTP_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TOTP_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TOTP_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TOTP_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TOTP_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TOTP_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TOTP_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TOTP_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TOTP_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TOTP_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TOTP_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TOTP_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TOTP_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TOTP_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TOTP_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TOTP_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TOTP_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TOTP_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TOTP_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TOTP_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TOTP_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TOTP_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TOTP_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TOTP_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TOTP_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TOTP_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TOTP_TA_ERROR_LOG Register TOTP_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TOTP_TA_ERROR_LOG 0x1858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ERROR_LOG 0x1FF01858u //! Register Reset Value #define TOTP_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TOTP_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TOTP_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TOTP_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TOTP_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TOTP_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TOTP_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TOTP_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TOTP_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TOTP_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TOTP_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TOTP_TA_ERROR_LOG_ADDR Register TOTP_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TOTP_TA_ERROR_LOG_ADDR 0x1860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ERROR_LOG_ADDR 0x1FF01860u //! Register Reset Value #define TOTP_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TOTP_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TOTP_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_TA_BANDWIDTH_0 Register TOTP_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TOTP_TA_BANDWIDTH_0 0x1900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_BANDWIDTH_0 0x1FF01900u //! Register Reset Value #define TOTP_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TOTP_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TOTP_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TOTP_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TOTP_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TOTP_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TOTP_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TOTP_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TOTP_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_BANDWIDTH_1 Register TOTP_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TOTP_TA_BANDWIDTH_1 0x1908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_BANDWIDTH_1 0x1FF01908u //! Register Reset Value #define TOTP_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TOTP_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TOTP_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TOTP_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TOTP_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TOTP_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TOTP_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TOTP_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TOTP_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_BANDWIDTH_2 Register TOTP_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TOTP_TA_BANDWIDTH_2 0x1910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_BANDWIDTH_2 0x1FF01910u //! Register Reset Value #define TOTP_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TOTP_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TOTP_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TOTP_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TOTP_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TOTP_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TOTP_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TOTP_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TOTP_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_BANDWIDTH_3 Register TOTP_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TOTP_TA_BANDWIDTH_3 0x1918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_BANDWIDTH_3 0x1FF01918u //! Register Reset Value #define TOTP_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TOTP_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TOTP_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TOTP_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TOTP_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TOTP_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TOTP_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TOTP_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TOTP_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_ALLOC_LIMIT_0 Register TOTP_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TOTP_TA_ALLOC_LIMIT_0 0x1A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ALLOC_LIMIT_0 0x1FF01A00u //! Register Reset Value #define TOTP_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TOTP_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TOTP_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_ALLOC_LIMIT_1 Register TOTP_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TOTP_TA_ALLOC_LIMIT_1 0x1A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ALLOC_LIMIT_1 0x1FF01A08u //! Register Reset Value #define TOTP_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TOTP_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TOTP_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_ALLOC_LIMIT_2 Register TOTP_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TOTP_TA_ALLOC_LIMIT_2 0x1A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ALLOC_LIMIT_2 0x1FF01A10u //! Register Reset Value #define TOTP_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TOTP_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TOTP_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TOTP_TA_ALLOC_LIMIT_3 Register TOTP_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TOTP_TA_ALLOC_LIMIT_3 0x1A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_TA_ALLOC_LIMIT_3 0x1FF01A18u //! Register Reset Value #define TOTP_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TOTP_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TOTP_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_COMPONENT Register TCBM1_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TCBM1_TA_COMPONENT 0x1C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_COMPONENT 0x1FF01C00u //! Register Reset Value #define TCBM1_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TCBM1_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TCBM1_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TCBM1_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TCBM1_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TCBM1_TA_CORE Register TCBM1_TA_CORE - core //! @{ //! Register Offset (relative) #define TCBM1_TA_CORE 0x1C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_CORE 0x1FF01C18u //! Register Reset Value #define TCBM1_TA_CORE_RST 0x000050C500090001u //! Field REV_CODE - rev_code #define TCBM1_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TCBM1_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TCBM1_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TCBM1_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TCBM1_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TCBM1_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TCBM1_TA_AGENT_CONTROL Register TCBM1_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TCBM1_TA_AGENT_CONTROL 0x1C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_AGENT_CONTROL 0x1FF01C20u //! Register Reset Value #define TCBM1_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TCBM1_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TCBM1_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TCBM1_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TCBM1_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TCBM1_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TCBM1_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM1_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM1_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TCBM1_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TCBM1_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TCBM1_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TCBM1_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TCBM1_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TCBM1_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TCBM1_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TCBM1_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TCBM1_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TCBM1_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TCBM1_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TCBM1_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TCBM1_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TCBM1_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TCBM1_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TCBM1_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TCBM1_TA_AGENT_STATUS Register TCBM1_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TCBM1_TA_AGENT_STATUS 0x1C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_AGENT_STATUS 0x1FF01C28u //! Register Reset Value #define TCBM1_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TCBM1_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TCBM1_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM1_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM1_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TCBM1_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TCBM1_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TCBM1_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TCBM1_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TCBM1_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TCBM1_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TCBM1_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TCBM1_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TCBM1_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TCBM1_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TCBM1_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TCBM1_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TCBM1_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TCBM1_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TCBM1_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TCBM1_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TCBM1_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TCBM1_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TCBM1_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TCBM1_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TCBM1_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TCBM1_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TCBM1_TA_ERROR_LOG Register TCBM1_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TCBM1_TA_ERROR_LOG 0x1C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ERROR_LOG 0x1FF01C58u //! Register Reset Value #define TCBM1_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TCBM1_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TCBM1_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TCBM1_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TCBM1_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TCBM1_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TCBM1_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TCBM1_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TCBM1_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TCBM1_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TCBM1_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TCBM1_TA_ERROR_LOG_ADDR Register TCBM1_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TCBM1_TA_ERROR_LOG_ADDR 0x1C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ERROR_LOG_ADDR 0x1FF01C60u //! Register Reset Value #define TCBM1_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TCBM1_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TCBM1_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_TA_BANDWIDTH_0 Register TCBM1_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TCBM1_TA_BANDWIDTH_0 0x1D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_BANDWIDTH_0 0x1FF01D00u //! Register Reset Value #define TCBM1_TA_BANDWIDTH_0_RST 0x2000200020002000u //! Field FRACTION_0 - fraction_0 #define TCBM1_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TCBM1_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TCBM1_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TCBM1_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TCBM1_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TCBM1_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TCBM1_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TCBM1_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_BANDWIDTH_1 Register TCBM1_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TCBM1_TA_BANDWIDTH_1 0x1D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_BANDWIDTH_1 0x1FF01D08u //! Register Reset Value #define TCBM1_TA_BANDWIDTH_1_RST 0x0000200020002000u //! Field FRACTION_4 - fraction_4 #define TCBM1_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TCBM1_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TCBM1_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TCBM1_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TCBM1_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TCBM1_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TCBM1_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TCBM1_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_BANDWIDTH_2 Register TCBM1_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TCBM1_TA_BANDWIDTH_2 0x1D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_BANDWIDTH_2 0x1FF01D10u //! Register Reset Value #define TCBM1_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TCBM1_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TCBM1_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TCBM1_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TCBM1_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TCBM1_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TCBM1_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TCBM1_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TCBM1_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_BANDWIDTH_3 Register TCBM1_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TCBM1_TA_BANDWIDTH_3 0x1D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_BANDWIDTH_3 0x1FF01D18u //! Register Reset Value #define TCBM1_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TCBM1_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TCBM1_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TCBM1_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TCBM1_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TCBM1_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TCBM1_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TCBM1_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TCBM1_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_ALLOC_LIMIT_0 Register TCBM1_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TCBM1_TA_ALLOC_LIMIT_0 0x1E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ALLOC_LIMIT_0 0x1FF01E00u //! Register Reset Value #define TCBM1_TA_ALLOC_LIMIT_0_RST 0x0404040404040404u //! Field MIN_VALUE_0 - min_value_0 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TCBM1_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TCBM1_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_ALLOC_LIMIT_1 Register TCBM1_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TCBM1_TA_ALLOC_LIMIT_1 0x1E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ALLOC_LIMIT_1 0x1FF01E08u //! Register Reset Value #define TCBM1_TA_ALLOC_LIMIT_1_RST 0x0000040404040404u //! Field MIN_VALUE_4 - min_value_4 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TCBM1_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TCBM1_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_ALLOC_LIMIT_2 Register TCBM1_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TCBM1_TA_ALLOC_LIMIT_2 0x1E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ALLOC_LIMIT_2 0x1FF01E10u //! Register Reset Value #define TCBM1_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TCBM1_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TCBM1_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM1_TA_ALLOC_LIMIT_3 Register TCBM1_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TCBM1_TA_ALLOC_LIMIT_3 0x1E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_TA_ALLOC_LIMIT_3 0x1FF01E18u //! Register Reset Value #define TCBM1_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TCBM1_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TCBM1_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_COMPONENT Register TCBM2_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TCBM2_TA_COMPONENT 0x2000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_COMPONENT 0x1FF02000u //! Register Reset Value #define TCBM2_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TCBM2_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TCBM2_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TCBM2_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TCBM2_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TCBM2_TA_CORE Register TCBM2_TA_CORE - core //! @{ //! Register Offset (relative) #define TCBM2_TA_CORE 0x2018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_CORE 0x1FF02018u //! Register Reset Value #define TCBM2_TA_CORE_RST 0x000050C501090001u //! Field REV_CODE - rev_code #define TCBM2_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TCBM2_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TCBM2_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TCBM2_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TCBM2_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TCBM2_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TCBM2_TA_AGENT_CONTROL Register TCBM2_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TCBM2_TA_AGENT_CONTROL 0x2020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_AGENT_CONTROL 0x1FF02020u //! Register Reset Value #define TCBM2_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TCBM2_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TCBM2_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TCBM2_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TCBM2_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TCBM2_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TCBM2_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM2_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM2_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TCBM2_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TCBM2_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TCBM2_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TCBM2_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TCBM2_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TCBM2_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TCBM2_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TCBM2_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TCBM2_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TCBM2_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TCBM2_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TCBM2_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TCBM2_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TCBM2_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TCBM2_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TCBM2_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TCBM2_TA_AGENT_STATUS Register TCBM2_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TCBM2_TA_AGENT_STATUS 0x2028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_AGENT_STATUS 0x1FF02028u //! Register Reset Value #define TCBM2_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TCBM2_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TCBM2_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM2_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TCBM2_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TCBM2_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TCBM2_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TCBM2_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TCBM2_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TCBM2_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TCBM2_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TCBM2_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TCBM2_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TCBM2_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TCBM2_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TCBM2_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TCBM2_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TCBM2_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TCBM2_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TCBM2_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TCBM2_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TCBM2_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TCBM2_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TCBM2_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TCBM2_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TCBM2_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TCBM2_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TCBM2_TA_ERROR_LOG Register TCBM2_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TCBM2_TA_ERROR_LOG 0x2058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ERROR_LOG 0x1FF02058u //! Register Reset Value #define TCBM2_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TCBM2_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TCBM2_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TCBM2_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TCBM2_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TCBM2_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TCBM2_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TCBM2_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TCBM2_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TCBM2_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TCBM2_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TCBM2_TA_ERROR_LOG_ADDR Register TCBM2_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TCBM2_TA_ERROR_LOG_ADDR 0x2060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ERROR_LOG_ADDR 0x1FF02060u //! Register Reset Value #define TCBM2_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TCBM2_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TCBM2_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_TA_BANDWIDTH_0 Register TCBM2_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TCBM2_TA_BANDWIDTH_0 0x2100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_BANDWIDTH_0 0x1FF02100u //! Register Reset Value #define TCBM2_TA_BANDWIDTH_0_RST 0x2000200020002000u //! Field FRACTION_0 - fraction_0 #define TCBM2_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TCBM2_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TCBM2_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TCBM2_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TCBM2_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TCBM2_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TCBM2_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TCBM2_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_BANDWIDTH_1 Register TCBM2_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TCBM2_TA_BANDWIDTH_1 0x2108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_BANDWIDTH_1 0x1FF02108u //! Register Reset Value #define TCBM2_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TCBM2_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TCBM2_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TCBM2_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TCBM2_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TCBM2_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TCBM2_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TCBM2_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TCBM2_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_BANDWIDTH_2 Register TCBM2_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TCBM2_TA_BANDWIDTH_2 0x2110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_BANDWIDTH_2 0x1FF02110u //! Register Reset Value #define TCBM2_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TCBM2_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TCBM2_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TCBM2_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TCBM2_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TCBM2_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TCBM2_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TCBM2_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TCBM2_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_BANDWIDTH_3 Register TCBM2_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TCBM2_TA_BANDWIDTH_3 0x2118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_BANDWIDTH_3 0x1FF02118u //! Register Reset Value #define TCBM2_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TCBM2_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TCBM2_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TCBM2_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TCBM2_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TCBM2_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TCBM2_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TCBM2_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TCBM2_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_ALLOC_LIMIT_0 Register TCBM2_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TCBM2_TA_ALLOC_LIMIT_0 0x2200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ALLOC_LIMIT_0 0x1FF02200u //! Register Reset Value #define TCBM2_TA_ALLOC_LIMIT_0_RST 0x0404040404040404u //! Field MIN_VALUE_0 - min_value_0 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TCBM2_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TCBM2_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_ALLOC_LIMIT_1 Register TCBM2_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TCBM2_TA_ALLOC_LIMIT_1 0x2208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ALLOC_LIMIT_1 0x1FF02208u //! Register Reset Value #define TCBM2_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TCBM2_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TCBM2_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_ALLOC_LIMIT_2 Register TCBM2_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TCBM2_TA_ALLOC_LIMIT_2 0x2210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ALLOC_LIMIT_2 0x1FF02210u //! Register Reset Value #define TCBM2_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TCBM2_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TCBM2_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TCBM2_TA_ALLOC_LIMIT_3 Register TCBM2_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TCBM2_TA_ALLOC_LIMIT_3 0x2218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_TA_ALLOC_LIMIT_3 0x1FF02218u //! Register Reset Value #define TCBM2_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TCBM2_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TCBM2_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_COMPONENT Register TE97_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TE97_TA_COMPONENT 0x2400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_COMPONENT 0x1FF02400u //! Register Reset Value #define TE97_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TE97_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TE97_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TE97_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TE97_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TE97_TA_CORE Register TE97_TA_CORE - core //! @{ //! Register Offset (relative) #define TE97_TA_CORE 0x2418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_CORE 0x1FF02418u //! Register Reset Value #define TE97_TA_CORE_RST 0x000050C5000E0001u //! Field REV_CODE - rev_code #define TE97_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TE97_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TE97_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TE97_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TE97_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TE97_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TE97_TA_AGENT_CONTROL Register TE97_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TE97_TA_AGENT_CONTROL 0x2420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_AGENT_CONTROL 0x1FF02420u //! Register Reset Value #define TE97_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TE97_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TE97_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TE97_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TE97_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TE97_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TE97_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE97_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE97_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TE97_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TE97_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TE97_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TE97_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TE97_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TE97_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TE97_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TE97_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TE97_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TE97_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TE97_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TE97_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TE97_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TE97_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TE97_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TE97_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TE97_TA_AGENT_STATUS Register TE97_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TE97_TA_AGENT_STATUS 0x2428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_AGENT_STATUS 0x1FF02428u //! Register Reset Value #define TE97_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TE97_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TE97_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE97_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE97_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TE97_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TE97_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TE97_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TE97_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TE97_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TE97_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TE97_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TE97_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TE97_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TE97_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TE97_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TE97_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TE97_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TE97_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TE97_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TE97_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TE97_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TE97_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TE97_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TE97_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TE97_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TE97_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TE97_TA_ERROR_LOG Register TE97_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TE97_TA_ERROR_LOG 0x2458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ERROR_LOG 0x1FF02458u //! Register Reset Value #define TE97_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TE97_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TE97_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TE97_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TE97_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TE97_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TE97_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TE97_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TE97_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TE97_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TE97_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TE97_TA_ERROR_LOG_ADDR Register TE97_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TE97_TA_ERROR_LOG_ADDR 0x2460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ERROR_LOG_ADDR 0x1FF02460u //! Register Reset Value #define TE97_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TE97_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TE97_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_TA_BANDWIDTH_0 Register TE97_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TE97_TA_BANDWIDTH_0 0x2500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_BANDWIDTH_0 0x1FF02500u //! Register Reset Value #define TE97_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TE97_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TE97_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TE97_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TE97_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TE97_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TE97_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TE97_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TE97_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_BANDWIDTH_1 Register TE97_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TE97_TA_BANDWIDTH_1 0x2508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_BANDWIDTH_1 0x1FF02508u //! Register Reset Value #define TE97_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TE97_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TE97_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TE97_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TE97_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TE97_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TE97_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TE97_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TE97_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_BANDWIDTH_2 Register TE97_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TE97_TA_BANDWIDTH_2 0x2510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_BANDWIDTH_2 0x1FF02510u //! Register Reset Value #define TE97_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TE97_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TE97_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TE97_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TE97_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TE97_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TE97_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TE97_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TE97_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_BANDWIDTH_3 Register TE97_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TE97_TA_BANDWIDTH_3 0x2518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_BANDWIDTH_3 0x1FF02518u //! Register Reset Value #define TE97_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TE97_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TE97_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TE97_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TE97_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TE97_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TE97_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TE97_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TE97_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_ALLOC_LIMIT_0 Register TE97_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TE97_TA_ALLOC_LIMIT_0 0x2600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ALLOC_LIMIT_0 0x1FF02600u //! Register Reset Value #define TE97_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TE97_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TE97_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_ALLOC_LIMIT_1 Register TE97_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TE97_TA_ALLOC_LIMIT_1 0x2608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ALLOC_LIMIT_1 0x1FF02608u //! Register Reset Value #define TE97_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TE97_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TE97_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_ALLOC_LIMIT_2 Register TE97_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TE97_TA_ALLOC_LIMIT_2 0x2610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ALLOC_LIMIT_2 0x1FF02610u //! Register Reset Value #define TE97_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TE97_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TE97_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TE97_TA_ALLOC_LIMIT_3 Register TE97_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TE97_TA_ALLOC_LIMIT_3 0x2618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_TA_ALLOC_LIMIT_3 0x1FF02618u //! Register Reset Value #define TE97_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TE97_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TE97_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_COMPONENT Register TE123_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TE123_TA_COMPONENT 0x2800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_COMPONENT 0x1FF02800u //! Register Reset Value #define TE123_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TE123_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TE123_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TE123_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TE123_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TE123_TA_CORE Register TE123_TA_CORE - core //! @{ //! Register Offset (relative) #define TE123_TA_CORE 0x2818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_CORE 0x1FF02818u //! Register Reset Value #define TE123_TA_CORE_RST 0x0000CAFE000F0000u //! Field REV_CODE - rev_code #define TE123_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TE123_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TE123_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TE123_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TE123_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TE123_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TE123_TA_AGENT_CONTROL Register TE123_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TE123_TA_AGENT_CONTROL 0x2820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_AGENT_CONTROL 0x1FF02820u //! Register Reset Value #define TE123_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TE123_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TE123_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TE123_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TE123_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TE123_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TE123_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE123_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE123_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TE123_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TE123_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TE123_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TE123_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TE123_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TE123_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TE123_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TE123_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TE123_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TE123_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TE123_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TE123_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TE123_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TE123_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TE123_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TE123_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TE123_TA_AGENT_STATUS Register TE123_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TE123_TA_AGENT_STATUS 0x2828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_AGENT_STATUS 0x1FF02828u //! Register Reset Value #define TE123_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TE123_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TE123_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE123_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TE123_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TE123_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TE123_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TE123_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TE123_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TE123_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TE123_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TE123_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TE123_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TE123_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TE123_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TE123_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TE123_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TE123_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TE123_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TE123_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TE123_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TE123_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TE123_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TE123_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TE123_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TE123_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TE123_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TE123_TA_ERROR_LOG Register TE123_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TE123_TA_ERROR_LOG 0x2858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ERROR_LOG 0x1FF02858u //! Register Reset Value #define TE123_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TE123_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TE123_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TE123_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TE123_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TE123_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TE123_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TE123_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TE123_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TE123_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TE123_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TE123_TA_ERROR_LOG_ADDR Register TE123_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TE123_TA_ERROR_LOG_ADDR 0x2860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ERROR_LOG_ADDR 0x1FF02860u //! Register Reset Value #define TE123_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TE123_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TE123_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_TA_BANDWIDTH_0 Register TE123_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TE123_TA_BANDWIDTH_0 0x2900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_BANDWIDTH_0 0x1FF02900u //! Register Reset Value #define TE123_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TE123_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TE123_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TE123_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TE123_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TE123_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TE123_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TE123_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TE123_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_BANDWIDTH_1 Register TE123_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TE123_TA_BANDWIDTH_1 0x2908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_BANDWIDTH_1 0x1FF02908u //! Register Reset Value #define TE123_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TE123_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TE123_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TE123_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TE123_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TE123_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TE123_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TE123_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TE123_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_BANDWIDTH_2 Register TE123_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TE123_TA_BANDWIDTH_2 0x2910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_BANDWIDTH_2 0x1FF02910u //! Register Reset Value #define TE123_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TE123_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TE123_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TE123_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TE123_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TE123_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TE123_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TE123_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TE123_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_BANDWIDTH_3 Register TE123_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TE123_TA_BANDWIDTH_3 0x2918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_BANDWIDTH_3 0x1FF02918u //! Register Reset Value #define TE123_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TE123_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TE123_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TE123_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TE123_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TE123_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TE123_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TE123_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TE123_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_ALLOC_LIMIT_0 Register TE123_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TE123_TA_ALLOC_LIMIT_0 0x2A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ALLOC_LIMIT_0 0x1FF02A00u //! Register Reset Value #define TE123_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TE123_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TE123_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_ALLOC_LIMIT_1 Register TE123_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TE123_TA_ALLOC_LIMIT_1 0x2A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ALLOC_LIMIT_1 0x1FF02A08u //! Register Reset Value #define TE123_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TE123_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TE123_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_ALLOC_LIMIT_2 Register TE123_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TE123_TA_ALLOC_LIMIT_2 0x2A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ALLOC_LIMIT_2 0x1FF02A10u //! Register Reset Value #define TE123_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TE123_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TE123_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TE123_TA_ALLOC_LIMIT_3 Register TE123_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TE123_TA_ALLOC_LIMIT_3 0x2A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_TA_ALLOC_LIMIT_3 0x1FF02A18u //! Register Reset Value #define TE123_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TE123_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TE123_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_COMPONENT Register TDM3_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TDM3_TA_COMPONENT 0x2C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_COMPONENT 0x1FF02C00u //! Register Reset Value #define TDM3_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TDM3_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TDM3_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TDM3_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TDM3_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TDM3_TA_CORE Register TDM3_TA_CORE - core //! @{ //! Register Offset (relative) #define TDM3_TA_CORE 0x2C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_CORE 0x1FF02C18u //! Register Reset Value #define TDM3_TA_CORE_RST 0x000088C3000C0001u //! Field REV_CODE - rev_code #define TDM3_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TDM3_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TDM3_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TDM3_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TDM3_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TDM3_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TDM3_TA_AGENT_CONTROL Register TDM3_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TDM3_TA_AGENT_CONTROL 0x2C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_AGENT_CONTROL 0x1FF02C20u //! Register Reset Value #define TDM3_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TDM3_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TDM3_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TDM3_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TDM3_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TDM3_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TDM3_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM3_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM3_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TDM3_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TDM3_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TDM3_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TDM3_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TDM3_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TDM3_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TDM3_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TDM3_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TDM3_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TDM3_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TDM3_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TDM3_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TDM3_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TDM3_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TDM3_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TDM3_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TDM3_TA_AGENT_STATUS Register TDM3_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TDM3_TA_AGENT_STATUS 0x2C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_AGENT_STATUS 0x1FF02C28u //! Register Reset Value #define TDM3_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TDM3_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TDM3_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM3_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM3_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TDM3_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TDM3_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TDM3_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TDM3_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TDM3_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TDM3_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TDM3_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TDM3_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TDM3_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TDM3_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TDM3_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TDM3_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TDM3_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TDM3_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TDM3_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TDM3_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TDM3_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TDM3_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TDM3_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TDM3_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TDM3_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TDM3_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TDM3_TA_ERROR_LOG Register TDM3_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TDM3_TA_ERROR_LOG 0x2C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ERROR_LOG 0x1FF02C58u //! Register Reset Value #define TDM3_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TDM3_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TDM3_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TDM3_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TDM3_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TDM3_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TDM3_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TDM3_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TDM3_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TDM3_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TDM3_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TDM3_TA_ERROR_LOG_ADDR Register TDM3_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TDM3_TA_ERROR_LOG_ADDR 0x2C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ERROR_LOG_ADDR 0x1FF02C60u //! Register Reset Value #define TDM3_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TDM3_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TDM3_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_TA_BANDWIDTH_0 Register TDM3_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TDM3_TA_BANDWIDTH_0 0x2D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_BANDWIDTH_0 0x1FF02D00u //! Register Reset Value #define TDM3_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TDM3_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TDM3_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TDM3_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TDM3_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TDM3_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TDM3_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TDM3_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TDM3_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_BANDWIDTH_1 Register TDM3_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TDM3_TA_BANDWIDTH_1 0x2D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_BANDWIDTH_1 0x1FF02D08u //! Register Reset Value #define TDM3_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TDM3_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TDM3_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TDM3_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TDM3_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TDM3_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TDM3_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TDM3_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TDM3_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_BANDWIDTH_2 Register TDM3_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TDM3_TA_BANDWIDTH_2 0x2D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_BANDWIDTH_2 0x1FF02D10u //! Register Reset Value #define TDM3_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TDM3_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TDM3_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TDM3_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TDM3_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TDM3_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TDM3_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TDM3_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TDM3_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_BANDWIDTH_3 Register TDM3_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TDM3_TA_BANDWIDTH_3 0x2D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_BANDWIDTH_3 0x1FF02D18u //! Register Reset Value #define TDM3_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TDM3_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TDM3_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TDM3_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TDM3_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TDM3_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TDM3_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TDM3_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TDM3_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_ALLOC_LIMIT_0 Register TDM3_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TDM3_TA_ALLOC_LIMIT_0 0x2E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ALLOC_LIMIT_0 0x1FF02E00u //! Register Reset Value #define TDM3_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TDM3_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TDM3_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_ALLOC_LIMIT_1 Register TDM3_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TDM3_TA_ALLOC_LIMIT_1 0x2E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ALLOC_LIMIT_1 0x1FF02E08u //! Register Reset Value #define TDM3_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TDM3_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TDM3_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_ALLOC_LIMIT_2 Register TDM3_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TDM3_TA_ALLOC_LIMIT_2 0x2E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ALLOC_LIMIT_2 0x1FF02E10u //! Register Reset Value #define TDM3_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TDM3_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TDM3_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TDM3_TA_ALLOC_LIMIT_3 Register TDM3_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TDM3_TA_ALLOC_LIMIT_3 0x2E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_TA_ALLOC_LIMIT_3 0x1FF02E18u //! Register Reset Value #define TDM3_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TDM3_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TDM3_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_COMPONENT Register TDM4_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TDM4_TA_COMPONENT 0x3000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_COMPONENT 0x1FF03000u //! Register Reset Value #define TDM4_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TDM4_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TDM4_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TDM4_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TDM4_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TDM4_TA_CORE Register TDM4_TA_CORE - core //! @{ //! Register Offset (relative) #define TDM4_TA_CORE 0x3018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_CORE 0x1FF03018u //! Register Reset Value #define TDM4_TA_CORE_RST 0x000088C3000D0001u //! Field REV_CODE - rev_code #define TDM4_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TDM4_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TDM4_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TDM4_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TDM4_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TDM4_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TDM4_TA_AGENT_CONTROL Register TDM4_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TDM4_TA_AGENT_CONTROL 0x3020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_AGENT_CONTROL 0x1FF03020u //! Register Reset Value #define TDM4_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TDM4_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TDM4_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TDM4_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TDM4_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TDM4_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TDM4_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM4_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM4_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TDM4_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TDM4_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TDM4_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TDM4_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TDM4_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TDM4_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TDM4_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TDM4_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TDM4_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TDM4_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TDM4_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TDM4_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TDM4_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TDM4_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TDM4_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TDM4_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TDM4_TA_AGENT_STATUS Register TDM4_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TDM4_TA_AGENT_STATUS 0x3028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_AGENT_STATUS 0x1FF03028u //! Register Reset Value #define TDM4_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TDM4_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TDM4_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM4_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TDM4_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TDM4_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TDM4_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TDM4_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TDM4_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TDM4_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TDM4_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TDM4_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TDM4_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TDM4_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TDM4_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TDM4_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TDM4_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TDM4_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TDM4_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TDM4_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TDM4_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TDM4_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TDM4_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TDM4_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TDM4_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TDM4_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TDM4_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TDM4_TA_ERROR_LOG Register TDM4_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TDM4_TA_ERROR_LOG 0x3058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ERROR_LOG 0x1FF03058u //! Register Reset Value #define TDM4_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TDM4_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TDM4_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TDM4_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TDM4_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TDM4_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TDM4_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TDM4_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TDM4_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TDM4_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TDM4_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TDM4_TA_ERROR_LOG_ADDR Register TDM4_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TDM4_TA_ERROR_LOG_ADDR 0x3060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ERROR_LOG_ADDR 0x1FF03060u //! Register Reset Value #define TDM4_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TDM4_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TDM4_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_TA_BANDWIDTH_0 Register TDM4_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TDM4_TA_BANDWIDTH_0 0x3100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_BANDWIDTH_0 0x1FF03100u //! Register Reset Value #define TDM4_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TDM4_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TDM4_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TDM4_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TDM4_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TDM4_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TDM4_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TDM4_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TDM4_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_BANDWIDTH_1 Register TDM4_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TDM4_TA_BANDWIDTH_1 0x3108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_BANDWIDTH_1 0x1FF03108u //! Register Reset Value #define TDM4_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TDM4_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TDM4_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TDM4_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TDM4_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TDM4_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TDM4_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TDM4_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TDM4_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_BANDWIDTH_2 Register TDM4_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TDM4_TA_BANDWIDTH_2 0x3110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_BANDWIDTH_2 0x1FF03110u //! Register Reset Value #define TDM4_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TDM4_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TDM4_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TDM4_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TDM4_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TDM4_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TDM4_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TDM4_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TDM4_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_BANDWIDTH_3 Register TDM4_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TDM4_TA_BANDWIDTH_3 0x3118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_BANDWIDTH_3 0x1FF03118u //! Register Reset Value #define TDM4_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TDM4_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TDM4_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TDM4_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TDM4_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TDM4_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TDM4_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TDM4_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TDM4_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_ALLOC_LIMIT_0 Register TDM4_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TDM4_TA_ALLOC_LIMIT_0 0x3200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ALLOC_LIMIT_0 0x1FF03200u //! Register Reset Value #define TDM4_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TDM4_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TDM4_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_ALLOC_LIMIT_1 Register TDM4_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TDM4_TA_ALLOC_LIMIT_1 0x3208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ALLOC_LIMIT_1 0x1FF03208u //! Register Reset Value #define TDM4_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TDM4_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TDM4_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_ALLOC_LIMIT_2 Register TDM4_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TDM4_TA_ALLOC_LIMIT_2 0x3210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ALLOC_LIMIT_2 0x1FF03210u //! Register Reset Value #define TDM4_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TDM4_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TDM4_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TDM4_TA_ALLOC_LIMIT_3 Register TDM4_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TDM4_TA_ALLOC_LIMIT_3 0x3218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_TA_ALLOC_LIMIT_3 0x1FF03218u //! Register Reset Value #define TDM4_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TDM4_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TDM4_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_COMPONENT Register TLN01_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TLN01_TA_COMPONENT 0x3400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_COMPONENT 0x1FF03400u //! Register Reset Value #define TLN01_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TLN01_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TLN01_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TLN01_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TLN01_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TLN01_TA_CORE Register TLN01_TA_CORE - core //! @{ //! Register Offset (relative) #define TLN01_TA_CORE 0x3418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_CORE 0x1FF03418u //! Register Reset Value #define TLN01_TA_CORE_RST 0x000050C50F010001u //! Field REV_CODE - rev_code #define TLN01_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TLN01_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TLN01_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TLN01_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TLN01_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TLN01_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TLN01_TA_AGENT_CONTROL Register TLN01_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TLN01_TA_AGENT_CONTROL 0x3420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_AGENT_CONTROL 0x1FF03420u //! Register Reset Value #define TLN01_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN01_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN01_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TLN01_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TLN01_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TLN01_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN01_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN01_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN01_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TLN01_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TLN01_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN01_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN01_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN01_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN01_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN01_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN01_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TLN01_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN01_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN01_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN01_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN01_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TLN01_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TLN01_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TLN01_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TLN01_TA_AGENT_STATUS Register TLN01_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TLN01_TA_AGENT_STATUS 0x3428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_AGENT_STATUS 0x1FF03428u //! Register Reset Value #define TLN01_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN01_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN01_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN01_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN01_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TLN01_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TLN01_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TLN01_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TLN01_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TLN01_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TLN01_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TLN01_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TLN01_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TLN01_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN01_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TLN01_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TLN01_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TLN01_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TLN01_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TLN01_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TLN01_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TLN01_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN01_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN01_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN01_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN01_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TLN01_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TLN01_TA_ERROR_LOG Register TLN01_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN01_TA_ERROR_LOG 0x3458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ERROR_LOG 0x1FF03458u //! Register Reset Value #define TLN01_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN01_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN01_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TLN01_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN01_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TLN01_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN01_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TLN01_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN01_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TLN01_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TLN01_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TLN01_TA_ERROR_LOG_ADDR Register TLN01_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TLN01_TA_ERROR_LOG_ADDR 0x3460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ERROR_LOG_ADDR 0x1FF03460u //! Register Reset Value #define TLN01_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TLN01_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TLN01_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_TA_BANDWIDTH_0 Register TLN01_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TLN01_TA_BANDWIDTH_0 0x3500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_BANDWIDTH_0 0x1FF03500u //! Register Reset Value #define TLN01_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TLN01_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TLN01_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TLN01_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TLN01_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TLN01_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TLN01_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TLN01_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TLN01_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_BANDWIDTH_1 Register TLN01_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TLN01_TA_BANDWIDTH_1 0x3508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_BANDWIDTH_1 0x1FF03508u //! Register Reset Value #define TLN01_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TLN01_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TLN01_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TLN01_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TLN01_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TLN01_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TLN01_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TLN01_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TLN01_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_BANDWIDTH_2 Register TLN01_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TLN01_TA_BANDWIDTH_2 0x3510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_BANDWIDTH_2 0x1FF03510u //! Register Reset Value #define TLN01_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TLN01_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TLN01_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TLN01_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TLN01_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TLN01_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TLN01_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TLN01_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TLN01_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_BANDWIDTH_3 Register TLN01_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TLN01_TA_BANDWIDTH_3 0x3518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_BANDWIDTH_3 0x1FF03518u //! Register Reset Value #define TLN01_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TLN01_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TLN01_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TLN01_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TLN01_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TLN01_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TLN01_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TLN01_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TLN01_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_ALLOC_LIMIT_0 Register TLN01_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TLN01_TA_ALLOC_LIMIT_0 0x3600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ALLOC_LIMIT_0 0x1FF03600u //! Register Reset Value #define TLN01_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TLN01_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TLN01_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_ALLOC_LIMIT_1 Register TLN01_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TLN01_TA_ALLOC_LIMIT_1 0x3608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ALLOC_LIMIT_1 0x1FF03608u //! Register Reset Value #define TLN01_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TLN01_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TLN01_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_ALLOC_LIMIT_2 Register TLN01_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TLN01_TA_ALLOC_LIMIT_2 0x3610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ALLOC_LIMIT_2 0x1FF03610u //! Register Reset Value #define TLN01_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TLN01_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TLN01_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN01_TA_ALLOC_LIMIT_3 Register TLN01_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TLN01_TA_ALLOC_LIMIT_3 0x3618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_TA_ALLOC_LIMIT_3 0x1FF03618u //! Register Reset Value #define TLN01_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TLN01_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TLN01_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_COMPONENT Register TLN02_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TLN02_TA_COMPONENT 0x3800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_COMPONENT 0x1FF03800u //! Register Reset Value #define TLN02_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TLN02_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TLN02_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TLN02_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TLN02_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TLN02_TA_CORE Register TLN02_TA_CORE - core //! @{ //! Register Offset (relative) #define TLN02_TA_CORE 0x3818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_CORE 0x1FF03818u //! Register Reset Value #define TLN02_TA_CORE_RST 0x000050C50F020001u //! Field REV_CODE - rev_code #define TLN02_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TLN02_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TLN02_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TLN02_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TLN02_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TLN02_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TLN02_TA_AGENT_CONTROL Register TLN02_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TLN02_TA_AGENT_CONTROL 0x3820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_AGENT_CONTROL 0x1FF03820u //! Register Reset Value #define TLN02_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN02_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN02_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TLN02_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TLN02_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TLN02_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN02_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN02_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN02_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TLN02_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TLN02_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN02_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN02_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN02_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN02_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN02_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN02_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TLN02_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN02_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN02_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN02_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN02_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TLN02_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TLN02_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TLN02_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TLN02_TA_AGENT_STATUS Register TLN02_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TLN02_TA_AGENT_STATUS 0x3828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_AGENT_STATUS 0x1FF03828u //! Register Reset Value #define TLN02_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN02_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN02_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN02_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN02_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TLN02_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TLN02_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TLN02_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TLN02_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TLN02_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TLN02_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TLN02_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TLN02_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TLN02_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN02_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TLN02_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TLN02_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TLN02_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TLN02_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TLN02_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TLN02_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TLN02_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN02_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN02_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN02_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN02_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TLN02_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TLN02_TA_ERROR_LOG Register TLN02_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN02_TA_ERROR_LOG 0x3858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ERROR_LOG 0x1FF03858u //! Register Reset Value #define TLN02_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN02_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN02_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TLN02_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN02_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TLN02_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN02_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TLN02_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN02_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TLN02_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TLN02_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TLN02_TA_ERROR_LOG_ADDR Register TLN02_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TLN02_TA_ERROR_LOG_ADDR 0x3860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ERROR_LOG_ADDR 0x1FF03860u //! Register Reset Value #define TLN02_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TLN02_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TLN02_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_TA_BANDWIDTH_0 Register TLN02_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TLN02_TA_BANDWIDTH_0 0x3900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_BANDWIDTH_0 0x1FF03900u //! Register Reset Value #define TLN02_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TLN02_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TLN02_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TLN02_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TLN02_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TLN02_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TLN02_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TLN02_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TLN02_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_BANDWIDTH_1 Register TLN02_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TLN02_TA_BANDWIDTH_1 0x3908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_BANDWIDTH_1 0x1FF03908u //! Register Reset Value #define TLN02_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TLN02_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TLN02_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TLN02_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TLN02_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TLN02_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TLN02_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TLN02_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TLN02_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_BANDWIDTH_2 Register TLN02_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TLN02_TA_BANDWIDTH_2 0x3910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_BANDWIDTH_2 0x1FF03910u //! Register Reset Value #define TLN02_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TLN02_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TLN02_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TLN02_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TLN02_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TLN02_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TLN02_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TLN02_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TLN02_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_BANDWIDTH_3 Register TLN02_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TLN02_TA_BANDWIDTH_3 0x3918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_BANDWIDTH_3 0x1FF03918u //! Register Reset Value #define TLN02_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TLN02_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TLN02_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TLN02_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TLN02_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TLN02_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TLN02_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TLN02_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TLN02_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_ALLOC_LIMIT_0 Register TLN02_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TLN02_TA_ALLOC_LIMIT_0 0x3A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ALLOC_LIMIT_0 0x1FF03A00u //! Register Reset Value #define TLN02_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TLN02_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TLN02_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_ALLOC_LIMIT_1 Register TLN02_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TLN02_TA_ALLOC_LIMIT_1 0x3A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ALLOC_LIMIT_1 0x1FF03A08u //! Register Reset Value #define TLN02_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TLN02_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TLN02_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_ALLOC_LIMIT_2 Register TLN02_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TLN02_TA_ALLOC_LIMIT_2 0x3A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ALLOC_LIMIT_2 0x1FF03A10u //! Register Reset Value #define TLN02_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TLN02_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TLN02_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN02_TA_ALLOC_LIMIT_3 Register TLN02_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TLN02_TA_ALLOC_LIMIT_3 0x3A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_TA_ALLOC_LIMIT_3 0x1FF03A18u //! Register Reset Value #define TLN02_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TLN02_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TLN02_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_COMPONENT Register TLN03_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TLN03_TA_COMPONENT 0x3C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_COMPONENT 0x1FF03C00u //! Register Reset Value #define TLN03_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TLN03_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TLN03_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TLN03_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TLN03_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TLN03_TA_CORE Register TLN03_TA_CORE - core //! @{ //! Register Offset (relative) #define TLN03_TA_CORE 0x3C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_CORE 0x1FF03C18u //! Register Reset Value #define TLN03_TA_CORE_RST 0x000050C50F030001u //! Field REV_CODE - rev_code #define TLN03_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TLN03_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TLN03_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TLN03_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TLN03_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TLN03_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TLN03_TA_AGENT_CONTROL Register TLN03_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TLN03_TA_AGENT_CONTROL 0x3C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_AGENT_CONTROL 0x1FF03C20u //! Register Reset Value #define TLN03_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN03_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN03_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TLN03_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TLN03_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TLN03_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN03_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN03_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN03_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TLN03_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TLN03_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN03_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN03_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN03_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN03_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN03_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN03_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TLN03_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN03_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN03_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN03_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN03_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TLN03_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TLN03_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TLN03_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TLN03_TA_AGENT_STATUS Register TLN03_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TLN03_TA_AGENT_STATUS 0x3C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_AGENT_STATUS 0x1FF03C28u //! Register Reset Value #define TLN03_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN03_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN03_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN03_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN03_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TLN03_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TLN03_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TLN03_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TLN03_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TLN03_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TLN03_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TLN03_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TLN03_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TLN03_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN03_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TLN03_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TLN03_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TLN03_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TLN03_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TLN03_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TLN03_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TLN03_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN03_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN03_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN03_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN03_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TLN03_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TLN03_TA_ERROR_LOG Register TLN03_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN03_TA_ERROR_LOG 0x3C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ERROR_LOG 0x1FF03C58u //! Register Reset Value #define TLN03_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN03_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN03_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TLN03_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN03_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TLN03_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN03_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TLN03_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN03_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TLN03_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TLN03_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TLN03_TA_ERROR_LOG_ADDR Register TLN03_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TLN03_TA_ERROR_LOG_ADDR 0x3C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ERROR_LOG_ADDR 0x1FF03C60u //! Register Reset Value #define TLN03_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TLN03_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TLN03_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_TA_BANDWIDTH_0 Register TLN03_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TLN03_TA_BANDWIDTH_0 0x3D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_BANDWIDTH_0 0x1FF03D00u //! Register Reset Value #define TLN03_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TLN03_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TLN03_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TLN03_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TLN03_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TLN03_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TLN03_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TLN03_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TLN03_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_BANDWIDTH_1 Register TLN03_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TLN03_TA_BANDWIDTH_1 0x3D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_BANDWIDTH_1 0x1FF03D08u //! Register Reset Value #define TLN03_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TLN03_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TLN03_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TLN03_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TLN03_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TLN03_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TLN03_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TLN03_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TLN03_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_BANDWIDTH_2 Register TLN03_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TLN03_TA_BANDWIDTH_2 0x3D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_BANDWIDTH_2 0x1FF03D10u //! Register Reset Value #define TLN03_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TLN03_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TLN03_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TLN03_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TLN03_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TLN03_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TLN03_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TLN03_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TLN03_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_BANDWIDTH_3 Register TLN03_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TLN03_TA_BANDWIDTH_3 0x3D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_BANDWIDTH_3 0x1FF03D18u //! Register Reset Value #define TLN03_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TLN03_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TLN03_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TLN03_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TLN03_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TLN03_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TLN03_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TLN03_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TLN03_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_ALLOC_LIMIT_0 Register TLN03_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TLN03_TA_ALLOC_LIMIT_0 0x3E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ALLOC_LIMIT_0 0x1FF03E00u //! Register Reset Value #define TLN03_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TLN03_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TLN03_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_ALLOC_LIMIT_1 Register TLN03_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TLN03_TA_ALLOC_LIMIT_1 0x3E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ALLOC_LIMIT_1 0x1FF03E08u //! Register Reset Value #define TLN03_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TLN03_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TLN03_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_ALLOC_LIMIT_2 Register TLN03_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TLN03_TA_ALLOC_LIMIT_2 0x3E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ALLOC_LIMIT_2 0x1FF03E10u //! Register Reset Value #define TLN03_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TLN03_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TLN03_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN03_TA_ALLOC_LIMIT_3 Register TLN03_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TLN03_TA_ALLOC_LIMIT_3 0x3E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_TA_ALLOC_LIMIT_3 0x1FF03E18u //! Register Reset Value #define TLN03_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TLN03_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TLN03_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_COMPONENT Register TEX04_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TEX04_TA_COMPONENT 0x4000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_COMPONENT 0x1FF04000u //! Register Reset Value #define TEX04_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TEX04_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TEX04_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TEX04_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TEX04_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TEX04_TA_CORE Register TEX04_TA_CORE - core //! @{ //! Register Offset (relative) #define TEX04_TA_CORE 0x4018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_CORE 0x1FF04018u //! Register Reset Value #define TEX04_TA_CORE_RST 0x000050C50F040001u //! Field REV_CODE - rev_code #define TEX04_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TEX04_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TEX04_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TEX04_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TEX04_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TEX04_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TEX04_TA_AGENT_CONTROL Register TEX04_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TEX04_TA_AGENT_CONTROL 0x4020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_AGENT_CONTROL 0x1FF04020u //! Register Reset Value #define TEX04_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TEX04_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TEX04_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TEX04_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TEX04_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TEX04_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TEX04_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX04_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX04_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TEX04_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TEX04_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TEX04_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TEX04_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TEX04_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TEX04_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TEX04_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TEX04_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TEX04_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TEX04_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TEX04_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TEX04_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TEX04_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TEX04_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TEX04_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TEX04_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TEX04_TA_AGENT_STATUS Register TEX04_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TEX04_TA_AGENT_STATUS 0x4028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_AGENT_STATUS 0x1FF04028u //! Register Reset Value #define TEX04_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TEX04_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TEX04_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX04_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX04_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TEX04_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TEX04_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TEX04_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TEX04_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TEX04_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TEX04_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TEX04_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TEX04_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TEX04_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TEX04_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TEX04_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TEX04_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TEX04_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TEX04_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TEX04_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TEX04_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TEX04_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TEX04_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TEX04_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TEX04_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TEX04_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TEX04_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TEX04_TA_ERROR_LOG Register TEX04_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TEX04_TA_ERROR_LOG 0x4058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ERROR_LOG 0x1FF04058u //! Register Reset Value #define TEX04_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TEX04_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TEX04_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TEX04_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TEX04_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TEX04_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TEX04_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TEX04_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TEX04_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TEX04_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TEX04_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TEX04_TA_ERROR_LOG_ADDR Register TEX04_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TEX04_TA_ERROR_LOG_ADDR 0x4060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ERROR_LOG_ADDR 0x1FF04060u //! Register Reset Value #define TEX04_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TEX04_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TEX04_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_TA_BANDWIDTH_0 Register TEX04_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TEX04_TA_BANDWIDTH_0 0x4100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_BANDWIDTH_0 0x1FF04100u //! Register Reset Value #define TEX04_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TEX04_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TEX04_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TEX04_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TEX04_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TEX04_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TEX04_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TEX04_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TEX04_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_BANDWIDTH_1 Register TEX04_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TEX04_TA_BANDWIDTH_1 0x4108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_BANDWIDTH_1 0x1FF04108u //! Register Reset Value #define TEX04_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TEX04_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TEX04_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TEX04_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TEX04_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TEX04_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TEX04_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TEX04_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TEX04_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_BANDWIDTH_2 Register TEX04_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TEX04_TA_BANDWIDTH_2 0x4110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_BANDWIDTH_2 0x1FF04110u //! Register Reset Value #define TEX04_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TEX04_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TEX04_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TEX04_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TEX04_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TEX04_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TEX04_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TEX04_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TEX04_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_BANDWIDTH_3 Register TEX04_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TEX04_TA_BANDWIDTH_3 0x4118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_BANDWIDTH_3 0x1FF04118u //! Register Reset Value #define TEX04_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TEX04_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TEX04_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TEX04_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TEX04_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TEX04_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TEX04_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TEX04_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TEX04_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_ALLOC_LIMIT_0 Register TEX04_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TEX04_TA_ALLOC_LIMIT_0 0x4200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ALLOC_LIMIT_0 0x1FF04200u //! Register Reset Value #define TEX04_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TEX04_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TEX04_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_ALLOC_LIMIT_1 Register TEX04_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TEX04_TA_ALLOC_LIMIT_1 0x4208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ALLOC_LIMIT_1 0x1FF04208u //! Register Reset Value #define TEX04_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TEX04_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TEX04_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_ALLOC_LIMIT_2 Register TEX04_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TEX04_TA_ALLOC_LIMIT_2 0x4210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ALLOC_LIMIT_2 0x1FF04210u //! Register Reset Value #define TEX04_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TEX04_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TEX04_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TEX04_TA_ALLOC_LIMIT_3 Register TEX04_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TEX04_TA_ALLOC_LIMIT_3 0x4218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_TA_ALLOC_LIMIT_3 0x1FF04218u //! Register Reset Value #define TEX04_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TEX04_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TEX04_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_COMPONENT Register TEX05_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TEX05_TA_COMPONENT 0x4400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_COMPONENT 0x1FF04400u //! Register Reset Value #define TEX05_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TEX05_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TEX05_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TEX05_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TEX05_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TEX05_TA_CORE Register TEX05_TA_CORE - core //! @{ //! Register Offset (relative) #define TEX05_TA_CORE 0x4418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_CORE 0x1FF04418u //! Register Reset Value #define TEX05_TA_CORE_RST 0x000050C50F050001u //! Field REV_CODE - rev_code #define TEX05_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TEX05_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TEX05_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TEX05_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TEX05_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TEX05_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TEX05_TA_AGENT_CONTROL Register TEX05_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TEX05_TA_AGENT_CONTROL 0x4420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_AGENT_CONTROL 0x1FF04420u //! Register Reset Value #define TEX05_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TEX05_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TEX05_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TEX05_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TEX05_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TEX05_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TEX05_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX05_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX05_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TEX05_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TEX05_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TEX05_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TEX05_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TEX05_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TEX05_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TEX05_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TEX05_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TEX05_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TEX05_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TEX05_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TEX05_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TEX05_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TEX05_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TEX05_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TEX05_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TEX05_TA_AGENT_STATUS Register TEX05_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TEX05_TA_AGENT_STATUS 0x4428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_AGENT_STATUS 0x1FF04428u //! Register Reset Value #define TEX05_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TEX05_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TEX05_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX05_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TEX05_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TEX05_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TEX05_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TEX05_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TEX05_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TEX05_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TEX05_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TEX05_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TEX05_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TEX05_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TEX05_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TEX05_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TEX05_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TEX05_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TEX05_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TEX05_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TEX05_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TEX05_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TEX05_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TEX05_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TEX05_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TEX05_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TEX05_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TEX05_TA_ERROR_LOG Register TEX05_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TEX05_TA_ERROR_LOG 0x4458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ERROR_LOG 0x1FF04458u //! Register Reset Value #define TEX05_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TEX05_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TEX05_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TEX05_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TEX05_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TEX05_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TEX05_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TEX05_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TEX05_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TEX05_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TEX05_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TEX05_TA_ERROR_LOG_ADDR Register TEX05_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TEX05_TA_ERROR_LOG_ADDR 0x4460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ERROR_LOG_ADDR 0x1FF04460u //! Register Reset Value #define TEX05_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TEX05_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TEX05_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_TA_BANDWIDTH_0 Register TEX05_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TEX05_TA_BANDWIDTH_0 0x4500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_BANDWIDTH_0 0x1FF04500u //! Register Reset Value #define TEX05_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TEX05_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TEX05_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TEX05_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TEX05_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TEX05_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TEX05_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TEX05_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TEX05_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_BANDWIDTH_1 Register TEX05_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TEX05_TA_BANDWIDTH_1 0x4508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_BANDWIDTH_1 0x1FF04508u //! Register Reset Value #define TEX05_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TEX05_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TEX05_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TEX05_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TEX05_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TEX05_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TEX05_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TEX05_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TEX05_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_BANDWIDTH_2 Register TEX05_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TEX05_TA_BANDWIDTH_2 0x4510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_BANDWIDTH_2 0x1FF04510u //! Register Reset Value #define TEX05_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TEX05_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TEX05_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TEX05_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TEX05_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TEX05_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TEX05_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TEX05_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TEX05_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_BANDWIDTH_3 Register TEX05_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TEX05_TA_BANDWIDTH_3 0x4518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_BANDWIDTH_3 0x1FF04518u //! Register Reset Value #define TEX05_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TEX05_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TEX05_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TEX05_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TEX05_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TEX05_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TEX05_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TEX05_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TEX05_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_ALLOC_LIMIT_0 Register TEX05_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TEX05_TA_ALLOC_LIMIT_0 0x4600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ALLOC_LIMIT_0 0x1FF04600u //! Register Reset Value #define TEX05_TA_ALLOC_LIMIT_0_RST 0x0000000000000000u //! Field MIN_VALUE_0 - min_value_0 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TEX05_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TEX05_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_ALLOC_LIMIT_1 Register TEX05_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TEX05_TA_ALLOC_LIMIT_1 0x4608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ALLOC_LIMIT_1 0x1FF04608u //! Register Reset Value #define TEX05_TA_ALLOC_LIMIT_1_RST 0x0000000000000000u //! Field MIN_VALUE_4 - min_value_4 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TEX05_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TEX05_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_ALLOC_LIMIT_2 Register TEX05_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TEX05_TA_ALLOC_LIMIT_2 0x4610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ALLOC_LIMIT_2 0x1FF04610u //! Register Reset Value #define TEX05_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TEX05_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TEX05_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TEX05_TA_ALLOC_LIMIT_3 Register TEX05_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TEX05_TA_ALLOC_LIMIT_3 0x4618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_TA_ALLOC_LIMIT_3 0x1FF04618u //! Register Reset Value #define TEX05_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TEX05_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TEX05_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_COMPONENT Register TLN06_TA_COMPONENT - component //! @{ //! Register Offset (relative) #define TLN06_TA_COMPONENT 0x4800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_COMPONENT 0x1FF04800u //! Register Reset Value #define TLN06_TA_COMPONENT_RST 0x0000000060203532u //! Field REV - rev #define TLN06_TA_COMPONENT_REV_POS 0 //! Field REV - rev #define TLN06_TA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define TLN06_TA_COMPONENT_CODE_POS 16 //! Field CODE - code #define TLN06_TA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup TLN06_TA_CORE Register TLN06_TA_CORE - core //! @{ //! Register Offset (relative) #define TLN06_TA_CORE 0x4818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_CORE 0x1FF04818u //! Register Reset Value #define TLN06_TA_CORE_RST 0x000050C50F060001u //! Field REV_CODE - rev_code #define TLN06_TA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define TLN06_TA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define TLN06_TA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define TLN06_TA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define TLN06_TA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define TLN06_TA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup TLN06_TA_AGENT_CONTROL Register TLN06_TA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define TLN06_TA_AGENT_CONTROL 0x4820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_AGENT_CONTROL 0x1FF04820u //! Register Reset Value #define TLN06_TA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN06_TA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN06_TA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define TLN06_TA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define TLN06_TA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field REQ_TIMEOUT - req_timeout #define TLN06_TA_AGENT_CONTROL_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN06_TA_AGENT_CONTROL_REQ_TIMEOUT_MASK 0x700u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN06_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_POS 16 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN06_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_MASK 0x70000u //! Field SERROR_REP - serror_rep #define TLN06_TA_AGENT_CONTROL_SERROR_REP_POS 24 //! Field SERROR_REP - serror_rep #define TLN06_TA_AGENT_CONTROL_SERROR_REP_MASK 0x1000000u //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN06_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_POS 25 //! Field REQ_TIMEOUT_REP - req_timeout_rep #define TLN06_TA_AGENT_CONTROL_REQ_TIMEOUT_REP_MASK 0x2000000u //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN06_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_POS 26 //! Field FUNCTIONAL_RESET_TIMEOUT_REP - functional_reset_timeout_rep #define TLN06_TA_AGENT_CONTROL_FUNCTIONAL_RESET_TIMEOUT_REP_MASK 0x4000000u //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN06_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_POS 27 //! Field AUTO_WAKEUP_RESP_CODE - auto_wakeup_resp_code #define TLN06_TA_AGENT_CONTROL_AUTO_WAKEUP_RESP_CODE_MASK 0x8000000u //! Field RFU0 - rfu0 #define TLN06_TA_AGENT_CONTROL_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN06_TA_AGENT_CONTROL_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN06_TA_AGENT_CONTROL_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN06_TA_AGENT_CONTROL_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN06_TA_AGENT_CONTROL_RFU2_POS 30 //! Field RFU2 - rfu2 #define TLN06_TA_AGENT_CONTROL_RFU2_MASK 0x40000000u //! Field RFU3 - rfu3 #define TLN06_TA_AGENT_CONTROL_RFU3_POS 31 //! Field RFU3 - rfu3 #define TLN06_TA_AGENT_CONTROL_RFU3_MASK 0x80000000u //! @} //! \defgroup TLN06_TA_AGENT_STATUS Register TLN06_TA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define TLN06_TA_AGENT_STATUS 0x4828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_AGENT_STATUS 0x1FF04828u //! Register Reset Value #define TLN06_TA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define TLN06_TA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define TLN06_TA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN06_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_POS 3 //! Field FUNCTIONAL_RESET_TIMEOUT - functional_reset_timeout #define TLN06_TA_AGENT_STATUS_FUNCTIONAL_RESET_TIMEOUT_MASK 0x8u //! Field REQ_WAITING - req_waiting #define TLN06_TA_AGENT_STATUS_REQ_WAITING_POS 4 //! Field REQ_WAITING - req_waiting #define TLN06_TA_AGENT_STATUS_REQ_WAITING_MASK 0x10u //! Field RESP_ACTIVE - resp_active #define TLN06_TA_AGENT_STATUS_RESP_ACTIVE_POS 5 //! Field RESP_ACTIVE - resp_active #define TLN06_TA_AGENT_STATUS_RESP_ACTIVE_MASK 0x20u //! Field BURST - burst #define TLN06_TA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define TLN06_TA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define TLN06_TA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define TLN06_TA_AGENT_STATUS_READEX_MASK 0x80u //! Field REQ_TIMEOUT - req_timeout #define TLN06_TA_AGENT_STATUS_REQ_TIMEOUT_POS 8 //! Field REQ_TIMEOUT - req_timeout #define TLN06_TA_AGENT_STATUS_REQ_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define TLN06_TA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define TLN06_TA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_CLOSE - burst_close #define TLN06_TA_AGENT_STATUS_BURST_CLOSE_POS 16 //! Field BURST_CLOSE - burst_close #define TLN06_TA_AGENT_STATUS_BURST_CLOSE_MASK 0x10000u //! Field SERROR - serror #define TLN06_TA_AGENT_STATUS_SERROR_POS 24 //! Field SERROR - serror #define TLN06_TA_AGENT_STATUS_SERROR_MASK 0x1000000u //! Field RFU0 - rfu0 #define TLN06_TA_AGENT_STATUS_RFU0_POS 28 //! Field RFU0 - rfu0 #define TLN06_TA_AGENT_STATUS_RFU0_MASK 0x10000000u //! Field RFU1 - rfu1 #define TLN06_TA_AGENT_STATUS_RFU1_POS 29 //! Field RFU1 - rfu1 #define TLN06_TA_AGENT_STATUS_RFU1_MASK 0x20000000u //! Field RFU2 - rfu2 #define TLN06_TA_AGENT_STATUS_RFU2_POS 31 //! Field RFU2 - rfu2 #define TLN06_TA_AGENT_STATUS_RFU2_MASK 0x80000000u //! @} //! \defgroup TLN06_TA_ERROR_LOG Register TLN06_TA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN06_TA_ERROR_LOG 0x4858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ERROR_LOG 0x1FF04858u //! Register Reset Value #define TLN06_TA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN06_TA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN06_TA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define TLN06_TA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN06_TA_ERROR_LOG_INITID_MASK 0xFF00u //! Field CODE - code #define TLN06_TA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN06_TA_ERROR_LOG_CODE_MASK 0xF000000u //! Field MULTI - multi #define TLN06_TA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN06_TA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define TLN06_TA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define TLN06_TA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup TLN06_TA_ERROR_LOG_ADDR Register TLN06_TA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define TLN06_TA_ERROR_LOG_ADDR 0x4860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ERROR_LOG_ADDR 0x1FF04860u //! Register Reset Value #define TLN06_TA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define TLN06_TA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define TLN06_TA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_TA_BANDWIDTH_0 Register TLN06_TA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define TLN06_TA_BANDWIDTH_0 0x4900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_BANDWIDTH_0 0x1FF04900u //! Register Reset Value #define TLN06_TA_BANDWIDTH_0_RST 0x0000000000000000u //! Field FRACTION_0 - fraction_0 #define TLN06_TA_BANDWIDTH_0_FRACTION_0_POS 8 //! Field FRACTION_0 - fraction_0 #define TLN06_TA_BANDWIDTH_0_FRACTION_0_MASK 0xFF00u //! Field FRACTION_1 - fraction_1 #define TLN06_TA_BANDWIDTH_0_FRACTION_1_POS 24 //! Field FRACTION_1 - fraction_1 #define TLN06_TA_BANDWIDTH_0_FRACTION_1_MASK 0xFF000000u //! Field FRACTION_2 - fraction_2 #define TLN06_TA_BANDWIDTH_0_FRACTION_2_POS 40 //! Field FRACTION_2 - fraction_2 #define TLN06_TA_BANDWIDTH_0_FRACTION_2_MASK 0xFF0000000000u //! Field FRACTION_3 - fraction_3 #define TLN06_TA_BANDWIDTH_0_FRACTION_3_POS 56 //! Field FRACTION_3 - fraction_3 #define TLN06_TA_BANDWIDTH_0_FRACTION_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_BANDWIDTH_1 Register TLN06_TA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define TLN06_TA_BANDWIDTH_1 0x4908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_BANDWIDTH_1 0x1FF04908u //! Register Reset Value #define TLN06_TA_BANDWIDTH_1_RST 0x0000000000000000u //! Field FRACTION_4 - fraction_4 #define TLN06_TA_BANDWIDTH_1_FRACTION_4_POS 8 //! Field FRACTION_4 - fraction_4 #define TLN06_TA_BANDWIDTH_1_FRACTION_4_MASK 0xFF00u //! Field FRACTION_5 - fraction_5 #define TLN06_TA_BANDWIDTH_1_FRACTION_5_POS 24 //! Field FRACTION_5 - fraction_5 #define TLN06_TA_BANDWIDTH_1_FRACTION_5_MASK 0xFF000000u //! Field FRACTION_6 - fraction_6 #define TLN06_TA_BANDWIDTH_1_FRACTION_6_POS 40 //! Field FRACTION_6 - fraction_6 #define TLN06_TA_BANDWIDTH_1_FRACTION_6_MASK 0xFF0000000000u //! Field FRACTION_7 - fraction_7 #define TLN06_TA_BANDWIDTH_1_FRACTION_7_POS 56 //! Field FRACTION_7 - fraction_7 #define TLN06_TA_BANDWIDTH_1_FRACTION_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_BANDWIDTH_2 Register TLN06_TA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define TLN06_TA_BANDWIDTH_2 0x4910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_BANDWIDTH_2 0x1FF04910u //! Register Reset Value #define TLN06_TA_BANDWIDTH_2_RST 0x0000000000000000u //! Field FRACTION_8 - fraction_8 #define TLN06_TA_BANDWIDTH_2_FRACTION_8_POS 8 //! Field FRACTION_8 - fraction_8 #define TLN06_TA_BANDWIDTH_2_FRACTION_8_MASK 0xFF00u //! Field FRACTION_9 - fraction_9 #define TLN06_TA_BANDWIDTH_2_FRACTION_9_POS 24 //! Field FRACTION_9 - fraction_9 #define TLN06_TA_BANDWIDTH_2_FRACTION_9_MASK 0xFF000000u //! Field FRACTION_10 - fraction_10 #define TLN06_TA_BANDWIDTH_2_FRACTION_10_POS 40 //! Field FRACTION_10 - fraction_10 #define TLN06_TA_BANDWIDTH_2_FRACTION_10_MASK 0xFF0000000000u //! Field FRACTION_11 - fraction_11 #define TLN06_TA_BANDWIDTH_2_FRACTION_11_POS 56 //! Field FRACTION_11 - fraction_11 #define TLN06_TA_BANDWIDTH_2_FRACTION_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_BANDWIDTH_3 Register TLN06_TA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define TLN06_TA_BANDWIDTH_3 0x4918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_BANDWIDTH_3 0x1FF04918u //! Register Reset Value #define TLN06_TA_BANDWIDTH_3_RST 0x0000000000000000u //! Field FRACTION_12 - fraction_12 #define TLN06_TA_BANDWIDTH_3_FRACTION_12_POS 8 //! Field FRACTION_12 - fraction_12 #define TLN06_TA_BANDWIDTH_3_FRACTION_12_MASK 0xFF00u //! Field FRACTION_13 - fraction_13 #define TLN06_TA_BANDWIDTH_3_FRACTION_13_POS 24 //! Field FRACTION_13 - fraction_13 #define TLN06_TA_BANDWIDTH_3_FRACTION_13_MASK 0xFF000000u //! Field FRACTION_14 - fraction_14 #define TLN06_TA_BANDWIDTH_3_FRACTION_14_POS 40 //! Field FRACTION_14 - fraction_14 #define TLN06_TA_BANDWIDTH_3_FRACTION_14_MASK 0xFF0000000000u //! Field FRACTION_15 - fraction_15 #define TLN06_TA_BANDWIDTH_3_FRACTION_15_POS 56 //! Field FRACTION_15 - fraction_15 #define TLN06_TA_BANDWIDTH_3_FRACTION_15_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_ALLOC_LIMIT_0 Register TLN06_TA_ALLOC_LIMIT_0 - alloc_limit_0 //! @{ //! Register Offset (relative) #define TLN06_TA_ALLOC_LIMIT_0 0x4A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ALLOC_LIMIT_0 0x1FF04A00u //! Register Reset Value #define TLN06_TA_ALLOC_LIMIT_0_RST 0x0101010101010101u //! Field MIN_VALUE_0 - min_value_0 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_0_POS 0 //! Field MIN_VALUE_0 - min_value_0 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_0_MASK 0xFFu //! Field MAX_VALUE_0 - max_value_0 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_0_POS 8 //! Field MAX_VALUE_0 - max_value_0 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_0_MASK 0xFF00u //! Field MIN_VALUE_1 - min_value_1 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_1_POS 16 //! Field MIN_VALUE_1 - min_value_1 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_1_MASK 0xFF0000u //! Field MAX_VALUE_1 - max_value_1 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_1_POS 24 //! Field MAX_VALUE_1 - max_value_1 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_1_MASK 0xFF000000u //! Field MIN_VALUE_2 - min_value_2 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_2_POS 32 //! Field MIN_VALUE_2 - min_value_2 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_2_MASK 0xFF00000000u //! Field MAX_VALUE_2 - max_value_2 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_2_POS 40 //! Field MAX_VALUE_2 - max_value_2 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_2_MASK 0xFF0000000000u //! Field MIN_VALUE_3 - min_value_3 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_3_POS 48 //! Field MIN_VALUE_3 - min_value_3 #define TLN06_TA_ALLOC_LIMIT_0_MIN_VALUE_3_MASK 0xFF000000000000u //! Field MAX_VALUE_3 - max_value_3 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_3_POS 56 //! Field MAX_VALUE_3 - max_value_3 #define TLN06_TA_ALLOC_LIMIT_0_MAX_VALUE_3_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_ALLOC_LIMIT_1 Register TLN06_TA_ALLOC_LIMIT_1 - alloc_limit_1 //! @{ //! Register Offset (relative) #define TLN06_TA_ALLOC_LIMIT_1 0x4A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ALLOC_LIMIT_1 0x1FF04A08u //! Register Reset Value #define TLN06_TA_ALLOC_LIMIT_1_RST 0x0000010101010101u //! Field MIN_VALUE_4 - min_value_4 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_4_POS 0 //! Field MIN_VALUE_4 - min_value_4 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_4_MASK 0xFFu //! Field MAX_VALUE_4 - max_value_4 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_4_POS 8 //! Field MAX_VALUE_4 - max_value_4 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_4_MASK 0xFF00u //! Field MIN_VALUE_5 - min_value_5 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_5_POS 16 //! Field MIN_VALUE_5 - min_value_5 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_5_MASK 0xFF0000u //! Field MAX_VALUE_5 - max_value_5 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_5_POS 24 //! Field MAX_VALUE_5 - max_value_5 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_5_MASK 0xFF000000u //! Field MIN_VALUE_6 - min_value_6 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_6_POS 32 //! Field MIN_VALUE_6 - min_value_6 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_6_MASK 0xFF00000000u //! Field MAX_VALUE_6 - max_value_6 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_6_POS 40 //! Field MAX_VALUE_6 - max_value_6 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_6_MASK 0xFF0000000000u //! Field MIN_VALUE_7 - min_value_7 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_7_POS 48 //! Field MIN_VALUE_7 - min_value_7 #define TLN06_TA_ALLOC_LIMIT_1_MIN_VALUE_7_MASK 0xFF000000000000u //! Field MAX_VALUE_7 - max_value_7 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_7_POS 56 //! Field MAX_VALUE_7 - max_value_7 #define TLN06_TA_ALLOC_LIMIT_1_MAX_VALUE_7_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_ALLOC_LIMIT_2 Register TLN06_TA_ALLOC_LIMIT_2 - alloc_limit_2 //! @{ //! Register Offset (relative) #define TLN06_TA_ALLOC_LIMIT_2 0x4A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ALLOC_LIMIT_2 0x1FF04A10u //! Register Reset Value #define TLN06_TA_ALLOC_LIMIT_2_RST 0x0000000000000000u //! Field MIN_VALUE_8 - min_value_8 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_8_POS 0 //! Field MIN_VALUE_8 - min_value_8 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_8_MASK 0xFFu //! Field MAX_VALUE_8 - max_value_8 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_8_POS 8 //! Field MAX_VALUE_8 - max_value_8 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_8_MASK 0xFF00u //! Field MIN_VALUE_9 - min_value_9 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_9_POS 16 //! Field MIN_VALUE_9 - min_value_9 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_9_MASK 0xFF0000u //! Field MAX_VALUE_9 - max_value_9 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_9_POS 24 //! Field MAX_VALUE_9 - max_value_9 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_9_MASK 0xFF000000u //! Field MIN_VALUE_10 - min_value_10 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_10_POS 32 //! Field MIN_VALUE_10 - min_value_10 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_10_MASK 0xFF00000000u //! Field MAX_VALUE_10 - max_value_10 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_10_POS 40 //! Field MAX_VALUE_10 - max_value_10 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_10_MASK 0xFF0000000000u //! Field MIN_VALUE_11 - min_value_11 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_11_POS 48 //! Field MIN_VALUE_11 - min_value_11 #define TLN06_TA_ALLOC_LIMIT_2_MIN_VALUE_11_MASK 0xFF000000000000u //! Field MAX_VALUE_11 - max_value_11 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_11_POS 56 //! Field MAX_VALUE_11 - max_value_11 #define TLN06_TA_ALLOC_LIMIT_2_MAX_VALUE_11_MASK 0xFF00000000000000u //! @} //! \defgroup TLN06_TA_ALLOC_LIMIT_3 Register TLN06_TA_ALLOC_LIMIT_3 - alloc_limit_3 //! @{ //! Register Offset (relative) #define TLN06_TA_ALLOC_LIMIT_3 0x4A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_TA_ALLOC_LIMIT_3 0x1FF04A18u //! Register Reset Value #define TLN06_TA_ALLOC_LIMIT_3_RST 0x0000000000000000u //! Field MIN_VALUE_12 - min_value_12 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_12_POS 0 //! Field MIN_VALUE_12 - min_value_12 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_12_MASK 0xFFu //! Field MAX_VALUE_12 - max_value_12 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_12_POS 8 //! Field MAX_VALUE_12 - max_value_12 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_12_MASK 0xFF00u //! Field MIN_VALUE_13 - min_value_13 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_13_POS 16 //! Field MIN_VALUE_13 - min_value_13 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_13_MASK 0xFF0000u //! Field MAX_VALUE_13 - max_value_13 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_13_POS 24 //! Field MAX_VALUE_13 - max_value_13 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_13_MASK 0xFF000000u //! Field MIN_VALUE_14 - min_value_14 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_14_POS 32 //! Field MIN_VALUE_14 - min_value_14 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_14_MASK 0xFF00000000u //! Field MAX_VALUE_14 - max_value_14 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_14_POS 40 //! Field MAX_VALUE_14 - max_value_14 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_14_MASK 0xFF0000000000u //! Field MIN_VALUE_15 - min_value_15 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_15_POS 48 //! Field MIN_VALUE_15 - min_value_15 #define TLN06_TA_ALLOC_LIMIT_3_MIN_VALUE_15_MASK 0xFF000000000000u //! Field MAX_VALUE_15 - max_value_15 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_15_POS 56 //! Field MAX_VALUE_15 - max_value_15 #define TLN06_TA_ALLOC_LIMIT_3_MAX_VALUE_15_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_COMPONENT Register IE97W_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IE97W_IA_COMPONENT 0x10000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_COMPONENT 0x1FF10000u //! Register Reset Value #define IE97W_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IE97W_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IE97W_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IE97W_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IE97W_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IE97W_IA_CORE Register IE97W_IA_CORE - core //! @{ //! Register Offset (relative) #define IE97W_IA_CORE 0x10018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_CORE 0x1FF10018u //! Register Reset Value #define IE97W_IA_CORE_RST 0x0000CAFE010E0000u //! Field REV_CODE - rev_code #define IE97W_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IE97W_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IE97W_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IE97W_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IE97W_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IE97W_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IE97W_IA_AGENT_CONTROL Register IE97W_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IE97W_IA_AGENT_CONTROL 0x10020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_AGENT_CONTROL 0x1FF10020u //! Register Reset Value #define IE97W_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE97W_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE97W_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IE97W_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IE97W_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IE97W_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE97W_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IE97W_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE97W_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IE97W_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IE97W_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE97W_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE97W_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE97W_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE97W_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE97W_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE97W_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE97W_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE97W_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE97W_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE97W_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE97W_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE97W_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IE97W_IA_AGENT_STATUS Register IE97W_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IE97W_IA_AGENT_STATUS 0x10028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_AGENT_STATUS 0x1FF10028u //! Register Reset Value #define IE97W_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE97W_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE97W_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IE97W_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IE97W_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IE97W_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IE97W_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IE97W_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IE97W_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IE97W_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IE97W_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IE97W_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE97W_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IE97W_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IE97W_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IE97W_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE97W_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IE97W_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IE97W_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE97W_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE97W_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE97W_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE97W_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IE97W_IA_ERROR_LOG Register IE97W_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IE97W_IA_ERROR_LOG 0x10058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_ERROR_LOG 0x1FF10058u //! Register Reset Value #define IE97W_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IE97W_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IE97W_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IE97W_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IE97W_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IE97W_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IE97W_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IE97W_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IE97W_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IE97W_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IE97W_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IE97W_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IE97W_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IE97W_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IE97W_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IE97W_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IE97W_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IE97W_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IE97W_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IE97W_IA_ERROR_LOG_ADDR Register IE97W_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IE97W_IA_ERROR_LOG_ADDR 0x10060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_ERROR_LOG_ADDR 0x1FF10060u //! Register Reset Value #define IE97W_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IE97W_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IE97W_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IE97W_IA_CORE_FLAG Register IE97W_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IE97W_IA_CORE_FLAG 0x10068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_CORE_FLAG 0x1FF10068u //! Register Reset Value #define IE97W_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IE97W_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IE97W_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IE97W_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IE97W_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IE97W_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IE97W_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IE97W_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IE97W_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IE97W_IA_ADDR_FILL_IN Register IE97W_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IE97W_IA_ADDR_FILL_IN 0x10070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_ADDR_FILL_IN 0x1FF10070u //! Register Reset Value #define IE97W_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IE97W_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IE97W_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IE97W_IA_BANDWIDTH_0 Register IE97W_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_0 0x10100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_0 0x1FF10100u //! Register Reset Value #define IE97W_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IE97W_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_1 Register IE97W_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_1 0x10108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_1 0x1FF10108u //! Register Reset Value #define IE97W_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IE97W_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_2 Register IE97W_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_2 0x10110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_2 0x1FF10110u //! Register Reset Value #define IE97W_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IE97W_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_3 Register IE97W_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_3 0x10118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_3 0x1FF10118u //! Register Reset Value #define IE97W_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IE97W_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_4 Register IE97W_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_4 0x10120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_4 0x1FF10120u //! Register Reset Value #define IE97W_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IE97W_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_5 Register IE97W_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_5 0x10128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_5 0x1FF10128u //! Register Reset Value #define IE97W_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IE97W_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_6 Register IE97W_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_6 0x10130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_6 0x1FF10130u //! Register Reset Value #define IE97W_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IE97W_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IE97W_IA_BANDWIDTH_7 Register IE97W_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IE97W_IA_BANDWIDTH_7 0x10138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97W_IA_BANDWIDTH_7 0x1FF10138u //! Register Reset Value #define IE97W_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IE97W_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_COMPONENT Register IE97R_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IE97R_IA_COMPONENT 0x10400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_COMPONENT 0x1FF10400u //! Register Reset Value #define IE97R_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IE97R_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IE97R_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IE97R_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IE97R_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IE97R_IA_CORE Register IE97R_IA_CORE - core //! @{ //! Register Offset (relative) #define IE97R_IA_CORE 0x10418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_CORE 0x1FF10418u //! Register Reset Value #define IE97R_IA_CORE_RST 0x0000CAFE000E0000u //! Field REV_CODE - rev_code #define IE97R_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IE97R_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IE97R_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IE97R_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IE97R_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IE97R_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IE97R_IA_AGENT_CONTROL Register IE97R_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IE97R_IA_AGENT_CONTROL 0x10420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_AGENT_CONTROL 0x1FF10420u //! Register Reset Value #define IE97R_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE97R_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE97R_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IE97R_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IE97R_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IE97R_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE97R_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IE97R_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE97R_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IE97R_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IE97R_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE97R_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE97R_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE97R_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE97R_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE97R_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE97R_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE97R_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE97R_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE97R_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE97R_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE97R_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE97R_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IE97R_IA_AGENT_STATUS Register IE97R_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IE97R_IA_AGENT_STATUS 0x10428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_AGENT_STATUS 0x1FF10428u //! Register Reset Value #define IE97R_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE97R_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE97R_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IE97R_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IE97R_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IE97R_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IE97R_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IE97R_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IE97R_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IE97R_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IE97R_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IE97R_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE97R_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IE97R_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IE97R_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IE97R_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE97R_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IE97R_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IE97R_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE97R_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE97R_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE97R_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE97R_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IE97R_IA_ERROR_LOG Register IE97R_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IE97R_IA_ERROR_LOG 0x10458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_ERROR_LOG 0x1FF10458u //! Register Reset Value #define IE97R_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IE97R_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IE97R_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IE97R_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IE97R_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IE97R_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IE97R_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IE97R_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IE97R_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IE97R_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IE97R_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IE97R_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IE97R_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IE97R_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IE97R_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IE97R_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IE97R_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IE97R_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IE97R_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IE97R_IA_ERROR_LOG_ADDR Register IE97R_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IE97R_IA_ERROR_LOG_ADDR 0x10460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_ERROR_LOG_ADDR 0x1FF10460u //! Register Reset Value #define IE97R_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IE97R_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IE97R_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IE97R_IA_CORE_FLAG Register IE97R_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IE97R_IA_CORE_FLAG 0x10468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_CORE_FLAG 0x1FF10468u //! Register Reset Value #define IE97R_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IE97R_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IE97R_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IE97R_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IE97R_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IE97R_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IE97R_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IE97R_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IE97R_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IE97R_IA_ADDR_FILL_IN Register IE97R_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IE97R_IA_ADDR_FILL_IN 0x10470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_ADDR_FILL_IN 0x1FF10470u //! Register Reset Value #define IE97R_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IE97R_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IE97R_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IE97R_IA_BANDWIDTH_0 Register IE97R_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_0 0x10500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_0 0x1FF10500u //! Register Reset Value #define IE97R_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IE97R_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_1 Register IE97R_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_1 0x10508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_1 0x1FF10508u //! Register Reset Value #define IE97R_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IE97R_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_2 Register IE97R_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_2 0x10510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_2 0x1FF10510u //! Register Reset Value #define IE97R_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IE97R_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_3 Register IE97R_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_3 0x10518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_3 0x1FF10518u //! Register Reset Value #define IE97R_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IE97R_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_4 Register IE97R_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_4 0x10520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_4 0x1FF10520u //! Register Reset Value #define IE97R_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IE97R_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_5 Register IE97R_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_5 0x10528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_5 0x1FF10528u //! Register Reset Value #define IE97R_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IE97R_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_6 Register IE97R_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_6 0x10530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_6 0x1FF10530u //! Register Reset Value #define IE97R_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IE97R_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IE97R_IA_BANDWIDTH_7 Register IE97R_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IE97R_IA_BANDWIDTH_7 0x10538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE97R_IA_BANDWIDTH_7 0x1FF10538u //! Register Reset Value #define IE97R_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IE97R_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_COMPONENT Register IE123W_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IE123W_IA_COMPONENT 0x10800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_COMPONENT 0x1FF10800u //! Register Reset Value #define IE123W_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IE123W_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IE123W_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IE123W_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IE123W_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IE123W_IA_CORE Register IE123W_IA_CORE - core //! @{ //! Register Offset (relative) #define IE123W_IA_CORE 0x10818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_CORE 0x1FF10818u //! Register Reset Value #define IE123W_IA_CORE_RST 0x0000CAFE010F0000u //! Field REV_CODE - rev_code #define IE123W_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IE123W_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IE123W_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IE123W_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IE123W_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IE123W_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IE123W_IA_AGENT_CONTROL Register IE123W_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IE123W_IA_AGENT_CONTROL 0x10820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_AGENT_CONTROL 0x1FF10820u //! Register Reset Value #define IE123W_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE123W_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE123W_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IE123W_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IE123W_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IE123W_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE123W_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IE123W_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE123W_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IE123W_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IE123W_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE123W_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE123W_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE123W_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE123W_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE123W_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE123W_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE123W_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE123W_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE123W_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE123W_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE123W_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE123W_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IE123W_IA_AGENT_STATUS Register IE123W_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IE123W_IA_AGENT_STATUS 0x10828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_AGENT_STATUS 0x1FF10828u //! Register Reset Value #define IE123W_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE123W_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE123W_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IE123W_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IE123W_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IE123W_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IE123W_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IE123W_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IE123W_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IE123W_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IE123W_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IE123W_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE123W_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IE123W_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IE123W_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IE123W_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE123W_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IE123W_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IE123W_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE123W_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE123W_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE123W_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE123W_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IE123W_IA_ERROR_LOG Register IE123W_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IE123W_IA_ERROR_LOG 0x10858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_ERROR_LOG 0x1FF10858u //! Register Reset Value #define IE123W_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IE123W_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IE123W_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IE123W_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IE123W_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IE123W_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IE123W_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IE123W_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IE123W_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IE123W_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IE123W_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IE123W_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IE123W_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IE123W_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IE123W_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IE123W_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IE123W_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IE123W_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IE123W_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IE123W_IA_ERROR_LOG_ADDR Register IE123W_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IE123W_IA_ERROR_LOG_ADDR 0x10860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_ERROR_LOG_ADDR 0x1FF10860u //! Register Reset Value #define IE123W_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IE123W_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IE123W_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IE123W_IA_CORE_FLAG Register IE123W_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IE123W_IA_CORE_FLAG 0x10868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_CORE_FLAG 0x1FF10868u //! Register Reset Value #define IE123W_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IE123W_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IE123W_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IE123W_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IE123W_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IE123W_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IE123W_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IE123W_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IE123W_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IE123W_IA_ADDR_FILL_IN Register IE123W_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IE123W_IA_ADDR_FILL_IN 0x10870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_ADDR_FILL_IN 0x1FF10870u //! Register Reset Value #define IE123W_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IE123W_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IE123W_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IE123W_IA_BANDWIDTH_0 Register IE123W_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_0 0x10900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_0 0x1FF10900u //! Register Reset Value #define IE123W_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IE123W_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_1 Register IE123W_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_1 0x10908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_1 0x1FF10908u //! Register Reset Value #define IE123W_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IE123W_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_2 Register IE123W_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_2 0x10910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_2 0x1FF10910u //! Register Reset Value #define IE123W_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IE123W_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_3 Register IE123W_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_3 0x10918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_3 0x1FF10918u //! Register Reset Value #define IE123W_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IE123W_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_4 Register IE123W_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_4 0x10920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_4 0x1FF10920u //! Register Reset Value #define IE123W_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IE123W_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_5 Register IE123W_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_5 0x10928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_5 0x1FF10928u //! Register Reset Value #define IE123W_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IE123W_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_6 Register IE123W_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_6 0x10930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_6 0x1FF10930u //! Register Reset Value #define IE123W_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IE123W_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IE123W_IA_BANDWIDTH_7 Register IE123W_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IE123W_IA_BANDWIDTH_7 0x10938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123W_IA_BANDWIDTH_7 0x1FF10938u //! Register Reset Value #define IE123W_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IE123W_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_COMPONENT Register IE123R_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IE123R_IA_COMPONENT 0x10C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_COMPONENT 0x1FF10C00u //! Register Reset Value #define IE123R_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IE123R_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IE123R_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IE123R_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IE123R_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IE123R_IA_CORE Register IE123R_IA_CORE - core //! @{ //! Register Offset (relative) #define IE123R_IA_CORE 0x10C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_CORE 0x1FF10C18u //! Register Reset Value #define IE123R_IA_CORE_RST 0x0000CAFE000F0000u //! Field REV_CODE - rev_code #define IE123R_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IE123R_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IE123R_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IE123R_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IE123R_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IE123R_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IE123R_IA_AGENT_CONTROL Register IE123R_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IE123R_IA_AGENT_CONTROL 0x10C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_AGENT_CONTROL 0x1FF10C20u //! Register Reset Value #define IE123R_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE123R_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE123R_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IE123R_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IE123R_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IE123R_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE123R_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IE123R_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE123R_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IE123R_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IE123R_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE123R_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IE123R_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE123R_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IE123R_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE123R_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IE123R_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE123R_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IE123R_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE123R_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IE123R_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE123R_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IE123R_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IE123R_IA_AGENT_STATUS Register IE123R_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IE123R_IA_AGENT_STATUS 0x10C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_AGENT_STATUS 0x1FF10C28u //! Register Reset Value #define IE123R_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IE123R_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IE123R_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IE123R_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IE123R_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IE123R_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IE123R_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IE123R_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IE123R_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IE123R_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IE123R_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IE123R_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IE123R_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IE123R_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IE123R_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IE123R_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IE123R_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IE123R_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IE123R_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE123R_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IE123R_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE123R_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IE123R_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IE123R_IA_ERROR_LOG Register IE123R_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IE123R_IA_ERROR_LOG 0x10C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_ERROR_LOG 0x1FF10C58u //! Register Reset Value #define IE123R_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IE123R_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IE123R_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IE123R_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IE123R_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IE123R_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IE123R_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IE123R_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IE123R_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IE123R_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IE123R_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IE123R_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IE123R_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IE123R_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IE123R_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IE123R_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IE123R_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IE123R_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IE123R_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IE123R_IA_ERROR_LOG_ADDR Register IE123R_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IE123R_IA_ERROR_LOG_ADDR 0x10C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_ERROR_LOG_ADDR 0x1FF10C60u //! Register Reset Value #define IE123R_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IE123R_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IE123R_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IE123R_IA_CORE_FLAG Register IE123R_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IE123R_IA_CORE_FLAG 0x10C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_CORE_FLAG 0x1FF10C68u //! Register Reset Value #define IE123R_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IE123R_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IE123R_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IE123R_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IE123R_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IE123R_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IE123R_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IE123R_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IE123R_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IE123R_IA_ADDR_FILL_IN Register IE123R_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IE123R_IA_ADDR_FILL_IN 0x10C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_ADDR_FILL_IN 0x1FF10C70u //! Register Reset Value #define IE123R_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IE123R_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IE123R_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IE123R_IA_BANDWIDTH_0 Register IE123R_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_0 0x10D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_0 0x1FF10D00u //! Register Reset Value #define IE123R_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IE123R_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_1 Register IE123R_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_1 0x10D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_1 0x1FF10D08u //! Register Reset Value #define IE123R_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IE123R_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_2 Register IE123R_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_2 0x10D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_2 0x1FF10D10u //! Register Reset Value #define IE123R_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IE123R_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_3 Register IE123R_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_3 0x10D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_3 0x1FF10D18u //! Register Reset Value #define IE123R_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IE123R_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_4 Register IE123R_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_4 0x10D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_4 0x1FF10D20u //! Register Reset Value #define IE123R_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IE123R_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_5 Register IE123R_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_5 0x10D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_5 0x1FF10D28u //! Register Reset Value #define IE123R_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IE123R_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_6 Register IE123R_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_6 0x10D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_6 0x1FF10D30u //! Register Reset Value #define IE123R_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IE123R_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IE123R_IA_BANDWIDTH_7 Register IE123R_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IE123R_IA_BANDWIDTH_7 0x10D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IE123R_IA_BANDWIDTH_7 0x1FF10D38u //! Register Reset Value #define IE123R_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IE123R_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_COMPONENT Register IDM0_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IDM0_IA_COMPONENT 0x11000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_COMPONENT 0x1FF11000u //! Register Reset Value #define IDM0_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IDM0_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IDM0_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IDM0_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IDM0_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IDM0_IA_CORE Register IDM0_IA_CORE - core //! @{ //! Register Offset (relative) #define IDM0_IA_CORE 0x11018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_CORE 0x1FF11018u //! Register Reset Value #define IDM0_IA_CORE_RST 0x000050C5004F0001u //! Field REV_CODE - rev_code #define IDM0_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IDM0_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IDM0_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IDM0_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IDM0_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IDM0_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IDM0_IA_AGENT_CONTROL Register IDM0_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IDM0_IA_AGENT_CONTROL 0x11020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_AGENT_CONTROL 0x1FF11020u //! Register Reset Value #define IDM0_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM0_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM0_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IDM0_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IDM0_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IDM0_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM0_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IDM0_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM0_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IDM0_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IDM0_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM0_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM0_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM0_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM0_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM0_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM0_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM0_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM0_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM0_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM0_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM0_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM0_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IDM0_IA_AGENT_STATUS Register IDM0_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IDM0_IA_AGENT_STATUS 0x11028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_AGENT_STATUS 0x1FF11028u //! Register Reset Value #define IDM0_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM0_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM0_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IDM0_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IDM0_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IDM0_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IDM0_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IDM0_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IDM0_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IDM0_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IDM0_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IDM0_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM0_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IDM0_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IDM0_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IDM0_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM0_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IDM0_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IDM0_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM0_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM0_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM0_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM0_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IDM0_IA_ERROR_LOG Register IDM0_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IDM0_IA_ERROR_LOG 0x11058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_ERROR_LOG 0x1FF11058u //! Register Reset Value #define IDM0_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IDM0_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IDM0_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IDM0_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IDM0_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IDM0_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IDM0_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IDM0_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IDM0_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IDM0_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IDM0_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IDM0_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IDM0_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IDM0_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IDM0_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IDM0_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IDM0_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IDM0_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IDM0_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IDM0_IA_ERROR_LOG_ADDR Register IDM0_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IDM0_IA_ERROR_LOG_ADDR 0x11060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_ERROR_LOG_ADDR 0x1FF11060u //! Register Reset Value #define IDM0_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IDM0_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IDM0_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IDM0_IA_CORE_FLAG Register IDM0_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IDM0_IA_CORE_FLAG 0x11068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_CORE_FLAG 0x1FF11068u //! Register Reset Value #define IDM0_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IDM0_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IDM0_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IDM0_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IDM0_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IDM0_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IDM0_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IDM0_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IDM0_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IDM0_IA_ADDR_FILL_IN Register IDM0_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IDM0_IA_ADDR_FILL_IN 0x11070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_ADDR_FILL_IN 0x1FF11070u //! Register Reset Value #define IDM0_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IDM0_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IDM0_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IDM0_IA_BANDWIDTH_0 Register IDM0_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_0 0x11100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_0 0x1FF11100u //! Register Reset Value #define IDM0_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IDM0_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_1 Register IDM0_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_1 0x11108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_1 0x1FF11108u //! Register Reset Value #define IDM0_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IDM0_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_2 Register IDM0_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_2 0x11110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_2 0x1FF11110u //! Register Reset Value #define IDM0_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IDM0_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_3 Register IDM0_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_3 0x11118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_3 0x1FF11118u //! Register Reset Value #define IDM0_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IDM0_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_4 Register IDM0_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_4 0x11120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_4 0x1FF11120u //! Register Reset Value #define IDM0_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IDM0_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_5 Register IDM0_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_5 0x11128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_5 0x1FF11128u //! Register Reset Value #define IDM0_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IDM0_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_6 Register IDM0_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_6 0x11130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_6 0x1FF11130u //! Register Reset Value #define IDM0_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IDM0_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IDM0_IA_BANDWIDTH_7 Register IDM0_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IDM0_IA_BANDWIDTH_7 0x11138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM0_IA_BANDWIDTH_7 0x1FF11138u //! Register Reset Value #define IDM0_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IDM0_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_COMPONENT Register IDM3_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IDM3_IA_COMPONENT 0x11400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_COMPONENT 0x1FF11400u //! Register Reset Value #define IDM3_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IDM3_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IDM3_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IDM3_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IDM3_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IDM3_IA_CORE Register IDM3_IA_CORE - core //! @{ //! Register Offset (relative) #define IDM3_IA_CORE 0x11418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_CORE 0x1FF11418u //! Register Reset Value #define IDM3_IA_CORE_RST 0x000050C5000C0001u //! Field REV_CODE - rev_code #define IDM3_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IDM3_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IDM3_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IDM3_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IDM3_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IDM3_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IDM3_IA_AGENT_CONTROL Register IDM3_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IDM3_IA_AGENT_CONTROL 0x11420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_AGENT_CONTROL 0x1FF11420u //! Register Reset Value #define IDM3_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM3_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM3_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IDM3_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IDM3_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IDM3_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM3_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IDM3_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM3_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IDM3_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IDM3_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM3_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM3_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM3_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM3_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM3_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM3_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM3_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM3_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM3_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM3_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM3_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM3_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IDM3_IA_AGENT_STATUS Register IDM3_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IDM3_IA_AGENT_STATUS 0x11428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_AGENT_STATUS 0x1FF11428u //! Register Reset Value #define IDM3_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM3_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM3_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IDM3_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IDM3_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IDM3_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IDM3_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IDM3_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IDM3_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IDM3_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IDM3_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IDM3_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM3_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IDM3_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IDM3_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IDM3_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM3_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IDM3_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IDM3_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM3_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM3_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM3_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM3_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IDM3_IA_ERROR_LOG Register IDM3_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IDM3_IA_ERROR_LOG 0x11458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_ERROR_LOG 0x1FF11458u //! Register Reset Value #define IDM3_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IDM3_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IDM3_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IDM3_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IDM3_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IDM3_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IDM3_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IDM3_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IDM3_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IDM3_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IDM3_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IDM3_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IDM3_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IDM3_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IDM3_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IDM3_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IDM3_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IDM3_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IDM3_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IDM3_IA_ERROR_LOG_ADDR Register IDM3_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IDM3_IA_ERROR_LOG_ADDR 0x11460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_ERROR_LOG_ADDR 0x1FF11460u //! Register Reset Value #define IDM3_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IDM3_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IDM3_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IDM3_IA_CORE_FLAG Register IDM3_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IDM3_IA_CORE_FLAG 0x11468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_CORE_FLAG 0x1FF11468u //! Register Reset Value #define IDM3_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IDM3_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IDM3_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IDM3_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IDM3_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IDM3_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IDM3_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IDM3_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IDM3_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IDM3_IA_ADDR_FILL_IN Register IDM3_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IDM3_IA_ADDR_FILL_IN 0x11470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_ADDR_FILL_IN 0x1FF11470u //! Register Reset Value #define IDM3_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IDM3_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IDM3_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IDM3_IA_BANDWIDTH_0 Register IDM3_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_0 0x11500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_0 0x1FF11500u //! Register Reset Value #define IDM3_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IDM3_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_1 Register IDM3_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_1 0x11508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_1 0x1FF11508u //! Register Reset Value #define IDM3_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IDM3_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_2 Register IDM3_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_2 0x11510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_2 0x1FF11510u //! Register Reset Value #define IDM3_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IDM3_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_3 Register IDM3_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_3 0x11518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_3 0x1FF11518u //! Register Reset Value #define IDM3_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IDM3_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_4 Register IDM3_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_4 0x11520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_4 0x1FF11520u //! Register Reset Value #define IDM3_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IDM3_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_5 Register IDM3_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_5 0x11528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_5 0x1FF11528u //! Register Reset Value #define IDM3_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IDM3_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_6 Register IDM3_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_6 0x11530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_6 0x1FF11530u //! Register Reset Value #define IDM3_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IDM3_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IDM3_IA_BANDWIDTH_7 Register IDM3_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IDM3_IA_BANDWIDTH_7 0x11538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM3_IA_BANDWIDTH_7 0x1FF11538u //! Register Reset Value #define IDM3_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IDM3_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_COMPONENT Register IDM4_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IDM4_IA_COMPONENT 0x11800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_COMPONENT 0x1FF11800u //! Register Reset Value #define IDM4_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IDM4_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IDM4_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IDM4_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IDM4_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IDM4_IA_CORE Register IDM4_IA_CORE - core //! @{ //! Register Offset (relative) #define IDM4_IA_CORE 0x11818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_CORE 0x1FF11818u //! Register Reset Value #define IDM4_IA_CORE_RST 0x000050C5000D0001u //! Field REV_CODE - rev_code #define IDM4_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IDM4_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IDM4_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IDM4_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IDM4_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IDM4_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IDM4_IA_AGENT_CONTROL Register IDM4_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IDM4_IA_AGENT_CONTROL 0x11820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_AGENT_CONTROL 0x1FF11820u //! Register Reset Value #define IDM4_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM4_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM4_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IDM4_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IDM4_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IDM4_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM4_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IDM4_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM4_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IDM4_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IDM4_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM4_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IDM4_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM4_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IDM4_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM4_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IDM4_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM4_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IDM4_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM4_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IDM4_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM4_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IDM4_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IDM4_IA_AGENT_STATUS Register IDM4_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IDM4_IA_AGENT_STATUS 0x11828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_AGENT_STATUS 0x1FF11828u //! Register Reset Value #define IDM4_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IDM4_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IDM4_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IDM4_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IDM4_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IDM4_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IDM4_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IDM4_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IDM4_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IDM4_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IDM4_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IDM4_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IDM4_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IDM4_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IDM4_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IDM4_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IDM4_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IDM4_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IDM4_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM4_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IDM4_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM4_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IDM4_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IDM4_IA_ERROR_LOG Register IDM4_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IDM4_IA_ERROR_LOG 0x11858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_ERROR_LOG 0x1FF11858u //! Register Reset Value #define IDM4_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IDM4_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IDM4_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IDM4_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IDM4_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IDM4_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IDM4_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IDM4_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IDM4_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IDM4_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IDM4_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IDM4_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IDM4_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IDM4_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IDM4_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IDM4_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IDM4_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IDM4_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IDM4_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IDM4_IA_ERROR_LOG_ADDR Register IDM4_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IDM4_IA_ERROR_LOG_ADDR 0x11860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_ERROR_LOG_ADDR 0x1FF11860u //! Register Reset Value #define IDM4_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IDM4_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IDM4_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IDM4_IA_CORE_FLAG Register IDM4_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IDM4_IA_CORE_FLAG 0x11868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_CORE_FLAG 0x1FF11868u //! Register Reset Value #define IDM4_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IDM4_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IDM4_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IDM4_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IDM4_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IDM4_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IDM4_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IDM4_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IDM4_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IDM4_IA_ADDR_FILL_IN Register IDM4_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IDM4_IA_ADDR_FILL_IN 0x11870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_ADDR_FILL_IN 0x1FF11870u //! Register Reset Value #define IDM4_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IDM4_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IDM4_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IDM4_IA_BANDWIDTH_0 Register IDM4_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_0 0x11900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_0 0x1FF11900u //! Register Reset Value #define IDM4_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IDM4_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_1 Register IDM4_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_1 0x11908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_1 0x1FF11908u //! Register Reset Value #define IDM4_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IDM4_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_2 Register IDM4_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_2 0x11910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_2 0x1FF11910u //! Register Reset Value #define IDM4_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IDM4_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_3 Register IDM4_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_3 0x11918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_3 0x1FF11918u //! Register Reset Value #define IDM4_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IDM4_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_4 Register IDM4_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_4 0x11920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_4 0x1FF11920u //! Register Reset Value #define IDM4_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IDM4_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_5 Register IDM4_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_5 0x11928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_5 0x1FF11928u //! Register Reset Value #define IDM4_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IDM4_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_6 Register IDM4_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_6 0x11930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_6 0x1FF11930u //! Register Reset Value #define IDM4_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IDM4_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IDM4_IA_BANDWIDTH_7 Register IDM4_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IDM4_IA_BANDWIDTH_7 0x11938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IDM4_IA_BANDWIDTH_7 0x1FF11938u //! Register Reset Value #define IDM4_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IDM4_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_COMPONENT Register ILN10_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define ILN10_IA_COMPONENT 0x11C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_COMPONENT 0x1FF11C00u //! Register Reset Value #define ILN10_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define ILN10_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define ILN10_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define ILN10_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define ILN10_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup ILN10_IA_CORE Register ILN10_IA_CORE - core //! @{ //! Register Offset (relative) #define ILN10_IA_CORE 0x11C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_CORE 0x1FF11C18u //! Register Reset Value #define ILN10_IA_CORE_RST 0x000050C50F010001u //! Field REV_CODE - rev_code #define ILN10_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define ILN10_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define ILN10_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define ILN10_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define ILN10_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define ILN10_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup ILN10_IA_AGENT_CONTROL Register ILN10_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define ILN10_IA_AGENT_CONTROL 0x11C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_AGENT_CONTROL 0x1FF11C20u //! Register Reset Value #define ILN10_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN10_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN10_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define ILN10_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define ILN10_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define ILN10_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN10_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define ILN10_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN10_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define ILN10_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define ILN10_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN10_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN10_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN10_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN10_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN10_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN10_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN10_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN10_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN10_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN10_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN10_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN10_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup ILN10_IA_AGENT_STATUS Register ILN10_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define ILN10_IA_AGENT_STATUS 0x11C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_AGENT_STATUS 0x1FF11C28u //! Register Reset Value #define ILN10_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN10_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN10_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define ILN10_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define ILN10_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define ILN10_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define ILN10_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define ILN10_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define ILN10_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define ILN10_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define ILN10_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define ILN10_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN10_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define ILN10_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define ILN10_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define ILN10_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN10_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define ILN10_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define ILN10_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN10_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN10_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN10_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN10_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup ILN10_IA_ERROR_LOG Register ILN10_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define ILN10_IA_ERROR_LOG 0x11C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_ERROR_LOG 0x1FF11C58u //! Register Reset Value #define ILN10_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define ILN10_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define ILN10_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define ILN10_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define ILN10_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define ILN10_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define ILN10_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define ILN10_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define ILN10_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define ILN10_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define ILN10_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define ILN10_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define ILN10_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define ILN10_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define ILN10_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define ILN10_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define ILN10_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define ILN10_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define ILN10_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup ILN10_IA_ERROR_LOG_ADDR Register ILN10_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define ILN10_IA_ERROR_LOG_ADDR 0x11C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_ERROR_LOG_ADDR 0x1FF11C60u //! Register Reset Value #define ILN10_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define ILN10_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define ILN10_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup ILN10_IA_CORE_FLAG Register ILN10_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define ILN10_IA_CORE_FLAG 0x11C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_CORE_FLAG 0x1FF11C68u //! Register Reset Value #define ILN10_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define ILN10_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define ILN10_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define ILN10_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define ILN10_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define ILN10_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define ILN10_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define ILN10_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define ILN10_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup ILN10_IA_ADDR_FILL_IN Register ILN10_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define ILN10_IA_ADDR_FILL_IN 0x11C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_ADDR_FILL_IN 0x1FF11C70u //! Register Reset Value #define ILN10_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define ILN10_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define ILN10_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup ILN10_IA_BANDWIDTH_0 Register ILN10_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_0 0x11D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_0 0x1FF11D00u //! Register Reset Value #define ILN10_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define ILN10_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_1 Register ILN10_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_1 0x11D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_1 0x1FF11D08u //! Register Reset Value #define ILN10_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define ILN10_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_2 Register ILN10_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_2 0x11D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_2 0x1FF11D10u //! Register Reset Value #define ILN10_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define ILN10_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_3 Register ILN10_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_3 0x11D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_3 0x1FF11D18u //! Register Reset Value #define ILN10_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define ILN10_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_4 Register ILN10_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_4 0x11D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_4 0x1FF11D20u //! Register Reset Value #define ILN10_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define ILN10_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_5 Register ILN10_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_5 0x11D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_5 0x1FF11D28u //! Register Reset Value #define ILN10_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define ILN10_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_6 Register ILN10_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_6 0x11D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_6 0x1FF11D30u //! Register Reset Value #define ILN10_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define ILN10_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup ILN10_IA_BANDWIDTH_7 Register ILN10_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define ILN10_IA_BANDWIDTH_7 0x11D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN10_IA_BANDWIDTH_7 0x1FF11D38u //! Register Reset Value #define ILN10_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define ILN10_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_COMPONENT Register ILN20_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define ILN20_IA_COMPONENT 0x12000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_COMPONENT 0x1FF12000u //! Register Reset Value #define ILN20_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define ILN20_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define ILN20_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define ILN20_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define ILN20_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup ILN20_IA_CORE Register ILN20_IA_CORE - core //! @{ //! Register Offset (relative) #define ILN20_IA_CORE 0x12018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_CORE 0x1FF12018u //! Register Reset Value #define ILN20_IA_CORE_RST 0x000050C50F020001u //! Field REV_CODE - rev_code #define ILN20_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define ILN20_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define ILN20_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define ILN20_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define ILN20_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define ILN20_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup ILN20_IA_AGENT_CONTROL Register ILN20_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define ILN20_IA_AGENT_CONTROL 0x12020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_AGENT_CONTROL 0x1FF12020u //! Register Reset Value #define ILN20_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN20_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN20_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define ILN20_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define ILN20_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define ILN20_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN20_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define ILN20_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN20_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define ILN20_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define ILN20_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN20_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN20_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN20_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN20_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN20_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN20_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN20_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN20_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN20_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN20_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN20_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN20_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup ILN20_IA_AGENT_STATUS Register ILN20_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define ILN20_IA_AGENT_STATUS 0x12028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_AGENT_STATUS 0x1FF12028u //! Register Reset Value #define ILN20_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN20_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN20_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define ILN20_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define ILN20_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define ILN20_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define ILN20_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define ILN20_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define ILN20_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define ILN20_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define ILN20_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define ILN20_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN20_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define ILN20_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define ILN20_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define ILN20_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN20_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define ILN20_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define ILN20_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN20_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN20_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN20_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN20_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup ILN20_IA_ERROR_LOG Register ILN20_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define ILN20_IA_ERROR_LOG 0x12058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_ERROR_LOG 0x1FF12058u //! Register Reset Value #define ILN20_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define ILN20_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define ILN20_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define ILN20_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define ILN20_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define ILN20_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define ILN20_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define ILN20_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define ILN20_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define ILN20_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define ILN20_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define ILN20_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define ILN20_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define ILN20_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define ILN20_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define ILN20_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define ILN20_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define ILN20_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define ILN20_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup ILN20_IA_ERROR_LOG_ADDR Register ILN20_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define ILN20_IA_ERROR_LOG_ADDR 0x12060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_ERROR_LOG_ADDR 0x1FF12060u //! Register Reset Value #define ILN20_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define ILN20_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define ILN20_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup ILN20_IA_CORE_FLAG Register ILN20_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define ILN20_IA_CORE_FLAG 0x12068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_CORE_FLAG 0x1FF12068u //! Register Reset Value #define ILN20_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define ILN20_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define ILN20_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define ILN20_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define ILN20_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define ILN20_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define ILN20_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define ILN20_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define ILN20_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup ILN20_IA_ADDR_FILL_IN Register ILN20_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define ILN20_IA_ADDR_FILL_IN 0x12070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_ADDR_FILL_IN 0x1FF12070u //! Register Reset Value #define ILN20_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define ILN20_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define ILN20_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup ILN20_IA_BANDWIDTH_0 Register ILN20_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_0 0x12100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_0 0x1FF12100u //! Register Reset Value #define ILN20_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define ILN20_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_1 Register ILN20_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_1 0x12108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_1 0x1FF12108u //! Register Reset Value #define ILN20_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define ILN20_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_2 Register ILN20_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_2 0x12110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_2 0x1FF12110u //! Register Reset Value #define ILN20_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define ILN20_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_3 Register ILN20_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_3 0x12118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_3 0x1FF12118u //! Register Reset Value #define ILN20_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define ILN20_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_4 Register ILN20_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_4 0x12120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_4 0x1FF12120u //! Register Reset Value #define ILN20_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define ILN20_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_5 Register ILN20_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_5 0x12128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_5 0x1FF12128u //! Register Reset Value #define ILN20_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define ILN20_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_6 Register ILN20_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_6 0x12130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_6 0x1FF12130u //! Register Reset Value #define ILN20_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define ILN20_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup ILN20_IA_BANDWIDTH_7 Register ILN20_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define ILN20_IA_BANDWIDTH_7 0x12138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN20_IA_BANDWIDTH_7 0x1FF12138u //! Register Reset Value #define ILN20_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define ILN20_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_COMPONENT Register ILN30_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define ILN30_IA_COMPONENT 0x12400 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_COMPONENT 0x1FF12400u //! Register Reset Value #define ILN30_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define ILN30_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define ILN30_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define ILN30_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define ILN30_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup ILN30_IA_CORE Register ILN30_IA_CORE - core //! @{ //! Register Offset (relative) #define ILN30_IA_CORE 0x12418 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_CORE 0x1FF12418u //! Register Reset Value #define ILN30_IA_CORE_RST 0x000050C50F030001u //! Field REV_CODE - rev_code #define ILN30_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define ILN30_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define ILN30_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define ILN30_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define ILN30_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define ILN30_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup ILN30_IA_AGENT_CONTROL Register ILN30_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define ILN30_IA_AGENT_CONTROL 0x12420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_AGENT_CONTROL 0x1FF12420u //! Register Reset Value #define ILN30_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN30_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN30_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define ILN30_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define ILN30_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define ILN30_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN30_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define ILN30_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN30_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define ILN30_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define ILN30_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN30_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN30_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN30_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN30_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN30_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN30_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN30_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN30_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN30_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN30_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN30_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN30_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup ILN30_IA_AGENT_STATUS Register ILN30_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define ILN30_IA_AGENT_STATUS 0x12428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_AGENT_STATUS 0x1FF12428u //! Register Reset Value #define ILN30_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN30_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN30_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define ILN30_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define ILN30_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define ILN30_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define ILN30_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define ILN30_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define ILN30_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define ILN30_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define ILN30_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define ILN30_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN30_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define ILN30_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define ILN30_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define ILN30_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN30_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define ILN30_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define ILN30_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN30_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN30_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN30_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN30_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup ILN30_IA_ERROR_LOG Register ILN30_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define ILN30_IA_ERROR_LOG 0x12458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_ERROR_LOG 0x1FF12458u //! Register Reset Value #define ILN30_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define ILN30_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define ILN30_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define ILN30_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define ILN30_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define ILN30_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define ILN30_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define ILN30_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define ILN30_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define ILN30_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define ILN30_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define ILN30_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define ILN30_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define ILN30_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define ILN30_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define ILN30_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define ILN30_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define ILN30_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define ILN30_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup ILN30_IA_ERROR_LOG_ADDR Register ILN30_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define ILN30_IA_ERROR_LOG_ADDR 0x12460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_ERROR_LOG_ADDR 0x1FF12460u //! Register Reset Value #define ILN30_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define ILN30_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define ILN30_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup ILN30_IA_CORE_FLAG Register ILN30_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define ILN30_IA_CORE_FLAG 0x12468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_CORE_FLAG 0x1FF12468u //! Register Reset Value #define ILN30_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define ILN30_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define ILN30_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define ILN30_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define ILN30_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define ILN30_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define ILN30_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define ILN30_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define ILN30_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup ILN30_IA_ADDR_FILL_IN Register ILN30_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define ILN30_IA_ADDR_FILL_IN 0x12470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_ADDR_FILL_IN 0x1FF12470u //! Register Reset Value #define ILN30_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define ILN30_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define ILN30_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup ILN30_IA_BANDWIDTH_0 Register ILN30_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_0 0x12500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_0 0x1FF12500u //! Register Reset Value #define ILN30_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define ILN30_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_1 Register ILN30_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_1 0x12508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_1 0x1FF12508u //! Register Reset Value #define ILN30_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define ILN30_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_2 Register ILN30_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_2 0x12510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_2 0x1FF12510u //! Register Reset Value #define ILN30_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define ILN30_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_3 Register ILN30_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_3 0x12518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_3 0x1FF12518u //! Register Reset Value #define ILN30_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define ILN30_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_4 Register ILN30_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_4 0x12520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_4 0x1FF12520u //! Register Reset Value #define ILN30_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define ILN30_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_5 Register ILN30_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_5 0x12528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_5 0x1FF12528u //! Register Reset Value #define ILN30_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define ILN30_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_6 Register ILN30_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_6 0x12530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_6 0x1FF12530u //! Register Reset Value #define ILN30_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define ILN30_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup ILN30_IA_BANDWIDTH_7 Register ILN30_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define ILN30_IA_BANDWIDTH_7 0x12538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN30_IA_BANDWIDTH_7 0x1FF12538u //! Register Reset Value #define ILN30_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define ILN30_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_COMPONENT Register IEX50_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define IEX50_IA_COMPONENT 0x12800 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_COMPONENT 0x1FF12800u //! Register Reset Value #define IEX50_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define IEX50_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define IEX50_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define IEX50_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define IEX50_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup IEX50_IA_CORE Register IEX50_IA_CORE - core //! @{ //! Register Offset (relative) #define IEX50_IA_CORE 0x12818 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_CORE 0x1FF12818u //! Register Reset Value #define IEX50_IA_CORE_RST 0x0000CAFE0F050000u //! Field REV_CODE - rev_code #define IEX50_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define IEX50_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define IEX50_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define IEX50_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define IEX50_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define IEX50_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup IEX50_IA_AGENT_CONTROL Register IEX50_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define IEX50_IA_AGENT_CONTROL 0x12820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_AGENT_CONTROL 0x1FF12820u //! Register Reset Value #define IEX50_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IEX50_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IEX50_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define IEX50_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define IEX50_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define IEX50_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IEX50_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define IEX50_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IEX50_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define IEX50_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define IEX50_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IEX50_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define IEX50_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IEX50_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define IEX50_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IEX50_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define IEX50_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IEX50_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define IEX50_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IEX50_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define IEX50_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IEX50_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define IEX50_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup IEX50_IA_AGENT_STATUS Register IEX50_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define IEX50_IA_AGENT_STATUS 0x12828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_AGENT_STATUS 0x1FF12828u //! Register Reset Value #define IEX50_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define IEX50_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define IEX50_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define IEX50_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define IEX50_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define IEX50_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define IEX50_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define IEX50_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define IEX50_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define IEX50_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define IEX50_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define IEX50_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define IEX50_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define IEX50_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define IEX50_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define IEX50_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define IEX50_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define IEX50_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define IEX50_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IEX50_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define IEX50_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IEX50_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define IEX50_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup IEX50_IA_ERROR_LOG Register IEX50_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define IEX50_IA_ERROR_LOG 0x12858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_ERROR_LOG 0x1FF12858u //! Register Reset Value #define IEX50_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define IEX50_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define IEX50_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define IEX50_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define IEX50_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define IEX50_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define IEX50_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define IEX50_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define IEX50_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define IEX50_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define IEX50_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define IEX50_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define IEX50_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define IEX50_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define IEX50_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define IEX50_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define IEX50_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define IEX50_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define IEX50_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup IEX50_IA_ERROR_LOG_ADDR Register IEX50_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define IEX50_IA_ERROR_LOG_ADDR 0x12860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_ERROR_LOG_ADDR 0x1FF12860u //! Register Reset Value #define IEX50_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define IEX50_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define IEX50_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup IEX50_IA_CORE_FLAG Register IEX50_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define IEX50_IA_CORE_FLAG 0x12868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_CORE_FLAG 0x1FF12868u //! Register Reset Value #define IEX50_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define IEX50_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define IEX50_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define IEX50_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define IEX50_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define IEX50_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define IEX50_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define IEX50_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define IEX50_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup IEX50_IA_ADDR_FILL_IN Register IEX50_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define IEX50_IA_ADDR_FILL_IN 0x12870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_ADDR_FILL_IN 0x1FF12870u //! Register Reset Value #define IEX50_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define IEX50_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define IEX50_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup IEX50_IA_BANDWIDTH_0 Register IEX50_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_0 0x12900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_0 0x1FF12900u //! Register Reset Value #define IEX50_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define IEX50_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_1 Register IEX50_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_1 0x12908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_1 0x1FF12908u //! Register Reset Value #define IEX50_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define IEX50_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_2 Register IEX50_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_2 0x12910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_2 0x1FF12910u //! Register Reset Value #define IEX50_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define IEX50_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_3 Register IEX50_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_3 0x12918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_3 0x1FF12918u //! Register Reset Value #define IEX50_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define IEX50_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_4 Register IEX50_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_4 0x12920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_4 0x1FF12920u //! Register Reset Value #define IEX50_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define IEX50_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_5 Register IEX50_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_5 0x12928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_5 0x1FF12928u //! Register Reset Value #define IEX50_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define IEX50_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_6 Register IEX50_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_6 0x12930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_6 0x1FF12930u //! Register Reset Value #define IEX50_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define IEX50_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup IEX50_IA_BANDWIDTH_7 Register IEX50_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define IEX50_IA_BANDWIDTH_7 0x12938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_IEX50_IA_BANDWIDTH_7 0x1FF12938u //! Register Reset Value #define IEX50_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define IEX50_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_COMPONENT Register ILN60_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define ILN60_IA_COMPONENT 0x12C00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_COMPONENT 0x1FF12C00u //! Register Reset Value #define ILN60_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define ILN60_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define ILN60_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define ILN60_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define ILN60_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup ILN60_IA_CORE Register ILN60_IA_CORE - core //! @{ //! Register Offset (relative) #define ILN60_IA_CORE 0x12C18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_CORE 0x1FF12C18u //! Register Reset Value #define ILN60_IA_CORE_RST 0x000050C50F060001u //! Field REV_CODE - rev_code #define ILN60_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define ILN60_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define ILN60_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define ILN60_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define ILN60_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define ILN60_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup ILN60_IA_AGENT_CONTROL Register ILN60_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define ILN60_IA_AGENT_CONTROL 0x12C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_AGENT_CONTROL 0x1FF12C20u //! Register Reset Value #define ILN60_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN60_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN60_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define ILN60_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define ILN60_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define ILN60_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN60_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define ILN60_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN60_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define ILN60_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define ILN60_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN60_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ILN60_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN60_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ILN60_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN60_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ILN60_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN60_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ILN60_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN60_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ILN60_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN60_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ILN60_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup ILN60_IA_AGENT_STATUS Register ILN60_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define ILN60_IA_AGENT_STATUS 0x12C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_AGENT_STATUS 0x1FF12C28u //! Register Reset Value #define ILN60_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ILN60_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ILN60_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define ILN60_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define ILN60_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define ILN60_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define ILN60_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define ILN60_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define ILN60_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define ILN60_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define ILN60_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define ILN60_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ILN60_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define ILN60_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define ILN60_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define ILN60_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ILN60_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define ILN60_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define ILN60_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN60_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ILN60_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN60_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ILN60_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup ILN60_IA_ERROR_LOG Register ILN60_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define ILN60_IA_ERROR_LOG 0x12C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_ERROR_LOG 0x1FF12C58u //! Register Reset Value #define ILN60_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define ILN60_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define ILN60_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define ILN60_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define ILN60_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define ILN60_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define ILN60_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define ILN60_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define ILN60_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define ILN60_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define ILN60_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define ILN60_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define ILN60_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define ILN60_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define ILN60_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define ILN60_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define ILN60_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define ILN60_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define ILN60_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup ILN60_IA_ERROR_LOG_ADDR Register ILN60_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define ILN60_IA_ERROR_LOG_ADDR 0x12C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_ERROR_LOG_ADDR 0x1FF12C60u //! Register Reset Value #define ILN60_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define ILN60_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define ILN60_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup ILN60_IA_CORE_FLAG Register ILN60_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define ILN60_IA_CORE_FLAG 0x12C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_CORE_FLAG 0x1FF12C68u //! Register Reset Value #define ILN60_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define ILN60_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define ILN60_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define ILN60_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define ILN60_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define ILN60_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define ILN60_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define ILN60_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define ILN60_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup ILN60_IA_ADDR_FILL_IN Register ILN60_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define ILN60_IA_ADDR_FILL_IN 0x12C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_ADDR_FILL_IN 0x1FF12C70u //! Register Reset Value #define ILN60_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define ILN60_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define ILN60_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup ILN60_IA_BANDWIDTH_0 Register ILN60_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_0 0x12D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_0 0x1FF12D00u //! Register Reset Value #define ILN60_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define ILN60_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_1 Register ILN60_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_1 0x12D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_1 0x1FF12D08u //! Register Reset Value #define ILN60_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define ILN60_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_2 Register ILN60_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_2 0x12D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_2 0x1FF12D10u //! Register Reset Value #define ILN60_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define ILN60_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_3 Register ILN60_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_3 0x12D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_3 0x1FF12D18u //! Register Reset Value #define ILN60_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define ILN60_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_4 Register ILN60_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_4 0x12D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_4 0x1FF12D20u //! Register Reset Value #define ILN60_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define ILN60_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_5 Register ILN60_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_5 0x12D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_5 0x1FF12D28u //! Register Reset Value #define ILN60_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define ILN60_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_6 Register ILN60_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_6 0x12D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_6 0x1FF12D30u //! Register Reset Value #define ILN60_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define ILN60_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup ILN60_IA_BANDWIDTH_7 Register ILN60_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define ILN60_IA_BANDWIDTH_7 0x12D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ILN60_IA_BANDWIDTH_7 0x1FF12D38u //! Register Reset Value #define ILN60_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define ILN60_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_COMPONENT Register ITOE_IA_COMPONENT - component //! @{ //! Register Offset (relative) #define ITOE_IA_COMPONENT 0x13000 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_COMPONENT 0x1FF13000u //! Register Reset Value #define ITOE_IA_COMPONENT_RST 0x0000000060103532u //! Field REV - rev #define ITOE_IA_COMPONENT_REV_POS 0 //! Field REV - rev #define ITOE_IA_COMPONENT_REV_MASK 0xFFFFu //! Field CODE - code #define ITOE_IA_COMPONENT_CODE_POS 16 //! Field CODE - code #define ITOE_IA_COMPONENT_CODE_MASK 0xFFFF0000u //! @} //! \defgroup ITOE_IA_CORE Register ITOE_IA_CORE - core //! @{ //! Register Offset (relative) #define ITOE_IA_CORE 0x13018 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_CORE 0x1FF13018u //! Register Reset Value #define ITOE_IA_CORE_RST 0x000050C500070001u //! Field REV_CODE - rev_code #define ITOE_IA_CORE_REV_CODE_POS 0 //! Field REV_CODE - rev_code #define ITOE_IA_CORE_REV_CODE_MASK 0xFFFFu //! Field CORE_CODE - core_code #define ITOE_IA_CORE_CORE_CODE_POS 16 //! Field CORE_CODE - core_code #define ITOE_IA_CORE_CORE_CODE_MASK 0xFFFF0000u //! Field VENDOR_CODE - vendor_code #define ITOE_IA_CORE_VENDOR_CODE_POS 32 //! Field VENDOR_CODE - vendor_code #define ITOE_IA_CORE_VENDOR_CODE_MASK 0xFFFF00000000u //! @} //! \defgroup ITOE_IA_AGENT_CONTROL Register ITOE_IA_AGENT_CONTROL - agent_control //! @{ //! Register Offset (relative) #define ITOE_IA_AGENT_CONTROL 0x13020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_AGENT_CONTROL 0x1FF13020u //! Register Reset Value #define ITOE_IA_AGENT_CONTROL_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ITOE_IA_AGENT_CONTROL_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ITOE_IA_AGENT_CONTROL_CORE_RESET_MASK 0x1u //! Field REJECT - reject #define ITOE_IA_AGENT_CONTROL_REJECT_POS 4 //! Field REJECT - reject #define ITOE_IA_AGENT_CONTROL_REJECT_MASK 0x10u //! Field RESP_TIMEOUT - resp_timeout #define ITOE_IA_AGENT_CONTROL_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ITOE_IA_AGENT_CONTROL_RESP_TIMEOUT_MASK 0x700u //! Field BURST_TIMEOUT - burst_timeout #define ITOE_IA_AGENT_CONTROL_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ITOE_IA_AGENT_CONTROL_BURST_TIMEOUT_MASK 0x70000u //! Field MERROR_REP - merror_rep #define ITOE_IA_AGENT_CONTROL_MERROR_REP_POS 24 //! Field MERROR_REP - merror_rep #define ITOE_IA_AGENT_CONTROL_MERROR_REP_MASK 0x1000000u //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ITOE_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_POS 25 //! Field RESP_TIMEOUT_REP - resp_timeout_rep #define ITOE_IA_AGENT_CONTROL_RESP_TIMEOUT_REP_MASK 0x2000000u //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ITOE_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_POS 26 //! Field BURST_TIMEOUT_REP - burst_timeout_rep #define ITOE_IA_AGENT_CONTROL_BURST_TIMEOUT_REP_MASK 0x4000000u //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ITOE_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_POS 27 //! Field ALL_INBAND_ERROR_REP - all_inband_error_rep #define ITOE_IA_AGENT_CONTROL_ALL_INBAND_ERROR_REP_MASK 0x8000000u //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ITOE_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_POS 28 //! Field INBAND_ERROR_PRIMARY_REP - inband_error_primary_rep #define ITOE_IA_AGENT_CONTROL_INBAND_ERROR_PRIMARY_REP_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ITOE_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_POS 29 //! Field INBAND_ERROR_SECONDARY_REP - inband_error_secondary_rep #define ITOE_IA_AGENT_CONTROL_INBAND_ERROR_SECONDARY_REP_MASK 0x20000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ITOE_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define ITOE_IA_AGENT_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup ITOE_IA_AGENT_STATUS Register ITOE_IA_AGENT_STATUS - agent_status //! @{ //! Register Offset (relative) #define ITOE_IA_AGENT_STATUS 0x13028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_AGENT_STATUS 0x1FF13028u //! Register Reset Value #define ITOE_IA_AGENT_STATUS_RST 0x0000000000000000u //! Field CORE_RESET - core_reset #define ITOE_IA_AGENT_STATUS_CORE_RESET_POS 0 //! Field CORE_RESET - core_reset #define ITOE_IA_AGENT_STATUS_CORE_RESET_MASK 0x1u //! Field REQ_ACTIVE - req_active #define ITOE_IA_AGENT_STATUS_REQ_ACTIVE_POS 4 //! Field REQ_ACTIVE - req_active #define ITOE_IA_AGENT_STATUS_REQ_ACTIVE_MASK 0x10u //! Field RESP_WAITING - resp_waiting #define ITOE_IA_AGENT_STATUS_RESP_WAITING_POS 5 //! Field RESP_WAITING - resp_waiting #define ITOE_IA_AGENT_STATUS_RESP_WAITING_MASK 0x20u //! Field BURST - burst #define ITOE_IA_AGENT_STATUS_BURST_POS 6 //! Field BURST - burst #define ITOE_IA_AGENT_STATUS_BURST_MASK 0x40u //! Field READEX - readex #define ITOE_IA_AGENT_STATUS_READEX_POS 7 //! Field READEX - readex #define ITOE_IA_AGENT_STATUS_READEX_MASK 0x80u //! Field RESP_TIMEOUT - resp_timeout #define ITOE_IA_AGENT_STATUS_RESP_TIMEOUT_POS 8 //! Field RESP_TIMEOUT - resp_timeout #define ITOE_IA_AGENT_STATUS_RESP_TIMEOUT_MASK 0x100u //! Field TIMEBASE - timebase #define ITOE_IA_AGENT_STATUS_TIMEBASE_POS 12 //! Field TIMEBASE - timebase #define ITOE_IA_AGENT_STATUS_TIMEBASE_MASK 0xF000u //! Field BURST_TIMEOUT - burst_timeout #define ITOE_IA_AGENT_STATUS_BURST_TIMEOUT_POS 16 //! Field BURST_TIMEOUT - burst_timeout #define ITOE_IA_AGENT_STATUS_BURST_TIMEOUT_MASK 0x10000u //! Field MERROR - merror #define ITOE_IA_AGENT_STATUS_MERROR_POS 24 //! Field MERROR - merror #define ITOE_IA_AGENT_STATUS_MERROR_MASK 0x1000000u //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ITOE_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_POS 28 //! Field INBAND_ERROR_PRIMARY - inband_error_primary #define ITOE_IA_AGENT_STATUS_INBAND_ERROR_PRIMARY_MASK 0x10000000u //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ITOE_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_POS 29 //! Field INBAND_ERROR_SECONDARY - inband_error_secondary #define ITOE_IA_AGENT_STATUS_INBAND_ERROR_SECONDARY_MASK 0x20000000u //! @} //! \defgroup ITOE_IA_ERROR_LOG Register ITOE_IA_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define ITOE_IA_ERROR_LOG 0x13058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_ERROR_LOG 0x1FF13058u //! Register Reset Value #define ITOE_IA_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define ITOE_IA_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define ITOE_IA_ERROR_LOG_CMD_MASK 0x7u //! Field INITID - initid #define ITOE_IA_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define ITOE_IA_ERROR_LOG_INITID_MASK 0xFF00u //! Field RFU0 - rfu0 #define ITOE_IA_ERROR_LOG_RFU0_POS 16 //! Field RFU0 - rfu0 #define ITOE_IA_ERROR_LOG_RFU0_MASK 0x30000u //! Field RFU1 - rfu1 #define ITOE_IA_ERROR_LOG_RFU1_POS 18 //! Field RFU1 - rfu1 #define ITOE_IA_ERROR_LOG_RFU1_MASK 0xC0000u //! Field RFU2 - rfu2 #define ITOE_IA_ERROR_LOG_RFU2_POS 20 //! Field RFU2 - rfu2 #define ITOE_IA_ERROR_LOG_RFU2_MASK 0xF00000u //! Field CODE - code #define ITOE_IA_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define ITOE_IA_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define ITOE_IA_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define ITOE_IA_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define ITOE_IA_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define ITOE_IA_ERROR_LOG_MULTI_MASK 0x80000000u //! Field REQ_INFO - req_info #define ITOE_IA_ERROR_LOG_REQ_INFO_POS 32 //! Field REQ_INFO - req_info #define ITOE_IA_ERROR_LOG_REQ_INFO_MASK 0xFFFFFFFF00000000u //! @} //! \defgroup ITOE_IA_ERROR_LOG_ADDR Register ITOE_IA_ERROR_LOG_ADDR - error_log_addr //! @{ //! Register Offset (relative) #define ITOE_IA_ERROR_LOG_ADDR 0x13060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_ERROR_LOG_ADDR 0x1FF13060u //! Register Reset Value #define ITOE_IA_ERROR_LOG_ADDR_RST 0x0000000000000000u //! Field ADDR - addr #define ITOE_IA_ERROR_LOG_ADDR_ADDR_POS 0 //! Field ADDR - addr #define ITOE_IA_ERROR_LOG_ADDR_ADDR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup ITOE_IA_CORE_FLAG Register ITOE_IA_CORE_FLAG - core_flag //! @{ //! Register Offset (relative) #define ITOE_IA_CORE_FLAG 0x13068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_CORE_FLAG 0x1FF13068u //! Register Reset Value #define ITOE_IA_CORE_FLAG_RST 0x0000000000000000u //! Field ENABLE_0 - enable_0 #define ITOE_IA_CORE_FLAG_ENABLE_0_POS 0 //! Field ENABLE_0 - enable_0 #define ITOE_IA_CORE_FLAG_ENABLE_0_MASK 0x1u //! Field ENABLE_1 - enable_1 #define ITOE_IA_CORE_FLAG_ENABLE_1_POS 1 //! Field ENABLE_1 - enable_1 #define ITOE_IA_CORE_FLAG_ENABLE_1_MASK 0x2u //! Field ENABLE_2 - enable_2 #define ITOE_IA_CORE_FLAG_ENABLE_2_POS 2 //! Field ENABLE_2 - enable_2 #define ITOE_IA_CORE_FLAG_ENABLE_2_MASK 0x4u //! Field ENABLE_3 - enable_3 #define ITOE_IA_CORE_FLAG_ENABLE_3_POS 3 //! Field ENABLE_3 - enable_3 #define ITOE_IA_CORE_FLAG_ENABLE_3_MASK 0x8u //! @} //! \defgroup ITOE_IA_ADDR_FILL_IN Register ITOE_IA_ADDR_FILL_IN - addr_fill_in //! @{ //! Register Offset (relative) #define ITOE_IA_ADDR_FILL_IN 0x13070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_ADDR_FILL_IN 0x1FF13070u //! Register Reset Value #define ITOE_IA_ADDR_FILL_IN_RST 0x0000000000000000u //! Field VALUE - value #define ITOE_IA_ADDR_FILL_IN_VALUE_POS 10 //! Field VALUE - value #define ITOE_IA_ADDR_FILL_IN_VALUE_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup ITOE_IA_BANDWIDTH_0 Register ITOE_IA_BANDWIDTH_0 - bandwidth_0 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_0 0x13100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_0 0x1FF13100u //! Register Reset Value #define ITOE_IA_BANDWIDTH_0_RST 0x0101010101010101u //! Field TARGET_GROUP_0 - target_group_0 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_0_POS 0 //! Field TARGET_GROUP_0 - target_group_0 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_0_MASK 0xFFu //! Field TARGET_GROUP_1 - target_group_1 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_1_POS 8 //! Field TARGET_GROUP_1 - target_group_1 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_1_MASK 0xFF00u //! Field TARGET_GROUP_2 - target_group_2 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_2_POS 16 //! Field TARGET_GROUP_2 - target_group_2 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_2_MASK 0xFF0000u //! Field TARGET_GROUP_3 - target_group_3 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_3_POS 24 //! Field TARGET_GROUP_3 - target_group_3 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_3_MASK 0xFF000000u //! Field TARGET_GROUP_4 - target_group_4 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_4_POS 32 //! Field TARGET_GROUP_4 - target_group_4 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_4_MASK 0xFF00000000u //! Field TARGET_GROUP_5 - target_group_5 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_5_POS 40 //! Field TARGET_GROUP_5 - target_group_5 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_5_MASK 0xFF0000000000u //! Field TARGET_GROUP_6 - target_group_6 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_6_POS 48 //! Field TARGET_GROUP_6 - target_group_6 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_6_MASK 0xFF000000000000u //! Field TARGET_GROUP_7 - target_group_7 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_7_POS 56 //! Field TARGET_GROUP_7 - target_group_7 #define ITOE_IA_BANDWIDTH_0_TARGET_GROUP_7_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_1 Register ITOE_IA_BANDWIDTH_1 - bandwidth_1 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_1 0x13108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_1 0x1FF13108u //! Register Reset Value #define ITOE_IA_BANDWIDTH_1_RST 0x0101010101010101u //! Field TARGET_GROUP_8 - target_group_8 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_8_POS 0 //! Field TARGET_GROUP_8 - target_group_8 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_8_MASK 0xFFu //! Field TARGET_GROUP_9 - target_group_9 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_9_POS 8 //! Field TARGET_GROUP_9 - target_group_9 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_9_MASK 0xFF00u //! Field TARGET_GROUP_10 - target_group_10 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_10_POS 16 //! Field TARGET_GROUP_10 - target_group_10 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_10_MASK 0xFF0000u //! Field TARGET_GROUP_11 - target_group_11 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_11_POS 24 //! Field TARGET_GROUP_11 - target_group_11 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_11_MASK 0xFF000000u //! Field TARGET_GROUP_12 - target_group_12 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_12_POS 32 //! Field TARGET_GROUP_12 - target_group_12 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_12_MASK 0xFF00000000u //! Field TARGET_GROUP_13 - target_group_13 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_13_POS 40 //! Field TARGET_GROUP_13 - target_group_13 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_13_MASK 0xFF0000000000u //! Field TARGET_GROUP_14 - target_group_14 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_14_POS 48 //! Field TARGET_GROUP_14 - target_group_14 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_14_MASK 0xFF000000000000u //! Field TARGET_GROUP_15 - target_group_15 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_15_POS 56 //! Field TARGET_GROUP_15 - target_group_15 #define ITOE_IA_BANDWIDTH_1_TARGET_GROUP_15_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_2 Register ITOE_IA_BANDWIDTH_2 - bandwidth_2 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_2 0x13110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_2 0x1FF13110u //! Register Reset Value #define ITOE_IA_BANDWIDTH_2_RST 0x0101010101010101u //! Field TARGET_GROUP_16 - target_group_16 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_16_POS 0 //! Field TARGET_GROUP_16 - target_group_16 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_16_MASK 0xFFu //! Field TARGET_GROUP_17 - target_group_17 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_17_POS 8 //! Field TARGET_GROUP_17 - target_group_17 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_17_MASK 0xFF00u //! Field TARGET_GROUP_18 - target_group_18 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_18_POS 16 //! Field TARGET_GROUP_18 - target_group_18 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_18_MASK 0xFF0000u //! Field TARGET_GROUP_19 - target_group_19 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_19_POS 24 //! Field TARGET_GROUP_19 - target_group_19 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_19_MASK 0xFF000000u //! Field TARGET_GROUP_20 - target_group_20 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_20_POS 32 //! Field TARGET_GROUP_20 - target_group_20 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_20_MASK 0xFF00000000u //! Field TARGET_GROUP_21 - target_group_21 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_21_POS 40 //! Field TARGET_GROUP_21 - target_group_21 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_21_MASK 0xFF0000000000u //! Field TARGET_GROUP_22 - target_group_22 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_22_POS 48 //! Field TARGET_GROUP_22 - target_group_22 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_22_MASK 0xFF000000000000u //! Field TARGET_GROUP_23 - target_group_23 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_23_POS 56 //! Field TARGET_GROUP_23 - target_group_23 #define ITOE_IA_BANDWIDTH_2_TARGET_GROUP_23_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_3 Register ITOE_IA_BANDWIDTH_3 - bandwidth_3 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_3 0x13118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_3 0x1FF13118u //! Register Reset Value #define ITOE_IA_BANDWIDTH_3_RST 0x0101010101010101u //! Field TARGET_GROUP_24 - target_group_24 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_24_POS 0 //! Field TARGET_GROUP_24 - target_group_24 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_24_MASK 0xFFu //! Field TARGET_GROUP_25 - target_group_25 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_25_POS 8 //! Field TARGET_GROUP_25 - target_group_25 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_25_MASK 0xFF00u //! Field TARGET_GROUP_26 - target_group_26 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_26_POS 16 //! Field TARGET_GROUP_26 - target_group_26 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_26_MASK 0xFF0000u //! Field TARGET_GROUP_27 - target_group_27 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_27_POS 24 //! Field TARGET_GROUP_27 - target_group_27 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_27_MASK 0xFF000000u //! Field TARGET_GROUP_28 - target_group_28 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_28_POS 32 //! Field TARGET_GROUP_28 - target_group_28 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_28_MASK 0xFF00000000u //! Field TARGET_GROUP_29 - target_group_29 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_29_POS 40 //! Field TARGET_GROUP_29 - target_group_29 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_29_MASK 0xFF0000000000u //! Field TARGET_GROUP_30 - target_group_30 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_30_POS 48 //! Field TARGET_GROUP_30 - target_group_30 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_30_MASK 0xFF000000000000u //! Field TARGET_GROUP_31 - target_group_31 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_31_POS 56 //! Field TARGET_GROUP_31 - target_group_31 #define ITOE_IA_BANDWIDTH_3_TARGET_GROUP_31_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_4 Register ITOE_IA_BANDWIDTH_4 - bandwidth_4 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_4 0x13120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_4 0x1FF13120u //! Register Reset Value #define ITOE_IA_BANDWIDTH_4_RST 0x0101010101010101u //! Field TARGET_GROUP_32 - target_group_32 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_32_POS 0 //! Field TARGET_GROUP_32 - target_group_32 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_32_MASK 0xFFu //! Field TARGET_GROUP_33 - target_group_33 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_33_POS 8 //! Field TARGET_GROUP_33 - target_group_33 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_33_MASK 0xFF00u //! Field TARGET_GROUP_34 - target_group_34 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_34_POS 16 //! Field TARGET_GROUP_34 - target_group_34 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_34_MASK 0xFF0000u //! Field TARGET_GROUP_35 - target_group_35 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_35_POS 24 //! Field TARGET_GROUP_35 - target_group_35 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_35_MASK 0xFF000000u //! Field TARGET_GROUP_36 - target_group_36 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_36_POS 32 //! Field TARGET_GROUP_36 - target_group_36 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_36_MASK 0xFF00000000u //! Field TARGET_GROUP_37 - target_group_37 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_37_POS 40 //! Field TARGET_GROUP_37 - target_group_37 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_37_MASK 0xFF0000000000u //! Field TARGET_GROUP_38 - target_group_38 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_38_POS 48 //! Field TARGET_GROUP_38 - target_group_38 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_38_MASK 0xFF000000000000u //! Field TARGET_GROUP_39 - target_group_39 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_39_POS 56 //! Field TARGET_GROUP_39 - target_group_39 #define ITOE_IA_BANDWIDTH_4_TARGET_GROUP_39_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_5 Register ITOE_IA_BANDWIDTH_5 - bandwidth_5 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_5 0x13128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_5 0x1FF13128u //! Register Reset Value #define ITOE_IA_BANDWIDTH_5_RST 0x0101010101010101u //! Field TARGET_GROUP_40 - target_group_40 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_40_POS 0 //! Field TARGET_GROUP_40 - target_group_40 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_40_MASK 0xFFu //! Field TARGET_GROUP_41 - target_group_41 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_41_POS 8 //! Field TARGET_GROUP_41 - target_group_41 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_41_MASK 0xFF00u //! Field TARGET_GROUP_42 - target_group_42 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_42_POS 16 //! Field TARGET_GROUP_42 - target_group_42 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_42_MASK 0xFF0000u //! Field TARGET_GROUP_43 - target_group_43 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_43_POS 24 //! Field TARGET_GROUP_43 - target_group_43 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_43_MASK 0xFF000000u //! Field TARGET_GROUP_44 - target_group_44 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_44_POS 32 //! Field TARGET_GROUP_44 - target_group_44 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_44_MASK 0xFF00000000u //! Field TARGET_GROUP_45 - target_group_45 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_45_POS 40 //! Field TARGET_GROUP_45 - target_group_45 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_45_MASK 0xFF0000000000u //! Field TARGET_GROUP_46 - target_group_46 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_46_POS 48 //! Field TARGET_GROUP_46 - target_group_46 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_46_MASK 0xFF000000000000u //! Field TARGET_GROUP_47 - target_group_47 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_47_POS 56 //! Field TARGET_GROUP_47 - target_group_47 #define ITOE_IA_BANDWIDTH_5_TARGET_GROUP_47_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_6 Register ITOE_IA_BANDWIDTH_6 - bandwidth_6 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_6 0x13130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_6 0x1FF13130u //! Register Reset Value #define ITOE_IA_BANDWIDTH_6_RST 0x0101010101010101u //! Field TARGET_GROUP_48 - target_group_48 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_48_POS 0 //! Field TARGET_GROUP_48 - target_group_48 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_48_MASK 0xFFu //! Field TARGET_GROUP_49 - target_group_49 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_49_POS 8 //! Field TARGET_GROUP_49 - target_group_49 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_49_MASK 0xFF00u //! Field TARGET_GROUP_50 - target_group_50 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_50_POS 16 //! Field TARGET_GROUP_50 - target_group_50 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_50_MASK 0xFF0000u //! Field TARGET_GROUP_51 - target_group_51 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_51_POS 24 //! Field TARGET_GROUP_51 - target_group_51 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_51_MASK 0xFF000000u //! Field TARGET_GROUP_52 - target_group_52 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_52_POS 32 //! Field TARGET_GROUP_52 - target_group_52 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_52_MASK 0xFF00000000u //! Field TARGET_GROUP_53 - target_group_53 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_53_POS 40 //! Field TARGET_GROUP_53 - target_group_53 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_53_MASK 0xFF0000000000u //! Field TARGET_GROUP_54 - target_group_54 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_54_POS 48 //! Field TARGET_GROUP_54 - target_group_54 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_54_MASK 0xFF000000000000u //! Field TARGET_GROUP_55 - target_group_55 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_55_POS 56 //! Field TARGET_GROUP_55 - target_group_55 #define ITOE_IA_BANDWIDTH_6_TARGET_GROUP_55_MASK 0xFF00000000000000u //! @} //! \defgroup ITOE_IA_BANDWIDTH_7 Register ITOE_IA_BANDWIDTH_7 - bandwidth_7 //! @{ //! Register Offset (relative) #define ITOE_IA_BANDWIDTH_7 0x13138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_ITOE_IA_BANDWIDTH_7 0x1FF13138u //! Register Reset Value #define ITOE_IA_BANDWIDTH_7_RST 0x0101010101010101u //! Field TARGET_GROUP_56 - target_group_56 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_56_POS 0 //! Field TARGET_GROUP_56 - target_group_56 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_56_MASK 0xFFu //! Field TARGET_GROUP_57 - target_group_57 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_57_POS 8 //! Field TARGET_GROUP_57 - target_group_57 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_57_MASK 0xFF00u //! Field TARGET_GROUP_58 - target_group_58 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_58_POS 16 //! Field TARGET_GROUP_58 - target_group_58 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_58_MASK 0xFF0000u //! Field TARGET_GROUP_59 - target_group_59 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_59_POS 24 //! Field TARGET_GROUP_59 - target_group_59 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_59_MASK 0xFF000000u //! Field TARGET_GROUP_60 - target_group_60 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_60_POS 32 //! Field TARGET_GROUP_60 - target_group_60 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_60_MASK 0xFF00000000u //! Field TARGET_GROUP_61 - target_group_61 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_61_POS 40 //! Field TARGET_GROUP_61 - target_group_61 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_61_MASK 0xFF0000000000u //! Field TARGET_GROUP_62 - target_group_62 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_62_POS 48 //! Field TARGET_GROUP_62 - target_group_62 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_62_MASK 0xFF000000000000u //! Field TARGET_GROUP_63 - target_group_63 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_63_POS 56 //! Field TARGET_GROUP_63 - target_group_63 #define ITOE_IA_BANDWIDTH_7_TARGET_GROUP_63_MASK 0xFF00000000000000u //! @} //! \defgroup TREG0_PM_ERROR_LOG Register TREG0_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TREG0_PM_ERROR_LOG 0x80020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ERROR_LOG 0x1FF80020u //! Register Reset Value #define TREG0_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TREG0_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TREG0_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TREG0_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TREG0_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TREG0_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TREG0_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TREG0_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TREG0_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TREG0_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TREG0_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TREG0_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TREG0_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TREG0_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TREG0_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TREG0_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TREG0_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TREG0_PM_CONTROL Register TREG0_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TREG0_PM_CONTROL 0x80028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_CONTROL 0x1FF80028u //! Register Reset Value #define TREG0_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TREG0_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TREG0_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TREG0_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TREG0_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TREG0_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TREG0_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TREG0_PM_ERROR_CLEAR_SINGLE Register TREG0_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TREG0_PM_ERROR_CLEAR_SINGLE 0x80030 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ERROR_CLEAR_SINGLE 0x1FF80030u //! Register Reset Value #define TREG0_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TREG0_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TREG0_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TREG0_PM_ERROR_CLEAR_MULTI Register TREG0_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TREG0_PM_ERROR_CLEAR_MULTI 0x80038 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ERROR_CLEAR_MULTI 0x1FF80038u //! Register Reset Value #define TREG0_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TREG0_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TREG0_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_0 Register TREG0_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_0 0x80048 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_0 0x1FF80048u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_0 Register TREG0_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_0 0x80050 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_0 0x1FF80050u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_0 Register TREG0_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_0 0x80058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_0 0x1FF80058u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_1 Register TREG0_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_1 0x80060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_1 0x1FF80060u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_1_RST 0x0000000000080050u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_1 Register TREG0_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_1 0x80068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_1 0x1FF80068u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_1 Register TREG0_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_1 0x80070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_1 0x1FF80070u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_1_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_1 Register TREG0_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_1 0x80078 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_1 0x1FF80078u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_1_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_2 Register TREG0_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_2 0x80080 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_2 0x1FF80080u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_2 Register TREG0_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_2 0x80088 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_2 0x1FF80088u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_2 Register TREG0_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_2 0x80090 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_2 0x1FF80090u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_2 Register TREG0_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_2 0x80098 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_2 0x1FF80098u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_3 Register TREG0_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_3 0x800A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_3 0x1FF800A0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_3 Register TREG0_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_3 0x800A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_3 0x1FF800A8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_3 Register TREG0_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_3 0x800B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_3 0x1FF800B0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_3 Register TREG0_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_3 0x800B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_3 0x1FF800B8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_4 Register TREG0_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_4 0x800C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_4 0x1FF800C0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_4 Register TREG0_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_4 0x800C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_4 0x1FF800C8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_4 Register TREG0_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_4 0x800D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_4 0x1FF800D0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_4 Register TREG0_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_4 0x800D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_4 0x1FF800D8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_5 Register TREG0_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_5 0x800E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_5 0x1FF800E0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_5 Register TREG0_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_5 0x800E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_5 0x1FF800E8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_5 Register TREG0_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_5 0x800F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_5 0x1FF800F0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_5 Register TREG0_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_5 0x800F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_5 0x1FF800F8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_6 Register TREG0_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_6 0x80100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_6 0x1FF80100u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_6 Register TREG0_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_6 0x80108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_6 0x1FF80108u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_6 Register TREG0_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_6 0x80110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_6 0x1FF80110u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_6 Register TREG0_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_6 0x80118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_6 0x1FF80118u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_7 Register TREG0_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_7 0x80120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_7 0x1FF80120u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_7 Register TREG0_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_7 0x80128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_7 0x1FF80128u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_7 Register TREG0_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_7 0x80130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_7 0x1FF80130u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_7 Register TREG0_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_7 0x80138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_7 0x1FF80138u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_8 Register TREG0_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_8 0x80140 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_8 0x1FF80140u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_8 Register TREG0_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_8 0x80148 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_8 0x1FF80148u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_8 Register TREG0_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_8 0x80150 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_8 0x1FF80150u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_8 Register TREG0_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_8 0x80158 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_8 0x1FF80158u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_9 Register TREG0_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_9 0x80160 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_9 0x1FF80160u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_9 Register TREG0_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_9 0x80168 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_9 0x1FF80168u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_9 Register TREG0_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_9 0x80170 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_9 0x1FF80170u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_9 Register TREG0_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_9 0x80178 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_9 0x1FF80178u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_10 Register TREG0_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_10 0x80180 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_10 0x1FF80180u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_10 Register TREG0_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_10 0x80188 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_10 0x1FF80188u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_10 Register TREG0_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_10 0x80190 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_10 0x1FF80190u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_10 Register TREG0_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_10 0x80198 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_10 0x1FF80198u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_11 Register TREG0_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_11 0x801A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_11 0x1FF801A0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_11 Register TREG0_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_11 0x801A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_11 0x1FF801A8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_11 Register TREG0_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_11 0x801B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_11 0x1FF801B0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_11 Register TREG0_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_11 0x801B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_11 0x1FF801B8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_12 Register TREG0_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_12 0x801C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_12 0x1FF801C0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_12 Register TREG0_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_12 0x801C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_12 0x1FF801C8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_12 Register TREG0_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_12 0x801D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_12 0x1FF801D0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_12 Register TREG0_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_12 0x801D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_12 0x1FF801D8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_13 Register TREG0_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_13 0x801E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_13 0x1FF801E0u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_13 Register TREG0_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_13 0x801E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_13 0x1FF801E8u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_13 Register TREG0_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_13 0x801F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_13 0x1FF801F0u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_13 Register TREG0_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_13 0x801F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_13 0x1FF801F8u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_14 Register TREG0_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_14 0x80200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_14 0x1FF80200u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_14 Register TREG0_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_14 0x80208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_14 0x1FF80208u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_14 Register TREG0_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_14 0x80210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_14 0x1FF80210u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_14 Register TREG0_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_14 0x80218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_14 0x1FF80218u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_ADDR_MATCH_15 Register TREG0_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TREG0_PM_ADDR_MATCH_15 0x80220 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_ADDR_MATCH_15 0x1FF80220u //! Register Reset Value #define TREG0_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TREG0_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TREG0_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TREG0_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TREG0_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TREG0_PM_REQ_INFO_PERMISSION_15 Register TREG0_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TREG0_PM_REQ_INFO_PERMISSION_15 0x80228 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_REQ_INFO_PERMISSION_15 0x1FF80228u //! Register Reset Value #define TREG0_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TREG0_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TREG0_PM_READ_PERMISSION_15 Register TREG0_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TREG0_PM_READ_PERMISSION_15 0x80230 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_READ_PERMISSION_15 0x1FF80230u //! Register Reset Value #define TREG0_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TREG0_PM_WRITE_PERMISSION_15 Register TREG0_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TREG0_PM_WRITE_PERMISSION_15 0x80238 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TREG0_PM_WRITE_PERMISSION_15 0x1FF80238u //! Register Reset Value #define TREG0_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TREG0_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ERROR_LOG Register TSSB_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TSSB_PM_ERROR_LOG 0x80420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ERROR_LOG 0x1FF80420u //! Register Reset Value #define TSSB_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TSSB_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TSSB_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TSSB_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TSSB_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TSSB_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TSSB_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TSSB_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TSSB_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TSSB_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TSSB_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TSSB_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TSSB_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TSSB_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TSSB_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TSSB_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TSSB_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TSSB_PM_CONTROL Register TSSB_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TSSB_PM_CONTROL 0x80428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_CONTROL 0x1FF80428u //! Register Reset Value #define TSSB_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TSSB_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TSSB_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TSSB_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TSSB_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TSSB_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TSSB_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TSSB_PM_ERROR_CLEAR_SINGLE Register TSSB_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TSSB_PM_ERROR_CLEAR_SINGLE 0x80430 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ERROR_CLEAR_SINGLE 0x1FF80430u //! Register Reset Value #define TSSB_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TSSB_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TSSB_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TSSB_PM_ERROR_CLEAR_MULTI Register TSSB_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TSSB_PM_ERROR_CLEAR_MULTI 0x80438 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ERROR_CLEAR_MULTI 0x1FF80438u //! Register Reset Value #define TSSB_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TSSB_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TSSB_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_0 Register TSSB_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_0 0x80448 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_0 0x1FF80448u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_0 Register TSSB_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_0 0x80450 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_0 0x1FF80450u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_0 Register TSSB_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_0 0x80458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_0 0x1FF80458u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_1 Register TSSB_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_1 0x80460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_1 0x1FF80460u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_1 Register TSSB_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_1 0x80468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_1 0x1FF80468u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_1 Register TSSB_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_1 0x80470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_1 0x1FF80470u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_1_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_1 Register TSSB_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_1 0x80478 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_1 0x1FF80478u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_1_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_2 Register TSSB_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_2 0x80480 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_2 0x1FF80480u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_2_RST 0x000000001F800228u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_2 Register TSSB_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_2 0x80488 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_2 0x1FF80488u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_2 Register TSSB_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_2 0x80490 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_2 0x1FF80490u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_2_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_2 Register TSSB_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_2 0x80498 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_2 0x1FF80498u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_2_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_3 Register TSSB_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_3 0x804A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_3 0x1FF804A0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_3_RST 0x000000001F804220u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_3 Register TSSB_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_3 0x804A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_3 0x1FF804A8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_3 Register TSSB_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_3 0x804B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_3 0x1FF804B0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_3_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_3 Register TSSB_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_3 0x804B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_3 0x1FF804B8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_3_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_4 Register TSSB_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_4 0x804C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_4 0x1FF804C0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_4_RST 0x00000000B0000228u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_4 Register TSSB_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_4 0x804C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_4 0x1FF804C8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_4 Register TSSB_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_4 0x804D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_4 0x1FF804D0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_4_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_4 Register TSSB_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_4 0x804D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_4 0x1FF804D8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_4_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_5 Register TSSB_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_5 0x804E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_5 0x1FF804E0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_5_RST 0x00000000B0004220u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_5 Register TSSB_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_5 0x804E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_5 0x1FF804E8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_5 Register TSSB_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_5 0x804F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_5 0x1FF804F0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_5_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_5 Register TSSB_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_5 0x804F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_5 0x1FF804F8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_5_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_6 Register TSSB_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_6 0x80500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_6 0x1FF80500u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_6 Register TSSB_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_6 0x80508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_6 0x1FF80508u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_6 Register TSSB_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_6 0x80510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_6 0x1FF80510u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_6 Register TSSB_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_6 0x80518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_6 0x1FF80518u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_7 Register TSSB_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_7 0x80520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_7 0x1FF80520u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_7 Register TSSB_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_7 0x80528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_7 0x1FF80528u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_7 Register TSSB_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_7 0x80530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_7 0x1FF80530u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_7 Register TSSB_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_7 0x80538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_7 0x1FF80538u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_8 Register TSSB_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_8 0x80540 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_8 0x1FF80540u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_8 Register TSSB_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_8 0x80548 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_8 0x1FF80548u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_8 Register TSSB_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_8 0x80550 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_8 0x1FF80550u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_8 Register TSSB_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_8 0x80558 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_8 0x1FF80558u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_9 Register TSSB_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_9 0x80560 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_9 0x1FF80560u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_9 Register TSSB_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_9 0x80568 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_9 0x1FF80568u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_9 Register TSSB_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_9 0x80570 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_9 0x1FF80570u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_9 Register TSSB_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_9 0x80578 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_9 0x1FF80578u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_10 Register TSSB_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_10 0x80580 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_10 0x1FF80580u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_10 Register TSSB_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_10 0x80588 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_10 0x1FF80588u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_10 Register TSSB_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_10 0x80590 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_10 0x1FF80590u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_10 Register TSSB_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_10 0x80598 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_10 0x1FF80598u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_11 Register TSSB_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_11 0x805A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_11 0x1FF805A0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_11 Register TSSB_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_11 0x805A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_11 0x1FF805A8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_11 Register TSSB_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_11 0x805B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_11 0x1FF805B0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_11 Register TSSB_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_11 0x805B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_11 0x1FF805B8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_12 Register TSSB_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_12 0x805C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_12 0x1FF805C0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_12 Register TSSB_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_12 0x805C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_12 0x1FF805C8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_12 Register TSSB_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_12 0x805D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_12 0x1FF805D0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_12 Register TSSB_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_12 0x805D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_12 0x1FF805D8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_13 Register TSSB_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_13 0x805E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_13 0x1FF805E0u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_13 Register TSSB_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_13 0x805E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_13 0x1FF805E8u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_13 Register TSSB_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_13 0x805F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_13 0x1FF805F0u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_13 Register TSSB_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_13 0x805F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_13 0x1FF805F8u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_14 Register TSSB_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_14 0x80600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_14 0x1FF80600u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_14 Register TSSB_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_14 0x80608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_14 0x1FF80608u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_14 Register TSSB_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_14 0x80610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_14 0x1FF80610u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_14 Register TSSB_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_14 0x80618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_14 0x1FF80618u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_ADDR_MATCH_15 Register TSSB_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TSSB_PM_ADDR_MATCH_15 0x80620 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_ADDR_MATCH_15 0x1FF80620u //! Register Reset Value #define TSSB_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TSSB_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TSSB_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TSSB_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TSSB_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TSSB_PM_REQ_INFO_PERMISSION_15 Register TSSB_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TSSB_PM_REQ_INFO_PERMISSION_15 0x80628 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_REQ_INFO_PERMISSION_15 0x1FF80628u //! Register Reset Value #define TSSB_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TSSB_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TSSB_PM_READ_PERMISSION_15 Register TSSB_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TSSB_PM_READ_PERMISSION_15 0x80630 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_READ_PERMISSION_15 0x1FF80630u //! Register Reset Value #define TSSB_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TSSB_PM_WRITE_PERMISSION_15 Register TSSB_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TSSB_PM_WRITE_PERMISSION_15 0x80638 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TSSB_PM_WRITE_PERMISSION_15 0x1FF80638u //! Register Reset Value #define TSSB_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TSSB_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ERROR_LOG Register TROM_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TROM_PM_ERROR_LOG 0x80820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ERROR_LOG 0x1FF80820u //! Register Reset Value #define TROM_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TROM_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TROM_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TROM_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TROM_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TROM_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TROM_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TROM_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TROM_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TROM_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TROM_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TROM_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TROM_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TROM_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TROM_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TROM_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TROM_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TROM_PM_CONTROL Register TROM_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TROM_PM_CONTROL 0x80828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_CONTROL 0x1FF80828u //! Register Reset Value #define TROM_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TROM_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TROM_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TROM_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TROM_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TROM_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TROM_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TROM_PM_ERROR_CLEAR_SINGLE Register TROM_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TROM_PM_ERROR_CLEAR_SINGLE 0x80830 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ERROR_CLEAR_SINGLE 0x1FF80830u //! Register Reset Value #define TROM_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TROM_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TROM_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TROM_PM_ERROR_CLEAR_MULTI Register TROM_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TROM_PM_ERROR_CLEAR_MULTI 0x80838 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ERROR_CLEAR_MULTI 0x1FF80838u //! Register Reset Value #define TROM_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TROM_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TROM_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_0 Register TROM_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_0 0x80848 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_0 0x1FF80848u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_0 Register TROM_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_0 0x80850 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_0 0x1FF80850u //! Register Reset Value #define TROM_PM_READ_PERMISSION_0_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_0 Register TROM_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_0 0x80858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_0 0x1FF80858u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_0_RST 0x000000000000001Fu //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TROM_PM_ADDR_MATCH_1 Register TROM_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_1 0x80860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_1 0x1FF80860u //! Register Reset Value #define TROM_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_1 Register TROM_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_1 0x80868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_1 0x1FF80868u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_1 Register TROM_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_1 0x80870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_1 0x1FF80870u //! Register Reset Value #define TROM_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_1 Register TROM_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_1 0x80878 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_1 0x1FF80878u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_2 Register TROM_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_2 0x80880 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_2 0x1FF80880u //! Register Reset Value #define TROM_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_2 Register TROM_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_2 0x80888 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_2 0x1FF80888u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_2 Register TROM_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_2 0x80890 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_2 0x1FF80890u //! Register Reset Value #define TROM_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_2 Register TROM_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_2 0x80898 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_2 0x1FF80898u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_3 Register TROM_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_3 0x808A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_3 0x1FF808A0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_3 Register TROM_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_3 0x808A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_3 0x1FF808A8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_3 Register TROM_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_3 0x808B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_3 0x1FF808B0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_3 Register TROM_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_3 0x808B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_3 0x1FF808B8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_4 Register TROM_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_4 0x808C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_4 0x1FF808C0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_4 Register TROM_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_4 0x808C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_4 0x1FF808C8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_4 Register TROM_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_4 0x808D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_4 0x1FF808D0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_4 Register TROM_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_4 0x808D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_4 0x1FF808D8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_5 Register TROM_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_5 0x808E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_5 0x1FF808E0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_5 Register TROM_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_5 0x808E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_5 0x1FF808E8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_5 Register TROM_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_5 0x808F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_5 0x1FF808F0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_5 Register TROM_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_5 0x808F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_5 0x1FF808F8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_6 Register TROM_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_6 0x80900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_6 0x1FF80900u //! Register Reset Value #define TROM_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_6 Register TROM_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_6 0x80908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_6 0x1FF80908u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_6 Register TROM_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_6 0x80910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_6 0x1FF80910u //! Register Reset Value #define TROM_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_6 Register TROM_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_6 0x80918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_6 0x1FF80918u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_7 Register TROM_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_7 0x80920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_7 0x1FF80920u //! Register Reset Value #define TROM_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_7 Register TROM_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_7 0x80928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_7 0x1FF80928u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_7 Register TROM_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_7 0x80930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_7 0x1FF80930u //! Register Reset Value #define TROM_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_7 Register TROM_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_7 0x80938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_7 0x1FF80938u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_8 Register TROM_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_8 0x80940 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_8 0x1FF80940u //! Register Reset Value #define TROM_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_8 Register TROM_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_8 0x80948 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_8 0x1FF80948u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_8 Register TROM_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_8 0x80950 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_8 0x1FF80950u //! Register Reset Value #define TROM_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_8 Register TROM_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_8 0x80958 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_8 0x1FF80958u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_9 Register TROM_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_9 0x80960 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_9 0x1FF80960u //! Register Reset Value #define TROM_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_9 Register TROM_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_9 0x80968 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_9 0x1FF80968u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_9 Register TROM_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_9 0x80970 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_9 0x1FF80970u //! Register Reset Value #define TROM_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_9 Register TROM_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_9 0x80978 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_9 0x1FF80978u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_10 Register TROM_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_10 0x80980 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_10 0x1FF80980u //! Register Reset Value #define TROM_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_10 Register TROM_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_10 0x80988 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_10 0x1FF80988u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_10 Register TROM_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_10 0x80990 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_10 0x1FF80990u //! Register Reset Value #define TROM_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_10 Register TROM_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_10 0x80998 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_10 0x1FF80998u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_11 Register TROM_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_11 0x809A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_11 0x1FF809A0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_11 Register TROM_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_11 0x809A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_11 0x1FF809A8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_11 Register TROM_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_11 0x809B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_11 0x1FF809B0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_11 Register TROM_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_11 0x809B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_11 0x1FF809B8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_12 Register TROM_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_12 0x809C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_12 0x1FF809C0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_12 Register TROM_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_12 0x809C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_12 0x1FF809C8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_12 Register TROM_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_12 0x809D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_12 0x1FF809D0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_12 Register TROM_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_12 0x809D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_12 0x1FF809D8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_13 Register TROM_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_13 0x809E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_13 0x1FF809E0u //! Register Reset Value #define TROM_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_13 Register TROM_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_13 0x809E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_13 0x1FF809E8u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_13 Register TROM_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_13 0x809F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_13 0x1FF809F0u //! Register Reset Value #define TROM_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_13 Register TROM_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_13 0x809F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_13 0x1FF809F8u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_14 Register TROM_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_14 0x80A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_14 0x1FF80A00u //! Register Reset Value #define TROM_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_14 Register TROM_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_14 0x80A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_14 0x1FF80A08u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_14 Register TROM_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_14 0x80A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_14 0x1FF80A10u //! Register Reset Value #define TROM_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_14 Register TROM_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_14 0x80A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_14 0x1FF80A18u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_ADDR_MATCH_15 Register TROM_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TROM_PM_ADDR_MATCH_15 0x80A20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_ADDR_MATCH_15 0x1FF80A20u //! Register Reset Value #define TROM_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TROM_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TROM_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TROM_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TROM_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TROM_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TROM_PM_REQ_INFO_PERMISSION_15 Register TROM_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TROM_PM_REQ_INFO_PERMISSION_15 0x80A28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_REQ_INFO_PERMISSION_15 0x1FF80A28u //! Register Reset Value #define TROM_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TROM_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TROM_PM_READ_PERMISSION_15 Register TROM_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TROM_PM_READ_PERMISSION_15 0x80A30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_READ_PERMISSION_15 0x1FF80A30u //! Register Reset Value #define TROM_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TROM_PM_WRITE_PERMISSION_15 Register TROM_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TROM_PM_WRITE_PERMISSION_15 0x80A38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TROM_PM_WRITE_PERMISSION_15 0x1FF80A38u //! Register Reset Value #define TROM_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TROM_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ERROR_LOG Register TOTP_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TOTP_PM_ERROR_LOG 0x80C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ERROR_LOG 0x1FF80C20u //! Register Reset Value #define TOTP_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TOTP_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TOTP_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TOTP_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TOTP_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TOTP_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TOTP_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TOTP_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TOTP_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TOTP_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TOTP_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TOTP_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TOTP_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TOTP_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TOTP_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TOTP_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TOTP_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TOTP_PM_CONTROL Register TOTP_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TOTP_PM_CONTROL 0x80C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_CONTROL 0x1FF80C28u //! Register Reset Value #define TOTP_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TOTP_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TOTP_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TOTP_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TOTP_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TOTP_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TOTP_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TOTP_PM_ERROR_CLEAR_SINGLE Register TOTP_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TOTP_PM_ERROR_CLEAR_SINGLE 0x80C30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ERROR_CLEAR_SINGLE 0x1FF80C30u //! Register Reset Value #define TOTP_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TOTP_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TOTP_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TOTP_PM_ERROR_CLEAR_MULTI Register TOTP_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TOTP_PM_ERROR_CLEAR_MULTI 0x80C38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ERROR_CLEAR_MULTI 0x1FF80C38u //! Register Reset Value #define TOTP_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TOTP_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TOTP_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_0 Register TOTP_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_0 0x80C48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_0 0x1FF80C48u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_0 Register TOTP_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_0 0x80C50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_0 0x1FF80C50u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_0_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_0 Register TOTP_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_0 0x80C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_0 0x1FF80C58u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_1 Register TOTP_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_1 0x80C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_1 0x1FF80C60u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_1 Register TOTP_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_1 0x80C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_1 0x1FF80C68u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_1 Register TOTP_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_1 0x80C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_1 0x1FF80C70u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_1 Register TOTP_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_1 0x80C78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_1 0x1FF80C78u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_2 Register TOTP_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_2 0x80C80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_2 0x1FF80C80u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_2 Register TOTP_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_2 0x80C88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_2 0x1FF80C88u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_2 Register TOTP_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_2 0x80C90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_2 0x1FF80C90u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_2 Register TOTP_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_2 0x80C98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_2 0x1FF80C98u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_3 Register TOTP_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_3 0x80CA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_3 0x1FF80CA0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_3 Register TOTP_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_3 0x80CA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_3 0x1FF80CA8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_3 Register TOTP_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_3 0x80CB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_3 0x1FF80CB0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_3 Register TOTP_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_3 0x80CB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_3 0x1FF80CB8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_4 Register TOTP_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_4 0x80CC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_4 0x1FF80CC0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_4 Register TOTP_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_4 0x80CC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_4 0x1FF80CC8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_4 Register TOTP_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_4 0x80CD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_4 0x1FF80CD0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_4 Register TOTP_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_4 0x80CD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_4 0x1FF80CD8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_5 Register TOTP_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_5 0x80CE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_5 0x1FF80CE0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_5 Register TOTP_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_5 0x80CE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_5 0x1FF80CE8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_5 Register TOTP_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_5 0x80CF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_5 0x1FF80CF0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_5 Register TOTP_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_5 0x80CF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_5 0x1FF80CF8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_6 Register TOTP_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_6 0x80D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_6 0x1FF80D00u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_6 Register TOTP_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_6 0x80D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_6 0x1FF80D08u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_6 Register TOTP_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_6 0x80D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_6 0x1FF80D10u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_6 Register TOTP_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_6 0x80D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_6 0x1FF80D18u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_7 Register TOTP_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_7 0x80D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_7 0x1FF80D20u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_7 Register TOTP_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_7 0x80D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_7 0x1FF80D28u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_7 Register TOTP_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_7 0x80D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_7 0x1FF80D30u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_7 Register TOTP_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_7 0x80D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_7 0x1FF80D38u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_8 Register TOTP_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_8 0x80D40 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_8 0x1FF80D40u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_8 Register TOTP_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_8 0x80D48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_8 0x1FF80D48u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_8 Register TOTP_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_8 0x80D50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_8 0x1FF80D50u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_8 Register TOTP_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_8 0x80D58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_8 0x1FF80D58u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_9 Register TOTP_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_9 0x80D60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_9 0x1FF80D60u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_9 Register TOTP_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_9 0x80D68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_9 0x1FF80D68u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_9 Register TOTP_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_9 0x80D70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_9 0x1FF80D70u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_9 Register TOTP_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_9 0x80D78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_9 0x1FF80D78u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_10 Register TOTP_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_10 0x80D80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_10 0x1FF80D80u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_10 Register TOTP_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_10 0x80D88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_10 0x1FF80D88u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_10 Register TOTP_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_10 0x80D90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_10 0x1FF80D90u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_10 Register TOTP_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_10 0x80D98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_10 0x1FF80D98u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_11 Register TOTP_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_11 0x80DA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_11 0x1FF80DA0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_11 Register TOTP_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_11 0x80DA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_11 0x1FF80DA8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_11 Register TOTP_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_11 0x80DB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_11 0x1FF80DB0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_11 Register TOTP_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_11 0x80DB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_11 0x1FF80DB8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_12 Register TOTP_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_12 0x80DC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_12 0x1FF80DC0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_12 Register TOTP_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_12 0x80DC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_12 0x1FF80DC8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_12 Register TOTP_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_12 0x80DD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_12 0x1FF80DD0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_12 Register TOTP_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_12 0x80DD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_12 0x1FF80DD8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_13 Register TOTP_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_13 0x80DE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_13 0x1FF80DE0u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_13 Register TOTP_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_13 0x80DE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_13 0x1FF80DE8u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_13 Register TOTP_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_13 0x80DF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_13 0x1FF80DF0u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_13 Register TOTP_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_13 0x80DF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_13 0x1FF80DF8u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_14 Register TOTP_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_14 0x80E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_14 0x1FF80E00u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_14 Register TOTP_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_14 0x80E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_14 0x1FF80E08u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_14 Register TOTP_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_14 0x80E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_14 0x1FF80E10u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_14 Register TOTP_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_14 0x80E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_14 0x1FF80E18u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_ADDR_MATCH_15 Register TOTP_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TOTP_PM_ADDR_MATCH_15 0x80E20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_ADDR_MATCH_15 0x1FF80E20u //! Register Reset Value #define TOTP_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TOTP_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TOTP_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TOTP_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TOTP_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TOTP_PM_REQ_INFO_PERMISSION_15 Register TOTP_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TOTP_PM_REQ_INFO_PERMISSION_15 0x80E28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_REQ_INFO_PERMISSION_15 0x1FF80E28u //! Register Reset Value #define TOTP_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TOTP_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TOTP_PM_READ_PERMISSION_15 Register TOTP_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TOTP_PM_READ_PERMISSION_15 0x80E30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_READ_PERMISSION_15 0x1FF80E30u //! Register Reset Value #define TOTP_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TOTP_PM_WRITE_PERMISSION_15 Register TOTP_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TOTP_PM_WRITE_PERMISSION_15 0x80E38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TOTP_PM_WRITE_PERMISSION_15 0x1FF80E38u //! Register Reset Value #define TOTP_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TOTP_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ERROR_LOG Register TCBM1_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TCBM1_PM_ERROR_LOG 0x81020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ERROR_LOG 0x1FF81020u //! Register Reset Value #define TCBM1_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TCBM1_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TCBM1_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TCBM1_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TCBM1_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TCBM1_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TCBM1_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TCBM1_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TCBM1_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TCBM1_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TCBM1_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TCBM1_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TCBM1_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TCBM1_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TCBM1_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TCBM1_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TCBM1_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TCBM1_PM_CONTROL Register TCBM1_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TCBM1_PM_CONTROL 0x81028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_CONTROL 0x1FF81028u //! Register Reset Value #define TCBM1_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TCBM1_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TCBM1_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TCBM1_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TCBM1_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TCBM1_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TCBM1_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TCBM1_PM_ERROR_CLEAR_SINGLE Register TCBM1_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TCBM1_PM_ERROR_CLEAR_SINGLE 0x81030 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ERROR_CLEAR_SINGLE 0x1FF81030u //! Register Reset Value #define TCBM1_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TCBM1_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TCBM1_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TCBM1_PM_ERROR_CLEAR_MULTI Register TCBM1_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TCBM1_PM_ERROR_CLEAR_MULTI 0x81038 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ERROR_CLEAR_MULTI 0x1FF81038u //! Register Reset Value #define TCBM1_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TCBM1_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TCBM1_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_0 Register TCBM1_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_0 0x81048 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_0 0x1FF81048u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_0 Register TCBM1_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_0 0x81050 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_0 0x1FF81050u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_0 Register TCBM1_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_0 0x81058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_0 0x1FF81058u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_1 Register TCBM1_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_1 0x81060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_1 0x1FF81060u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_1 Register TCBM1_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_1 0x81068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_1 0x1FF81068u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_1 Register TCBM1_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_1 0x81070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_1 0x1FF81070u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_1 Register TCBM1_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_1 0x81078 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_1 0x1FF81078u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_2 Register TCBM1_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_2 0x81080 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_2 0x1FF81080u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_2 Register TCBM1_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_2 0x81088 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_2 0x1FF81088u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_2 Register TCBM1_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_2 0x81090 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_2 0x1FF81090u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_2 Register TCBM1_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_2 0x81098 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_2 0x1FF81098u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_3 Register TCBM1_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_3 0x810A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_3 0x1FF810A0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_3 Register TCBM1_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_3 0x810A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_3 0x1FF810A8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_3 Register TCBM1_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_3 0x810B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_3 0x1FF810B0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_3 Register TCBM1_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_3 0x810B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_3 0x1FF810B8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_4 Register TCBM1_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_4 0x810C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_4 0x1FF810C0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_4 Register TCBM1_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_4 0x810C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_4 0x1FF810C8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_4 Register TCBM1_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_4 0x810D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_4 0x1FF810D0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_4 Register TCBM1_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_4 0x810D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_4 0x1FF810D8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_5 Register TCBM1_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_5 0x810E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_5 0x1FF810E0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_5 Register TCBM1_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_5 0x810E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_5 0x1FF810E8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_5 Register TCBM1_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_5 0x810F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_5 0x1FF810F0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_5 Register TCBM1_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_5 0x810F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_5 0x1FF810F8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_6 Register TCBM1_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_6 0x81100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_6 0x1FF81100u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_6 Register TCBM1_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_6 0x81108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_6 0x1FF81108u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_6 Register TCBM1_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_6 0x81110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_6 0x1FF81110u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_6 Register TCBM1_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_6 0x81118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_6 0x1FF81118u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_7 Register TCBM1_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_7 0x81120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_7 0x1FF81120u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_7 Register TCBM1_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_7 0x81128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_7 0x1FF81128u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_7 Register TCBM1_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_7 0x81130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_7 0x1FF81130u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_7 Register TCBM1_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_7 0x81138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_7 0x1FF81138u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_8 Register TCBM1_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_8 0x81140 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_8 0x1FF81140u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_8 Register TCBM1_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_8 0x81148 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_8 0x1FF81148u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_8 Register TCBM1_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_8 0x81150 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_8 0x1FF81150u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_8 Register TCBM1_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_8 0x81158 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_8 0x1FF81158u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_9 Register TCBM1_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_9 0x81160 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_9 0x1FF81160u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_9 Register TCBM1_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_9 0x81168 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_9 0x1FF81168u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_9 Register TCBM1_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_9 0x81170 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_9 0x1FF81170u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_9 Register TCBM1_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_9 0x81178 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_9 0x1FF81178u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_10 Register TCBM1_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_10 0x81180 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_10 0x1FF81180u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_10 Register TCBM1_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_10 0x81188 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_10 0x1FF81188u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_10 Register TCBM1_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_10 0x81190 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_10 0x1FF81190u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_10 Register TCBM1_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_10 0x81198 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_10 0x1FF81198u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_11 Register TCBM1_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_11 0x811A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_11 0x1FF811A0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_11 Register TCBM1_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_11 0x811A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_11 0x1FF811A8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_11 Register TCBM1_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_11 0x811B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_11 0x1FF811B0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_11 Register TCBM1_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_11 0x811B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_11 0x1FF811B8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_12 Register TCBM1_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_12 0x811C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_12 0x1FF811C0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_12 Register TCBM1_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_12 0x811C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_12 0x1FF811C8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_12 Register TCBM1_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_12 0x811D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_12 0x1FF811D0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_12 Register TCBM1_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_12 0x811D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_12 0x1FF811D8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_13 Register TCBM1_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_13 0x811E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_13 0x1FF811E0u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_13 Register TCBM1_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_13 0x811E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_13 0x1FF811E8u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_13 Register TCBM1_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_13 0x811F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_13 0x1FF811F0u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_13 Register TCBM1_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_13 0x811F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_13 0x1FF811F8u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_14 Register TCBM1_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_14 0x81200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_14 0x1FF81200u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_14 Register TCBM1_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_14 0x81208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_14 0x1FF81208u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_14 Register TCBM1_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_14 0x81210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_14 0x1FF81210u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_14 Register TCBM1_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_14 0x81218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_14 0x1FF81218u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_ADDR_MATCH_15 Register TCBM1_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TCBM1_PM_ADDR_MATCH_15 0x81220 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_ADDR_MATCH_15 0x1FF81220u //! Register Reset Value #define TCBM1_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM1_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TCBM1_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TCBM1_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM1_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM1_PM_REQ_INFO_PERMISSION_15 Register TCBM1_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TCBM1_PM_REQ_INFO_PERMISSION_15 0x81228 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_REQ_INFO_PERMISSION_15 0x1FF81228u //! Register Reset Value #define TCBM1_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM1_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM1_PM_READ_PERMISSION_15 Register TCBM1_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TCBM1_PM_READ_PERMISSION_15 0x81230 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_READ_PERMISSION_15 0x1FF81230u //! Register Reset Value #define TCBM1_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM1_PM_WRITE_PERMISSION_15 Register TCBM1_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TCBM1_PM_WRITE_PERMISSION_15 0x81238 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM1_PM_WRITE_PERMISSION_15 0x1FF81238u //! Register Reset Value #define TCBM1_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM1_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ERROR_LOG Register TCBM2_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TCBM2_PM_ERROR_LOG 0x81420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ERROR_LOG 0x1FF81420u //! Register Reset Value #define TCBM2_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TCBM2_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TCBM2_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TCBM2_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TCBM2_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TCBM2_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TCBM2_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TCBM2_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TCBM2_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TCBM2_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TCBM2_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TCBM2_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TCBM2_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TCBM2_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TCBM2_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TCBM2_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TCBM2_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TCBM2_PM_CONTROL Register TCBM2_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TCBM2_PM_CONTROL 0x81428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_CONTROL 0x1FF81428u //! Register Reset Value #define TCBM2_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TCBM2_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TCBM2_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TCBM2_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TCBM2_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TCBM2_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TCBM2_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TCBM2_PM_ERROR_CLEAR_SINGLE Register TCBM2_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TCBM2_PM_ERROR_CLEAR_SINGLE 0x81430 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ERROR_CLEAR_SINGLE 0x1FF81430u //! Register Reset Value #define TCBM2_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TCBM2_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TCBM2_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TCBM2_PM_ERROR_CLEAR_MULTI Register TCBM2_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TCBM2_PM_ERROR_CLEAR_MULTI 0x81438 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ERROR_CLEAR_MULTI 0x1FF81438u //! Register Reset Value #define TCBM2_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TCBM2_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TCBM2_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_0 Register TCBM2_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_0 0x81448 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_0 0x1FF81448u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_0 Register TCBM2_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_0 0x81450 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_0 0x1FF81450u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_0 Register TCBM2_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_0 0x81458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_0 0x1FF81458u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_1 Register TCBM2_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_1 0x81460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_1 0x1FF81460u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_1 Register TCBM2_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_1 0x81468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_1 0x1FF81468u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_1 Register TCBM2_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_1 0x81470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_1 0x1FF81470u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_1 Register TCBM2_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_1 0x81478 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_1 0x1FF81478u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_2 Register TCBM2_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_2 0x81480 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_2 0x1FF81480u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_2 Register TCBM2_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_2 0x81488 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_2 0x1FF81488u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_2 Register TCBM2_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_2 0x81490 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_2 0x1FF81490u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_2 Register TCBM2_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_2 0x81498 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_2 0x1FF81498u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_3 Register TCBM2_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_3 0x814A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_3 0x1FF814A0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_3 Register TCBM2_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_3 0x814A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_3 0x1FF814A8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_3 Register TCBM2_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_3 0x814B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_3 0x1FF814B0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_3 Register TCBM2_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_3 0x814B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_3 0x1FF814B8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_4 Register TCBM2_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_4 0x814C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_4 0x1FF814C0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_4 Register TCBM2_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_4 0x814C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_4 0x1FF814C8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_4 Register TCBM2_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_4 0x814D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_4 0x1FF814D0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_4 Register TCBM2_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_4 0x814D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_4 0x1FF814D8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_5 Register TCBM2_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_5 0x814E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_5 0x1FF814E0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_5 Register TCBM2_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_5 0x814E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_5 0x1FF814E8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_5 Register TCBM2_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_5 0x814F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_5 0x1FF814F0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_5 Register TCBM2_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_5 0x814F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_5 0x1FF814F8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_6 Register TCBM2_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_6 0x81500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_6 0x1FF81500u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_6 Register TCBM2_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_6 0x81508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_6 0x1FF81508u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_6 Register TCBM2_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_6 0x81510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_6 0x1FF81510u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_6 Register TCBM2_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_6 0x81518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_6 0x1FF81518u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_7 Register TCBM2_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_7 0x81520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_7 0x1FF81520u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_7 Register TCBM2_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_7 0x81528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_7 0x1FF81528u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_7 Register TCBM2_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_7 0x81530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_7 0x1FF81530u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_7 Register TCBM2_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_7 0x81538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_7 0x1FF81538u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_8 Register TCBM2_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_8 0x81540 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_8 0x1FF81540u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_8 Register TCBM2_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_8 0x81548 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_8 0x1FF81548u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_8 Register TCBM2_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_8 0x81550 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_8 0x1FF81550u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_8 Register TCBM2_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_8 0x81558 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_8 0x1FF81558u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_9 Register TCBM2_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_9 0x81560 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_9 0x1FF81560u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_9 Register TCBM2_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_9 0x81568 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_9 0x1FF81568u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_9 Register TCBM2_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_9 0x81570 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_9 0x1FF81570u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_9 Register TCBM2_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_9 0x81578 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_9 0x1FF81578u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_10 Register TCBM2_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_10 0x81580 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_10 0x1FF81580u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_10 Register TCBM2_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_10 0x81588 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_10 0x1FF81588u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_10 Register TCBM2_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_10 0x81590 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_10 0x1FF81590u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_10 Register TCBM2_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_10 0x81598 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_10 0x1FF81598u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_11 Register TCBM2_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_11 0x815A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_11 0x1FF815A0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_11 Register TCBM2_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_11 0x815A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_11 0x1FF815A8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_11 Register TCBM2_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_11 0x815B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_11 0x1FF815B0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_11 Register TCBM2_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_11 0x815B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_11 0x1FF815B8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_12 Register TCBM2_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_12 0x815C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_12 0x1FF815C0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_12 Register TCBM2_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_12 0x815C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_12 0x1FF815C8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_12 Register TCBM2_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_12 0x815D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_12 0x1FF815D0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_12 Register TCBM2_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_12 0x815D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_12 0x1FF815D8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_13 Register TCBM2_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_13 0x815E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_13 0x1FF815E0u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_13 Register TCBM2_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_13 0x815E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_13 0x1FF815E8u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_13 Register TCBM2_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_13 0x815F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_13 0x1FF815F0u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_13 Register TCBM2_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_13 0x815F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_13 0x1FF815F8u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_14 Register TCBM2_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_14 0x81600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_14 0x1FF81600u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_14 Register TCBM2_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_14 0x81608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_14 0x1FF81608u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_14 Register TCBM2_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_14 0x81610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_14 0x1FF81610u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_14 Register TCBM2_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_14 0x81618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_14 0x1FF81618u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_ADDR_MATCH_15 Register TCBM2_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TCBM2_PM_ADDR_MATCH_15 0x81620 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_ADDR_MATCH_15 0x1FF81620u //! Register Reset Value #define TCBM2_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TCBM2_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TCBM2_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TCBM2_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TCBM2_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TCBM2_PM_REQ_INFO_PERMISSION_15 Register TCBM2_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TCBM2_PM_REQ_INFO_PERMISSION_15 0x81628 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_REQ_INFO_PERMISSION_15 0x1FF81628u //! Register Reset Value #define TCBM2_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TCBM2_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TCBM2_PM_READ_PERMISSION_15 Register TCBM2_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TCBM2_PM_READ_PERMISSION_15 0x81630 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_READ_PERMISSION_15 0x1FF81630u //! Register Reset Value #define TCBM2_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TCBM2_PM_WRITE_PERMISSION_15 Register TCBM2_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TCBM2_PM_WRITE_PERMISSION_15 0x81638 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TCBM2_PM_WRITE_PERMISSION_15 0x1FF81638u //! Register Reset Value #define TCBM2_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TCBM2_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ERROR_LOG Register TE97_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TE97_PM_ERROR_LOG 0x81820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ERROR_LOG 0x1FF81820u //! Register Reset Value #define TE97_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TE97_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TE97_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TE97_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TE97_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TE97_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TE97_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TE97_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TE97_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TE97_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TE97_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TE97_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TE97_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TE97_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TE97_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TE97_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TE97_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TE97_PM_CONTROL Register TE97_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TE97_PM_CONTROL 0x81828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_CONTROL 0x1FF81828u //! Register Reset Value #define TE97_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TE97_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TE97_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TE97_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TE97_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TE97_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TE97_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TE97_PM_ERROR_CLEAR_SINGLE Register TE97_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TE97_PM_ERROR_CLEAR_SINGLE 0x81830 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ERROR_CLEAR_SINGLE 0x1FF81830u //! Register Reset Value #define TE97_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TE97_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TE97_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TE97_PM_ERROR_CLEAR_MULTI Register TE97_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TE97_PM_ERROR_CLEAR_MULTI 0x81838 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ERROR_CLEAR_MULTI 0x1FF81838u //! Register Reset Value #define TE97_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TE97_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TE97_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_0 Register TE97_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_0 0x81848 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_0 0x1FF81848u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_0 Register TE97_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_0 0x81850 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_0 0x1FF81850u //! Register Reset Value #define TE97_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_0 Register TE97_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_0 0x81858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_0 0x1FF81858u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TE97_PM_ADDR_MATCH_1 Register TE97_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_1 0x81860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_1 0x1FF81860u //! Register Reset Value #define TE97_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_1 Register TE97_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_1 0x81868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_1 0x1FF81868u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_1 Register TE97_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_1 0x81870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_1 0x1FF81870u //! Register Reset Value #define TE97_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_1 Register TE97_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_1 0x81878 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_1 0x1FF81878u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_2 Register TE97_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_2 0x81880 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_2 0x1FF81880u //! Register Reset Value #define TE97_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_2 Register TE97_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_2 0x81888 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_2 0x1FF81888u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_2 Register TE97_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_2 0x81890 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_2 0x1FF81890u //! Register Reset Value #define TE97_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_2 Register TE97_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_2 0x81898 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_2 0x1FF81898u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_3 Register TE97_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_3 0x818A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_3 0x1FF818A0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_3 Register TE97_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_3 0x818A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_3 0x1FF818A8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_3 Register TE97_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_3 0x818B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_3 0x1FF818B0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_3 Register TE97_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_3 0x818B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_3 0x1FF818B8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_4 Register TE97_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_4 0x818C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_4 0x1FF818C0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_4 Register TE97_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_4 0x818C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_4 0x1FF818C8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_4 Register TE97_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_4 0x818D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_4 0x1FF818D0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_4 Register TE97_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_4 0x818D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_4 0x1FF818D8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_5 Register TE97_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_5 0x818E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_5 0x1FF818E0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_5 Register TE97_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_5 0x818E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_5 0x1FF818E8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_5 Register TE97_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_5 0x818F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_5 0x1FF818F0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_5 Register TE97_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_5 0x818F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_5 0x1FF818F8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_6 Register TE97_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_6 0x81900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_6 0x1FF81900u //! Register Reset Value #define TE97_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_6 Register TE97_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_6 0x81908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_6 0x1FF81908u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_6 Register TE97_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_6 0x81910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_6 0x1FF81910u //! Register Reset Value #define TE97_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_6 Register TE97_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_6 0x81918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_6 0x1FF81918u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_7 Register TE97_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_7 0x81920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_7 0x1FF81920u //! Register Reset Value #define TE97_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_7 Register TE97_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_7 0x81928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_7 0x1FF81928u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_7 Register TE97_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_7 0x81930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_7 0x1FF81930u //! Register Reset Value #define TE97_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_7 Register TE97_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_7 0x81938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_7 0x1FF81938u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_8 Register TE97_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_8 0x81940 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_8 0x1FF81940u //! Register Reset Value #define TE97_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_8 Register TE97_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_8 0x81948 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_8 0x1FF81948u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_8 Register TE97_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_8 0x81950 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_8 0x1FF81950u //! Register Reset Value #define TE97_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_8 Register TE97_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_8 0x81958 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_8 0x1FF81958u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_9 Register TE97_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_9 0x81960 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_9 0x1FF81960u //! Register Reset Value #define TE97_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_9 Register TE97_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_9 0x81968 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_9 0x1FF81968u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_9 Register TE97_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_9 0x81970 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_9 0x1FF81970u //! Register Reset Value #define TE97_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_9 Register TE97_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_9 0x81978 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_9 0x1FF81978u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_10 Register TE97_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_10 0x81980 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_10 0x1FF81980u //! Register Reset Value #define TE97_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_10 Register TE97_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_10 0x81988 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_10 0x1FF81988u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_10 Register TE97_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_10 0x81990 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_10 0x1FF81990u //! Register Reset Value #define TE97_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_10 Register TE97_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_10 0x81998 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_10 0x1FF81998u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_11 Register TE97_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_11 0x819A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_11 0x1FF819A0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_11 Register TE97_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_11 0x819A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_11 0x1FF819A8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_11 Register TE97_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_11 0x819B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_11 0x1FF819B0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_11 Register TE97_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_11 0x819B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_11 0x1FF819B8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_12 Register TE97_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_12 0x819C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_12 0x1FF819C0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_12 Register TE97_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_12 0x819C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_12 0x1FF819C8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_12 Register TE97_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_12 0x819D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_12 0x1FF819D0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_12 Register TE97_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_12 0x819D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_12 0x1FF819D8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_13 Register TE97_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_13 0x819E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_13 0x1FF819E0u //! Register Reset Value #define TE97_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_13 Register TE97_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_13 0x819E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_13 0x1FF819E8u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_13 Register TE97_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_13 0x819F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_13 0x1FF819F0u //! Register Reset Value #define TE97_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_13 Register TE97_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_13 0x819F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_13 0x1FF819F8u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_14 Register TE97_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_14 0x81A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_14 0x1FF81A00u //! Register Reset Value #define TE97_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_14 Register TE97_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_14 0x81A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_14 0x1FF81A08u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_14 Register TE97_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_14 0x81A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_14 0x1FF81A10u //! Register Reset Value #define TE97_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_14 Register TE97_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_14 0x81A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_14 0x1FF81A18u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_ADDR_MATCH_15 Register TE97_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TE97_PM_ADDR_MATCH_15 0x81A20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_ADDR_MATCH_15 0x1FF81A20u //! Register Reset Value #define TE97_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE97_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE97_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TE97_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TE97_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE97_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE97_PM_REQ_INFO_PERMISSION_15 Register TE97_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TE97_PM_REQ_INFO_PERMISSION_15 0x81A28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_REQ_INFO_PERMISSION_15 0x1FF81A28u //! Register Reset Value #define TE97_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE97_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE97_PM_READ_PERMISSION_15 Register TE97_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TE97_PM_READ_PERMISSION_15 0x81A30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_READ_PERMISSION_15 0x1FF81A30u //! Register Reset Value #define TE97_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE97_PM_WRITE_PERMISSION_15 Register TE97_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TE97_PM_WRITE_PERMISSION_15 0x81A38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE97_PM_WRITE_PERMISSION_15 0x1FF81A38u //! Register Reset Value #define TE97_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE97_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ERROR_LOG Register TE123_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TE123_PM_ERROR_LOG 0x81C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ERROR_LOG 0x1FF81C20u //! Register Reset Value #define TE123_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TE123_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TE123_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TE123_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TE123_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TE123_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TE123_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TE123_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TE123_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TE123_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TE123_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TE123_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TE123_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TE123_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TE123_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TE123_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TE123_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TE123_PM_CONTROL Register TE123_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TE123_PM_CONTROL 0x81C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_CONTROL 0x1FF81C28u //! Register Reset Value #define TE123_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TE123_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TE123_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TE123_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TE123_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TE123_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TE123_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TE123_PM_ERROR_CLEAR_SINGLE Register TE123_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TE123_PM_ERROR_CLEAR_SINGLE 0x81C30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ERROR_CLEAR_SINGLE 0x1FF81C30u //! Register Reset Value #define TE123_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TE123_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TE123_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TE123_PM_ERROR_CLEAR_MULTI Register TE123_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TE123_PM_ERROR_CLEAR_MULTI 0x81C38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ERROR_CLEAR_MULTI 0x1FF81C38u //! Register Reset Value #define TE123_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TE123_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TE123_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_0 Register TE123_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_0 0x81C48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_0 0x1FF81C48u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_0 Register TE123_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_0 0x81C50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_0 0x1FF81C50u //! Register Reset Value #define TE123_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_0 Register TE123_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_0 0x81C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_0 0x1FF81C58u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TE123_PM_ADDR_MATCH_1 Register TE123_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_1 0x81C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_1 0x1FF81C60u //! Register Reset Value #define TE123_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_1 Register TE123_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_1 0x81C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_1 0x1FF81C68u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_1 Register TE123_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_1 0x81C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_1 0x1FF81C70u //! Register Reset Value #define TE123_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_1 Register TE123_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_1 0x81C78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_1 0x1FF81C78u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_2 Register TE123_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_2 0x81C80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_2 0x1FF81C80u //! Register Reset Value #define TE123_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_2 Register TE123_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_2 0x81C88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_2 0x1FF81C88u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_2 Register TE123_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_2 0x81C90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_2 0x1FF81C90u //! Register Reset Value #define TE123_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_2 Register TE123_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_2 0x81C98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_2 0x1FF81C98u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_3 Register TE123_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_3 0x81CA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_3 0x1FF81CA0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_3 Register TE123_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_3 0x81CA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_3 0x1FF81CA8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_3 Register TE123_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_3 0x81CB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_3 0x1FF81CB0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_3 Register TE123_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_3 0x81CB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_3 0x1FF81CB8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_4 Register TE123_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_4 0x81CC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_4 0x1FF81CC0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_4 Register TE123_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_4 0x81CC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_4 0x1FF81CC8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_4 Register TE123_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_4 0x81CD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_4 0x1FF81CD0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_4 Register TE123_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_4 0x81CD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_4 0x1FF81CD8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_5 Register TE123_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_5 0x81CE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_5 0x1FF81CE0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_5 Register TE123_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_5 0x81CE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_5 0x1FF81CE8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_5 Register TE123_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_5 0x81CF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_5 0x1FF81CF0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_5 Register TE123_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_5 0x81CF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_5 0x1FF81CF8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_6 Register TE123_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_6 0x81D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_6 0x1FF81D00u //! Register Reset Value #define TE123_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_6 Register TE123_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_6 0x81D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_6 0x1FF81D08u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_6 Register TE123_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_6 0x81D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_6 0x1FF81D10u //! Register Reset Value #define TE123_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_6 Register TE123_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_6 0x81D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_6 0x1FF81D18u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_7 Register TE123_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_7 0x81D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_7 0x1FF81D20u //! Register Reset Value #define TE123_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_7 Register TE123_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_7 0x81D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_7 0x1FF81D28u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_7 Register TE123_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_7 0x81D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_7 0x1FF81D30u //! Register Reset Value #define TE123_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_7 Register TE123_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_7 0x81D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_7 0x1FF81D38u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_8 Register TE123_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_8 0x81D40 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_8 0x1FF81D40u //! Register Reset Value #define TE123_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_8 Register TE123_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_8 0x81D48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_8 0x1FF81D48u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_8 Register TE123_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_8 0x81D50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_8 0x1FF81D50u //! Register Reset Value #define TE123_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_8 Register TE123_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_8 0x81D58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_8 0x1FF81D58u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_9 Register TE123_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_9 0x81D60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_9 0x1FF81D60u //! Register Reset Value #define TE123_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_9 Register TE123_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_9 0x81D68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_9 0x1FF81D68u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_9 Register TE123_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_9 0x81D70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_9 0x1FF81D70u //! Register Reset Value #define TE123_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_9 Register TE123_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_9 0x81D78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_9 0x1FF81D78u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_10 Register TE123_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_10 0x81D80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_10 0x1FF81D80u //! Register Reset Value #define TE123_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_10 Register TE123_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_10 0x81D88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_10 0x1FF81D88u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_10 Register TE123_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_10 0x81D90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_10 0x1FF81D90u //! Register Reset Value #define TE123_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_10 Register TE123_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_10 0x81D98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_10 0x1FF81D98u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_11 Register TE123_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_11 0x81DA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_11 0x1FF81DA0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_11 Register TE123_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_11 0x81DA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_11 0x1FF81DA8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_11 Register TE123_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_11 0x81DB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_11 0x1FF81DB0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_11 Register TE123_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_11 0x81DB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_11 0x1FF81DB8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_12 Register TE123_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_12 0x81DC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_12 0x1FF81DC0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_12 Register TE123_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_12 0x81DC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_12 0x1FF81DC8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_12 Register TE123_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_12 0x81DD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_12 0x1FF81DD0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_12 Register TE123_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_12 0x81DD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_12 0x1FF81DD8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_13 Register TE123_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_13 0x81DE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_13 0x1FF81DE0u //! Register Reset Value #define TE123_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_13 Register TE123_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_13 0x81DE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_13 0x1FF81DE8u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_13 Register TE123_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_13 0x81DF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_13 0x1FF81DF0u //! Register Reset Value #define TE123_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_13 Register TE123_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_13 0x81DF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_13 0x1FF81DF8u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_14 Register TE123_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_14 0x81E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_14 0x1FF81E00u //! Register Reset Value #define TE123_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_14 Register TE123_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_14 0x81E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_14 0x1FF81E08u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_14 Register TE123_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_14 0x81E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_14 0x1FF81E10u //! Register Reset Value #define TE123_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_14 Register TE123_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_14 0x81E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_14 0x1FF81E18u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_ADDR_MATCH_15 Register TE123_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TE123_PM_ADDR_MATCH_15 0x81E20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_ADDR_MATCH_15 0x1FF81E20u //! Register Reset Value #define TE123_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TE123_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TE123_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TE123_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TE123_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TE123_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TE123_PM_REQ_INFO_PERMISSION_15 Register TE123_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TE123_PM_REQ_INFO_PERMISSION_15 0x81E28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_REQ_INFO_PERMISSION_15 0x1FF81E28u //! Register Reset Value #define TE123_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TE123_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TE123_PM_READ_PERMISSION_15 Register TE123_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TE123_PM_READ_PERMISSION_15 0x81E30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_READ_PERMISSION_15 0x1FF81E30u //! Register Reset Value #define TE123_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TE123_PM_WRITE_PERMISSION_15 Register TE123_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TE123_PM_WRITE_PERMISSION_15 0x81E38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TE123_PM_WRITE_PERMISSION_15 0x1FF81E38u //! Register Reset Value #define TE123_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TE123_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ERROR_LOG Register TDM3_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TDM3_PM_ERROR_LOG 0x82020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ERROR_LOG 0x1FF82020u //! Register Reset Value #define TDM3_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TDM3_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TDM3_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TDM3_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TDM3_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TDM3_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TDM3_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TDM3_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TDM3_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TDM3_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TDM3_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TDM3_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TDM3_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TDM3_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TDM3_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TDM3_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TDM3_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TDM3_PM_CONTROL Register TDM3_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TDM3_PM_CONTROL 0x82028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_CONTROL 0x1FF82028u //! Register Reset Value #define TDM3_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TDM3_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TDM3_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TDM3_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TDM3_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TDM3_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TDM3_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TDM3_PM_ERROR_CLEAR_SINGLE Register TDM3_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TDM3_PM_ERROR_CLEAR_SINGLE 0x82030 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ERROR_CLEAR_SINGLE 0x1FF82030u //! Register Reset Value #define TDM3_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TDM3_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TDM3_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TDM3_PM_ERROR_CLEAR_MULTI Register TDM3_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TDM3_PM_ERROR_CLEAR_MULTI 0x82038 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ERROR_CLEAR_MULTI 0x1FF82038u //! Register Reset Value #define TDM3_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TDM3_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TDM3_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_0 Register TDM3_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_0 0x82048 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_0 0x1FF82048u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_0 Register TDM3_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_0 0x82050 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_0 0x1FF82050u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_0 Register TDM3_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_0 0x82058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_0 0x1FF82058u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_1 Register TDM3_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_1 0x82060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_1 0x1FF82060u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_1 Register TDM3_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_1 0x82068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_1 0x1FF82068u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_1 Register TDM3_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_1 0x82070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_1 0x1FF82070u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_1 Register TDM3_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_1 0x82078 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_1 0x1FF82078u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_2 Register TDM3_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_2 0x82080 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_2 0x1FF82080u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_2 Register TDM3_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_2 0x82088 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_2 0x1FF82088u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_2 Register TDM3_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_2 0x82090 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_2 0x1FF82090u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_2 Register TDM3_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_2 0x82098 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_2 0x1FF82098u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_3 Register TDM3_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_3 0x820A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_3 0x1FF820A0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_3 Register TDM3_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_3 0x820A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_3 0x1FF820A8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_3 Register TDM3_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_3 0x820B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_3 0x1FF820B0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_3 Register TDM3_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_3 0x820B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_3 0x1FF820B8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_4 Register TDM3_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_4 0x820C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_4 0x1FF820C0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_4 Register TDM3_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_4 0x820C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_4 0x1FF820C8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_4 Register TDM3_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_4 0x820D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_4 0x1FF820D0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_4 Register TDM3_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_4 0x820D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_4 0x1FF820D8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_5 Register TDM3_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_5 0x820E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_5 0x1FF820E0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_5 Register TDM3_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_5 0x820E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_5 0x1FF820E8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_5 Register TDM3_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_5 0x820F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_5 0x1FF820F0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_5 Register TDM3_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_5 0x820F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_5 0x1FF820F8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_6 Register TDM3_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_6 0x82100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_6 0x1FF82100u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_6 Register TDM3_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_6 0x82108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_6 0x1FF82108u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_6 Register TDM3_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_6 0x82110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_6 0x1FF82110u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_6 Register TDM3_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_6 0x82118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_6 0x1FF82118u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_7 Register TDM3_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_7 0x82120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_7 0x1FF82120u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_7 Register TDM3_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_7 0x82128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_7 0x1FF82128u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_7 Register TDM3_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_7 0x82130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_7 0x1FF82130u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_7 Register TDM3_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_7 0x82138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_7 0x1FF82138u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_8 Register TDM3_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_8 0x82140 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_8 0x1FF82140u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_8 Register TDM3_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_8 0x82148 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_8 0x1FF82148u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_8 Register TDM3_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_8 0x82150 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_8 0x1FF82150u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_8 Register TDM3_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_8 0x82158 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_8 0x1FF82158u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_9 Register TDM3_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_9 0x82160 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_9 0x1FF82160u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_9 Register TDM3_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_9 0x82168 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_9 0x1FF82168u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_9 Register TDM3_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_9 0x82170 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_9 0x1FF82170u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_9 Register TDM3_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_9 0x82178 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_9 0x1FF82178u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_10 Register TDM3_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_10 0x82180 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_10 0x1FF82180u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_10 Register TDM3_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_10 0x82188 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_10 0x1FF82188u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_10 Register TDM3_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_10 0x82190 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_10 0x1FF82190u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_10 Register TDM3_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_10 0x82198 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_10 0x1FF82198u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_11 Register TDM3_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_11 0x821A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_11 0x1FF821A0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_11 Register TDM3_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_11 0x821A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_11 0x1FF821A8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_11 Register TDM3_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_11 0x821B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_11 0x1FF821B0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_11 Register TDM3_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_11 0x821B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_11 0x1FF821B8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_12 Register TDM3_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_12 0x821C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_12 0x1FF821C0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_12 Register TDM3_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_12 0x821C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_12 0x1FF821C8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_12 Register TDM3_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_12 0x821D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_12 0x1FF821D0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_12 Register TDM3_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_12 0x821D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_12 0x1FF821D8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_13 Register TDM3_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_13 0x821E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_13 0x1FF821E0u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_13 Register TDM3_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_13 0x821E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_13 0x1FF821E8u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_13 Register TDM3_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_13 0x821F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_13 0x1FF821F0u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_13 Register TDM3_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_13 0x821F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_13 0x1FF821F8u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_14 Register TDM3_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_14 0x82200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_14 0x1FF82200u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_14 Register TDM3_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_14 0x82208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_14 0x1FF82208u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_14 Register TDM3_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_14 0x82210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_14 0x1FF82210u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_14 Register TDM3_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_14 0x82218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_14 0x1FF82218u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_ADDR_MATCH_15 Register TDM3_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TDM3_PM_ADDR_MATCH_15 0x82220 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_ADDR_MATCH_15 0x1FF82220u //! Register Reset Value #define TDM3_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM3_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TDM3_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TDM3_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM3_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM3_PM_REQ_INFO_PERMISSION_15 Register TDM3_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TDM3_PM_REQ_INFO_PERMISSION_15 0x82228 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_REQ_INFO_PERMISSION_15 0x1FF82228u //! Register Reset Value #define TDM3_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM3_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM3_PM_READ_PERMISSION_15 Register TDM3_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TDM3_PM_READ_PERMISSION_15 0x82230 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_READ_PERMISSION_15 0x1FF82230u //! Register Reset Value #define TDM3_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM3_PM_WRITE_PERMISSION_15 Register TDM3_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TDM3_PM_WRITE_PERMISSION_15 0x82238 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM3_PM_WRITE_PERMISSION_15 0x1FF82238u //! Register Reset Value #define TDM3_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM3_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ERROR_LOG Register TDM4_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TDM4_PM_ERROR_LOG 0x82420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ERROR_LOG 0x1FF82420u //! Register Reset Value #define TDM4_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TDM4_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TDM4_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TDM4_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TDM4_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TDM4_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TDM4_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TDM4_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TDM4_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TDM4_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TDM4_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TDM4_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TDM4_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TDM4_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TDM4_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TDM4_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TDM4_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TDM4_PM_CONTROL Register TDM4_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TDM4_PM_CONTROL 0x82428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_CONTROL 0x1FF82428u //! Register Reset Value #define TDM4_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TDM4_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TDM4_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TDM4_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TDM4_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TDM4_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TDM4_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TDM4_PM_ERROR_CLEAR_SINGLE Register TDM4_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TDM4_PM_ERROR_CLEAR_SINGLE 0x82430 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ERROR_CLEAR_SINGLE 0x1FF82430u //! Register Reset Value #define TDM4_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TDM4_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TDM4_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TDM4_PM_ERROR_CLEAR_MULTI Register TDM4_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TDM4_PM_ERROR_CLEAR_MULTI 0x82438 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ERROR_CLEAR_MULTI 0x1FF82438u //! Register Reset Value #define TDM4_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TDM4_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TDM4_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_0 Register TDM4_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_0 0x82448 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_0 0x1FF82448u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_0 Register TDM4_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_0 0x82450 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_0 0x1FF82450u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_0 Register TDM4_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_0 0x82458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_0 0x1FF82458u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_1 Register TDM4_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_1 0x82460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_1 0x1FF82460u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_1 Register TDM4_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_1 0x82468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_1 0x1FF82468u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_1 Register TDM4_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_1 0x82470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_1 0x1FF82470u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_1 Register TDM4_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_1 0x82478 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_1 0x1FF82478u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_2 Register TDM4_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_2 0x82480 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_2 0x1FF82480u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_2 Register TDM4_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_2 0x82488 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_2 0x1FF82488u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_2 Register TDM4_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_2 0x82490 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_2 0x1FF82490u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_2 Register TDM4_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_2 0x82498 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_2 0x1FF82498u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_3 Register TDM4_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_3 0x824A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_3 0x1FF824A0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_3 Register TDM4_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_3 0x824A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_3 0x1FF824A8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_3 Register TDM4_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_3 0x824B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_3 0x1FF824B0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_3 Register TDM4_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_3 0x824B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_3 0x1FF824B8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_4 Register TDM4_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_4 0x824C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_4 0x1FF824C0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_4 Register TDM4_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_4 0x824C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_4 0x1FF824C8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_4 Register TDM4_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_4 0x824D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_4 0x1FF824D0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_4 Register TDM4_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_4 0x824D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_4 0x1FF824D8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_5 Register TDM4_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_5 0x824E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_5 0x1FF824E0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_5 Register TDM4_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_5 0x824E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_5 0x1FF824E8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_5 Register TDM4_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_5 0x824F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_5 0x1FF824F0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_5 Register TDM4_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_5 0x824F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_5 0x1FF824F8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_6 Register TDM4_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_6 0x82500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_6 0x1FF82500u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_6 Register TDM4_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_6 0x82508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_6 0x1FF82508u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_6 Register TDM4_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_6 0x82510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_6 0x1FF82510u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_6 Register TDM4_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_6 0x82518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_6 0x1FF82518u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_7 Register TDM4_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_7 0x82520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_7 0x1FF82520u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_7 Register TDM4_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_7 0x82528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_7 0x1FF82528u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_7 Register TDM4_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_7 0x82530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_7 0x1FF82530u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_7 Register TDM4_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_7 0x82538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_7 0x1FF82538u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_8 Register TDM4_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_8 0x82540 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_8 0x1FF82540u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_8 Register TDM4_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_8 0x82548 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_8 0x1FF82548u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_8 Register TDM4_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_8 0x82550 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_8 0x1FF82550u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_8 Register TDM4_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_8 0x82558 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_8 0x1FF82558u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_9 Register TDM4_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_9 0x82560 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_9 0x1FF82560u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_9 Register TDM4_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_9 0x82568 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_9 0x1FF82568u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_9 Register TDM4_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_9 0x82570 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_9 0x1FF82570u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_9 Register TDM4_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_9 0x82578 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_9 0x1FF82578u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_10 Register TDM4_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_10 0x82580 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_10 0x1FF82580u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_10 Register TDM4_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_10 0x82588 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_10 0x1FF82588u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_10 Register TDM4_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_10 0x82590 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_10 0x1FF82590u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_10 Register TDM4_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_10 0x82598 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_10 0x1FF82598u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_11 Register TDM4_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_11 0x825A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_11 0x1FF825A0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_11 Register TDM4_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_11 0x825A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_11 0x1FF825A8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_11 Register TDM4_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_11 0x825B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_11 0x1FF825B0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_11 Register TDM4_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_11 0x825B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_11 0x1FF825B8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_12 Register TDM4_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_12 0x825C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_12 0x1FF825C0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_12 Register TDM4_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_12 0x825C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_12 0x1FF825C8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_12 Register TDM4_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_12 0x825D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_12 0x1FF825D0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_12 Register TDM4_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_12 0x825D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_12 0x1FF825D8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_13 Register TDM4_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_13 0x825E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_13 0x1FF825E0u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_13 Register TDM4_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_13 0x825E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_13 0x1FF825E8u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_13 Register TDM4_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_13 0x825F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_13 0x1FF825F0u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_13 Register TDM4_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_13 0x825F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_13 0x1FF825F8u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_14 Register TDM4_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_14 0x82600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_14 0x1FF82600u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_14 Register TDM4_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_14 0x82608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_14 0x1FF82608u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_14 Register TDM4_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_14 0x82610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_14 0x1FF82610u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_14 Register TDM4_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_14 0x82618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_14 0x1FF82618u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_ADDR_MATCH_15 Register TDM4_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TDM4_PM_ADDR_MATCH_15 0x82620 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_ADDR_MATCH_15 0x1FF82620u //! Register Reset Value #define TDM4_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TDM4_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TDM4_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TDM4_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TDM4_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TDM4_PM_REQ_INFO_PERMISSION_15 Register TDM4_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TDM4_PM_REQ_INFO_PERMISSION_15 0x82628 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_REQ_INFO_PERMISSION_15 0x1FF82628u //! Register Reset Value #define TDM4_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TDM4_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TDM4_PM_READ_PERMISSION_15 Register TDM4_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TDM4_PM_READ_PERMISSION_15 0x82630 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_READ_PERMISSION_15 0x1FF82630u //! Register Reset Value #define TDM4_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TDM4_PM_WRITE_PERMISSION_15 Register TDM4_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TDM4_PM_WRITE_PERMISSION_15 0x82638 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TDM4_PM_WRITE_PERMISSION_15 0x1FF82638u //! Register Reset Value #define TDM4_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TDM4_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ERROR_LOG Register TLN01_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN01_PM_ERROR_LOG 0x82820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ERROR_LOG 0x1FF82820u //! Register Reset Value #define TLN01_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN01_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN01_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TLN01_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TLN01_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TLN01_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN01_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TLN01_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TLN01_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TLN01_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN01_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TLN01_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TLN01_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TLN01_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN01_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TLN01_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TLN01_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TLN01_PM_CONTROL Register TLN01_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TLN01_PM_CONTROL 0x82828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_CONTROL 0x1FF82828u //! Register Reset Value #define TLN01_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN01_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN01_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN01_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN01_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN01_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN01_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TLN01_PM_ERROR_CLEAR_SINGLE Register TLN01_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TLN01_PM_ERROR_CLEAR_SINGLE 0x82830 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ERROR_CLEAR_SINGLE 0x1FF82830u //! Register Reset Value #define TLN01_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN01_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TLN01_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TLN01_PM_ERROR_CLEAR_MULTI Register TLN01_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TLN01_PM_ERROR_CLEAR_MULTI 0x82838 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ERROR_CLEAR_MULTI 0x1FF82838u //! Register Reset Value #define TLN01_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN01_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TLN01_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_0 Register TLN01_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_0 0x82848 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_0 0x1FF82848u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_0 Register TLN01_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_0 0x82850 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_0 0x1FF82850u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_0 Register TLN01_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_0 0x82858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_0 0x1FF82858u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_1 Register TLN01_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_1 0x82860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_1 0x1FF82860u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_1 Register TLN01_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_1 0x82868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_1 0x1FF82868u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_1 Register TLN01_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_1 0x82870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_1 0x1FF82870u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_1 Register TLN01_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_1 0x82878 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_1 0x1FF82878u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_2 Register TLN01_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_2 0x82880 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_2 0x1FF82880u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_2 Register TLN01_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_2 0x82888 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_2 0x1FF82888u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_2 Register TLN01_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_2 0x82890 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_2 0x1FF82890u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_2 Register TLN01_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_2 0x82898 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_2 0x1FF82898u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_3 Register TLN01_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_3 0x828A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_3 0x1FF828A0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_3 Register TLN01_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_3 0x828A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_3 0x1FF828A8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_3 Register TLN01_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_3 0x828B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_3 0x1FF828B0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_3 Register TLN01_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_3 0x828B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_3 0x1FF828B8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_4 Register TLN01_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_4 0x828C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_4 0x1FF828C0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_4 Register TLN01_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_4 0x828C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_4 0x1FF828C8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_4 Register TLN01_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_4 0x828D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_4 0x1FF828D0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_4 Register TLN01_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_4 0x828D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_4 0x1FF828D8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_5 Register TLN01_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_5 0x828E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_5 0x1FF828E0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_5 Register TLN01_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_5 0x828E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_5 0x1FF828E8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_5 Register TLN01_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_5 0x828F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_5 0x1FF828F0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_5 Register TLN01_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_5 0x828F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_5 0x1FF828F8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_6 Register TLN01_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_6 0x82900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_6 0x1FF82900u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_6 Register TLN01_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_6 0x82908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_6 0x1FF82908u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_6 Register TLN01_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_6 0x82910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_6 0x1FF82910u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_6 Register TLN01_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_6 0x82918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_6 0x1FF82918u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_7 Register TLN01_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_7 0x82920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_7 0x1FF82920u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_7 Register TLN01_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_7 0x82928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_7 0x1FF82928u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_7 Register TLN01_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_7 0x82930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_7 0x1FF82930u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_7 Register TLN01_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_7 0x82938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_7 0x1FF82938u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_8 Register TLN01_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_8 0x82940 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_8 0x1FF82940u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_8 Register TLN01_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_8 0x82948 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_8 0x1FF82948u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_8 Register TLN01_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_8 0x82950 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_8 0x1FF82950u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_8 Register TLN01_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_8 0x82958 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_8 0x1FF82958u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_9 Register TLN01_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_9 0x82960 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_9 0x1FF82960u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_9 Register TLN01_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_9 0x82968 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_9 0x1FF82968u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_9 Register TLN01_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_9 0x82970 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_9 0x1FF82970u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_9 Register TLN01_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_9 0x82978 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_9 0x1FF82978u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_10 Register TLN01_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_10 0x82980 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_10 0x1FF82980u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_10 Register TLN01_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_10 0x82988 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_10 0x1FF82988u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_10 Register TLN01_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_10 0x82990 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_10 0x1FF82990u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_10 Register TLN01_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_10 0x82998 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_10 0x1FF82998u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_11 Register TLN01_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_11 0x829A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_11 0x1FF829A0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_11 Register TLN01_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_11 0x829A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_11 0x1FF829A8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_11 Register TLN01_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_11 0x829B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_11 0x1FF829B0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_11 Register TLN01_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_11 0x829B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_11 0x1FF829B8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_12 Register TLN01_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_12 0x829C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_12 0x1FF829C0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_12 Register TLN01_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_12 0x829C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_12 0x1FF829C8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_12 Register TLN01_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_12 0x829D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_12 0x1FF829D0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_12 Register TLN01_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_12 0x829D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_12 0x1FF829D8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_13 Register TLN01_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_13 0x829E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_13 0x1FF829E0u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_13 Register TLN01_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_13 0x829E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_13 0x1FF829E8u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_13 Register TLN01_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_13 0x829F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_13 0x1FF829F0u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_13 Register TLN01_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_13 0x829F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_13 0x1FF829F8u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_14 Register TLN01_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_14 0x82A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_14 0x1FF82A00u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_14 Register TLN01_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_14 0x82A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_14 0x1FF82A08u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_14 Register TLN01_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_14 0x82A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_14 0x1FF82A10u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_14 Register TLN01_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_14 0x82A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_14 0x1FF82A18u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_ADDR_MATCH_15 Register TLN01_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TLN01_PM_ADDR_MATCH_15 0x82A20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_ADDR_MATCH_15 0x1FF82A20u //! Register Reset Value #define TLN01_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN01_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TLN01_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TLN01_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN01_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN01_PM_REQ_INFO_PERMISSION_15 Register TLN01_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TLN01_PM_REQ_INFO_PERMISSION_15 0x82A28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_REQ_INFO_PERMISSION_15 0x1FF82A28u //! Register Reset Value #define TLN01_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN01_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN01_PM_READ_PERMISSION_15 Register TLN01_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TLN01_PM_READ_PERMISSION_15 0x82A30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_READ_PERMISSION_15 0x1FF82A30u //! Register Reset Value #define TLN01_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN01_PM_WRITE_PERMISSION_15 Register TLN01_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TLN01_PM_WRITE_PERMISSION_15 0x82A38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN01_PM_WRITE_PERMISSION_15 0x1FF82A38u //! Register Reset Value #define TLN01_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN01_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ERROR_LOG Register TLN02_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN02_PM_ERROR_LOG 0x82C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ERROR_LOG 0x1FF82C20u //! Register Reset Value #define TLN02_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN02_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN02_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TLN02_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TLN02_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TLN02_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN02_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TLN02_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TLN02_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TLN02_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN02_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TLN02_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TLN02_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TLN02_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN02_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TLN02_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TLN02_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TLN02_PM_CONTROL Register TLN02_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TLN02_PM_CONTROL 0x82C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_CONTROL 0x1FF82C28u //! Register Reset Value #define TLN02_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN02_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN02_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN02_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN02_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN02_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN02_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TLN02_PM_ERROR_CLEAR_SINGLE Register TLN02_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TLN02_PM_ERROR_CLEAR_SINGLE 0x82C30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ERROR_CLEAR_SINGLE 0x1FF82C30u //! Register Reset Value #define TLN02_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN02_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TLN02_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TLN02_PM_ERROR_CLEAR_MULTI Register TLN02_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TLN02_PM_ERROR_CLEAR_MULTI 0x82C38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ERROR_CLEAR_MULTI 0x1FF82C38u //! Register Reset Value #define TLN02_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN02_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TLN02_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_0 Register TLN02_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_0 0x82C48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_0 0x1FF82C48u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_0 Register TLN02_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_0 0x82C50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_0 0x1FF82C50u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_0 Register TLN02_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_0 0x82C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_0 0x1FF82C58u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_1 Register TLN02_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_1 0x82C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_1 0x1FF82C60u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_1 Register TLN02_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_1 0x82C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_1 0x1FF82C68u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_1 Register TLN02_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_1 0x82C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_1 0x1FF82C70u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_1 Register TLN02_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_1 0x82C78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_1 0x1FF82C78u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_2 Register TLN02_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_2 0x82C80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_2 0x1FF82C80u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_2 Register TLN02_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_2 0x82C88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_2 0x1FF82C88u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_2 Register TLN02_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_2 0x82C90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_2 0x1FF82C90u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_2 Register TLN02_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_2 0x82C98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_2 0x1FF82C98u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_3 Register TLN02_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_3 0x82CA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_3 0x1FF82CA0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_3 Register TLN02_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_3 0x82CA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_3 0x1FF82CA8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_3 Register TLN02_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_3 0x82CB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_3 0x1FF82CB0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_3 Register TLN02_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_3 0x82CB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_3 0x1FF82CB8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_4 Register TLN02_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_4 0x82CC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_4 0x1FF82CC0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_4 Register TLN02_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_4 0x82CC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_4 0x1FF82CC8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_4 Register TLN02_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_4 0x82CD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_4 0x1FF82CD0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_4 Register TLN02_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_4 0x82CD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_4 0x1FF82CD8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_5 Register TLN02_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_5 0x82CE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_5 0x1FF82CE0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_5 Register TLN02_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_5 0x82CE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_5 0x1FF82CE8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_5 Register TLN02_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_5 0x82CF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_5 0x1FF82CF0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_5 Register TLN02_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_5 0x82CF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_5 0x1FF82CF8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_6 Register TLN02_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_6 0x82D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_6 0x1FF82D00u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_6 Register TLN02_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_6 0x82D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_6 0x1FF82D08u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_6 Register TLN02_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_6 0x82D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_6 0x1FF82D10u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_6 Register TLN02_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_6 0x82D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_6 0x1FF82D18u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_7 Register TLN02_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_7 0x82D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_7 0x1FF82D20u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_7 Register TLN02_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_7 0x82D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_7 0x1FF82D28u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_7 Register TLN02_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_7 0x82D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_7 0x1FF82D30u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_7 Register TLN02_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_7 0x82D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_7 0x1FF82D38u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_8 Register TLN02_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_8 0x82D40 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_8 0x1FF82D40u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_8 Register TLN02_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_8 0x82D48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_8 0x1FF82D48u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_8 Register TLN02_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_8 0x82D50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_8 0x1FF82D50u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_8 Register TLN02_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_8 0x82D58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_8 0x1FF82D58u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_9 Register TLN02_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_9 0x82D60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_9 0x1FF82D60u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_9 Register TLN02_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_9 0x82D68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_9 0x1FF82D68u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_9 Register TLN02_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_9 0x82D70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_9 0x1FF82D70u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_9 Register TLN02_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_9 0x82D78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_9 0x1FF82D78u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_10 Register TLN02_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_10 0x82D80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_10 0x1FF82D80u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_10 Register TLN02_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_10 0x82D88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_10 0x1FF82D88u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_10 Register TLN02_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_10 0x82D90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_10 0x1FF82D90u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_10 Register TLN02_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_10 0x82D98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_10 0x1FF82D98u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_11 Register TLN02_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_11 0x82DA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_11 0x1FF82DA0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_11 Register TLN02_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_11 0x82DA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_11 0x1FF82DA8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_11 Register TLN02_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_11 0x82DB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_11 0x1FF82DB0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_11 Register TLN02_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_11 0x82DB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_11 0x1FF82DB8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_12 Register TLN02_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_12 0x82DC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_12 0x1FF82DC0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_12 Register TLN02_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_12 0x82DC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_12 0x1FF82DC8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_12 Register TLN02_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_12 0x82DD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_12 0x1FF82DD0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_12 Register TLN02_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_12 0x82DD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_12 0x1FF82DD8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_13 Register TLN02_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_13 0x82DE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_13 0x1FF82DE0u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_13 Register TLN02_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_13 0x82DE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_13 0x1FF82DE8u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_13 Register TLN02_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_13 0x82DF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_13 0x1FF82DF0u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_13 Register TLN02_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_13 0x82DF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_13 0x1FF82DF8u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_14 Register TLN02_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_14 0x82E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_14 0x1FF82E00u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_14 Register TLN02_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_14 0x82E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_14 0x1FF82E08u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_14 Register TLN02_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_14 0x82E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_14 0x1FF82E10u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_14 Register TLN02_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_14 0x82E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_14 0x1FF82E18u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_ADDR_MATCH_15 Register TLN02_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TLN02_PM_ADDR_MATCH_15 0x82E20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_ADDR_MATCH_15 0x1FF82E20u //! Register Reset Value #define TLN02_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN02_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TLN02_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TLN02_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN02_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN02_PM_REQ_INFO_PERMISSION_15 Register TLN02_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TLN02_PM_REQ_INFO_PERMISSION_15 0x82E28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_REQ_INFO_PERMISSION_15 0x1FF82E28u //! Register Reset Value #define TLN02_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN02_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN02_PM_READ_PERMISSION_15 Register TLN02_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TLN02_PM_READ_PERMISSION_15 0x82E30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_READ_PERMISSION_15 0x1FF82E30u //! Register Reset Value #define TLN02_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN02_PM_WRITE_PERMISSION_15 Register TLN02_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TLN02_PM_WRITE_PERMISSION_15 0x82E38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN02_PM_WRITE_PERMISSION_15 0x1FF82E38u //! Register Reset Value #define TLN02_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN02_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ERROR_LOG Register TLN03_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN03_PM_ERROR_LOG 0x83020 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ERROR_LOG 0x1FF83020u //! Register Reset Value #define TLN03_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN03_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN03_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TLN03_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TLN03_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TLN03_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN03_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TLN03_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TLN03_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TLN03_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN03_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TLN03_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TLN03_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TLN03_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN03_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TLN03_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TLN03_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TLN03_PM_CONTROL Register TLN03_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TLN03_PM_CONTROL 0x83028 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_CONTROL 0x1FF83028u //! Register Reset Value #define TLN03_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN03_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN03_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN03_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN03_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN03_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN03_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TLN03_PM_ERROR_CLEAR_SINGLE Register TLN03_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TLN03_PM_ERROR_CLEAR_SINGLE 0x83030 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ERROR_CLEAR_SINGLE 0x1FF83030u //! Register Reset Value #define TLN03_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN03_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TLN03_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TLN03_PM_ERROR_CLEAR_MULTI Register TLN03_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TLN03_PM_ERROR_CLEAR_MULTI 0x83038 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ERROR_CLEAR_MULTI 0x1FF83038u //! Register Reset Value #define TLN03_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN03_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TLN03_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_0 Register TLN03_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_0 0x83048 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_0 0x1FF83048u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_0 Register TLN03_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_0 0x83050 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_0 0x1FF83050u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_0 Register TLN03_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_0 0x83058 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_0 0x1FF83058u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_1 Register TLN03_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_1 0x83060 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_1 0x1FF83060u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_1 Register TLN03_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_1 0x83068 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_1 0x1FF83068u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_1 Register TLN03_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_1 0x83070 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_1 0x1FF83070u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_1 Register TLN03_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_1 0x83078 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_1 0x1FF83078u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_2 Register TLN03_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_2 0x83080 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_2 0x1FF83080u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_2 Register TLN03_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_2 0x83088 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_2 0x1FF83088u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_2 Register TLN03_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_2 0x83090 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_2 0x1FF83090u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_2 Register TLN03_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_2 0x83098 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_2 0x1FF83098u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_3 Register TLN03_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_3 0x830A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_3 0x1FF830A0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_3 Register TLN03_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_3 0x830A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_3 0x1FF830A8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_3 Register TLN03_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_3 0x830B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_3 0x1FF830B0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_3 Register TLN03_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_3 0x830B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_3 0x1FF830B8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_4 Register TLN03_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_4 0x830C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_4 0x1FF830C0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_4 Register TLN03_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_4 0x830C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_4 0x1FF830C8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_4 Register TLN03_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_4 0x830D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_4 0x1FF830D0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_4 Register TLN03_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_4 0x830D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_4 0x1FF830D8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_5 Register TLN03_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_5 0x830E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_5 0x1FF830E0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_5 Register TLN03_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_5 0x830E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_5 0x1FF830E8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_5 Register TLN03_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_5 0x830F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_5 0x1FF830F0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_5 Register TLN03_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_5 0x830F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_5 0x1FF830F8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_6 Register TLN03_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_6 0x83100 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_6 0x1FF83100u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_6 Register TLN03_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_6 0x83108 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_6 0x1FF83108u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_6 Register TLN03_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_6 0x83110 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_6 0x1FF83110u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_6 Register TLN03_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_6 0x83118 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_6 0x1FF83118u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_7 Register TLN03_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_7 0x83120 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_7 0x1FF83120u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_7 Register TLN03_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_7 0x83128 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_7 0x1FF83128u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_7 Register TLN03_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_7 0x83130 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_7 0x1FF83130u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_7 Register TLN03_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_7 0x83138 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_7 0x1FF83138u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_8 Register TLN03_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_8 0x83140 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_8 0x1FF83140u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_8 Register TLN03_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_8 0x83148 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_8 0x1FF83148u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_8 Register TLN03_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_8 0x83150 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_8 0x1FF83150u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_8 Register TLN03_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_8 0x83158 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_8 0x1FF83158u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_9 Register TLN03_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_9 0x83160 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_9 0x1FF83160u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_9 Register TLN03_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_9 0x83168 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_9 0x1FF83168u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_9 Register TLN03_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_9 0x83170 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_9 0x1FF83170u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_9 Register TLN03_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_9 0x83178 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_9 0x1FF83178u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_10 Register TLN03_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_10 0x83180 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_10 0x1FF83180u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_10 Register TLN03_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_10 0x83188 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_10 0x1FF83188u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_10 Register TLN03_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_10 0x83190 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_10 0x1FF83190u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_10 Register TLN03_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_10 0x83198 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_10 0x1FF83198u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_11 Register TLN03_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_11 0x831A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_11 0x1FF831A0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_11 Register TLN03_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_11 0x831A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_11 0x1FF831A8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_11 Register TLN03_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_11 0x831B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_11 0x1FF831B0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_11 Register TLN03_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_11 0x831B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_11 0x1FF831B8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_12 Register TLN03_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_12 0x831C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_12 0x1FF831C0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_12 Register TLN03_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_12 0x831C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_12 0x1FF831C8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_12 Register TLN03_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_12 0x831D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_12 0x1FF831D0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_12 Register TLN03_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_12 0x831D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_12 0x1FF831D8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_13 Register TLN03_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_13 0x831E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_13 0x1FF831E0u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_13 Register TLN03_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_13 0x831E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_13 0x1FF831E8u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_13 Register TLN03_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_13 0x831F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_13 0x1FF831F0u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_13 Register TLN03_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_13 0x831F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_13 0x1FF831F8u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_14 Register TLN03_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_14 0x83200 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_14 0x1FF83200u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_14 Register TLN03_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_14 0x83208 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_14 0x1FF83208u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_14 Register TLN03_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_14 0x83210 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_14 0x1FF83210u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_14 Register TLN03_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_14 0x83218 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_14 0x1FF83218u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_ADDR_MATCH_15 Register TLN03_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TLN03_PM_ADDR_MATCH_15 0x83220 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_ADDR_MATCH_15 0x1FF83220u //! Register Reset Value #define TLN03_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN03_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TLN03_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TLN03_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN03_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN03_PM_REQ_INFO_PERMISSION_15 Register TLN03_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TLN03_PM_REQ_INFO_PERMISSION_15 0x83228 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_REQ_INFO_PERMISSION_15 0x1FF83228u //! Register Reset Value #define TLN03_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN03_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN03_PM_READ_PERMISSION_15 Register TLN03_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TLN03_PM_READ_PERMISSION_15 0x83230 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_READ_PERMISSION_15 0x1FF83230u //! Register Reset Value #define TLN03_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN03_PM_WRITE_PERMISSION_15 Register TLN03_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TLN03_PM_WRITE_PERMISSION_15 0x83238 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN03_PM_WRITE_PERMISSION_15 0x1FF83238u //! Register Reset Value #define TLN03_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN03_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ERROR_LOG Register TEX04_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TEX04_PM_ERROR_LOG 0x83420 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ERROR_LOG 0x1FF83420u //! Register Reset Value #define TEX04_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TEX04_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TEX04_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TEX04_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TEX04_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TEX04_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TEX04_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TEX04_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TEX04_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TEX04_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TEX04_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TEX04_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TEX04_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TEX04_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TEX04_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TEX04_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TEX04_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TEX04_PM_CONTROL Register TEX04_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TEX04_PM_CONTROL 0x83428 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_CONTROL 0x1FF83428u //! Register Reset Value #define TEX04_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TEX04_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TEX04_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TEX04_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TEX04_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TEX04_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TEX04_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TEX04_PM_ERROR_CLEAR_SINGLE Register TEX04_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TEX04_PM_ERROR_CLEAR_SINGLE 0x83430 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ERROR_CLEAR_SINGLE 0x1FF83430u //! Register Reset Value #define TEX04_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TEX04_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TEX04_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TEX04_PM_ERROR_CLEAR_MULTI Register TEX04_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TEX04_PM_ERROR_CLEAR_MULTI 0x83438 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ERROR_CLEAR_MULTI 0x1FF83438u //! Register Reset Value #define TEX04_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TEX04_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TEX04_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_0 Register TEX04_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_0 0x83448 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_0 0x1FF83448u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_0 Register TEX04_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_0 0x83450 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_0 0x1FF83450u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_0 Register TEX04_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_0 0x83458 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_0 0x1FF83458u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_1 Register TEX04_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_1 0x83460 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_1 0x1FF83460u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_1 Register TEX04_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_1 0x83468 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_1 0x1FF83468u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_1 Register TEX04_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_1 0x83470 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_1 0x1FF83470u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_1 Register TEX04_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_1 0x83478 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_1 0x1FF83478u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_2 Register TEX04_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_2 0x83480 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_2 0x1FF83480u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_2 Register TEX04_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_2 0x83488 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_2 0x1FF83488u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_2 Register TEX04_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_2 0x83490 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_2 0x1FF83490u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_2 Register TEX04_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_2 0x83498 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_2 0x1FF83498u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_3 Register TEX04_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_3 0x834A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_3 0x1FF834A0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_3 Register TEX04_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_3 0x834A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_3 0x1FF834A8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_3 Register TEX04_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_3 0x834B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_3 0x1FF834B0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_3 Register TEX04_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_3 0x834B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_3 0x1FF834B8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_4 Register TEX04_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_4 0x834C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_4 0x1FF834C0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_4 Register TEX04_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_4 0x834C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_4 0x1FF834C8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_4 Register TEX04_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_4 0x834D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_4 0x1FF834D0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_4 Register TEX04_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_4 0x834D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_4 0x1FF834D8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_5 Register TEX04_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_5 0x834E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_5 0x1FF834E0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_5 Register TEX04_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_5 0x834E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_5 0x1FF834E8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_5 Register TEX04_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_5 0x834F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_5 0x1FF834F0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_5 Register TEX04_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_5 0x834F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_5 0x1FF834F8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_6 Register TEX04_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_6 0x83500 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_6 0x1FF83500u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_6 Register TEX04_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_6 0x83508 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_6 0x1FF83508u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_6 Register TEX04_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_6 0x83510 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_6 0x1FF83510u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_6 Register TEX04_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_6 0x83518 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_6 0x1FF83518u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_7 Register TEX04_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_7 0x83520 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_7 0x1FF83520u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_7 Register TEX04_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_7 0x83528 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_7 0x1FF83528u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_7 Register TEX04_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_7 0x83530 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_7 0x1FF83530u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_7 Register TEX04_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_7 0x83538 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_7 0x1FF83538u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_8 Register TEX04_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_8 0x83540 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_8 0x1FF83540u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_8 Register TEX04_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_8 0x83548 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_8 0x1FF83548u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_8 Register TEX04_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_8 0x83550 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_8 0x1FF83550u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_8 Register TEX04_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_8 0x83558 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_8 0x1FF83558u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_9 Register TEX04_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_9 0x83560 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_9 0x1FF83560u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_9 Register TEX04_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_9 0x83568 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_9 0x1FF83568u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_9 Register TEX04_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_9 0x83570 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_9 0x1FF83570u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_9 Register TEX04_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_9 0x83578 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_9 0x1FF83578u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_10 Register TEX04_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_10 0x83580 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_10 0x1FF83580u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_10 Register TEX04_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_10 0x83588 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_10 0x1FF83588u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_10 Register TEX04_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_10 0x83590 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_10 0x1FF83590u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_10 Register TEX04_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_10 0x83598 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_10 0x1FF83598u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_11 Register TEX04_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_11 0x835A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_11 0x1FF835A0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_11 Register TEX04_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_11 0x835A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_11 0x1FF835A8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_11 Register TEX04_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_11 0x835B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_11 0x1FF835B0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_11 Register TEX04_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_11 0x835B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_11 0x1FF835B8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_12 Register TEX04_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_12 0x835C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_12 0x1FF835C0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_12 Register TEX04_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_12 0x835C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_12 0x1FF835C8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_12 Register TEX04_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_12 0x835D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_12 0x1FF835D0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_12 Register TEX04_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_12 0x835D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_12 0x1FF835D8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_13 Register TEX04_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_13 0x835E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_13 0x1FF835E0u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_13 Register TEX04_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_13 0x835E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_13 0x1FF835E8u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_13 Register TEX04_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_13 0x835F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_13 0x1FF835F0u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_13 Register TEX04_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_13 0x835F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_13 0x1FF835F8u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_14 Register TEX04_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_14 0x83600 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_14 0x1FF83600u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_14 Register TEX04_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_14 0x83608 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_14 0x1FF83608u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_14 Register TEX04_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_14 0x83610 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_14 0x1FF83610u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_14 Register TEX04_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_14 0x83618 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_14 0x1FF83618u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_ADDR_MATCH_15 Register TEX04_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TEX04_PM_ADDR_MATCH_15 0x83620 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_ADDR_MATCH_15 0x1FF83620u //! Register Reset Value #define TEX04_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX04_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TEX04_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TEX04_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX04_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX04_PM_REQ_INFO_PERMISSION_15 Register TEX04_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TEX04_PM_REQ_INFO_PERMISSION_15 0x83628 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_REQ_INFO_PERMISSION_15 0x1FF83628u //! Register Reset Value #define TEX04_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX04_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX04_PM_READ_PERMISSION_15 Register TEX04_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TEX04_PM_READ_PERMISSION_15 0x83630 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_READ_PERMISSION_15 0x1FF83630u //! Register Reset Value #define TEX04_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX04_PM_WRITE_PERMISSION_15 Register TEX04_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TEX04_PM_WRITE_PERMISSION_15 0x83638 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX04_PM_WRITE_PERMISSION_15 0x1FF83638u //! Register Reset Value #define TEX04_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX04_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ERROR_LOG Register TEX05_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TEX05_PM_ERROR_LOG 0x83820 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ERROR_LOG 0x1FF83820u //! Register Reset Value #define TEX05_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TEX05_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TEX05_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TEX05_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TEX05_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TEX05_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TEX05_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TEX05_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TEX05_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TEX05_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TEX05_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TEX05_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TEX05_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TEX05_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TEX05_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TEX05_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TEX05_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TEX05_PM_CONTROL Register TEX05_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TEX05_PM_CONTROL 0x83828 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_CONTROL 0x1FF83828u //! Register Reset Value #define TEX05_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TEX05_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TEX05_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TEX05_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TEX05_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TEX05_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TEX05_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TEX05_PM_ERROR_CLEAR_SINGLE Register TEX05_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TEX05_PM_ERROR_CLEAR_SINGLE 0x83830 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ERROR_CLEAR_SINGLE 0x1FF83830u //! Register Reset Value #define TEX05_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TEX05_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TEX05_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TEX05_PM_ERROR_CLEAR_MULTI Register TEX05_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TEX05_PM_ERROR_CLEAR_MULTI 0x83838 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ERROR_CLEAR_MULTI 0x1FF83838u //! Register Reset Value #define TEX05_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TEX05_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TEX05_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_0 Register TEX05_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_0 0x83848 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_0 0x1FF83848u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_0 Register TEX05_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_0 0x83850 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_0 0x1FF83850u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_0 Register TEX05_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_0 0x83858 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_0 0x1FF83858u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1Fu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_1 Register TEX05_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_1 0x83860 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_1 0x1FF83860u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_1 Register TEX05_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_1 0x83868 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_1 0x1FF83868u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_1 Register TEX05_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_1 0x83870 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_1 0x1FF83870u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_1 Register TEX05_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_1 0x83878 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_1 0x1FF83878u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_2 Register TEX05_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_2 0x83880 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_2 0x1FF83880u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_2 Register TEX05_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_2 0x83888 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_2 0x1FF83888u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_2 Register TEX05_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_2 0x83890 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_2 0x1FF83890u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_2 Register TEX05_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_2 0x83898 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_2 0x1FF83898u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_3 Register TEX05_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_3 0x838A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_3 0x1FF838A0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_3 Register TEX05_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_3 0x838A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_3 0x1FF838A8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_3 Register TEX05_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_3 0x838B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_3 0x1FF838B0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_3 Register TEX05_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_3 0x838B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_3 0x1FF838B8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_4 Register TEX05_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_4 0x838C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_4 0x1FF838C0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_4 Register TEX05_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_4 0x838C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_4 0x1FF838C8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_4 Register TEX05_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_4 0x838D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_4 0x1FF838D0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_4 Register TEX05_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_4 0x838D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_4 0x1FF838D8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_5 Register TEX05_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_5 0x838E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_5 0x1FF838E0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_5 Register TEX05_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_5 0x838E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_5 0x1FF838E8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_5 Register TEX05_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_5 0x838F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_5 0x1FF838F0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_5 Register TEX05_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_5 0x838F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_5 0x1FF838F8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_6 Register TEX05_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_6 0x83900 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_6 0x1FF83900u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_6 Register TEX05_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_6 0x83908 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_6 0x1FF83908u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_6 Register TEX05_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_6 0x83910 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_6 0x1FF83910u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_6 Register TEX05_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_6 0x83918 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_6 0x1FF83918u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_7 Register TEX05_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_7 0x83920 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_7 0x1FF83920u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_7 Register TEX05_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_7 0x83928 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_7 0x1FF83928u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_7 Register TEX05_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_7 0x83930 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_7 0x1FF83930u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_7 Register TEX05_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_7 0x83938 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_7 0x1FF83938u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_8 Register TEX05_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_8 0x83940 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_8 0x1FF83940u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_8 Register TEX05_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_8 0x83948 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_8 0x1FF83948u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_8 Register TEX05_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_8 0x83950 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_8 0x1FF83950u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_8 Register TEX05_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_8 0x83958 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_8 0x1FF83958u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_9 Register TEX05_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_9 0x83960 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_9 0x1FF83960u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_9 Register TEX05_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_9 0x83968 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_9 0x1FF83968u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_9 Register TEX05_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_9 0x83970 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_9 0x1FF83970u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_9 Register TEX05_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_9 0x83978 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_9 0x1FF83978u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_10 Register TEX05_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_10 0x83980 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_10 0x1FF83980u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_10 Register TEX05_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_10 0x83988 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_10 0x1FF83988u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_10 Register TEX05_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_10 0x83990 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_10 0x1FF83990u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_10 Register TEX05_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_10 0x83998 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_10 0x1FF83998u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_11 Register TEX05_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_11 0x839A0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_11 0x1FF839A0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_11 Register TEX05_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_11 0x839A8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_11 0x1FF839A8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_11 Register TEX05_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_11 0x839B0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_11 0x1FF839B0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_11 Register TEX05_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_11 0x839B8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_11 0x1FF839B8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_12 Register TEX05_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_12 0x839C0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_12 0x1FF839C0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_12 Register TEX05_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_12 0x839C8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_12 0x1FF839C8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_12 Register TEX05_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_12 0x839D0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_12 0x1FF839D0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_12 Register TEX05_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_12 0x839D8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_12 0x1FF839D8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_13 Register TEX05_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_13 0x839E0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_13 0x1FF839E0u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_13 Register TEX05_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_13 0x839E8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_13 0x1FF839E8u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_13 Register TEX05_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_13 0x839F0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_13 0x1FF839F0u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_13 Register TEX05_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_13 0x839F8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_13 0x1FF839F8u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_14 Register TEX05_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_14 0x83A00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_14 0x1FF83A00u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_14 Register TEX05_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_14 0x83A08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_14 0x1FF83A08u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_14 Register TEX05_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_14 0x83A10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_14 0x1FF83A10u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_14 Register TEX05_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_14 0x83A18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_14 0x1FF83A18u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_ADDR_MATCH_15 Register TEX05_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TEX05_PM_ADDR_MATCH_15 0x83A20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_ADDR_MATCH_15 0x1FF83A20u //! Register Reset Value #define TEX05_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TEX05_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TEX05_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TEX05_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TEX05_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TEX05_PM_REQ_INFO_PERMISSION_15 Register TEX05_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TEX05_PM_REQ_INFO_PERMISSION_15 0x83A28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_REQ_INFO_PERMISSION_15 0x1FF83A28u //! Register Reset Value #define TEX05_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TEX05_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TEX05_PM_READ_PERMISSION_15 Register TEX05_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TEX05_PM_READ_PERMISSION_15 0x83A30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_READ_PERMISSION_15 0x1FF83A30u //! Register Reset Value #define TEX05_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEX05_PM_WRITE_PERMISSION_15 Register TEX05_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TEX05_PM_WRITE_PERMISSION_15 0x83A38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TEX05_PM_WRITE_PERMISSION_15 0x1FF83A38u //! Register Reset Value #define TEX05_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TEX05_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ERROR_LOG Register TLN06_PM_ERROR_LOG - error_log //! @{ //! Register Offset (relative) #define TLN06_PM_ERROR_LOG 0x83C20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ERROR_LOG 0x1FF83C20u //! Register Reset Value #define TLN06_PM_ERROR_LOG_RST 0x0000000000000000u //! Field CMD - cmd #define TLN06_PM_ERROR_LOG_CMD_POS 0 //! Field CMD - cmd #define TLN06_PM_ERROR_LOG_CMD_MASK 0x7u //! Field REGION - region #define TLN06_PM_ERROR_LOG_REGION_POS 4 //! Field REGION - region #define TLN06_PM_ERROR_LOG_REGION_MASK 0xF0u //! Field INITID - initid #define TLN06_PM_ERROR_LOG_INITID_POS 8 //! Field INITID - initid #define TLN06_PM_ERROR_LOG_INITID_MASK 0xFF00u //! Field REQ_INFO - req_info #define TLN06_PM_ERROR_LOG_REQ_INFO_POS 16 //! Field REQ_INFO - req_info #define TLN06_PM_ERROR_LOG_REQ_INFO_MASK 0x1F0000u //! Field CODE - code #define TLN06_PM_ERROR_LOG_CODE_POS 24 //! Field CODE - code #define TLN06_PM_ERROR_LOG_CODE_MASK 0xF000000u //! Field SECONDARY - secondary #define TLN06_PM_ERROR_LOG_SECONDARY_POS 30 //! Field SECONDARY - secondary #define TLN06_PM_ERROR_LOG_SECONDARY_MASK 0x40000000u //! Field MULTI - multi #define TLN06_PM_ERROR_LOG_MULTI_POS 31 //! Field MULTI - multi #define TLN06_PM_ERROR_LOG_MULTI_MASK 0x80000000u //! Field GROUP - group #define TLN06_PM_ERROR_LOG_GROUP_POS 32 //! Field GROUP - group #define TLN06_PM_ERROR_LOG_GROUP_MASK 0x3F00000000u //! @} //! \defgroup TLN06_PM_CONTROL Register TLN06_PM_CONTROL - control //! @{ //! Register Offset (relative) #define TLN06_PM_CONTROL 0x83C28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_CONTROL 0x1FF83C28u //! Register Reset Value #define TLN06_PM_CONTROL_RST 0x0000000000000000u //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN06_PM_CONTROL_ERROR_PRIMARY_REP_POS 24 //! Field ERROR_PRIMARY_REP - error_primary_rep #define TLN06_PM_CONTROL_ERROR_PRIMARY_REP_MASK 0x1000000u //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN06_PM_CONTROL_ERROR_SECONDARY_REP_POS 25 //! Field ERROR_SECONDARY_REP - error_secondary_rep #define TLN06_PM_CONTROL_ERROR_SECONDARY_REP_MASK 0x2000000u //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN06_PM_CONTROL_SECONDARY_REP_SHADOW_POS 30 //! Field SECONDARY_REP_SHADOW - secondary_rep_shadow #define TLN06_PM_CONTROL_SECONDARY_REP_SHADOW_MASK 0x40000000u //! @} //! \defgroup TLN06_PM_ERROR_CLEAR_SINGLE Register TLN06_PM_ERROR_CLEAR_SINGLE - error_clear_single //! @{ //! Register Offset (relative) #define TLN06_PM_ERROR_CLEAR_SINGLE 0x83C30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ERROR_CLEAR_SINGLE 0x1FF83C30u //! Register Reset Value #define TLN06_PM_ERROR_CLEAR_SINGLE_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN06_PM_ERROR_CLEAR_SINGLE_CLEAR_POS 0 //! Field CLEAR - clear #define TLN06_PM_ERROR_CLEAR_SINGLE_CLEAR_MASK 0x1u //! @} //! \defgroup TLN06_PM_ERROR_CLEAR_MULTI Register TLN06_PM_ERROR_CLEAR_MULTI - error_clear_multi //! @{ //! Register Offset (relative) #define TLN06_PM_ERROR_CLEAR_MULTI 0x83C38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ERROR_CLEAR_MULTI 0x1FF83C38u //! Register Reset Value #define TLN06_PM_ERROR_CLEAR_MULTI_RST 0x0000000000000000u //! Field CLEAR - clear #define TLN06_PM_ERROR_CLEAR_MULTI_CLEAR_POS 0 //! Field CLEAR - clear #define TLN06_PM_ERROR_CLEAR_MULTI_CLEAR_MASK 0x1u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_0 Register TLN06_PM_REQ_INFO_PERMISSION_0 - req_info_permission_0 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_0 0x83C48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_0 0x1FF83C48u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_0_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_0_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_0_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_0 Register TLN06_PM_READ_PERMISSION_0 - read_permission_0 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_0 0x83C50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_0 0x1FF83C50u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_0_BIT_VECTOR_MASK 0x1u //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_0 Register TLN06_PM_WRITE_PERMISSION_0 - write_permission_0 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_0 0x83C58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_0 0x1FF83C58u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_0_RST 0x0000000000000001u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_0_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_0_BIT_VECTOR_MASK 0x1u //! @} //! \defgroup TLN06_PM_ADDR_MATCH_1 Register TLN06_PM_ADDR_MATCH_1 - addr_match_1 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_1 0x83C60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_1 0x1FF83C60u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_1_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_1_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_1_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_1_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_1_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_1_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_1_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_1_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_1_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_1 Register TLN06_PM_REQ_INFO_PERMISSION_1 - req_info_permission_1 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_1 0x83C68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_1 0x1FF83C68u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_1_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_1_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_1_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_1 Register TLN06_PM_READ_PERMISSION_1 - read_permission_1 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_1 0x83C70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_1 0x1FF83C70u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_1 Register TLN06_PM_WRITE_PERMISSION_1 - write_permission_1 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_1 0x83C78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_1 0x1FF83C78u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_1_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_1_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_1_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_2 Register TLN06_PM_ADDR_MATCH_2 - addr_match_2 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_2 0x83C80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_2 0x1FF83C80u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_2_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_2_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_2_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_2_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_2_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_2_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_2_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_2_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_2_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_2 Register TLN06_PM_REQ_INFO_PERMISSION_2 - req_info_permission_2 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_2 0x83C88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_2 0x1FF83C88u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_2_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_2_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_2_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_2 Register TLN06_PM_READ_PERMISSION_2 - read_permission_2 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_2 0x83C90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_2 0x1FF83C90u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_2 Register TLN06_PM_WRITE_PERMISSION_2 - write_permission_2 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_2 0x83C98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_2 0x1FF83C98u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_2_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_2_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_2_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_3 Register TLN06_PM_ADDR_MATCH_3 - addr_match_3 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_3 0x83CA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_3 0x1FF83CA0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_3_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_3_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_3_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_3_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_3_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_3_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_3_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_3_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_3_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_3 Register TLN06_PM_REQ_INFO_PERMISSION_3 - req_info_permission_3 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_3 0x83CA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_3 0x1FF83CA8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_3_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_3_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_3_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_3 Register TLN06_PM_READ_PERMISSION_3 - read_permission_3 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_3 0x83CB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_3 0x1FF83CB0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_3 Register TLN06_PM_WRITE_PERMISSION_3 - write_permission_3 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_3 0x83CB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_3 0x1FF83CB8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_3_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_3_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_3_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_4 Register TLN06_PM_ADDR_MATCH_4 - addr_match_4 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_4 0x83CC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_4 0x1FF83CC0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_4_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_4_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_4_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_4_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_4_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_4_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_4_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_4_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_4_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_4 Register TLN06_PM_REQ_INFO_PERMISSION_4 - req_info_permission_4 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_4 0x83CC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_4 0x1FF83CC8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_4_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_4_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_4_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_4 Register TLN06_PM_READ_PERMISSION_4 - read_permission_4 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_4 0x83CD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_4 0x1FF83CD0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_4 Register TLN06_PM_WRITE_PERMISSION_4 - write_permission_4 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_4 0x83CD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_4 0x1FF83CD8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_4_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_4_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_4_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_5 Register TLN06_PM_ADDR_MATCH_5 - addr_match_5 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_5 0x83CE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_5 0x1FF83CE0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_5_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_5_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_5_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_5_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_5_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_5_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_5_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_5_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_5_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_5 Register TLN06_PM_REQ_INFO_PERMISSION_5 - req_info_permission_5 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_5 0x83CE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_5 0x1FF83CE8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_5_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_5_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_5_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_5 Register TLN06_PM_READ_PERMISSION_5 - read_permission_5 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_5 0x83CF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_5 0x1FF83CF0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_5 Register TLN06_PM_WRITE_PERMISSION_5 - write_permission_5 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_5 0x83CF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_5 0x1FF83CF8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_5_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_5_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_5_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_6 Register TLN06_PM_ADDR_MATCH_6 - addr_match_6 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_6 0x83D00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_6 0x1FF83D00u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_6_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_6_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_6_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_6_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_6_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_6_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_6_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_6_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_6_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_6 Register TLN06_PM_REQ_INFO_PERMISSION_6 - req_info_permission_6 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_6 0x83D08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_6 0x1FF83D08u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_6_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_6_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_6_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_6 Register TLN06_PM_READ_PERMISSION_6 - read_permission_6 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_6 0x83D10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_6 0x1FF83D10u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_6 Register TLN06_PM_WRITE_PERMISSION_6 - write_permission_6 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_6 0x83D18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_6 0x1FF83D18u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_6_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_6_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_6_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_7 Register TLN06_PM_ADDR_MATCH_7 - addr_match_7 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_7 0x83D20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_7 0x1FF83D20u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_7_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_7_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_7_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_7_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_7_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_7_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_7_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_7_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_7_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_7 Register TLN06_PM_REQ_INFO_PERMISSION_7 - req_info_permission_7 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_7 0x83D28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_7 0x1FF83D28u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_7_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_7_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_7_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_7 Register TLN06_PM_READ_PERMISSION_7 - read_permission_7 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_7 0x83D30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_7 0x1FF83D30u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_7 Register TLN06_PM_WRITE_PERMISSION_7 - write_permission_7 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_7 0x83D38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_7 0x1FF83D38u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_7_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_7_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_7_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_8 Register TLN06_PM_ADDR_MATCH_8 - addr_match_8 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_8 0x83D40 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_8 0x1FF83D40u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_8_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_8_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_8_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_8_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_8_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_8_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_8_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_8_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_8_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_8 Register TLN06_PM_REQ_INFO_PERMISSION_8 - req_info_permission_8 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_8 0x83D48 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_8 0x1FF83D48u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_8_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_8_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_8_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_8 Register TLN06_PM_READ_PERMISSION_8 - read_permission_8 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_8 0x83D50 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_8 0x1FF83D50u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_8 Register TLN06_PM_WRITE_PERMISSION_8 - write_permission_8 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_8 0x83D58 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_8 0x1FF83D58u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_8_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_8_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_8_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_9 Register TLN06_PM_ADDR_MATCH_9 - addr_match_9 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_9 0x83D60 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_9 0x1FF83D60u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_9_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_9_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_9_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_9_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_9_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_9_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_9_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_9_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_9_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_9 Register TLN06_PM_REQ_INFO_PERMISSION_9 - req_info_permission_9 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_9 0x83D68 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_9 0x1FF83D68u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_9_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_9_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_9_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_9 Register TLN06_PM_READ_PERMISSION_9 - read_permission_9 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_9 0x83D70 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_9 0x1FF83D70u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_9 Register TLN06_PM_WRITE_PERMISSION_9 - write_permission_9 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_9 0x83D78 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_9 0x1FF83D78u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_9_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_9_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_9_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_10 Register TLN06_PM_ADDR_MATCH_10 - addr_match_10 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_10 0x83D80 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_10 0x1FF83D80u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_10_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_10_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_10_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_10_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_10_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_10_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_10_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_10_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_10_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_10 Register TLN06_PM_REQ_INFO_PERMISSION_10 - req_info_permission_10 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_10 0x83D88 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_10 0x1FF83D88u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_10_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_10_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_10_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_10 Register TLN06_PM_READ_PERMISSION_10 - read_permission_10 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_10 0x83D90 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_10 0x1FF83D90u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_10 Register TLN06_PM_WRITE_PERMISSION_10 - write_permission_10 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_10 0x83D98 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_10 0x1FF83D98u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_10_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_10_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_10_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_11 Register TLN06_PM_ADDR_MATCH_11 - addr_match_11 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_11 0x83DA0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_11 0x1FF83DA0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_11_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_11_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_11_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_11_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_11_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_11_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_11_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_11_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_11_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_11 Register TLN06_PM_REQ_INFO_PERMISSION_11 - req_info_permission_11 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_11 0x83DA8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_11 0x1FF83DA8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_11_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_11_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_11_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_11 Register TLN06_PM_READ_PERMISSION_11 - read_permission_11 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_11 0x83DB0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_11 0x1FF83DB0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_11 Register TLN06_PM_WRITE_PERMISSION_11 - write_permission_11 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_11 0x83DB8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_11 0x1FF83DB8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_11_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_11_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_11_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_12 Register TLN06_PM_ADDR_MATCH_12 - addr_match_12 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_12 0x83DC0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_12 0x1FF83DC0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_12_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_12_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_12_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_12_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_12_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_12_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_12_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_12_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_12_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_12 Register TLN06_PM_REQ_INFO_PERMISSION_12 - req_info_permission_12 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_12 0x83DC8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_12 0x1FF83DC8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_12_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_12_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_12_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_12 Register TLN06_PM_READ_PERMISSION_12 - read_permission_12 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_12 0x83DD0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_12 0x1FF83DD0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_12 Register TLN06_PM_WRITE_PERMISSION_12 - write_permission_12 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_12 0x83DD8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_12 0x1FF83DD8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_12_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_12_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_12_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_13 Register TLN06_PM_ADDR_MATCH_13 - addr_match_13 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_13 0x83DE0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_13 0x1FF83DE0u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_13_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_13_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_13_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_13_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_13_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_13_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_13_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_13_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_13_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_13 Register TLN06_PM_REQ_INFO_PERMISSION_13 - req_info_permission_13 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_13 0x83DE8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_13 0x1FF83DE8u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_13_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_13_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_13_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_13 Register TLN06_PM_READ_PERMISSION_13 - read_permission_13 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_13 0x83DF0 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_13 0x1FF83DF0u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_13 Register TLN06_PM_WRITE_PERMISSION_13 - write_permission_13 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_13 0x83DF8 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_13 0x1FF83DF8u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_13_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_13_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_13_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_14 Register TLN06_PM_ADDR_MATCH_14 - addr_match_14 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_14 0x83E00 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_14 0x1FF83E00u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_14_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_14_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_14_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_14_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_14_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_14_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_14_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_14_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_14_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_14 Register TLN06_PM_REQ_INFO_PERMISSION_14 - req_info_permission_14 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_14 0x83E08 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_14 0x1FF83E08u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_14_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_14_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_14_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_14 Register TLN06_PM_READ_PERMISSION_14 - read_permission_14 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_14 0x83E10 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_14 0x1FF83E10u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_14 Register TLN06_PM_WRITE_PERMISSION_14 - write_permission_14 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_14 0x83E18 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_14 0x1FF83E18u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_14_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_14_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_14_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_ADDR_MATCH_15 Register TLN06_PM_ADDR_MATCH_15 - addr_match_15 //! @{ //! Register Offset (relative) #define TLN06_PM_ADDR_MATCH_15 0x83E20 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_ADDR_MATCH_15 0x1FF83E20u //! Register Reset Value #define TLN06_PM_ADDR_MATCH_15_RST 0x0000000000000000u //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_15_ADDR_SPACE_POS 0 //! Field ADDR_SPACE - addr_space #define TLN06_PM_ADDR_MATCH_15_ADDR_SPACE_MASK 0x7u //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_15_SIZE_POS 3 //! Field SIZE - size #define TLN06_PM_ADDR_MATCH_15_SIZE_MASK 0xF8u //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_15_LEVEL_POS 9 //! Field LEVEL - level #define TLN06_PM_ADDR_MATCH_15_LEVEL_MASK 0x200u //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_15_BASE_ADDR_POS 10 //! Field BASE_ADDR - base_addr #define TLN06_PM_ADDR_MATCH_15_BASE_ADDR_MASK 0xFFFFFFFFFFFFFC00u //! @} //! \defgroup TLN06_PM_REQ_INFO_PERMISSION_15 Register TLN06_PM_REQ_INFO_PERMISSION_15 - req_info_permission_15 //! @{ //! Register Offset (relative) #define TLN06_PM_REQ_INFO_PERMISSION_15 0x83E28 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_REQ_INFO_PERMISSION_15 0x1FF83E28u //! Register Reset Value #define TLN06_PM_REQ_INFO_PERMISSION_15_RST 0x0000000000000000u //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_15_REQ_INFO_POS 0 //! Field REQ_INFO - req_info #define TLN06_PM_REQ_INFO_PERMISSION_15_REQ_INFO_MASK 0xFFFFFFFFu //! @} //! \defgroup TLN06_PM_READ_PERMISSION_15 Register TLN06_PM_READ_PERMISSION_15 - read_permission_15 //! @{ //! Register Offset (relative) #define TLN06_PM_READ_PERMISSION_15 0x83E30 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_READ_PERMISSION_15 0x1FF83E30u //! Register Reset Value #define TLN06_PM_READ_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_READ_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TLN06_PM_WRITE_PERMISSION_15 Register TLN06_PM_WRITE_PERMISSION_15 - write_permission_15 //! @{ //! Register Offset (relative) #define TLN06_PM_WRITE_PERMISSION_15 0x83E38 //! Register Offset (absolute) for 1st Instance SSX0_SSX #define SSX0_SSX_TLN06_PM_WRITE_PERMISSION_15 0x1FF83E38u //! Register Reset Value #define TLN06_PM_WRITE_PERMISSION_15_RST 0x0000000000000000u //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_15_BIT_VECTOR_POS 0 //! Field BIT_VECTOR - bit_vector #define TLN06_PM_WRITE_PERMISSION_15_BIT_VECTOR_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! @} #endif