#include "cbm.h"
#include <net/lantiq_cbm_api.h>
#include "cbm_config.h"

const struct cqm_config xrx500_cbm_config[] = {
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 2,
	  .data.dqm_cpu.tmu_queue = 35,
	  .data.dqm_cpu.cpu_port_type = DP_F_DEQ_CPU,
	  .data.dqm_cpu.num_desc = 2 },
	/*{
	 *.type = DQM_CPU_TYPE,
	 *.data.dqm_cpu.tmu_port = 0,
	 *.data.dqm_cpu.tmu_queue = 33,
	 *.data.dqm_cpu.cpu_port_type = DP_F_DEQ_CPU1,
	 *.data.dqm_cpu.num_desc = 2
	 *},
	 */
	{
		.type = DQM_CPU_TYPE,
		.data.dqm_cpu.tmu_port = 1,
		.data.dqm_cpu.tmu_queue = 34,
		.data.dqm_cpu.cpu_port_type = DP_F_DEQ_DL,
		.data.dqm_cpu.num_desc = 2 },
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 3,
	  .data.dqm_cpu.tmu_queue = 36,
	  .data.dqm_cpu.cpu_port_type = DP_F_DEQ_MPE,
	  .data.dqm_cpu.num_desc = 2 },
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 6,
		.data.dqm_dma.tmu_queue = 16,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 1,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 7,
		.data.dqm_dma.tmu_queue = 17,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 2,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 8,
		.data.dqm_dma.tmu_queue = 18,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 3,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 9,
		.data.dqm_dma.tmu_queue = 19,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 4,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 10,
		.data.dqm_dma.tmu_queue = 20,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 5,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 11,
		.data.dqm_dma.tmu_queue = 21,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 6,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 12,
		.data.dqm_dma.tmu_queue = 22,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 9,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 13,
		.data.dqm_dma.tmu_queue = 23,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 10,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 14,
		.data.dqm_dma.tmu_queue = 24,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 11,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 15,
		.data.dqm_dma.tmu_queue = 25,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 12,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 16,
		.data.dqm_dma.tmu_queue = 26,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 13,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 17,
		.data.dqm_dma.tmu_queue = 27,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 2,
		.data.dqm_dma.dma_chan = 14,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 18,
		.data.dqm_dma.tmu_queue = 0,
		.data.dqm_dma.tmu_queue_nos = 4,
		.data.dqm_dma.dma_ctrl = 1,
		.data.dqm_dma.dma_chan = 13,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 19,
		.data.dqm_dma.tmu_queue = 28,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 1,
		.data.dqm_dma.dma_chan = 15,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 20,
		.data.dqm_dma.tmu_queue = 29,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 1,
		.data.dqm_dma.dma_chan = 5,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 21,
		.data.dqm_dma.tmu_queue = 30,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 1,
		.data.dqm_dma.dma_chan = 6,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_DMA_TYPE,
		.data.dqm_dma.tmu_port = 22,
		.data.dqm_dma.tmu_queue = 41,
		.data.dqm_dma.tmu_queue_nos = 1,
		.data.dqm_dma.dma_ctrl = 1,
		.data.dqm_dma.dma_chan = 11,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	/*This entry to be placed after port 18 which
	 *is used for traffic from VRX318
	 */
	{
		.type = DQM_LDMA_TYPE,
		.data.dqm_dma.tmu_port = 23,
		.data.dqm_dma.tmu_queue = 31,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{
		.type = DQM_SCPU_TYPE,
		.data.dqm_dma.tmu_port = 5,
		.data.dqm_dma.tmu_queue = 37,
		.data.dqm_dma.port_enable = 1,
		.data.dqm_dma.num_desc = 2,
	},
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 4,
	  .data.dqm_cpu.tmu_queue = 32,
	  .data.dqm_cpu.cpu_port_type = 1,
	  .data.dqm_cpu.num_desc = 2 },
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 24,
	  .data.dqm_cpu.tmu_queue = 38,
	  .data.dqm_cpu.cpu_port_type = 1,
	  .data.dqm_cpu.num_desc = 32 },
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 25,
	  .data.dqm_cpu.tmu_queue = 39,
	  .data.dqm_cpu.cpu_port_type = 1,
	  .data.dqm_cpu.num_desc = 32 },
	{ .type = DQM_CPU_TYPE,
	  .data.dqm_cpu.tmu_port = 26,
	  .data.dqm_cpu.tmu_queue = 40,
	  .data.dqm_cpu.cpu_port_type = 1,
	  .data.dqm_cpu.num_desc = 32 },
	{ .type = EQM_CPU_TYPE,
	  .data.eqm_cpu.tmu_port = 0,
	  .data.eqm_cpu.port_type = 2,
	  .data.eqm_cpu.num_desc = 2 },
	{ .type = EQM_CPU_TYPE,
	  .data.eqm_cpu.tmu_port = 1,
	  .data.eqm_cpu.port_type = 3,
	  .data.eqm_cpu.num_desc = 2 },
	{ .type = EQM_CPU_TYPE,
	  .data.eqm_cpu.tmu_port = 2,
	  .data.eqm_cpu.port_type = 4,
	  .data.eqm_cpu.num_desc = 2 },
	{ .type = EQM_CPU_TYPE,
	  .data.eqm_cpu.tmu_port = 3,
	  .data.eqm_cpu.port_type = 5,
	  .data.eqm_cpu.num_desc = 2 },
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 5,
		.data.eqm_dma.dma_ctrl = 2,
		.data.eqm_dma.dma_chnl = 14,
		.data.eqm_dma.dma_chnl_type = 0,
		.data.eqm_dma.port_type = 7,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 5,
		.data.eqm_dma.dma_ctrl = 2,
		.data.eqm_dma.dma_chnl = 30,
		.data.eqm_dma.dma_chnl_type = 1,
		.data.eqm_dma.port_type = 7,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 6,
		.data.eqm_dma.dma_ctrl = 2,
		.data.eqm_dma.dma_chnl = 15,
		.data.eqm_dma.dma_chnl_type = 0,
		.data.eqm_dma.port_type = 7,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 6,
		.data.eqm_dma.dma_ctrl = 2,
		.data.eqm_dma.dma_chnl = 31,
		.data.eqm_dma.dma_chnl_type = 1,
		.data.eqm_dma.port_type = 7,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 7,
		.data.eqm_dma.dma_ctrl = 1,
		.data.eqm_dma.dma_chnl = 0,
		.data.eqm_dma.dma_chnl_type = 0,
		.data.eqm_dma.port_type = 8,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 7,
		.data.eqm_dma.dma_ctrl = 1,
		.data.eqm_dma.dma_chnl = 16,
		.data.eqm_dma.dma_chnl_type = 1,
		.data.eqm_dma.port_type = 8,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 8,
		.data.eqm_dma.dma_ctrl = 1,
		.data.eqm_dma.dma_chnl = 15,
		.data.eqm_dma.dma_chnl_type = 0,
		.data.eqm_dma.port_type = 8,
		.data.eqm_dma.num_desc = 2,
	},
	{
		.type = EQM_DMA_TYPE,
		.data.eqm_dma.tmu_port = 8,
		.data.eqm_dma.dma_ctrl = 1,
		.data.eqm_dma.dma_chnl = 31,
		.data.eqm_dma.dma_chnl_type = 1,
		.data.eqm_dma.port_type = 8,
		.data.eqm_dma.num_desc = 2,
	},
	{ .type = EQM_TOE_TYPE,
	  .data.eqm_cpu.tmu_port = 9,
	  .data.eqm_cpu.port_type = 9,
	  .data.eqm_cpu.num_desc = 2 },
	{ .type = EQM_VRX318_TYPE,
	  .data.eqm_cpu.tmu_port = 15,
	  .data.eqm_cpu.port_type = 10,
	  .data.eqm_cpu.num_desc = 32 },
	{ .type = EQM_DL_TYPE,
	  .data.eqm_dl.tmu_port = 12,
	  .data.eqm_dl.dma_ctrl = 1,
	  .data.eqm_dl.dma_chnl = 3,
	  .data.eqm_dl.port_type = 11,
	  .data.eqm_dl.num_desc = 1024 },
	{ .type = NONE_TYPE }
};