//----------------------------------------------------------------------------- // LSD Generator //----------------------------------------------------------------------------- // Perl Package : LSD::generator::targetC (v1.1) // LSD Source : C:/Users/huchunfe/Perforce/huchunfe_huchunfe-MOBL1_dev.FalcONT/ipg_lsd/lsd_sys/source/xml/reg_files/CBM_DQM.xml // Register File Name : CQEM_DEQ // Register File Title : Central QoS Manager - Dequeue Register Description // Register Width : 32 // Note : Doxygen compliant comments //----------------------------------------------------------------------------- #ifndef _CQEM_DEQ_H #define _CQEM_DEQ_H //! \defgroup CQEM_DEQ Register File CQEM_DEQ - Central QoS Manager - Dequeue Register Description //! @{ //! Base Address of CQEM_DEQ #define CQEM_DEQ_MODULE_BASE 0x190C0000u //! \defgroup CBM_DQM_CTRL Register CBM_DQM_CTRL - CBM Dequeue Manager Control Register //! @{ //! Register Offset (relative) #define CBM_DQM_CTRL 0x0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CBM_DQM_CTRL 0x190C0000u //! Register Reset Value #define CBM_DQM_CTRL_RST 0x00000000u //! Field DQM_EN - Enable Dequeue Manager Core State Machine #define CBM_DQM_CTRL_DQM_EN_POS 0 //! Field DQM_EN - Enable Dequeue Manager Core State Machine #define CBM_DQM_CTRL_DQM_EN_MASK 0x1u //! Constant DIS - DIS #define CONST_CBM_DQM_CTRL_DQM_EN_DIS 0x0 //! Constant EN - EN #define CONST_CBM_DQM_CTRL_DQM_EN_EN 0x1 //! Field DQM_FRZ - Freeze Dequeue Manager Core State Machine #define CBM_DQM_CTRL_DQM_FRZ_POS 1 //! Field DQM_FRZ - Freeze Dequeue Manager Core State Machine #define CBM_DQM_CTRL_DQM_FRZ_MASK 0x2u //! Constant DIS - DIS #define CONST_CBM_DQM_CTRL_DQM_FRZ_DIS 0x0 //! Constant EN - EN #define CONST_CBM_DQM_CTRL_DQM_FRZ_EN 0x1 //! Field DQM_ACT - Dequeue Manager Activity Status #define CBM_DQM_CTRL_DQM_ACT_POS 2 //! Field DQM_ACT - Dequeue Manager Activity Status #define CBM_DQM_CTRL_DQM_ACT_MASK 0x4u //! Constant INACTIVE - Inactive #define CONST_CBM_DQM_CTRL_DQM_ACT_INACTIVE 0x0 //! Constant ACTIVE - Active #define CONST_CBM_DQM_CTRL_DQM_ACT_ACTIVE 0x1 //! @} //! \defgroup DBG_DQM_0 Register DBG_DQM_0 - Hardware Debug Register //! @{ //! Register Offset (relative) #define DBG_DQM_0 0x10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DBG_DQM_0 0x190C0010u //! Register Reset Value #define DBG_DQM_0_RST 0x00000000u //! Field DBG - Debug #define DBG_DQM_0_DBG_POS 0 //! Field DBG - Debug #define DBG_DQM_0_DBG_MASK 0xFFFFFFFFu //! @} //! \defgroup DBG_DQM_1 Register DBG_DQM_1 - Hardware Debug Register //! @{ //! Register Offset (relative) #define DBG_DQM_1 0x14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DBG_DQM_1 0x190C0014u //! Register Reset Value #define DBG_DQM_1_RST 0x00000000u //! Field DBG - Debug #define DBG_DQM_1_DBG_POS 0 //! Field DBG - Debug #define DBG_DQM_1_DBG_MASK 0xFFFFFFFFu //! @} //! \defgroup TEST_DQM_0 Register TEST_DQM_0 - Hardware Test Register //! @{ //! Register Offset (relative) #define TEST_DQM_0 0x20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_TEST_DQM_0 0x190C0020u //! Register Reset Value #define TEST_DQM_0_RST 0x00000000u //! Field TEST - Test #define TEST_DQM_0_TEST_POS 0 //! Field TEST - Test #define TEST_DQM_0_TEST_MASK 0xFFFFFFFFu //! @} //! \defgroup TEST_DQM_1 Register TEST_DQM_1 - Hardware Test Register //! @{ //! Register Offset (relative) #define TEST_DQM_1 0x24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_TEST_DQM_1 0x190C0024u //! Register Reset Value #define TEST_DQM_1_RST 0x00000000u //! Field TEST - Test #define TEST_DQM_1_TEST_POS 0 //! Field TEST - Test #define TEST_DQM_1_TEST_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_CPU_EGP_0 Register CFG_CPU_EGP_0 - CPU Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_CPU_EGP_0 0x10000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_CPU_EGP_0 0x190D0000u //! Register Reset Value #define CFG_CPU_EGP_0_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_0_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_0_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_0_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_0_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_0_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_0_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_0_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_0_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_0_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_0_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_0_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_0_BFBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_0_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_0_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_0_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_0_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_0_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_0_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_0 Register DQPC_CPU_EGP_0 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_0 0x10004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_0 0x190D0004u //! Register Reset Value #define DQPC_CPU_EGP_0_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_0_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_0_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_0 Register IRNCR_CPU_EGP_0 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_0 0x10020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_0 0x190D0020u //! Register Reset Value #define IRNCR_CPU_EGP_0_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_0_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_0_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_0_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_0_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_0_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_0_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_0_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_0_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_0 Register IRNICR_CPU_EGP_0 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_0 0x10024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_0 0x190D0024u //! Register Reset Value #define IRNICR_CPU_EGP_0_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_0_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_0_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_0_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_0_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_0 Register IRNEN_CPU_EGP_0 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_0 0x10028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_0 0x190D0028u //! Register Reset Value #define IRNEN_CPU_EGP_0_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_0_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_0_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_0_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_0_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_0_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_0_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_0_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_0_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_0 Register DPTR_CPU_EGP_0 - CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_0 0x10030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_0 0x190D0030u //! Register Reset Value #define DPTR_CPU_EGP_0_RST 0x00000001u //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_0_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_0_ND_MASK 0x1u //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_0_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_0_DPTR_MASK 0x10000u //! @} //! \defgroup BPRC_CPU_EGP_0 Register BPRC_CPU_EGP_0 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_0 0x10034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_0 0x190D0034u //! Register Reset Value #define BPRC_CPU_EGP_0_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_0_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_0_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup PTR_RTN_CPU_DW2_EGP_0 Register PTR_RTN_CPU_DW2_EGP_0 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW2_EGP_0 0x10100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW2_EGP_0 0x190D0100u //! Register Reset Value #define PTR_RTN_CPU_DW2_EGP_0_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_0_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_0_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_CPU_DW3_EGP_0 Register PTR_RTN_CPU_DW3_EGP_0 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW3_EGP_0 0x10104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW3_EGP_0 0x190D0104u //! Register Reset Value #define PTR_RTN_CPU_DW3_EGP_0_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_0_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_0_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_0_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_0_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_0_CPU_EGP_0 Register DESC0_0_CPU_EGP_0 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_CPU_EGP_0 0x10200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_CPU_EGP_0 0x190D0200u //! Register Reset Value #define DESC0_0_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_CPU_EGP_0 Register DESC1_0_CPU_EGP_0 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_CPU_EGP_0 0x10204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_CPU_EGP_0 0x190D0204u //! Register Reset Value #define DESC1_0_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_CPU_EGP_0 Register DESC2_0_CPU_EGP_0 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_CPU_EGP_0 0x10208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_CPU_EGP_0 0x190D0208u //! Register Reset Value #define DESC2_0_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_CPU_EGP_0 Register DESC3_0_CPU_EGP_0 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_CPU_EGP_0 0x1020C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_CPU_EGP_0 0x190D020Cu //! Register Reset Value #define DESC3_0_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_1_CPU_EGP_0 Register DESC0_1_CPU_EGP_0 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_CPU_EGP_0 0x10210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_CPU_EGP_0 0x190D0210u //! Register Reset Value #define DESC0_1_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_CPU_EGP_0 Register DESC1_1_CPU_EGP_0 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_CPU_EGP_0 0x10214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_CPU_EGP_0 0x190D0214u //! Register Reset Value #define DESC1_1_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_CPU_EGP_0 Register DESC2_1_CPU_EGP_0 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_CPU_EGP_0 0x10218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_CPU_EGP_0 0x190D0218u //! Register Reset Value #define DESC2_1_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_CPU_EGP_0 Register DESC3_1_CPU_EGP_0 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_CPU_EGP_0 0x1021C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_CPU_EGP_0 0x190D021Cu //! Register Reset Value #define DESC3_1_CPU_EGP_0_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_0_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_0_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_CPU_EGP_1 Register CFG_CPU_EGP_1 - CPU Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_CPU_EGP_1 0x11000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_CPU_EGP_1 0x190D1000u //! Register Reset Value #define CFG_CPU_EGP_1_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_1_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_1_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_1_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_1_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_1_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_1_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_1_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_1_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_1_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_1_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_1_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_1_BFBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_1_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_1_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_1_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_1_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_1_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_1_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_1 Register DQPC_CPU_EGP_1 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_1 0x11004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_1 0x190D1004u //! Register Reset Value #define DQPC_CPU_EGP_1_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_1_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_1_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_1 Register IRNCR_CPU_EGP_1 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_1 0x11020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_1 0x190D1020u //! Register Reset Value #define IRNCR_CPU_EGP_1_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_1_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_1_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_1_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_1_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_1_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_1_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_1_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_1_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_1 Register IRNICR_CPU_EGP_1 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_1 0x11024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_1 0x190D1024u //! Register Reset Value #define IRNICR_CPU_EGP_1_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_1_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_1_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_1_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_1_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_1 Register IRNEN_CPU_EGP_1 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_1 0x11028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_1 0x190D1028u //! Register Reset Value #define IRNEN_CPU_EGP_1_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_1_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_1_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_1_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_1_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_1_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_1_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_1_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_1_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_1 Register DPTR_CPU_EGP_1 - CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_1 0x11030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_1 0x190D1030u //! Register Reset Value #define DPTR_CPU_EGP_1_RST 0x00000001u //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_1_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_1_ND_MASK 0x1u //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_1_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_1_DPTR_MASK 0x10000u //! @} //! \defgroup BPRC_CPU_EGP_1 Register BPRC_CPU_EGP_1 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_1 0x11034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_1 0x190D1034u //! Register Reset Value #define BPRC_CPU_EGP_1_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_1_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_1_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup PTR_RTN_CPU_DW2_EGP_1 Register PTR_RTN_CPU_DW2_EGP_1 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW2_EGP_1 0x11100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW2_EGP_1 0x190D1100u //! Register Reset Value #define PTR_RTN_CPU_DW2_EGP_1_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_1_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_1_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_CPU_DW3_EGP_1 Register PTR_RTN_CPU_DW3_EGP_1 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW3_EGP_1 0x11104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW3_EGP_1 0x190D1104u //! Register Reset Value #define PTR_RTN_CPU_DW3_EGP_1_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_1_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_1_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_1_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_1_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_0_CPU_EGP_1 Register DESC0_0_CPU_EGP_1 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_CPU_EGP_1 0x11200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_CPU_EGP_1 0x190D1200u //! Register Reset Value #define DESC0_0_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_CPU_EGP_1 Register DESC1_0_CPU_EGP_1 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_CPU_EGP_1 0x11204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_CPU_EGP_1 0x190D1204u //! Register Reset Value #define DESC1_0_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_CPU_EGP_1 Register DESC2_0_CPU_EGP_1 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_CPU_EGP_1 0x11208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_CPU_EGP_1 0x190D1208u //! Register Reset Value #define DESC2_0_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_CPU_EGP_1 Register DESC3_0_CPU_EGP_1 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_CPU_EGP_1 0x1120C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_CPU_EGP_1 0x190D120Cu //! Register Reset Value #define DESC3_0_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_1_CPU_EGP_1 Register DESC0_1_CPU_EGP_1 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_CPU_EGP_1 0x11210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_CPU_EGP_1 0x190D1210u //! Register Reset Value #define DESC0_1_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_CPU_EGP_1 Register DESC1_1_CPU_EGP_1 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_CPU_EGP_1 0x11214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_CPU_EGP_1 0x190D1214u //! Register Reset Value #define DESC1_1_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_CPU_EGP_1 Register DESC2_1_CPU_EGP_1 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_CPU_EGP_1 0x11218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_CPU_EGP_1 0x190D1218u //! Register Reset Value #define DESC2_1_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_CPU_EGP_1 Register DESC3_1_CPU_EGP_1 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_CPU_EGP_1 0x1121C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_CPU_EGP_1 0x190D121Cu //! Register Reset Value #define DESC3_1_CPU_EGP_1_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_1_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_1_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_CPU_EGP_2 Register CFG_CPU_EGP_2 - CPU Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_CPU_EGP_2 0x12000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_CPU_EGP_2 0x190D2000u //! Register Reset Value #define CFG_CPU_EGP_2_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_2_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_2_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_2_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_2_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_2_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_2_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_2_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_2_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_2_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_2_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_2_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_2_BFBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_2_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_2_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_2_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_2_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_2_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_2_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_2 Register DQPC_CPU_EGP_2 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_2 0x12004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_2 0x190D2004u //! Register Reset Value #define DQPC_CPU_EGP_2_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_2_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_2_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_2 Register IRNCR_CPU_EGP_2 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_2 0x12020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_2 0x190D2020u //! Register Reset Value #define IRNCR_CPU_EGP_2_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_2_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_2_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_2_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_2_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_2_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_2_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_2_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_2_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_2 Register IRNICR_CPU_EGP_2 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_2 0x12024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_2 0x190D2024u //! Register Reset Value #define IRNICR_CPU_EGP_2_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_2_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_2_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_2_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_2_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_2 Register IRNEN_CPU_EGP_2 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_2 0x12028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_2 0x190D2028u //! Register Reset Value #define IRNEN_CPU_EGP_2_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_2_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_2_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_2_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_2_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_2_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_2_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_2_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_2_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_2 Register DPTR_CPU_EGP_2 - CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_2 0x12030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_2 0x190D2030u //! Register Reset Value #define DPTR_CPU_EGP_2_RST 0x00000001u //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_2_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_2_ND_MASK 0x1u //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_2_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_2_DPTR_MASK 0x10000u //! @} //! \defgroup BPRC_CPU_EGP_2 Register BPRC_CPU_EGP_2 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_2 0x12034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_2 0x190D2034u //! Register Reset Value #define BPRC_CPU_EGP_2_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_2_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_2_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup PTR_RTN_CPU_DW2_EGP_2 Register PTR_RTN_CPU_DW2_EGP_2 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW2_EGP_2 0x12100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW2_EGP_2 0x190D2100u //! Register Reset Value #define PTR_RTN_CPU_DW2_EGP_2_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_2_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_2_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_CPU_DW3_EGP_2 Register PTR_RTN_CPU_DW3_EGP_2 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW3_EGP_2 0x12104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW3_EGP_2 0x190D2104u //! Register Reset Value #define PTR_RTN_CPU_DW3_EGP_2_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_2_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_2_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_2_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_2_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_0_CPU_EGP_2 Register DESC0_0_CPU_EGP_2 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_CPU_EGP_2 0x12200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_CPU_EGP_2 0x190D2200u //! Register Reset Value #define DESC0_0_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_CPU_EGP_2 Register DESC1_0_CPU_EGP_2 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_CPU_EGP_2 0x12204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_CPU_EGP_2 0x190D2204u //! Register Reset Value #define DESC1_0_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_CPU_EGP_2 Register DESC2_0_CPU_EGP_2 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_CPU_EGP_2 0x12208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_CPU_EGP_2 0x190D2208u //! Register Reset Value #define DESC2_0_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_CPU_EGP_2 Register DESC3_0_CPU_EGP_2 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_CPU_EGP_2 0x1220C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_CPU_EGP_2 0x190D220Cu //! Register Reset Value #define DESC3_0_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_1_CPU_EGP_2 Register DESC0_1_CPU_EGP_2 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_CPU_EGP_2 0x12210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_CPU_EGP_2 0x190D2210u //! Register Reset Value #define DESC0_1_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_CPU_EGP_2 Register DESC1_1_CPU_EGP_2 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_CPU_EGP_2 0x12214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_CPU_EGP_2 0x190D2214u //! Register Reset Value #define DESC1_1_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_CPU_EGP_2 Register DESC2_1_CPU_EGP_2 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_CPU_EGP_2 0x12218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_CPU_EGP_2 0x190D2218u //! Register Reset Value #define DESC2_1_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_CPU_EGP_2 Register DESC3_1_CPU_EGP_2 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_CPU_EGP_2 0x1221C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_CPU_EGP_2 0x190D221Cu //! Register Reset Value #define DESC3_1_CPU_EGP_2_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_2_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_2_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_CPU_EGP_3 Register CFG_CPU_EGP_3 - CPU Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_CPU_EGP_3 0x13000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_CPU_EGP_3 0x190D3000u //! Register Reset Value #define CFG_CPU_EGP_3_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_3_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_CPU_EGP_3_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_3_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_3_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_3_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_CPU_EGP_3_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_3_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_3_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_3_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_CPU_EGP_3_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_3_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_3_BFBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_3_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_CPU_EGP_3_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_CPU_EGP_3_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_CPU_EGP_3_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_3_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_CPU_EGP_3_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_3 Register DQPC_CPU_EGP_3 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_3 0x13004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_3 0x190D3004u //! Register Reset Value #define DQPC_CPU_EGP_3_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_3_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_3_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_3 Register IRNCR_CPU_EGP_3 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_3 0x13020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_3 0x190D3020u //! Register Reset Value #define IRNCR_CPU_EGP_3_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_3_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_3_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_3_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_3_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_3_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_3_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_3_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_3_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_3 Register IRNICR_CPU_EGP_3 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_3 0x13024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_3 0x190D3024u //! Register Reset Value #define IRNICR_CPU_EGP_3_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_3_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_3_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_3_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_3_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_3 Register IRNEN_CPU_EGP_3 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_3 0x13028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_3 0x190D3028u //! Register Reset Value #define IRNEN_CPU_EGP_3_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_3_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_3_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_3_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_3_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_3_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_3_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_3_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_3_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_3 Register DPTR_CPU_EGP_3 - CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_3 0x13030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_3 0x190D3030u //! Register Reset Value #define DPTR_CPU_EGP_3_RST 0x00000001u //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_3_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_3_ND_MASK 0x1u //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_3_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_3_DPTR_MASK 0x10000u //! @} //! \defgroup BPRC_CPU_EGP_3 Register BPRC_CPU_EGP_3 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_3 0x13034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_3 0x190D3034u //! Register Reset Value #define BPRC_CPU_EGP_3_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_3_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_3_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup PTR_RTN_CPU_DW2_EGP_3 Register PTR_RTN_CPU_DW2_EGP_3 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW2_EGP_3 0x13100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW2_EGP_3 0x190D3100u //! Register Reset Value #define PTR_RTN_CPU_DW2_EGP_3_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_3_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_CPU_DW2_EGP_3_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_CPU_DW3_EGP_3 Register PTR_RTN_CPU_DW3_EGP_3 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_CPU_DW3_EGP_3 0x13104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_CPU_DW3_EGP_3 0x190D3104u //! Register Reset Value #define PTR_RTN_CPU_DW3_EGP_3_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_3_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_3_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_3_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_CPU_DW3_EGP_3_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_0_CPU_EGP_3 Register DESC0_0_CPU_EGP_3 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_CPU_EGP_3 0x13200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_CPU_EGP_3 0x190D3200u //! Register Reset Value #define DESC0_0_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_CPU_EGP_3 Register DESC1_0_CPU_EGP_3 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_CPU_EGP_3 0x13204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_CPU_EGP_3 0x190D3204u //! Register Reset Value #define DESC1_0_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_CPU_EGP_3 Register DESC2_0_CPU_EGP_3 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_CPU_EGP_3 0x13208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_CPU_EGP_3 0x190D3208u //! Register Reset Value #define DESC2_0_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_CPU_EGP_3 Register DESC3_0_CPU_EGP_3 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_CPU_EGP_3 0x1320C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_CPU_EGP_3 0x190D320Cu //! Register Reset Value #define DESC3_0_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_1_CPU_EGP_3 Register DESC0_1_CPU_EGP_3 - CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_CPU_EGP_3 0x13210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_CPU_EGP_3 0x190D3210u //! Register Reset Value #define DESC0_1_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_CPU_EGP_3 Register DESC1_1_CPU_EGP_3 - CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_CPU_EGP_3 0x13214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_CPU_EGP_3 0x190D3214u //! Register Reset Value #define DESC1_1_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_CPU_EGP_3 Register DESC2_1_CPU_EGP_3 - CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_CPU_EGP_3 0x13218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_CPU_EGP_3 0x190D3218u //! Register Reset Value #define DESC2_1_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_CPU_EGP_3 Register DESC3_1_CPU_EGP_3 - CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_CPU_EGP_3 0x1321C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_CPU_EGP_3 0x190D321Cu //! Register Reset Value #define DESC3_1_CPU_EGP_3_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_3_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_CPU_EGP_3_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_ACA_EGP_4 Register CFG_ACA_EGP_4 - CPU ACA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_ACA_EGP_4 0x14000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_ACA_EGP_4 0x190D4000u //! Register Reset Value #define CFG_ACA_EGP_4_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_4_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_4_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_4_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_4_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_4_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_4_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_4_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_4_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_4_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_4_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_4_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_4_BFBPEN_EN 0x1 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_4_DQBPEN_POS 3 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_4_DQBPEN_MASK 0x8u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_4_DQBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_4_DQBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_4_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_4_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_4_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_4_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_4_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_4_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_4 Register DQPC_CPU_EGP_4 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_4 0x14004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_4 0x190D4004u //! Register Reset Value #define DQPC_CPU_EGP_4_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_4_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_4_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_4 Register IRNCR_CPU_EGP_4 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_4 0x14020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_4 0x190D4020u //! Register Reset Value #define IRNCR_CPU_EGP_4_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_4_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_4_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_4_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_4_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_4_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_4_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_4_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_4_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_4 Register IRNICR_CPU_EGP_4 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_4 0x14024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_4 0x190D4024u //! Register Reset Value #define IRNICR_CPU_EGP_4_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_4_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_4_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_4_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_4_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_4 Register IRNEN_CPU_EGP_4 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_4 0x14028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_4 0x190D4028u //! Register Reset Value #define IRNEN_CPU_EGP_4_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_4_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_4_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_4_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_4_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_4_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_4_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_4_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_4_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_4 Register DPTR_CPU_EGP_4 - Special CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_4 0x14030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_4 0x190D4030u //! Register Reset Value #define DPTR_CPU_EGP_4_RST 0x0000001Fu //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_4_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_4_ND_MASK 0x1Fu //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_4_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_4_DPTR_MASK 0x1F0000u //! @} //! \defgroup BPRC_CPU_EGP_4 Register BPRC_CPU_EGP_4 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_4 0x14034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_4 0x190D4034u //! Register Reset Value #define BPRC_CPU_EGP_4_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_4_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_4_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup BRPTR_SCPU_EGP_4 Register BRPTR_SCPU_EGP_4 - Special CPU Egress Port Buffer Return Pointer //! @{ //! Register Offset (relative) #define BRPTR_SCPU_EGP_4 0x14038 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BRPTR_SCPU_EGP_4 0x190D4038u //! Register Reset Value #define BRPTR_SCPU_EGP_4_RST 0x00000000u //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_4_PTRBR_POS 0 //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_4_PTRBR_MASK 0x1Fu //! @} //! \defgroup PTR_RTN_DW2_EP2_0_CPU_EGP_4 Register PTR_RTN_DW2_EP2_0_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_0_CPU_EGP_4 0x14100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_0_CPU_EGP_4 0x190D4100u //! Register Reset Value #define PTR_RTN_DW2_EP2_0_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_0_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_0_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_0_CPU_EGP_4 Register PTR_RTN_DW3_EP2_0_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_0_CPU_EGP_4 0x14104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_0_CPU_EGP_4 0x190D4104u //! Register Reset Value #define PTR_RTN_DW3_EP2_0_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_0_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_0_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_0_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_0_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_1_CPU_EGP_4 Register PTR_RTN_DW2_EP2_1_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_1_CPU_EGP_4 0x14108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_1_CPU_EGP_4 0x190D4108u //! Register Reset Value #define PTR_RTN_DW2_EP2_1_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_1_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_1_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_1_CPU_EGP_4 Register PTR_RTN_DW3_EP2_1_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_1_CPU_EGP_4 0x1410C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_1_CPU_EGP_4 0x190D410Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_1_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_1_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_1_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_1_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_1_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_2_CPU_EGP_4 Register PTR_RTN_DW2_EP2_2_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_2_CPU_EGP_4 0x14110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_2_CPU_EGP_4 0x190D4110u //! Register Reset Value #define PTR_RTN_DW2_EP2_2_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_2_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_2_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_2_CPU_EGP_4 Register PTR_RTN_DW3_EP2_2_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_2_CPU_EGP_4 0x14114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_2_CPU_EGP_4 0x190D4114u //! Register Reset Value #define PTR_RTN_DW3_EP2_2_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_2_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_2_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_2_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_2_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_3_CPU_EGP_4 Register PTR_RTN_DW2_EP2_3_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_3_CPU_EGP_4 0x14118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_3_CPU_EGP_4 0x190D4118u //! Register Reset Value #define PTR_RTN_DW2_EP2_3_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_3_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_3_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_3_CPU_EGP_4 Register PTR_RTN_DW3_EP2_3_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_3_CPU_EGP_4 0x1411C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_3_CPU_EGP_4 0x190D411Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_3_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_3_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_3_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_3_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_3_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_4_CPU_EGP_4 Register PTR_RTN_DW2_EP2_4_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_4_CPU_EGP_4 0x14120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_4_CPU_EGP_4 0x190D4120u //! Register Reset Value #define PTR_RTN_DW2_EP2_4_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_4_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_4_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_4_CPU_EGP_4 Register PTR_RTN_DW3_EP2_4_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_4_CPU_EGP_4 0x14124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_4_CPU_EGP_4 0x190D4124u //! Register Reset Value #define PTR_RTN_DW3_EP2_4_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_4_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_4_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_4_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_4_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_5_CPU_EGP_4 Register PTR_RTN_DW2_EP2_5_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_5_CPU_EGP_4 0x14128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_5_CPU_EGP_4 0x190D4128u //! Register Reset Value #define PTR_RTN_DW2_EP2_5_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_5_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_5_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_5_CPU_EGP_4 Register PTR_RTN_DW3_EP2_5_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_5_CPU_EGP_4 0x1412C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_5_CPU_EGP_4 0x190D412Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_5_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_5_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_5_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_5_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_5_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_6_CPU_EGP_4 Register PTR_RTN_DW2_EP2_6_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_6_CPU_EGP_4 0x14130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_6_CPU_EGP_4 0x190D4130u //! Register Reset Value #define PTR_RTN_DW2_EP2_6_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_6_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_6_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_6_CPU_EGP_4 Register PTR_RTN_DW3_EP2_6_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_6_CPU_EGP_4 0x14134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_6_CPU_EGP_4 0x190D4134u //! Register Reset Value #define PTR_RTN_DW3_EP2_6_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_6_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_6_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_6_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_6_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_7_CPU_EGP_4 Register PTR_RTN_DW2_EP2_7_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_7_CPU_EGP_4 0x14138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_7_CPU_EGP_4 0x190D4138u //! Register Reset Value #define PTR_RTN_DW2_EP2_7_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_7_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_7_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_7_CPU_EGP_4 Register PTR_RTN_DW3_EP2_7_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_7_CPU_EGP_4 0x1413C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_7_CPU_EGP_4 0x190D413Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_7_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_7_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_7_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_7_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_7_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_8_CPU_EGP_4 Register PTR_RTN_DW2_EP2_8_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_8_CPU_EGP_4 0x14140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_8_CPU_EGP_4 0x190D4140u //! Register Reset Value #define PTR_RTN_DW2_EP2_8_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_8_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_8_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_8_CPU_EGP_4 Register PTR_RTN_DW3_EP2_8_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_8_CPU_EGP_4 0x14144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_8_CPU_EGP_4 0x190D4144u //! Register Reset Value #define PTR_RTN_DW3_EP2_8_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_8_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_8_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_8_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_8_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_9_CPU_EGP_4 Register PTR_RTN_DW2_EP2_9_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_9_CPU_EGP_4 0x14148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_9_CPU_EGP_4 0x190D4148u //! Register Reset Value #define PTR_RTN_DW2_EP2_9_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_9_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_9_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_9_CPU_EGP_4 Register PTR_RTN_DW3_EP2_9_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_9_CPU_EGP_4 0x1414C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_9_CPU_EGP_4 0x190D414Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_9_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_9_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_9_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_9_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_9_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_10_CPU_EGP_4 Register PTR_RTN_DW2_EP2_10_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_10_CPU_EGP_4 0x14150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_10_CPU_EGP_4 0x190D4150u //! Register Reset Value #define PTR_RTN_DW2_EP2_10_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_10_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_10_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_10_CPU_EGP_4 Register PTR_RTN_DW3_EP2_10_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_10_CPU_EGP_4 0x14154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_10_CPU_EGP_4 0x190D4154u //! Register Reset Value #define PTR_RTN_DW3_EP2_10_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_10_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_10_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_10_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_10_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_11_CPU_EGP_4 Register PTR_RTN_DW2_EP2_11_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_11_CPU_EGP_4 0x14158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_11_CPU_EGP_4 0x190D4158u //! Register Reset Value #define PTR_RTN_DW2_EP2_11_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_11_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_11_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_11_CPU_EGP_4 Register PTR_RTN_DW3_EP2_11_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_11_CPU_EGP_4 0x1415C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_11_CPU_EGP_4 0x190D415Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_11_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_11_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_11_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_11_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_11_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_12_CPU_EGP_4 Register PTR_RTN_DW2_EP2_12_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_12_CPU_EGP_4 0x14160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_12_CPU_EGP_4 0x190D4160u //! Register Reset Value #define PTR_RTN_DW2_EP2_12_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_12_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_12_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_12_CPU_EGP_4 Register PTR_RTN_DW3_EP2_12_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_12_CPU_EGP_4 0x14164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_12_CPU_EGP_4 0x190D4164u //! Register Reset Value #define PTR_RTN_DW3_EP2_12_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_12_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_12_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_12_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_12_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_13_CPU_EGP_4 Register PTR_RTN_DW2_EP2_13_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_13_CPU_EGP_4 0x14168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_13_CPU_EGP_4 0x190D4168u //! Register Reset Value #define PTR_RTN_DW2_EP2_13_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_13_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_13_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_13_CPU_EGP_4 Register PTR_RTN_DW3_EP2_13_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_13_CPU_EGP_4 0x1416C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_13_CPU_EGP_4 0x190D416Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_13_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_13_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_13_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_13_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_13_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_14_CPU_EGP_4 Register PTR_RTN_DW2_EP2_14_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_14_CPU_EGP_4 0x14170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_14_CPU_EGP_4 0x190D4170u //! Register Reset Value #define PTR_RTN_DW2_EP2_14_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_14_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_14_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_14_CPU_EGP_4 Register PTR_RTN_DW3_EP2_14_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_14_CPU_EGP_4 0x14174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_14_CPU_EGP_4 0x190D4174u //! Register Reset Value #define PTR_RTN_DW3_EP2_14_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_14_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_14_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_14_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_14_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_15_CPU_EGP_4 Register PTR_RTN_DW2_EP2_15_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_15_CPU_EGP_4 0x14178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_15_CPU_EGP_4 0x190D4178u //! Register Reset Value #define PTR_RTN_DW2_EP2_15_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_15_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_15_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_15_CPU_EGP_4 Register PTR_RTN_DW3_EP2_15_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_15_CPU_EGP_4 0x1417C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_15_CPU_EGP_4 0x190D417Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_15_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_15_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_15_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_15_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_15_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_16_CPU_EGP_4 Register PTR_RTN_DW2_EP2_16_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_16_CPU_EGP_4 0x14180 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_16_CPU_EGP_4 0x190D4180u //! Register Reset Value #define PTR_RTN_DW2_EP2_16_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_16_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_16_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_16_CPU_EGP_4 Register PTR_RTN_DW3_EP2_16_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_16_CPU_EGP_4 0x14184 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_16_CPU_EGP_4 0x190D4184u //! Register Reset Value #define PTR_RTN_DW3_EP2_16_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_16_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_16_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_16_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_16_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_17_CPU_EGP_4 Register PTR_RTN_DW2_EP2_17_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_17_CPU_EGP_4 0x14188 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_17_CPU_EGP_4 0x190D4188u //! Register Reset Value #define PTR_RTN_DW2_EP2_17_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_17_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_17_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_17_CPU_EGP_4 Register PTR_RTN_DW3_EP2_17_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_17_CPU_EGP_4 0x1418C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_17_CPU_EGP_4 0x190D418Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_17_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_17_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_17_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_17_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_17_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_18_CPU_EGP_4 Register PTR_RTN_DW2_EP2_18_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_18_CPU_EGP_4 0x14190 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_18_CPU_EGP_4 0x190D4190u //! Register Reset Value #define PTR_RTN_DW2_EP2_18_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_18_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_18_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_18_CPU_EGP_4 Register PTR_RTN_DW3_EP2_18_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_18_CPU_EGP_4 0x14194 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_18_CPU_EGP_4 0x190D4194u //! Register Reset Value #define PTR_RTN_DW3_EP2_18_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_18_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_18_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_18_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_18_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_19_CPU_EGP_4 Register PTR_RTN_DW2_EP2_19_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_19_CPU_EGP_4 0x14198 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_19_CPU_EGP_4 0x190D4198u //! Register Reset Value #define PTR_RTN_DW2_EP2_19_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_19_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_19_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_19_CPU_EGP_4 Register PTR_RTN_DW3_EP2_19_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_19_CPU_EGP_4 0x1419C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_19_CPU_EGP_4 0x190D419Cu //! Register Reset Value #define PTR_RTN_DW3_EP2_19_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_19_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_19_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_19_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_19_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_20_CPU_EGP_4 Register PTR_RTN_DW2_EP2_20_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_20_CPU_EGP_4 0x141A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_20_CPU_EGP_4 0x190D41A0u //! Register Reset Value #define PTR_RTN_DW2_EP2_20_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_20_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_20_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_20_CPU_EGP_4 Register PTR_RTN_DW3_EP2_20_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_20_CPU_EGP_4 0x141A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_20_CPU_EGP_4 0x190D41A4u //! Register Reset Value #define PTR_RTN_DW3_EP2_20_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_20_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_20_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_20_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_20_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_21_CPU_EGP_4 Register PTR_RTN_DW2_EP2_21_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_21_CPU_EGP_4 0x141A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_21_CPU_EGP_4 0x190D41A8u //! Register Reset Value #define PTR_RTN_DW2_EP2_21_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_21_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_21_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_21_CPU_EGP_4 Register PTR_RTN_DW3_EP2_21_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_21_CPU_EGP_4 0x141AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_21_CPU_EGP_4 0x190D41ACu //! Register Reset Value #define PTR_RTN_DW3_EP2_21_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_21_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_21_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_21_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_21_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_22_CPU_EGP_4 Register PTR_RTN_DW2_EP2_22_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_22_CPU_EGP_4 0x141B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_22_CPU_EGP_4 0x190D41B0u //! Register Reset Value #define PTR_RTN_DW2_EP2_22_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_22_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_22_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_22_CPU_EGP_4 Register PTR_RTN_DW3_EP2_22_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_22_CPU_EGP_4 0x141B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_22_CPU_EGP_4 0x190D41B4u //! Register Reset Value #define PTR_RTN_DW3_EP2_22_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_22_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_22_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_22_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_22_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_23_CPU_EGP_4 Register PTR_RTN_DW2_EP2_23_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_23_CPU_EGP_4 0x141B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_23_CPU_EGP_4 0x190D41B8u //! Register Reset Value #define PTR_RTN_DW2_EP2_23_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_23_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_23_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_23_CPU_EGP_4 Register PTR_RTN_DW3_EP2_23_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_23_CPU_EGP_4 0x141BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_23_CPU_EGP_4 0x190D41BCu //! Register Reset Value #define PTR_RTN_DW3_EP2_23_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_23_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_23_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_23_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_23_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_24_CPU_EGP_4 Register PTR_RTN_DW2_EP2_24_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_24_CPU_EGP_4 0x141C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_24_CPU_EGP_4 0x190D41C0u //! Register Reset Value #define PTR_RTN_DW2_EP2_24_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_24_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_24_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_24_CPU_EGP_4 Register PTR_RTN_DW3_EP2_24_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_24_CPU_EGP_4 0x141C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_24_CPU_EGP_4 0x190D41C4u //! Register Reset Value #define PTR_RTN_DW3_EP2_24_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_24_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_24_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_24_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_24_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_25_CPU_EGP_4 Register PTR_RTN_DW2_EP2_25_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_25_CPU_EGP_4 0x141C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_25_CPU_EGP_4 0x190D41C8u //! Register Reset Value #define PTR_RTN_DW2_EP2_25_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_25_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_25_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_25_CPU_EGP_4 Register PTR_RTN_DW3_EP2_25_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_25_CPU_EGP_4 0x141CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_25_CPU_EGP_4 0x190D41CCu //! Register Reset Value #define PTR_RTN_DW3_EP2_25_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_25_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_25_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_25_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_25_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_26_CPU_EGP_4 Register PTR_RTN_DW2_EP2_26_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_26_CPU_EGP_4 0x141D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_26_CPU_EGP_4 0x190D41D0u //! Register Reset Value #define PTR_RTN_DW2_EP2_26_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_26_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_26_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_26_CPU_EGP_4 Register PTR_RTN_DW3_EP2_26_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_26_CPU_EGP_4 0x141D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_26_CPU_EGP_4 0x190D41D4u //! Register Reset Value #define PTR_RTN_DW3_EP2_26_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_26_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_26_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_26_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_26_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_27_CPU_EGP_4 Register PTR_RTN_DW2_EP2_27_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_27_CPU_EGP_4 0x141D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_27_CPU_EGP_4 0x190D41D8u //! Register Reset Value #define PTR_RTN_DW2_EP2_27_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_27_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_27_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_27_CPU_EGP_4 Register PTR_RTN_DW3_EP2_27_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_27_CPU_EGP_4 0x141DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_27_CPU_EGP_4 0x190D41DCu //! Register Reset Value #define PTR_RTN_DW3_EP2_27_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_27_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_27_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_27_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_27_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_28_CPU_EGP_4 Register PTR_RTN_DW2_EP2_28_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_28_CPU_EGP_4 0x141E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_28_CPU_EGP_4 0x190D41E0u //! Register Reset Value #define PTR_RTN_DW2_EP2_28_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_28_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_28_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_28_CPU_EGP_4 Register PTR_RTN_DW3_EP2_28_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_28_CPU_EGP_4 0x141E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_28_CPU_EGP_4 0x190D41E4u //! Register Reset Value #define PTR_RTN_DW3_EP2_28_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_28_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_28_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_28_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_28_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_29_CPU_EGP_4 Register PTR_RTN_DW2_EP2_29_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_29_CPU_EGP_4 0x141E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_29_CPU_EGP_4 0x190D41E8u //! Register Reset Value #define PTR_RTN_DW2_EP2_29_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_29_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_29_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_29_CPU_EGP_4 Register PTR_RTN_DW3_EP2_29_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_29_CPU_EGP_4 0x141EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_29_CPU_EGP_4 0x190D41ECu //! Register Reset Value #define PTR_RTN_DW3_EP2_29_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_29_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_29_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_29_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_29_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_30_CPU_EGP_4 Register PTR_RTN_DW2_EP2_30_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_30_CPU_EGP_4 0x141F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_30_CPU_EGP_4 0x190D41F0u //! Register Reset Value #define PTR_RTN_DW2_EP2_30_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_30_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_30_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_30_CPU_EGP_4 Register PTR_RTN_DW3_EP2_30_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_30_CPU_EGP_4 0x141F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_30_CPU_EGP_4 0x190D41F4u //! Register Reset Value #define PTR_RTN_DW3_EP2_30_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_30_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_30_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_30_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_30_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP2_31_CPU_EGP_4 Register PTR_RTN_DW2_EP2_31_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP2_31_CPU_EGP_4 0x141F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP2_31_CPU_EGP_4 0x190D41F8u //! Register Reset Value #define PTR_RTN_DW2_EP2_31_CPU_EGP_4_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_31_CPU_EGP_4_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP2_31_CPU_EGP_4_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP2_31_CPU_EGP_4 Register PTR_RTN_DW3_EP2_31_CPU_EGP_4 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP2_31_CPU_EGP_4 0x141FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP2_31_CPU_EGP_4 0x190D41FCu //! Register Reset Value #define PTR_RTN_DW3_EP2_31_CPU_EGP_4_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_31_CPU_EGP_4_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_31_CPU_EGP_4_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_31_CPU_EGP_4_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP2_31_CPU_EGP_4_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_EP4_0_CPU_EGP_4 Register DESC0_EP4_0_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_0_CPU_EGP_4 0x14200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_0_CPU_EGP_4 0x190D4200u //! Register Reset Value #define DESC0_EP4_0_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_0_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_0_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_0_CPU_EGP_4 Register DESC1_EP4_0_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_0_CPU_EGP_4 0x14204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_0_CPU_EGP_4 0x190D4204u //! Register Reset Value #define DESC1_EP4_0_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_0_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_0_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_0_CPU_EGP_4 Register DESC2_EP4_0_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_0_CPU_EGP_4 0x14208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_0_CPU_EGP_4 0x190D4208u //! Register Reset Value #define DESC2_EP4_0_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_0_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_0_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_0_CPU_EGP_4 Register DESC3_EP4_0_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_0_CPU_EGP_4 0x1420C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_0_CPU_EGP_4 0x190D420Cu //! Register Reset Value #define DESC3_EP4_0_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_0_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_0_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_1_CPU_EGP_4 Register DESC0_EP4_1_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_1_CPU_EGP_4 0x14210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_1_CPU_EGP_4 0x190D4210u //! Register Reset Value #define DESC0_EP4_1_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_1_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_1_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_1_CPU_EGP_4 Register DESC1_EP4_1_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_1_CPU_EGP_4 0x14214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_1_CPU_EGP_4 0x190D4214u //! Register Reset Value #define DESC1_EP4_1_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_1_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_1_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_1_CPU_EGP_4 Register DESC2_EP4_1_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_1_CPU_EGP_4 0x14218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_1_CPU_EGP_4 0x190D4218u //! Register Reset Value #define DESC2_EP4_1_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_1_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_1_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_1_CPU_EGP_4 Register DESC3_EP4_1_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_1_CPU_EGP_4 0x1421C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_1_CPU_EGP_4 0x190D421Cu //! Register Reset Value #define DESC3_EP4_1_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_1_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_1_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_2_CPU_EGP_4 Register DESC0_EP4_2_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_2_CPU_EGP_4 0x14220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_2_CPU_EGP_4 0x190D4220u //! Register Reset Value #define DESC0_EP4_2_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_2_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_2_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_2_CPU_EGP_4 Register DESC1_EP4_2_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_2_CPU_EGP_4 0x14224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_2_CPU_EGP_4 0x190D4224u //! Register Reset Value #define DESC1_EP4_2_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_2_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_2_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_2_CPU_EGP_4 Register DESC2_EP4_2_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_2_CPU_EGP_4 0x14228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_2_CPU_EGP_4 0x190D4228u //! Register Reset Value #define DESC2_EP4_2_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_2_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_2_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_2_CPU_EGP_4 Register DESC3_EP4_2_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_2_CPU_EGP_4 0x1422C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_2_CPU_EGP_4 0x190D422Cu //! Register Reset Value #define DESC3_EP4_2_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_2_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_2_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_3_CPU_EGP_4 Register DESC0_EP4_3_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_3_CPU_EGP_4 0x14230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_3_CPU_EGP_4 0x190D4230u //! Register Reset Value #define DESC0_EP4_3_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_3_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_3_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_3_CPU_EGP_4 Register DESC1_EP4_3_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_3_CPU_EGP_4 0x14234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_3_CPU_EGP_4 0x190D4234u //! Register Reset Value #define DESC1_EP4_3_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_3_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_3_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_3_CPU_EGP_4 Register DESC2_EP4_3_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_3_CPU_EGP_4 0x14238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_3_CPU_EGP_4 0x190D4238u //! Register Reset Value #define DESC2_EP4_3_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_3_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_3_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_3_CPU_EGP_4 Register DESC3_EP4_3_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_3_CPU_EGP_4 0x1423C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_3_CPU_EGP_4 0x190D423Cu //! Register Reset Value #define DESC3_EP4_3_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_3_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_3_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_4_CPU_EGP_4 Register DESC0_EP4_4_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_4_CPU_EGP_4 0x14240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_4_CPU_EGP_4 0x190D4240u //! Register Reset Value #define DESC0_EP4_4_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_4_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_4_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_4_CPU_EGP_4 Register DESC1_EP4_4_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_4_CPU_EGP_4 0x14244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_4_CPU_EGP_4 0x190D4244u //! Register Reset Value #define DESC1_EP4_4_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_4_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_4_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_4_CPU_EGP_4 Register DESC2_EP4_4_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_4_CPU_EGP_4 0x14248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_4_CPU_EGP_4 0x190D4248u //! Register Reset Value #define DESC2_EP4_4_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_4_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_4_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_4_CPU_EGP_4 Register DESC3_EP4_4_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_4_CPU_EGP_4 0x1424C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_4_CPU_EGP_4 0x190D424Cu //! Register Reset Value #define DESC3_EP4_4_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_4_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_4_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_5_CPU_EGP_4 Register DESC0_EP4_5_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_5_CPU_EGP_4 0x14250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_5_CPU_EGP_4 0x190D4250u //! Register Reset Value #define DESC0_EP4_5_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_5_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_5_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_5_CPU_EGP_4 Register DESC1_EP4_5_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_5_CPU_EGP_4 0x14254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_5_CPU_EGP_4 0x190D4254u //! Register Reset Value #define DESC1_EP4_5_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_5_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_5_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_5_CPU_EGP_4 Register DESC2_EP4_5_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_5_CPU_EGP_4 0x14258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_5_CPU_EGP_4 0x190D4258u //! Register Reset Value #define DESC2_EP4_5_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_5_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_5_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_5_CPU_EGP_4 Register DESC3_EP4_5_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_5_CPU_EGP_4 0x1425C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_5_CPU_EGP_4 0x190D425Cu //! Register Reset Value #define DESC3_EP4_5_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_5_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_5_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_6_CPU_EGP_4 Register DESC0_EP4_6_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_6_CPU_EGP_4 0x14260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_6_CPU_EGP_4 0x190D4260u //! Register Reset Value #define DESC0_EP4_6_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_6_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_6_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_6_CPU_EGP_4 Register DESC1_EP4_6_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_6_CPU_EGP_4 0x14264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_6_CPU_EGP_4 0x190D4264u //! Register Reset Value #define DESC1_EP4_6_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_6_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_6_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_6_CPU_EGP_4 Register DESC2_EP4_6_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_6_CPU_EGP_4 0x14268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_6_CPU_EGP_4 0x190D4268u //! Register Reset Value #define DESC2_EP4_6_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_6_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_6_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_6_CPU_EGP_4 Register DESC3_EP4_6_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_6_CPU_EGP_4 0x1426C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_6_CPU_EGP_4 0x190D426Cu //! Register Reset Value #define DESC3_EP4_6_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_6_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_6_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_7_CPU_EGP_4 Register DESC0_EP4_7_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_7_CPU_EGP_4 0x14270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_7_CPU_EGP_4 0x190D4270u //! Register Reset Value #define DESC0_EP4_7_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_7_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_7_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_7_CPU_EGP_4 Register DESC1_EP4_7_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_7_CPU_EGP_4 0x14274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_7_CPU_EGP_4 0x190D4274u //! Register Reset Value #define DESC1_EP4_7_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_7_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_7_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_7_CPU_EGP_4 Register DESC2_EP4_7_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_7_CPU_EGP_4 0x14278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_7_CPU_EGP_4 0x190D4278u //! Register Reset Value #define DESC2_EP4_7_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_7_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_7_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_7_CPU_EGP_4 Register DESC3_EP4_7_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_7_CPU_EGP_4 0x1427C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_7_CPU_EGP_4 0x190D427Cu //! Register Reset Value #define DESC3_EP4_7_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_7_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_7_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_8_CPU_EGP_4 Register DESC0_EP4_8_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_8_CPU_EGP_4 0x14280 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_8_CPU_EGP_4 0x190D4280u //! Register Reset Value #define DESC0_EP4_8_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_8_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_8_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_8_CPU_EGP_4 Register DESC1_EP4_8_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_8_CPU_EGP_4 0x14284 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_8_CPU_EGP_4 0x190D4284u //! Register Reset Value #define DESC1_EP4_8_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_8_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_8_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_8_CPU_EGP_4 Register DESC2_EP4_8_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_8_CPU_EGP_4 0x14288 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_8_CPU_EGP_4 0x190D4288u //! Register Reset Value #define DESC2_EP4_8_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_8_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_8_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_8_CPU_EGP_4 Register DESC3_EP4_8_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_8_CPU_EGP_4 0x1428C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_8_CPU_EGP_4 0x190D428Cu //! Register Reset Value #define DESC3_EP4_8_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_8_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_8_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_9_CPU_EGP_4 Register DESC0_EP4_9_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_9_CPU_EGP_4 0x14290 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_9_CPU_EGP_4 0x190D4290u //! Register Reset Value #define DESC0_EP4_9_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_9_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_9_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_9_CPU_EGP_4 Register DESC1_EP4_9_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_9_CPU_EGP_4 0x14294 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_9_CPU_EGP_4 0x190D4294u //! Register Reset Value #define DESC1_EP4_9_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_9_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_9_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_9_CPU_EGP_4 Register DESC2_EP4_9_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_9_CPU_EGP_4 0x14298 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_9_CPU_EGP_4 0x190D4298u //! Register Reset Value #define DESC2_EP4_9_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_9_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_9_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_9_CPU_EGP_4 Register DESC3_EP4_9_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_9_CPU_EGP_4 0x1429C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_9_CPU_EGP_4 0x190D429Cu //! Register Reset Value #define DESC3_EP4_9_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_9_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_9_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_10_CPU_EGP_4 Register DESC0_EP4_10_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_10_CPU_EGP_4 0x142A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_10_CPU_EGP_4 0x190D42A0u //! Register Reset Value #define DESC0_EP4_10_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_10_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_10_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_10_CPU_EGP_4 Register DESC1_EP4_10_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_10_CPU_EGP_4 0x142A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_10_CPU_EGP_4 0x190D42A4u //! Register Reset Value #define DESC1_EP4_10_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_10_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_10_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_10_CPU_EGP_4 Register DESC2_EP4_10_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_10_CPU_EGP_4 0x142A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_10_CPU_EGP_4 0x190D42A8u //! Register Reset Value #define DESC2_EP4_10_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_10_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_10_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_10_CPU_EGP_4 Register DESC3_EP4_10_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_10_CPU_EGP_4 0x142AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_10_CPU_EGP_4 0x190D42ACu //! Register Reset Value #define DESC3_EP4_10_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_10_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_10_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_11_CPU_EGP_4 Register DESC0_EP4_11_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_11_CPU_EGP_4 0x142B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_11_CPU_EGP_4 0x190D42B0u //! Register Reset Value #define DESC0_EP4_11_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_11_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_11_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_11_CPU_EGP_4 Register DESC1_EP4_11_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_11_CPU_EGP_4 0x142B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_11_CPU_EGP_4 0x190D42B4u //! Register Reset Value #define DESC1_EP4_11_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_11_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_11_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_11_CPU_EGP_4 Register DESC2_EP4_11_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_11_CPU_EGP_4 0x142B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_11_CPU_EGP_4 0x190D42B8u //! Register Reset Value #define DESC2_EP4_11_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_11_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_11_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_11_CPU_EGP_4 Register DESC3_EP4_11_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_11_CPU_EGP_4 0x142BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_11_CPU_EGP_4 0x190D42BCu //! Register Reset Value #define DESC3_EP4_11_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_11_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_11_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_12_CPU_EGP_4 Register DESC0_EP4_12_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_12_CPU_EGP_4 0x142C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_12_CPU_EGP_4 0x190D42C0u //! Register Reset Value #define DESC0_EP4_12_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_12_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_12_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_12_CPU_EGP_4 Register DESC1_EP4_12_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_12_CPU_EGP_4 0x142C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_12_CPU_EGP_4 0x190D42C4u //! Register Reset Value #define DESC1_EP4_12_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_12_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_12_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_12_CPU_EGP_4 Register DESC2_EP4_12_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_12_CPU_EGP_4 0x142C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_12_CPU_EGP_4 0x190D42C8u //! Register Reset Value #define DESC2_EP4_12_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_12_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_12_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_12_CPU_EGP_4 Register DESC3_EP4_12_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_12_CPU_EGP_4 0x142CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_12_CPU_EGP_4 0x190D42CCu //! Register Reset Value #define DESC3_EP4_12_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_12_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_12_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_13_CPU_EGP_4 Register DESC0_EP4_13_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_13_CPU_EGP_4 0x142D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_13_CPU_EGP_4 0x190D42D0u //! Register Reset Value #define DESC0_EP4_13_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_13_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_13_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_13_CPU_EGP_4 Register DESC1_EP4_13_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_13_CPU_EGP_4 0x142D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_13_CPU_EGP_4 0x190D42D4u //! Register Reset Value #define DESC1_EP4_13_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_13_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_13_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_13_CPU_EGP_4 Register DESC2_EP4_13_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_13_CPU_EGP_4 0x142D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_13_CPU_EGP_4 0x190D42D8u //! Register Reset Value #define DESC2_EP4_13_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_13_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_13_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_13_CPU_EGP_4 Register DESC3_EP4_13_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_13_CPU_EGP_4 0x142DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_13_CPU_EGP_4 0x190D42DCu //! Register Reset Value #define DESC3_EP4_13_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_13_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_13_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_14_CPU_EGP_4 Register DESC0_EP4_14_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_14_CPU_EGP_4 0x142E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_14_CPU_EGP_4 0x190D42E0u //! Register Reset Value #define DESC0_EP4_14_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_14_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_14_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_14_CPU_EGP_4 Register DESC1_EP4_14_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_14_CPU_EGP_4 0x142E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_14_CPU_EGP_4 0x190D42E4u //! Register Reset Value #define DESC1_EP4_14_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_14_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_14_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_14_CPU_EGP_4 Register DESC2_EP4_14_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_14_CPU_EGP_4 0x142E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_14_CPU_EGP_4 0x190D42E8u //! Register Reset Value #define DESC2_EP4_14_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_14_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_14_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_14_CPU_EGP_4 Register DESC3_EP4_14_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_14_CPU_EGP_4 0x142EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_14_CPU_EGP_4 0x190D42ECu //! Register Reset Value #define DESC3_EP4_14_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_14_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_14_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_15_CPU_EGP_4 Register DESC0_EP4_15_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_15_CPU_EGP_4 0x142F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_15_CPU_EGP_4 0x190D42F0u //! Register Reset Value #define DESC0_EP4_15_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_15_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_15_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_15_CPU_EGP_4 Register DESC1_EP4_15_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_15_CPU_EGP_4 0x142F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_15_CPU_EGP_4 0x190D42F4u //! Register Reset Value #define DESC1_EP4_15_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_15_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_15_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_15_CPU_EGP_4 Register DESC2_EP4_15_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_15_CPU_EGP_4 0x142F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_15_CPU_EGP_4 0x190D42F8u //! Register Reset Value #define DESC2_EP4_15_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_15_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_15_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_15_CPU_EGP_4 Register DESC3_EP4_15_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_15_CPU_EGP_4 0x142FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_15_CPU_EGP_4 0x190D42FCu //! Register Reset Value #define DESC3_EP4_15_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_15_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_15_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_16_CPU_EGP_4 Register DESC0_EP4_16_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_16_CPU_EGP_4 0x14300 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_16_CPU_EGP_4 0x190D4300u //! Register Reset Value #define DESC0_EP4_16_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_16_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_16_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_16_CPU_EGP_4 Register DESC1_EP4_16_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_16_CPU_EGP_4 0x14304 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_16_CPU_EGP_4 0x190D4304u //! Register Reset Value #define DESC1_EP4_16_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_16_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_16_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_16_CPU_EGP_4 Register DESC2_EP4_16_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_16_CPU_EGP_4 0x14308 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_16_CPU_EGP_4 0x190D4308u //! Register Reset Value #define DESC2_EP4_16_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_16_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_16_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_16_CPU_EGP_4 Register DESC3_EP4_16_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_16_CPU_EGP_4 0x1430C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_16_CPU_EGP_4 0x190D430Cu //! Register Reset Value #define DESC3_EP4_16_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_16_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_16_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_17_CPU_EGP_4 Register DESC0_EP4_17_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_17_CPU_EGP_4 0x14310 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_17_CPU_EGP_4 0x190D4310u //! Register Reset Value #define DESC0_EP4_17_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_17_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_17_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_17_CPU_EGP_4 Register DESC1_EP4_17_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_17_CPU_EGP_4 0x14314 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_17_CPU_EGP_4 0x190D4314u //! Register Reset Value #define DESC1_EP4_17_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_17_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_17_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_17_CPU_EGP_4 Register DESC2_EP4_17_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_17_CPU_EGP_4 0x14318 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_17_CPU_EGP_4 0x190D4318u //! Register Reset Value #define DESC2_EP4_17_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_17_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_17_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_17_CPU_EGP_4 Register DESC3_EP4_17_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_17_CPU_EGP_4 0x1431C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_17_CPU_EGP_4 0x190D431Cu //! Register Reset Value #define DESC3_EP4_17_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_17_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_17_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_18_CPU_EGP_4 Register DESC0_EP4_18_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_18_CPU_EGP_4 0x14320 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_18_CPU_EGP_4 0x190D4320u //! Register Reset Value #define DESC0_EP4_18_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_18_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_18_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_18_CPU_EGP_4 Register DESC1_EP4_18_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_18_CPU_EGP_4 0x14324 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_18_CPU_EGP_4 0x190D4324u //! Register Reset Value #define DESC1_EP4_18_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_18_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_18_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_18_CPU_EGP_4 Register DESC2_EP4_18_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_18_CPU_EGP_4 0x14328 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_18_CPU_EGP_4 0x190D4328u //! Register Reset Value #define DESC2_EP4_18_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_18_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_18_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_18_CPU_EGP_4 Register DESC3_EP4_18_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_18_CPU_EGP_4 0x1432C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_18_CPU_EGP_4 0x190D432Cu //! Register Reset Value #define DESC3_EP4_18_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_18_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_18_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_19_CPU_EGP_4 Register DESC0_EP4_19_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_19_CPU_EGP_4 0x14330 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_19_CPU_EGP_4 0x190D4330u //! Register Reset Value #define DESC0_EP4_19_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_19_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_19_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_19_CPU_EGP_4 Register DESC1_EP4_19_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_19_CPU_EGP_4 0x14334 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_19_CPU_EGP_4 0x190D4334u //! Register Reset Value #define DESC1_EP4_19_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_19_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_19_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_19_CPU_EGP_4 Register DESC2_EP4_19_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_19_CPU_EGP_4 0x14338 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_19_CPU_EGP_4 0x190D4338u //! Register Reset Value #define DESC2_EP4_19_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_19_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_19_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_19_CPU_EGP_4 Register DESC3_EP4_19_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_19_CPU_EGP_4 0x1433C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_19_CPU_EGP_4 0x190D433Cu //! Register Reset Value #define DESC3_EP4_19_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_19_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_19_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_20_CPU_EGP_4 Register DESC0_EP4_20_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_20_CPU_EGP_4 0x14340 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_20_CPU_EGP_4 0x190D4340u //! Register Reset Value #define DESC0_EP4_20_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_20_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_20_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_20_CPU_EGP_4 Register DESC1_EP4_20_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_20_CPU_EGP_4 0x14344 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_20_CPU_EGP_4 0x190D4344u //! Register Reset Value #define DESC1_EP4_20_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_20_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_20_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_20_CPU_EGP_4 Register DESC2_EP4_20_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_20_CPU_EGP_4 0x14348 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_20_CPU_EGP_4 0x190D4348u //! Register Reset Value #define DESC2_EP4_20_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_20_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_20_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_20_CPU_EGP_4 Register DESC3_EP4_20_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_20_CPU_EGP_4 0x1434C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_20_CPU_EGP_4 0x190D434Cu //! Register Reset Value #define DESC3_EP4_20_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_20_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_20_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_21_CPU_EGP_4 Register DESC0_EP4_21_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_21_CPU_EGP_4 0x14350 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_21_CPU_EGP_4 0x190D4350u //! Register Reset Value #define DESC0_EP4_21_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_21_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_21_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_21_CPU_EGP_4 Register DESC1_EP4_21_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_21_CPU_EGP_4 0x14354 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_21_CPU_EGP_4 0x190D4354u //! Register Reset Value #define DESC1_EP4_21_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_21_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_21_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_21_CPU_EGP_4 Register DESC2_EP4_21_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_21_CPU_EGP_4 0x14358 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_21_CPU_EGP_4 0x190D4358u //! Register Reset Value #define DESC2_EP4_21_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_21_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_21_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_21_CPU_EGP_4 Register DESC3_EP4_21_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_21_CPU_EGP_4 0x1435C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_21_CPU_EGP_4 0x190D435Cu //! Register Reset Value #define DESC3_EP4_21_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_21_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_21_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_22_CPU_EGP_4 Register DESC0_EP4_22_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_22_CPU_EGP_4 0x14360 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_22_CPU_EGP_4 0x190D4360u //! Register Reset Value #define DESC0_EP4_22_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_22_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_22_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_22_CPU_EGP_4 Register DESC1_EP4_22_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_22_CPU_EGP_4 0x14364 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_22_CPU_EGP_4 0x190D4364u //! Register Reset Value #define DESC1_EP4_22_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_22_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_22_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_22_CPU_EGP_4 Register DESC2_EP4_22_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_22_CPU_EGP_4 0x14368 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_22_CPU_EGP_4 0x190D4368u //! Register Reset Value #define DESC2_EP4_22_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_22_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_22_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_22_CPU_EGP_4 Register DESC3_EP4_22_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_22_CPU_EGP_4 0x1436C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_22_CPU_EGP_4 0x190D436Cu //! Register Reset Value #define DESC3_EP4_22_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_22_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_22_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_23_CPU_EGP_4 Register DESC0_EP4_23_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_23_CPU_EGP_4 0x14370 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_23_CPU_EGP_4 0x190D4370u //! Register Reset Value #define DESC0_EP4_23_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_23_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_23_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_23_CPU_EGP_4 Register DESC1_EP4_23_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_23_CPU_EGP_4 0x14374 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_23_CPU_EGP_4 0x190D4374u //! Register Reset Value #define DESC1_EP4_23_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_23_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_23_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_23_CPU_EGP_4 Register DESC2_EP4_23_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_23_CPU_EGP_4 0x14378 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_23_CPU_EGP_4 0x190D4378u //! Register Reset Value #define DESC2_EP4_23_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_23_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_23_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_23_CPU_EGP_4 Register DESC3_EP4_23_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_23_CPU_EGP_4 0x1437C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_23_CPU_EGP_4 0x190D437Cu //! Register Reset Value #define DESC3_EP4_23_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_23_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_23_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_24_CPU_EGP_4 Register DESC0_EP4_24_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_24_CPU_EGP_4 0x14380 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_24_CPU_EGP_4 0x190D4380u //! Register Reset Value #define DESC0_EP4_24_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_24_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_24_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_24_CPU_EGP_4 Register DESC1_EP4_24_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_24_CPU_EGP_4 0x14384 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_24_CPU_EGP_4 0x190D4384u //! Register Reset Value #define DESC1_EP4_24_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_24_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_24_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_24_CPU_EGP_4 Register DESC2_EP4_24_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_24_CPU_EGP_4 0x14388 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_24_CPU_EGP_4 0x190D4388u //! Register Reset Value #define DESC2_EP4_24_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_24_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_24_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_24_CPU_EGP_4 Register DESC3_EP4_24_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_24_CPU_EGP_4 0x1438C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_24_CPU_EGP_4 0x190D438Cu //! Register Reset Value #define DESC3_EP4_24_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_24_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_24_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_25_CPU_EGP_4 Register DESC0_EP4_25_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_25_CPU_EGP_4 0x14390 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_25_CPU_EGP_4 0x190D4390u //! Register Reset Value #define DESC0_EP4_25_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_25_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_25_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_25_CPU_EGP_4 Register DESC1_EP4_25_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_25_CPU_EGP_4 0x14394 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_25_CPU_EGP_4 0x190D4394u //! Register Reset Value #define DESC1_EP4_25_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_25_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_25_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_25_CPU_EGP_4 Register DESC2_EP4_25_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_25_CPU_EGP_4 0x14398 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_25_CPU_EGP_4 0x190D4398u //! Register Reset Value #define DESC2_EP4_25_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_25_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_25_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_25_CPU_EGP_4 Register DESC3_EP4_25_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_25_CPU_EGP_4 0x1439C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_25_CPU_EGP_4 0x190D439Cu //! Register Reset Value #define DESC3_EP4_25_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_25_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_25_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_26_CPU_EGP_4 Register DESC0_EP4_26_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_26_CPU_EGP_4 0x143A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_26_CPU_EGP_4 0x190D43A0u //! Register Reset Value #define DESC0_EP4_26_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_26_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_26_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_26_CPU_EGP_4 Register DESC1_EP4_26_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_26_CPU_EGP_4 0x143A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_26_CPU_EGP_4 0x190D43A4u //! Register Reset Value #define DESC1_EP4_26_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_26_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_26_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_26_CPU_EGP_4 Register DESC2_EP4_26_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_26_CPU_EGP_4 0x143A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_26_CPU_EGP_4 0x190D43A8u //! Register Reset Value #define DESC2_EP4_26_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_26_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_26_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_26_CPU_EGP_4 Register DESC3_EP4_26_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_26_CPU_EGP_4 0x143AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_26_CPU_EGP_4 0x190D43ACu //! Register Reset Value #define DESC3_EP4_26_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_26_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_26_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_27_CPU_EGP_4 Register DESC0_EP4_27_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_27_CPU_EGP_4 0x143B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_27_CPU_EGP_4 0x190D43B0u //! Register Reset Value #define DESC0_EP4_27_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_27_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_27_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_27_CPU_EGP_4 Register DESC1_EP4_27_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_27_CPU_EGP_4 0x143B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_27_CPU_EGP_4 0x190D43B4u //! Register Reset Value #define DESC1_EP4_27_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_27_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_27_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_27_CPU_EGP_4 Register DESC2_EP4_27_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_27_CPU_EGP_4 0x143B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_27_CPU_EGP_4 0x190D43B8u //! Register Reset Value #define DESC2_EP4_27_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_27_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_27_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_27_CPU_EGP_4 Register DESC3_EP4_27_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_27_CPU_EGP_4 0x143BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_27_CPU_EGP_4 0x190D43BCu //! Register Reset Value #define DESC3_EP4_27_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_27_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_27_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_28_CPU_EGP_4 Register DESC0_EP4_28_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_28_CPU_EGP_4 0x143C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_28_CPU_EGP_4 0x190D43C0u //! Register Reset Value #define DESC0_EP4_28_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_28_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_28_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_28_CPU_EGP_4 Register DESC1_EP4_28_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_28_CPU_EGP_4 0x143C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_28_CPU_EGP_4 0x190D43C4u //! Register Reset Value #define DESC1_EP4_28_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_28_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_28_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_28_CPU_EGP_4 Register DESC2_EP4_28_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_28_CPU_EGP_4 0x143C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_28_CPU_EGP_4 0x190D43C8u //! Register Reset Value #define DESC2_EP4_28_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_28_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_28_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_28_CPU_EGP_4 Register DESC3_EP4_28_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_28_CPU_EGP_4 0x143CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_28_CPU_EGP_4 0x190D43CCu //! Register Reset Value #define DESC3_EP4_28_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_28_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_28_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_29_CPU_EGP_4 Register DESC0_EP4_29_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_29_CPU_EGP_4 0x143D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_29_CPU_EGP_4 0x190D43D0u //! Register Reset Value #define DESC0_EP4_29_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_29_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_29_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_29_CPU_EGP_4 Register DESC1_EP4_29_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_29_CPU_EGP_4 0x143D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_29_CPU_EGP_4 0x190D43D4u //! Register Reset Value #define DESC1_EP4_29_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_29_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_29_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_29_CPU_EGP_4 Register DESC2_EP4_29_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_29_CPU_EGP_4 0x143D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_29_CPU_EGP_4 0x190D43D8u //! Register Reset Value #define DESC2_EP4_29_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_29_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_29_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_29_CPU_EGP_4 Register DESC3_EP4_29_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_29_CPU_EGP_4 0x143DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_29_CPU_EGP_4 0x190D43DCu //! Register Reset Value #define DESC3_EP4_29_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_29_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_29_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_30_CPU_EGP_4 Register DESC0_EP4_30_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_30_CPU_EGP_4 0x143E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_30_CPU_EGP_4 0x190D43E0u //! Register Reset Value #define DESC0_EP4_30_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_30_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_30_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_30_CPU_EGP_4 Register DESC1_EP4_30_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_30_CPU_EGP_4 0x143E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_30_CPU_EGP_4 0x190D43E4u //! Register Reset Value #define DESC1_EP4_30_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_30_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_30_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_30_CPU_EGP_4 Register DESC2_EP4_30_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_30_CPU_EGP_4 0x143E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_30_CPU_EGP_4 0x190D43E8u //! Register Reset Value #define DESC2_EP4_30_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_30_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_30_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_30_CPU_EGP_4 Register DESC3_EP4_30_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_30_CPU_EGP_4 0x143EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_30_CPU_EGP_4 0x190D43ECu //! Register Reset Value #define DESC3_EP4_30_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_30_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_30_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP4_31_CPU_EGP_4 Register DESC0_EP4_31_CPU_EGP_4 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP4_31_CPU_EGP_4 0x143F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP4_31_CPU_EGP_4 0x190D43F0u //! Register Reset Value #define DESC0_EP4_31_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_31_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP4_31_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP4_31_CPU_EGP_4 Register DESC1_EP4_31_CPU_EGP_4 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP4_31_CPU_EGP_4 0x143F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP4_31_CPU_EGP_4 0x190D43F4u //! Register Reset Value #define DESC1_EP4_31_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_31_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP4_31_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP4_31_CPU_EGP_4 Register DESC2_EP4_31_CPU_EGP_4 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP4_31_CPU_EGP_4 0x143F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP4_31_CPU_EGP_4 0x190D43F8u //! Register Reset Value #define DESC2_EP4_31_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_31_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP4_31_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP4_31_CPU_EGP_4 Register DESC3_EP4_31_CPU_EGP_4 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP4_31_CPU_EGP_4 0x143FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP4_31_CPU_EGP_4 0x190D43FCu //! Register Reset Value #define DESC3_EP4_31_CPU_EGP_4_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_31_CPU_EGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP4_31_CPU_EGP_4_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_ACA_EGP_5 Register CFG_ACA_EGP_5 - CPU ACA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_ACA_EGP_5 0x15000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_ACA_EGP_5 0x190D5000u //! Register Reset Value #define CFG_ACA_EGP_5_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_5_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_5_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_5_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_5_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_5_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_5_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_5_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_5_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_5_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_5_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_5_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_5_BFBPEN_EN 0x1 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_5_DQBPEN_POS 3 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_5_DQBPEN_MASK 0x8u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_5_DQBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_5_DQBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_5_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_5_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_5_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_5_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_5_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_5_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_5 Register DQPC_CPU_EGP_5 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_5 0x15004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_5 0x190D5004u //! Register Reset Value #define DQPC_CPU_EGP_5_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_5_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_5_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_5 Register IRNCR_CPU_EGP_5 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_5 0x15020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_5 0x190D5020u //! Register Reset Value #define IRNCR_CPU_EGP_5_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_5_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_5_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_5_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_5_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_5_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_5_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_5_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_5_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_5 Register IRNICR_CPU_EGP_5 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_5 0x15024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_5 0x190D5024u //! Register Reset Value #define IRNICR_CPU_EGP_5_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_5_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_5_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_5_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_5_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_5 Register IRNEN_CPU_EGP_5 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_5 0x15028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_5 0x190D5028u //! Register Reset Value #define IRNEN_CPU_EGP_5_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_5_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_5_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_5_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_5_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_5_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_5_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_5_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_5_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_5 Register DPTR_CPU_EGP_5 - Special CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_5 0x15030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_5 0x190D5030u //! Register Reset Value #define DPTR_CPU_EGP_5_RST 0x0000001Fu //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_5_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_5_ND_MASK 0x1Fu //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_5_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_5_DPTR_MASK 0x1F0000u //! @} //! \defgroup BPRC_CPU_EGP_5 Register BPRC_CPU_EGP_5 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_5 0x15034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_5 0x190D5034u //! Register Reset Value #define BPRC_CPU_EGP_5_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_5_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_5_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup BRPTR_SCPU_EGP_5 Register BRPTR_SCPU_EGP_5 - Special CPU Egress Port Buffer Return Pointer //! @{ //! Register Offset (relative) #define BRPTR_SCPU_EGP_5 0x15038 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BRPTR_SCPU_EGP_5 0x190D5038u //! Register Reset Value #define BRPTR_SCPU_EGP_5_RST 0x00000000u //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_5_PTRBR_POS 0 //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_5_PTRBR_MASK 0x1Fu //! @} //! \defgroup PTR_RTN_DW2_EP3_0_CPU_EGP_5 Register PTR_RTN_DW2_EP3_0_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_0_CPU_EGP_5 0x15100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_0_CPU_EGP_5 0x190D5100u //! Register Reset Value #define PTR_RTN_DW2_EP3_0_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_0_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_0_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_0_CPU_EGP_5 Register PTR_RTN_DW3_EP3_0_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_0_CPU_EGP_5 0x15104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_0_CPU_EGP_5 0x190D5104u //! Register Reset Value #define PTR_RTN_DW3_EP3_0_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_0_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_0_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_0_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_0_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_1_CPU_EGP_5 Register PTR_RTN_DW2_EP3_1_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_1_CPU_EGP_5 0x15108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_1_CPU_EGP_5 0x190D5108u //! Register Reset Value #define PTR_RTN_DW2_EP3_1_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_1_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_1_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_1_CPU_EGP_5 Register PTR_RTN_DW3_EP3_1_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_1_CPU_EGP_5 0x1510C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_1_CPU_EGP_5 0x190D510Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_1_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_1_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_1_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_1_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_1_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_2_CPU_EGP_5 Register PTR_RTN_DW2_EP3_2_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_2_CPU_EGP_5 0x15110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_2_CPU_EGP_5 0x190D5110u //! Register Reset Value #define PTR_RTN_DW2_EP3_2_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_2_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_2_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_2_CPU_EGP_5 Register PTR_RTN_DW3_EP3_2_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_2_CPU_EGP_5 0x15114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_2_CPU_EGP_5 0x190D5114u //! Register Reset Value #define PTR_RTN_DW3_EP3_2_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_2_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_2_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_2_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_2_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_3_CPU_EGP_5 Register PTR_RTN_DW2_EP3_3_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_3_CPU_EGP_5 0x15118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_3_CPU_EGP_5 0x190D5118u //! Register Reset Value #define PTR_RTN_DW2_EP3_3_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_3_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_3_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_3_CPU_EGP_5 Register PTR_RTN_DW3_EP3_3_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_3_CPU_EGP_5 0x1511C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_3_CPU_EGP_5 0x190D511Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_3_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_3_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_3_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_3_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_3_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_4_CPU_EGP_5 Register PTR_RTN_DW2_EP3_4_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_4_CPU_EGP_5 0x15120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_4_CPU_EGP_5 0x190D5120u //! Register Reset Value #define PTR_RTN_DW2_EP3_4_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_4_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_4_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_4_CPU_EGP_5 Register PTR_RTN_DW3_EP3_4_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_4_CPU_EGP_5 0x15124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_4_CPU_EGP_5 0x190D5124u //! Register Reset Value #define PTR_RTN_DW3_EP3_4_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_4_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_4_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_4_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_4_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_5_CPU_EGP_5 Register PTR_RTN_DW2_EP3_5_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_5_CPU_EGP_5 0x15128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_5_CPU_EGP_5 0x190D5128u //! Register Reset Value #define PTR_RTN_DW2_EP3_5_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_5_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_5_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_5_CPU_EGP_5 Register PTR_RTN_DW3_EP3_5_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_5_CPU_EGP_5 0x1512C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_5_CPU_EGP_5 0x190D512Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_5_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_5_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_5_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_5_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_5_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_6_CPU_EGP_5 Register PTR_RTN_DW2_EP3_6_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_6_CPU_EGP_5 0x15130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_6_CPU_EGP_5 0x190D5130u //! Register Reset Value #define PTR_RTN_DW2_EP3_6_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_6_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_6_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_6_CPU_EGP_5 Register PTR_RTN_DW3_EP3_6_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_6_CPU_EGP_5 0x15134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_6_CPU_EGP_5 0x190D5134u //! Register Reset Value #define PTR_RTN_DW3_EP3_6_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_6_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_6_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_6_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_6_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_7_CPU_EGP_5 Register PTR_RTN_DW2_EP3_7_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_7_CPU_EGP_5 0x15138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_7_CPU_EGP_5 0x190D5138u //! Register Reset Value #define PTR_RTN_DW2_EP3_7_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_7_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_7_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_7_CPU_EGP_5 Register PTR_RTN_DW3_EP3_7_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_7_CPU_EGP_5 0x1513C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_7_CPU_EGP_5 0x190D513Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_7_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_7_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_7_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_7_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_7_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_8_CPU_EGP_5 Register PTR_RTN_DW2_EP3_8_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_8_CPU_EGP_5 0x15140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_8_CPU_EGP_5 0x190D5140u //! Register Reset Value #define PTR_RTN_DW2_EP3_8_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_8_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_8_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_8_CPU_EGP_5 Register PTR_RTN_DW3_EP3_8_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_8_CPU_EGP_5 0x15144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_8_CPU_EGP_5 0x190D5144u //! Register Reset Value #define PTR_RTN_DW3_EP3_8_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_8_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_8_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_8_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_8_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_9_CPU_EGP_5 Register PTR_RTN_DW2_EP3_9_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_9_CPU_EGP_5 0x15148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_9_CPU_EGP_5 0x190D5148u //! Register Reset Value #define PTR_RTN_DW2_EP3_9_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_9_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_9_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_9_CPU_EGP_5 Register PTR_RTN_DW3_EP3_9_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_9_CPU_EGP_5 0x1514C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_9_CPU_EGP_5 0x190D514Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_9_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_9_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_9_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_9_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_9_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_10_CPU_EGP_5 Register PTR_RTN_DW2_EP3_10_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_10_CPU_EGP_5 0x15150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_10_CPU_EGP_5 0x190D5150u //! Register Reset Value #define PTR_RTN_DW2_EP3_10_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_10_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_10_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_10_CPU_EGP_5 Register PTR_RTN_DW3_EP3_10_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_10_CPU_EGP_5 0x15154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_10_CPU_EGP_5 0x190D5154u //! Register Reset Value #define PTR_RTN_DW3_EP3_10_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_10_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_10_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_10_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_10_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_11_CPU_EGP_5 Register PTR_RTN_DW2_EP3_11_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_11_CPU_EGP_5 0x15158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_11_CPU_EGP_5 0x190D5158u //! Register Reset Value #define PTR_RTN_DW2_EP3_11_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_11_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_11_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_11_CPU_EGP_5 Register PTR_RTN_DW3_EP3_11_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_11_CPU_EGP_5 0x1515C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_11_CPU_EGP_5 0x190D515Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_11_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_11_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_11_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_11_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_11_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_12_CPU_EGP_5 Register PTR_RTN_DW2_EP3_12_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_12_CPU_EGP_5 0x15160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_12_CPU_EGP_5 0x190D5160u //! Register Reset Value #define PTR_RTN_DW2_EP3_12_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_12_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_12_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_12_CPU_EGP_5 Register PTR_RTN_DW3_EP3_12_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_12_CPU_EGP_5 0x15164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_12_CPU_EGP_5 0x190D5164u //! Register Reset Value #define PTR_RTN_DW3_EP3_12_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_12_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_12_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_12_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_12_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_13_CPU_EGP_5 Register PTR_RTN_DW2_EP3_13_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_13_CPU_EGP_5 0x15168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_13_CPU_EGP_5 0x190D5168u //! Register Reset Value #define PTR_RTN_DW2_EP3_13_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_13_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_13_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_13_CPU_EGP_5 Register PTR_RTN_DW3_EP3_13_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_13_CPU_EGP_5 0x1516C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_13_CPU_EGP_5 0x190D516Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_13_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_13_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_13_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_13_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_13_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_14_CPU_EGP_5 Register PTR_RTN_DW2_EP3_14_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_14_CPU_EGP_5 0x15170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_14_CPU_EGP_5 0x190D5170u //! Register Reset Value #define PTR_RTN_DW2_EP3_14_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_14_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_14_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_14_CPU_EGP_5 Register PTR_RTN_DW3_EP3_14_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_14_CPU_EGP_5 0x15174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_14_CPU_EGP_5 0x190D5174u //! Register Reset Value #define PTR_RTN_DW3_EP3_14_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_14_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_14_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_14_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_14_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_15_CPU_EGP_5 Register PTR_RTN_DW2_EP3_15_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_15_CPU_EGP_5 0x15178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_15_CPU_EGP_5 0x190D5178u //! Register Reset Value #define PTR_RTN_DW2_EP3_15_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_15_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_15_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_15_CPU_EGP_5 Register PTR_RTN_DW3_EP3_15_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_15_CPU_EGP_5 0x1517C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_15_CPU_EGP_5 0x190D517Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_15_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_15_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_15_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_15_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_15_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_16_CPU_EGP_5 Register PTR_RTN_DW2_EP3_16_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_16_CPU_EGP_5 0x15180 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_16_CPU_EGP_5 0x190D5180u //! Register Reset Value #define PTR_RTN_DW2_EP3_16_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_16_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_16_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_16_CPU_EGP_5 Register PTR_RTN_DW3_EP3_16_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_16_CPU_EGP_5 0x15184 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_16_CPU_EGP_5 0x190D5184u //! Register Reset Value #define PTR_RTN_DW3_EP3_16_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_16_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_16_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_16_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_16_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_17_CPU_EGP_5 Register PTR_RTN_DW2_EP3_17_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_17_CPU_EGP_5 0x15188 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_17_CPU_EGP_5 0x190D5188u //! Register Reset Value #define PTR_RTN_DW2_EP3_17_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_17_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_17_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_17_CPU_EGP_5 Register PTR_RTN_DW3_EP3_17_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_17_CPU_EGP_5 0x1518C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_17_CPU_EGP_5 0x190D518Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_17_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_17_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_17_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_17_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_17_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_18_CPU_EGP_5 Register PTR_RTN_DW2_EP3_18_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_18_CPU_EGP_5 0x15190 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_18_CPU_EGP_5 0x190D5190u //! Register Reset Value #define PTR_RTN_DW2_EP3_18_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_18_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_18_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_18_CPU_EGP_5 Register PTR_RTN_DW3_EP3_18_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_18_CPU_EGP_5 0x15194 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_18_CPU_EGP_5 0x190D5194u //! Register Reset Value #define PTR_RTN_DW3_EP3_18_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_18_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_18_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_18_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_18_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_19_CPU_EGP_5 Register PTR_RTN_DW2_EP3_19_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_19_CPU_EGP_5 0x15198 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_19_CPU_EGP_5 0x190D5198u //! Register Reset Value #define PTR_RTN_DW2_EP3_19_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_19_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_19_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_19_CPU_EGP_5 Register PTR_RTN_DW3_EP3_19_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_19_CPU_EGP_5 0x1519C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_19_CPU_EGP_5 0x190D519Cu //! Register Reset Value #define PTR_RTN_DW3_EP3_19_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_19_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_19_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_19_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_19_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_20_CPU_EGP_5 Register PTR_RTN_DW2_EP3_20_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_20_CPU_EGP_5 0x151A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_20_CPU_EGP_5 0x190D51A0u //! Register Reset Value #define PTR_RTN_DW2_EP3_20_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_20_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_20_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_20_CPU_EGP_5 Register PTR_RTN_DW3_EP3_20_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_20_CPU_EGP_5 0x151A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_20_CPU_EGP_5 0x190D51A4u //! Register Reset Value #define PTR_RTN_DW3_EP3_20_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_20_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_20_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_20_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_20_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_21_CPU_EGP_5 Register PTR_RTN_DW2_EP3_21_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_21_CPU_EGP_5 0x151A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_21_CPU_EGP_5 0x190D51A8u //! Register Reset Value #define PTR_RTN_DW2_EP3_21_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_21_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_21_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_21_CPU_EGP_5 Register PTR_RTN_DW3_EP3_21_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_21_CPU_EGP_5 0x151AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_21_CPU_EGP_5 0x190D51ACu //! Register Reset Value #define PTR_RTN_DW3_EP3_21_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_21_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_21_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_21_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_21_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_22_CPU_EGP_5 Register PTR_RTN_DW2_EP3_22_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_22_CPU_EGP_5 0x151B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_22_CPU_EGP_5 0x190D51B0u //! Register Reset Value #define PTR_RTN_DW2_EP3_22_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_22_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_22_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_22_CPU_EGP_5 Register PTR_RTN_DW3_EP3_22_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_22_CPU_EGP_5 0x151B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_22_CPU_EGP_5 0x190D51B4u //! Register Reset Value #define PTR_RTN_DW3_EP3_22_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_22_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_22_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_22_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_22_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_23_CPU_EGP_5 Register PTR_RTN_DW2_EP3_23_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_23_CPU_EGP_5 0x151B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_23_CPU_EGP_5 0x190D51B8u //! Register Reset Value #define PTR_RTN_DW2_EP3_23_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_23_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_23_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_23_CPU_EGP_5 Register PTR_RTN_DW3_EP3_23_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_23_CPU_EGP_5 0x151BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_23_CPU_EGP_5 0x190D51BCu //! Register Reset Value #define PTR_RTN_DW3_EP3_23_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_23_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_23_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_23_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_23_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_24_CPU_EGP_5 Register PTR_RTN_DW2_EP3_24_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_24_CPU_EGP_5 0x151C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_24_CPU_EGP_5 0x190D51C0u //! Register Reset Value #define PTR_RTN_DW2_EP3_24_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_24_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_24_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_24_CPU_EGP_5 Register PTR_RTN_DW3_EP3_24_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_24_CPU_EGP_5 0x151C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_24_CPU_EGP_5 0x190D51C4u //! Register Reset Value #define PTR_RTN_DW3_EP3_24_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_24_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_24_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_24_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_24_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_25_CPU_EGP_5 Register PTR_RTN_DW2_EP3_25_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_25_CPU_EGP_5 0x151C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_25_CPU_EGP_5 0x190D51C8u //! Register Reset Value #define PTR_RTN_DW2_EP3_25_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_25_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_25_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_25_CPU_EGP_5 Register PTR_RTN_DW3_EP3_25_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_25_CPU_EGP_5 0x151CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_25_CPU_EGP_5 0x190D51CCu //! Register Reset Value #define PTR_RTN_DW3_EP3_25_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_25_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_25_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_25_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_25_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_26_CPU_EGP_5 Register PTR_RTN_DW2_EP3_26_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_26_CPU_EGP_5 0x151D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_26_CPU_EGP_5 0x190D51D0u //! Register Reset Value #define PTR_RTN_DW2_EP3_26_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_26_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_26_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_26_CPU_EGP_5 Register PTR_RTN_DW3_EP3_26_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_26_CPU_EGP_5 0x151D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_26_CPU_EGP_5 0x190D51D4u //! Register Reset Value #define PTR_RTN_DW3_EP3_26_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_26_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_26_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_26_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_26_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_27_CPU_EGP_5 Register PTR_RTN_DW2_EP3_27_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_27_CPU_EGP_5 0x151D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_27_CPU_EGP_5 0x190D51D8u //! Register Reset Value #define PTR_RTN_DW2_EP3_27_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_27_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_27_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_27_CPU_EGP_5 Register PTR_RTN_DW3_EP3_27_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_27_CPU_EGP_5 0x151DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_27_CPU_EGP_5 0x190D51DCu //! Register Reset Value #define PTR_RTN_DW3_EP3_27_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_27_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_27_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_27_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_27_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_28_CPU_EGP_5 Register PTR_RTN_DW2_EP3_28_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_28_CPU_EGP_5 0x151E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_28_CPU_EGP_5 0x190D51E0u //! Register Reset Value #define PTR_RTN_DW2_EP3_28_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_28_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_28_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_28_CPU_EGP_5 Register PTR_RTN_DW3_EP3_28_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_28_CPU_EGP_5 0x151E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_28_CPU_EGP_5 0x190D51E4u //! Register Reset Value #define PTR_RTN_DW3_EP3_28_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_28_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_28_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_28_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_28_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_29_CPU_EGP_5 Register PTR_RTN_DW2_EP3_29_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_29_CPU_EGP_5 0x151E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_29_CPU_EGP_5 0x190D51E8u //! Register Reset Value #define PTR_RTN_DW2_EP3_29_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_29_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_29_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_29_CPU_EGP_5 Register PTR_RTN_DW3_EP3_29_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_29_CPU_EGP_5 0x151EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_29_CPU_EGP_5 0x190D51ECu //! Register Reset Value #define PTR_RTN_DW3_EP3_29_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_29_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_29_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_29_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_29_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_30_CPU_EGP_5 Register PTR_RTN_DW2_EP3_30_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_30_CPU_EGP_5 0x151F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_30_CPU_EGP_5 0x190D51F0u //! Register Reset Value #define PTR_RTN_DW2_EP3_30_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_30_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_30_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_30_CPU_EGP_5 Register PTR_RTN_DW3_EP3_30_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_30_CPU_EGP_5 0x151F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_30_CPU_EGP_5 0x190D51F4u //! Register Reset Value #define PTR_RTN_DW3_EP3_30_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_30_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_30_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_30_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_30_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP3_31_CPU_EGP_5 Register PTR_RTN_DW2_EP3_31_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP3_31_CPU_EGP_5 0x151F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP3_31_CPU_EGP_5 0x190D51F8u //! Register Reset Value #define PTR_RTN_DW2_EP3_31_CPU_EGP_5_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_31_CPU_EGP_5_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP3_31_CPU_EGP_5_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP3_31_CPU_EGP_5 Register PTR_RTN_DW3_EP3_31_CPU_EGP_5 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP3_31_CPU_EGP_5 0x151FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP3_31_CPU_EGP_5 0x190D51FCu //! Register Reset Value #define PTR_RTN_DW3_EP3_31_CPU_EGP_5_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_31_CPU_EGP_5_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_31_CPU_EGP_5_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_31_CPU_EGP_5_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP3_31_CPU_EGP_5_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_EP5_0_CPU_EGP_5 Register DESC0_EP5_0_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_0_CPU_EGP_5 0x15200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_0_CPU_EGP_5 0x190D5200u //! Register Reset Value #define DESC0_EP5_0_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_0_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_0_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_0_CPU_EGP_5 Register DESC1_EP5_0_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_0_CPU_EGP_5 0x15204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_0_CPU_EGP_5 0x190D5204u //! Register Reset Value #define DESC1_EP5_0_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_0_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_0_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_0_CPU_EGP_5 Register DESC2_EP5_0_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_0_CPU_EGP_5 0x15208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_0_CPU_EGP_5 0x190D5208u //! Register Reset Value #define DESC2_EP5_0_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_0_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_0_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_0_CPU_EGP_5 Register DESC3_EP5_0_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_0_CPU_EGP_5 0x1520C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_0_CPU_EGP_5 0x190D520Cu //! Register Reset Value #define DESC3_EP5_0_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_0_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_0_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_1_CPU_EGP_5 Register DESC0_EP5_1_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_1_CPU_EGP_5 0x15210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_1_CPU_EGP_5 0x190D5210u //! Register Reset Value #define DESC0_EP5_1_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_1_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_1_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_1_CPU_EGP_5 Register DESC1_EP5_1_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_1_CPU_EGP_5 0x15214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_1_CPU_EGP_5 0x190D5214u //! Register Reset Value #define DESC1_EP5_1_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_1_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_1_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_1_CPU_EGP_5 Register DESC2_EP5_1_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_1_CPU_EGP_5 0x15218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_1_CPU_EGP_5 0x190D5218u //! Register Reset Value #define DESC2_EP5_1_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_1_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_1_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_1_CPU_EGP_5 Register DESC3_EP5_1_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_1_CPU_EGP_5 0x1521C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_1_CPU_EGP_5 0x190D521Cu //! Register Reset Value #define DESC3_EP5_1_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_1_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_1_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_2_CPU_EGP_5 Register DESC0_EP5_2_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_2_CPU_EGP_5 0x15220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_2_CPU_EGP_5 0x190D5220u //! Register Reset Value #define DESC0_EP5_2_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_2_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_2_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_2_CPU_EGP_5 Register DESC1_EP5_2_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_2_CPU_EGP_5 0x15224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_2_CPU_EGP_5 0x190D5224u //! Register Reset Value #define DESC1_EP5_2_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_2_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_2_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_2_CPU_EGP_5 Register DESC2_EP5_2_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_2_CPU_EGP_5 0x15228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_2_CPU_EGP_5 0x190D5228u //! Register Reset Value #define DESC2_EP5_2_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_2_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_2_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_2_CPU_EGP_5 Register DESC3_EP5_2_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_2_CPU_EGP_5 0x1522C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_2_CPU_EGP_5 0x190D522Cu //! Register Reset Value #define DESC3_EP5_2_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_2_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_2_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_3_CPU_EGP_5 Register DESC0_EP5_3_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_3_CPU_EGP_5 0x15230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_3_CPU_EGP_5 0x190D5230u //! Register Reset Value #define DESC0_EP5_3_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_3_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_3_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_3_CPU_EGP_5 Register DESC1_EP5_3_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_3_CPU_EGP_5 0x15234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_3_CPU_EGP_5 0x190D5234u //! Register Reset Value #define DESC1_EP5_3_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_3_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_3_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_3_CPU_EGP_5 Register DESC2_EP5_3_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_3_CPU_EGP_5 0x15238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_3_CPU_EGP_5 0x190D5238u //! Register Reset Value #define DESC2_EP5_3_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_3_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_3_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_3_CPU_EGP_5 Register DESC3_EP5_3_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_3_CPU_EGP_5 0x1523C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_3_CPU_EGP_5 0x190D523Cu //! Register Reset Value #define DESC3_EP5_3_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_3_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_3_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_4_CPU_EGP_5 Register DESC0_EP5_4_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_4_CPU_EGP_5 0x15240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_4_CPU_EGP_5 0x190D5240u //! Register Reset Value #define DESC0_EP5_4_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_4_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_4_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_4_CPU_EGP_5 Register DESC1_EP5_4_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_4_CPU_EGP_5 0x15244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_4_CPU_EGP_5 0x190D5244u //! Register Reset Value #define DESC1_EP5_4_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_4_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_4_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_4_CPU_EGP_5 Register DESC2_EP5_4_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_4_CPU_EGP_5 0x15248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_4_CPU_EGP_5 0x190D5248u //! Register Reset Value #define DESC2_EP5_4_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_4_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_4_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_4_CPU_EGP_5 Register DESC3_EP5_4_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_4_CPU_EGP_5 0x1524C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_4_CPU_EGP_5 0x190D524Cu //! Register Reset Value #define DESC3_EP5_4_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_4_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_4_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_5_CPU_EGP_5 Register DESC0_EP5_5_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_5_CPU_EGP_5 0x15250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_5_CPU_EGP_5 0x190D5250u //! Register Reset Value #define DESC0_EP5_5_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_5_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_5_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_5_CPU_EGP_5 Register DESC1_EP5_5_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_5_CPU_EGP_5 0x15254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_5_CPU_EGP_5 0x190D5254u //! Register Reset Value #define DESC1_EP5_5_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_5_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_5_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_5_CPU_EGP_5 Register DESC2_EP5_5_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_5_CPU_EGP_5 0x15258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_5_CPU_EGP_5 0x190D5258u //! Register Reset Value #define DESC2_EP5_5_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_5_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_5_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_5_CPU_EGP_5 Register DESC3_EP5_5_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_5_CPU_EGP_5 0x1525C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_5_CPU_EGP_5 0x190D525Cu //! Register Reset Value #define DESC3_EP5_5_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_5_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_5_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_6_CPU_EGP_5 Register DESC0_EP5_6_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_6_CPU_EGP_5 0x15260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_6_CPU_EGP_5 0x190D5260u //! Register Reset Value #define DESC0_EP5_6_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_6_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_6_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_6_CPU_EGP_5 Register DESC1_EP5_6_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_6_CPU_EGP_5 0x15264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_6_CPU_EGP_5 0x190D5264u //! Register Reset Value #define DESC1_EP5_6_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_6_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_6_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_6_CPU_EGP_5 Register DESC2_EP5_6_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_6_CPU_EGP_5 0x15268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_6_CPU_EGP_5 0x190D5268u //! Register Reset Value #define DESC2_EP5_6_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_6_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_6_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_6_CPU_EGP_5 Register DESC3_EP5_6_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_6_CPU_EGP_5 0x1526C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_6_CPU_EGP_5 0x190D526Cu //! Register Reset Value #define DESC3_EP5_6_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_6_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_6_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_7_CPU_EGP_5 Register DESC0_EP5_7_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_7_CPU_EGP_5 0x15270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_7_CPU_EGP_5 0x190D5270u //! Register Reset Value #define DESC0_EP5_7_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_7_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_7_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_7_CPU_EGP_5 Register DESC1_EP5_7_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_7_CPU_EGP_5 0x15274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_7_CPU_EGP_5 0x190D5274u //! Register Reset Value #define DESC1_EP5_7_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_7_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_7_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_7_CPU_EGP_5 Register DESC2_EP5_7_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_7_CPU_EGP_5 0x15278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_7_CPU_EGP_5 0x190D5278u //! Register Reset Value #define DESC2_EP5_7_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_7_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_7_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_7_CPU_EGP_5 Register DESC3_EP5_7_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_7_CPU_EGP_5 0x1527C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_7_CPU_EGP_5 0x190D527Cu //! Register Reset Value #define DESC3_EP5_7_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_7_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_7_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_8_CPU_EGP_5 Register DESC0_EP5_8_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_8_CPU_EGP_5 0x15280 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_8_CPU_EGP_5 0x190D5280u //! Register Reset Value #define DESC0_EP5_8_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_8_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_8_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_8_CPU_EGP_5 Register DESC1_EP5_8_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_8_CPU_EGP_5 0x15284 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_8_CPU_EGP_5 0x190D5284u //! Register Reset Value #define DESC1_EP5_8_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_8_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_8_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_8_CPU_EGP_5 Register DESC2_EP5_8_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_8_CPU_EGP_5 0x15288 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_8_CPU_EGP_5 0x190D5288u //! Register Reset Value #define DESC2_EP5_8_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_8_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_8_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_8_CPU_EGP_5 Register DESC3_EP5_8_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_8_CPU_EGP_5 0x1528C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_8_CPU_EGP_5 0x190D528Cu //! Register Reset Value #define DESC3_EP5_8_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_8_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_8_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_9_CPU_EGP_5 Register DESC0_EP5_9_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_9_CPU_EGP_5 0x15290 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_9_CPU_EGP_5 0x190D5290u //! Register Reset Value #define DESC0_EP5_9_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_9_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_9_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_9_CPU_EGP_5 Register DESC1_EP5_9_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_9_CPU_EGP_5 0x15294 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_9_CPU_EGP_5 0x190D5294u //! Register Reset Value #define DESC1_EP5_9_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_9_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_9_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_9_CPU_EGP_5 Register DESC2_EP5_9_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_9_CPU_EGP_5 0x15298 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_9_CPU_EGP_5 0x190D5298u //! Register Reset Value #define DESC2_EP5_9_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_9_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_9_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_9_CPU_EGP_5 Register DESC3_EP5_9_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_9_CPU_EGP_5 0x1529C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_9_CPU_EGP_5 0x190D529Cu //! Register Reset Value #define DESC3_EP5_9_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_9_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_9_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_10_CPU_EGP_5 Register DESC0_EP5_10_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_10_CPU_EGP_5 0x152A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_10_CPU_EGP_5 0x190D52A0u //! Register Reset Value #define DESC0_EP5_10_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_10_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_10_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_10_CPU_EGP_5 Register DESC1_EP5_10_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_10_CPU_EGP_5 0x152A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_10_CPU_EGP_5 0x190D52A4u //! Register Reset Value #define DESC1_EP5_10_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_10_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_10_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_10_CPU_EGP_5 Register DESC2_EP5_10_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_10_CPU_EGP_5 0x152A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_10_CPU_EGP_5 0x190D52A8u //! Register Reset Value #define DESC2_EP5_10_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_10_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_10_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_10_CPU_EGP_5 Register DESC3_EP5_10_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_10_CPU_EGP_5 0x152AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_10_CPU_EGP_5 0x190D52ACu //! Register Reset Value #define DESC3_EP5_10_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_10_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_10_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_11_CPU_EGP_5 Register DESC0_EP5_11_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_11_CPU_EGP_5 0x152B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_11_CPU_EGP_5 0x190D52B0u //! Register Reset Value #define DESC0_EP5_11_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_11_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_11_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_11_CPU_EGP_5 Register DESC1_EP5_11_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_11_CPU_EGP_5 0x152B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_11_CPU_EGP_5 0x190D52B4u //! Register Reset Value #define DESC1_EP5_11_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_11_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_11_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_11_CPU_EGP_5 Register DESC2_EP5_11_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_11_CPU_EGP_5 0x152B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_11_CPU_EGP_5 0x190D52B8u //! Register Reset Value #define DESC2_EP5_11_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_11_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_11_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_11_CPU_EGP_5 Register DESC3_EP5_11_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_11_CPU_EGP_5 0x152BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_11_CPU_EGP_5 0x190D52BCu //! Register Reset Value #define DESC3_EP5_11_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_11_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_11_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_12_CPU_EGP_5 Register DESC0_EP5_12_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_12_CPU_EGP_5 0x152C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_12_CPU_EGP_5 0x190D52C0u //! Register Reset Value #define DESC0_EP5_12_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_12_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_12_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_12_CPU_EGP_5 Register DESC1_EP5_12_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_12_CPU_EGP_5 0x152C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_12_CPU_EGP_5 0x190D52C4u //! Register Reset Value #define DESC1_EP5_12_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_12_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_12_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_12_CPU_EGP_5 Register DESC2_EP5_12_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_12_CPU_EGP_5 0x152C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_12_CPU_EGP_5 0x190D52C8u //! Register Reset Value #define DESC2_EP5_12_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_12_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_12_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_12_CPU_EGP_5 Register DESC3_EP5_12_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_12_CPU_EGP_5 0x152CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_12_CPU_EGP_5 0x190D52CCu //! Register Reset Value #define DESC3_EP5_12_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_12_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_12_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_13_CPU_EGP_5 Register DESC0_EP5_13_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_13_CPU_EGP_5 0x152D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_13_CPU_EGP_5 0x190D52D0u //! Register Reset Value #define DESC0_EP5_13_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_13_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_13_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_13_CPU_EGP_5 Register DESC1_EP5_13_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_13_CPU_EGP_5 0x152D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_13_CPU_EGP_5 0x190D52D4u //! Register Reset Value #define DESC1_EP5_13_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_13_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_13_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_13_CPU_EGP_5 Register DESC2_EP5_13_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_13_CPU_EGP_5 0x152D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_13_CPU_EGP_5 0x190D52D8u //! Register Reset Value #define DESC2_EP5_13_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_13_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_13_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_13_CPU_EGP_5 Register DESC3_EP5_13_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_13_CPU_EGP_5 0x152DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_13_CPU_EGP_5 0x190D52DCu //! Register Reset Value #define DESC3_EP5_13_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_13_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_13_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_14_CPU_EGP_5 Register DESC0_EP5_14_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_14_CPU_EGP_5 0x152E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_14_CPU_EGP_5 0x190D52E0u //! Register Reset Value #define DESC0_EP5_14_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_14_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_14_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_14_CPU_EGP_5 Register DESC1_EP5_14_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_14_CPU_EGP_5 0x152E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_14_CPU_EGP_5 0x190D52E4u //! Register Reset Value #define DESC1_EP5_14_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_14_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_14_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_14_CPU_EGP_5 Register DESC2_EP5_14_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_14_CPU_EGP_5 0x152E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_14_CPU_EGP_5 0x190D52E8u //! Register Reset Value #define DESC2_EP5_14_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_14_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_14_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_14_CPU_EGP_5 Register DESC3_EP5_14_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_14_CPU_EGP_5 0x152EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_14_CPU_EGP_5 0x190D52ECu //! Register Reset Value #define DESC3_EP5_14_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_14_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_14_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_15_CPU_EGP_5 Register DESC0_EP5_15_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_15_CPU_EGP_5 0x152F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_15_CPU_EGP_5 0x190D52F0u //! Register Reset Value #define DESC0_EP5_15_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_15_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_15_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_15_CPU_EGP_5 Register DESC1_EP5_15_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_15_CPU_EGP_5 0x152F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_15_CPU_EGP_5 0x190D52F4u //! Register Reset Value #define DESC1_EP5_15_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_15_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_15_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_15_CPU_EGP_5 Register DESC2_EP5_15_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_15_CPU_EGP_5 0x152F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_15_CPU_EGP_5 0x190D52F8u //! Register Reset Value #define DESC2_EP5_15_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_15_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_15_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_15_CPU_EGP_5 Register DESC3_EP5_15_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_15_CPU_EGP_5 0x152FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_15_CPU_EGP_5 0x190D52FCu //! Register Reset Value #define DESC3_EP5_15_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_15_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_15_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_16_CPU_EGP_5 Register DESC0_EP5_16_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_16_CPU_EGP_5 0x15300 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_16_CPU_EGP_5 0x190D5300u //! Register Reset Value #define DESC0_EP5_16_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_16_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_16_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_16_CPU_EGP_5 Register DESC1_EP5_16_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_16_CPU_EGP_5 0x15304 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_16_CPU_EGP_5 0x190D5304u //! Register Reset Value #define DESC1_EP5_16_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_16_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_16_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_16_CPU_EGP_5 Register DESC2_EP5_16_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_16_CPU_EGP_5 0x15308 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_16_CPU_EGP_5 0x190D5308u //! Register Reset Value #define DESC2_EP5_16_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_16_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_16_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_16_CPU_EGP_5 Register DESC3_EP5_16_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_16_CPU_EGP_5 0x1530C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_16_CPU_EGP_5 0x190D530Cu //! Register Reset Value #define DESC3_EP5_16_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_16_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_16_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_17_CPU_EGP_5 Register DESC0_EP5_17_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_17_CPU_EGP_5 0x15310 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_17_CPU_EGP_5 0x190D5310u //! Register Reset Value #define DESC0_EP5_17_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_17_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_17_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_17_CPU_EGP_5 Register DESC1_EP5_17_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_17_CPU_EGP_5 0x15314 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_17_CPU_EGP_5 0x190D5314u //! Register Reset Value #define DESC1_EP5_17_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_17_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_17_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_17_CPU_EGP_5 Register DESC2_EP5_17_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_17_CPU_EGP_5 0x15318 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_17_CPU_EGP_5 0x190D5318u //! Register Reset Value #define DESC2_EP5_17_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_17_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_17_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_17_CPU_EGP_5 Register DESC3_EP5_17_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_17_CPU_EGP_5 0x1531C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_17_CPU_EGP_5 0x190D531Cu //! Register Reset Value #define DESC3_EP5_17_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_17_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_17_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_18_CPU_EGP_5 Register DESC0_EP5_18_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_18_CPU_EGP_5 0x15320 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_18_CPU_EGP_5 0x190D5320u //! Register Reset Value #define DESC0_EP5_18_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_18_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_18_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_18_CPU_EGP_5 Register DESC1_EP5_18_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_18_CPU_EGP_5 0x15324 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_18_CPU_EGP_5 0x190D5324u //! Register Reset Value #define DESC1_EP5_18_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_18_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_18_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_18_CPU_EGP_5 Register DESC2_EP5_18_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_18_CPU_EGP_5 0x15328 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_18_CPU_EGP_5 0x190D5328u //! Register Reset Value #define DESC2_EP5_18_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_18_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_18_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_18_CPU_EGP_5 Register DESC3_EP5_18_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_18_CPU_EGP_5 0x1532C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_18_CPU_EGP_5 0x190D532Cu //! Register Reset Value #define DESC3_EP5_18_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_18_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_18_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_19_CPU_EGP_5 Register DESC0_EP5_19_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_19_CPU_EGP_5 0x15330 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_19_CPU_EGP_5 0x190D5330u //! Register Reset Value #define DESC0_EP5_19_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_19_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_19_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_19_CPU_EGP_5 Register DESC1_EP5_19_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_19_CPU_EGP_5 0x15334 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_19_CPU_EGP_5 0x190D5334u //! Register Reset Value #define DESC1_EP5_19_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_19_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_19_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_19_CPU_EGP_5 Register DESC2_EP5_19_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_19_CPU_EGP_5 0x15338 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_19_CPU_EGP_5 0x190D5338u //! Register Reset Value #define DESC2_EP5_19_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_19_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_19_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_19_CPU_EGP_5 Register DESC3_EP5_19_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_19_CPU_EGP_5 0x1533C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_19_CPU_EGP_5 0x190D533Cu //! Register Reset Value #define DESC3_EP5_19_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_19_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_19_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_20_CPU_EGP_5 Register DESC0_EP5_20_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_20_CPU_EGP_5 0x15340 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_20_CPU_EGP_5 0x190D5340u //! Register Reset Value #define DESC0_EP5_20_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_20_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_20_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_20_CPU_EGP_5 Register DESC1_EP5_20_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_20_CPU_EGP_5 0x15344 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_20_CPU_EGP_5 0x190D5344u //! Register Reset Value #define DESC1_EP5_20_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_20_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_20_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_20_CPU_EGP_5 Register DESC2_EP5_20_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_20_CPU_EGP_5 0x15348 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_20_CPU_EGP_5 0x190D5348u //! Register Reset Value #define DESC2_EP5_20_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_20_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_20_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_20_CPU_EGP_5 Register DESC3_EP5_20_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_20_CPU_EGP_5 0x1534C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_20_CPU_EGP_5 0x190D534Cu //! Register Reset Value #define DESC3_EP5_20_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_20_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_20_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_21_CPU_EGP_5 Register DESC0_EP5_21_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_21_CPU_EGP_5 0x15350 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_21_CPU_EGP_5 0x190D5350u //! Register Reset Value #define DESC0_EP5_21_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_21_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_21_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_21_CPU_EGP_5 Register DESC1_EP5_21_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_21_CPU_EGP_5 0x15354 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_21_CPU_EGP_5 0x190D5354u //! Register Reset Value #define DESC1_EP5_21_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_21_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_21_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_21_CPU_EGP_5 Register DESC2_EP5_21_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_21_CPU_EGP_5 0x15358 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_21_CPU_EGP_5 0x190D5358u //! Register Reset Value #define DESC2_EP5_21_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_21_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_21_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_21_CPU_EGP_5 Register DESC3_EP5_21_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_21_CPU_EGP_5 0x1535C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_21_CPU_EGP_5 0x190D535Cu //! Register Reset Value #define DESC3_EP5_21_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_21_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_21_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_22_CPU_EGP_5 Register DESC0_EP5_22_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_22_CPU_EGP_5 0x15360 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_22_CPU_EGP_5 0x190D5360u //! Register Reset Value #define DESC0_EP5_22_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_22_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_22_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_22_CPU_EGP_5 Register DESC1_EP5_22_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_22_CPU_EGP_5 0x15364 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_22_CPU_EGP_5 0x190D5364u //! Register Reset Value #define DESC1_EP5_22_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_22_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_22_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_22_CPU_EGP_5 Register DESC2_EP5_22_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_22_CPU_EGP_5 0x15368 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_22_CPU_EGP_5 0x190D5368u //! Register Reset Value #define DESC2_EP5_22_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_22_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_22_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_22_CPU_EGP_5 Register DESC3_EP5_22_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_22_CPU_EGP_5 0x1536C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_22_CPU_EGP_5 0x190D536Cu //! Register Reset Value #define DESC3_EP5_22_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_22_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_22_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_23_CPU_EGP_5 Register DESC0_EP5_23_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_23_CPU_EGP_5 0x15370 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_23_CPU_EGP_5 0x190D5370u //! Register Reset Value #define DESC0_EP5_23_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_23_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_23_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_23_CPU_EGP_5 Register DESC1_EP5_23_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_23_CPU_EGP_5 0x15374 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_23_CPU_EGP_5 0x190D5374u //! Register Reset Value #define DESC1_EP5_23_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_23_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_23_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_23_CPU_EGP_5 Register DESC2_EP5_23_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_23_CPU_EGP_5 0x15378 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_23_CPU_EGP_5 0x190D5378u //! Register Reset Value #define DESC2_EP5_23_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_23_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_23_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_23_CPU_EGP_5 Register DESC3_EP5_23_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_23_CPU_EGP_5 0x1537C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_23_CPU_EGP_5 0x190D537Cu //! Register Reset Value #define DESC3_EP5_23_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_23_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_23_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_24_CPU_EGP_5 Register DESC0_EP5_24_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_24_CPU_EGP_5 0x15380 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_24_CPU_EGP_5 0x190D5380u //! Register Reset Value #define DESC0_EP5_24_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_24_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_24_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_24_CPU_EGP_5 Register DESC1_EP5_24_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_24_CPU_EGP_5 0x15384 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_24_CPU_EGP_5 0x190D5384u //! Register Reset Value #define DESC1_EP5_24_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_24_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_24_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_24_CPU_EGP_5 Register DESC2_EP5_24_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_24_CPU_EGP_5 0x15388 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_24_CPU_EGP_5 0x190D5388u //! Register Reset Value #define DESC2_EP5_24_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_24_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_24_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_24_CPU_EGP_5 Register DESC3_EP5_24_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_24_CPU_EGP_5 0x1538C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_24_CPU_EGP_5 0x190D538Cu //! Register Reset Value #define DESC3_EP5_24_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_24_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_24_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_25_CPU_EGP_5 Register DESC0_EP5_25_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_25_CPU_EGP_5 0x15390 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_25_CPU_EGP_5 0x190D5390u //! Register Reset Value #define DESC0_EP5_25_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_25_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_25_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_25_CPU_EGP_5 Register DESC1_EP5_25_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_25_CPU_EGP_5 0x15394 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_25_CPU_EGP_5 0x190D5394u //! Register Reset Value #define DESC1_EP5_25_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_25_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_25_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_25_CPU_EGP_5 Register DESC2_EP5_25_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_25_CPU_EGP_5 0x15398 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_25_CPU_EGP_5 0x190D5398u //! Register Reset Value #define DESC2_EP5_25_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_25_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_25_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_25_CPU_EGP_5 Register DESC3_EP5_25_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_25_CPU_EGP_5 0x1539C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_25_CPU_EGP_5 0x190D539Cu //! Register Reset Value #define DESC3_EP5_25_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_25_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_25_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_26_CPU_EGP_5 Register DESC0_EP5_26_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_26_CPU_EGP_5 0x153A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_26_CPU_EGP_5 0x190D53A0u //! Register Reset Value #define DESC0_EP5_26_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_26_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_26_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_26_CPU_EGP_5 Register DESC1_EP5_26_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_26_CPU_EGP_5 0x153A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_26_CPU_EGP_5 0x190D53A4u //! Register Reset Value #define DESC1_EP5_26_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_26_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_26_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_26_CPU_EGP_5 Register DESC2_EP5_26_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_26_CPU_EGP_5 0x153A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_26_CPU_EGP_5 0x190D53A8u //! Register Reset Value #define DESC2_EP5_26_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_26_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_26_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_26_CPU_EGP_5 Register DESC3_EP5_26_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_26_CPU_EGP_5 0x153AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_26_CPU_EGP_5 0x190D53ACu //! Register Reset Value #define DESC3_EP5_26_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_26_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_26_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_27_CPU_EGP_5 Register DESC0_EP5_27_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_27_CPU_EGP_5 0x153B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_27_CPU_EGP_5 0x190D53B0u //! Register Reset Value #define DESC0_EP5_27_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_27_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_27_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_27_CPU_EGP_5 Register DESC1_EP5_27_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_27_CPU_EGP_5 0x153B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_27_CPU_EGP_5 0x190D53B4u //! Register Reset Value #define DESC1_EP5_27_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_27_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_27_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_27_CPU_EGP_5 Register DESC2_EP5_27_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_27_CPU_EGP_5 0x153B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_27_CPU_EGP_5 0x190D53B8u //! Register Reset Value #define DESC2_EP5_27_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_27_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_27_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_27_CPU_EGP_5 Register DESC3_EP5_27_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_27_CPU_EGP_5 0x153BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_27_CPU_EGP_5 0x190D53BCu //! Register Reset Value #define DESC3_EP5_27_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_27_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_27_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_28_CPU_EGP_5 Register DESC0_EP5_28_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_28_CPU_EGP_5 0x153C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_28_CPU_EGP_5 0x190D53C0u //! Register Reset Value #define DESC0_EP5_28_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_28_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_28_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_28_CPU_EGP_5 Register DESC1_EP5_28_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_28_CPU_EGP_5 0x153C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_28_CPU_EGP_5 0x190D53C4u //! Register Reset Value #define DESC1_EP5_28_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_28_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_28_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_28_CPU_EGP_5 Register DESC2_EP5_28_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_28_CPU_EGP_5 0x153C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_28_CPU_EGP_5 0x190D53C8u //! Register Reset Value #define DESC2_EP5_28_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_28_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_28_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_28_CPU_EGP_5 Register DESC3_EP5_28_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_28_CPU_EGP_5 0x153CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_28_CPU_EGP_5 0x190D53CCu //! Register Reset Value #define DESC3_EP5_28_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_28_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_28_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_29_CPU_EGP_5 Register DESC0_EP5_29_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_29_CPU_EGP_5 0x153D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_29_CPU_EGP_5 0x190D53D0u //! Register Reset Value #define DESC0_EP5_29_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_29_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_29_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_29_CPU_EGP_5 Register DESC1_EP5_29_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_29_CPU_EGP_5 0x153D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_29_CPU_EGP_5 0x190D53D4u //! Register Reset Value #define DESC1_EP5_29_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_29_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_29_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_29_CPU_EGP_5 Register DESC2_EP5_29_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_29_CPU_EGP_5 0x153D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_29_CPU_EGP_5 0x190D53D8u //! Register Reset Value #define DESC2_EP5_29_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_29_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_29_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_29_CPU_EGP_5 Register DESC3_EP5_29_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_29_CPU_EGP_5 0x153DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_29_CPU_EGP_5 0x190D53DCu //! Register Reset Value #define DESC3_EP5_29_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_29_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_29_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_30_CPU_EGP_5 Register DESC0_EP5_30_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_30_CPU_EGP_5 0x153E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_30_CPU_EGP_5 0x190D53E0u //! Register Reset Value #define DESC0_EP5_30_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_30_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_30_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_30_CPU_EGP_5 Register DESC1_EP5_30_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_30_CPU_EGP_5 0x153E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_30_CPU_EGP_5 0x190D53E4u //! Register Reset Value #define DESC1_EP5_30_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_30_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_30_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_30_CPU_EGP_5 Register DESC2_EP5_30_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_30_CPU_EGP_5 0x153E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_30_CPU_EGP_5 0x190D53E8u //! Register Reset Value #define DESC2_EP5_30_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_30_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_30_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_30_CPU_EGP_5 Register DESC3_EP5_30_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_30_CPU_EGP_5 0x153EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_30_CPU_EGP_5 0x190D53ECu //! Register Reset Value #define DESC3_EP5_30_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_30_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_30_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP5_31_CPU_EGP_5 Register DESC0_EP5_31_CPU_EGP_5 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP5_31_CPU_EGP_5 0x153F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP5_31_CPU_EGP_5 0x190D53F0u //! Register Reset Value #define DESC0_EP5_31_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_31_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP5_31_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP5_31_CPU_EGP_5 Register DESC1_EP5_31_CPU_EGP_5 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP5_31_CPU_EGP_5 0x153F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP5_31_CPU_EGP_5 0x190D53F4u //! Register Reset Value #define DESC1_EP5_31_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_31_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP5_31_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP5_31_CPU_EGP_5 Register DESC2_EP5_31_CPU_EGP_5 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP5_31_CPU_EGP_5 0x153F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP5_31_CPU_EGP_5 0x190D53F8u //! Register Reset Value #define DESC2_EP5_31_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_31_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP5_31_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP5_31_CPU_EGP_5 Register DESC3_EP5_31_CPU_EGP_5 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP5_31_CPU_EGP_5 0x153FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP5_31_CPU_EGP_5 0x190D53FCu //! Register Reset Value #define DESC3_EP5_31_CPU_EGP_5_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_31_CPU_EGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP5_31_CPU_EGP_5_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_ACA_EGP_6 Register CFG_ACA_EGP_6 - CPU ACA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_ACA_EGP_6 0x16000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_ACA_EGP_6 0x190D6000u //! Register Reset Value #define CFG_ACA_EGP_6_RST 0x00000000u //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_6_DQREQ_POS 0 //! Field DQREQ - Enable CPU Dequeue Request #define CFG_ACA_EGP_6_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_6_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_6_DQREQ_EN 0x1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_6_BUFRTN_POS 1 //! Field BUFRTN - Enable CPU Buffer Return #define CFG_ACA_EGP_6_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_6_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_6_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_6_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_ACA_EGP_6_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_6_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_6_BFBPEN_EN 0x1 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_6_DQBPEN_POS 3 //! Field DQBPEN - Dequeue Back Pressure Enable #define CFG_ACA_EGP_6_DQBPEN_MASK 0x8u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_6_DQBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_6_DQBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_6_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_ACA_EGP_6_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_ACA_EGP_6_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_ACA_EGP_6_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_6_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_ACA_EGP_6_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_CPU_EGP_6 Register DQPC_CPU_EGP_6 - CPU Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_CPU_EGP_6 0x16004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_CPU_EGP_6 0x190D6004u //! Register Reset Value #define DQPC_CPU_EGP_6_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_6_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_CPU_EGP_6_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_CPU_EGP_6 Register IRNCR_CPU_EGP_6 - CPU Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_CPU_EGP_6 0x16020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_CPU_EGP_6 0x190D6020u //! Register Reset Value #define IRNCR_CPU_EGP_6_RST 0x00000000u //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_6_PR_POS 0 //! Field PR - Pointer Ready #define IRNCR_CPU_EGP_6_PR_MASK 0x1u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_6_PR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_6_PR_INTOCC 0x1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_6_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_CPU_EGP_6_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_CPU_EGP_6_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_CPU_EGP_6_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_CPU_EGP_6 Register IRNICR_CPU_EGP_6 - CPU Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_CPU_EGP_6 0x16024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_CPU_EGP_6 0x190D6024u //! Register Reset Value #define IRNICR_CPU_EGP_6_RST 0x00000000u //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_6_PR_POS 0 //! Field PR - Pointer Ready #define IRNICR_CPU_EGP_6_PR_MASK 0x1u //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_6_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_CPU_EGP_6_DR_MASK 0x2u //! @} //! \defgroup IRNEN_CPU_EGP_6 Register IRNEN_CPU_EGP_6 - CPU Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_CPU_EGP_6 0x16028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_CPU_EGP_6 0x190D6028u //! Register Reset Value #define IRNEN_CPU_EGP_6_RST 0x00000000u //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_6_PR_POS 0 //! Field PR - Pointer Ready #define IRNEN_CPU_EGP_6_PR_MASK 0x1u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_6_PR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_6_PR_EN 0x1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_6_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_CPU_EGP_6_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_CPU_EGP_6_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_CPU_EGP_6_DR_EN 0x1 //! @} //! \defgroup DPTR_CPU_EGP_6 Register DPTR_CPU_EGP_6 - Special CPU Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_CPU_EGP_6 0x16030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_CPU_EGP_6 0x190D6030u //! Register Reset Value #define DPTR_CPU_EGP_6_RST 0x0000001Fu //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_6_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_CPU_EGP_6_ND_MASK 0x1Fu //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_6_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_CPU_EGP_6_DPTR_MASK 0x1F0000u //! @} //! \defgroup BPRC_CPU_EGP_6 Register BPRC_CPU_EGP_6 - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_CPU_EGP_6 0x16034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_CPU_EGP_6 0x190D6034u //! Register Reset Value #define BPRC_CPU_EGP_6_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_6_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_CPU_EGP_6_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup BRPTR_SCPU_EGP_6 Register BRPTR_SCPU_EGP_6 - Special CPU Egress Port Buffer Return Pointer //! @{ //! Register Offset (relative) #define BRPTR_SCPU_EGP_6 0x16038 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BRPTR_SCPU_EGP_6 0x190D6038u //! Register Reset Value #define BRPTR_SCPU_EGP_6_RST 0x00000000u //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_6_PTRBR_POS 0 //! Field PTRBR - Pointer of Buffer Return #define BRPTR_SCPU_EGP_6_PTRBR_MASK 0x1Fu //! @} //! \defgroup PTR_RTN_DW2_EP4_0_CPU_EGP_6 Register PTR_RTN_DW2_EP4_0_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_0_CPU_EGP_6 0x16100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_0_CPU_EGP_6 0x190D6100u //! Register Reset Value #define PTR_RTN_DW2_EP4_0_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_0_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_0_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_0_CPU_EGP_6 Register PTR_RTN_DW3_EP4_0_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_0_CPU_EGP_6 0x16104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_0_CPU_EGP_6 0x190D6104u //! Register Reset Value #define PTR_RTN_DW3_EP4_0_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_0_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_0_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_0_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_0_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_1_CPU_EGP_6 Register PTR_RTN_DW2_EP4_1_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_1_CPU_EGP_6 0x16108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_1_CPU_EGP_6 0x190D6108u //! Register Reset Value #define PTR_RTN_DW2_EP4_1_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_1_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_1_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_1_CPU_EGP_6 Register PTR_RTN_DW3_EP4_1_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_1_CPU_EGP_6 0x1610C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_1_CPU_EGP_6 0x190D610Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_1_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_1_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_1_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_1_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_1_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_2_CPU_EGP_6 Register PTR_RTN_DW2_EP4_2_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_2_CPU_EGP_6 0x16110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_2_CPU_EGP_6 0x190D6110u //! Register Reset Value #define PTR_RTN_DW2_EP4_2_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_2_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_2_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_2_CPU_EGP_6 Register PTR_RTN_DW3_EP4_2_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_2_CPU_EGP_6 0x16114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_2_CPU_EGP_6 0x190D6114u //! Register Reset Value #define PTR_RTN_DW3_EP4_2_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_2_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_2_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_2_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_2_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_3_CPU_EGP_6 Register PTR_RTN_DW2_EP4_3_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_3_CPU_EGP_6 0x16118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_3_CPU_EGP_6 0x190D6118u //! Register Reset Value #define PTR_RTN_DW2_EP4_3_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_3_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_3_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_3_CPU_EGP_6 Register PTR_RTN_DW3_EP4_3_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_3_CPU_EGP_6 0x1611C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_3_CPU_EGP_6 0x190D611Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_3_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_3_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_3_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_3_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_3_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_4_CPU_EGP_6 Register PTR_RTN_DW2_EP4_4_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_4_CPU_EGP_6 0x16120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_4_CPU_EGP_6 0x190D6120u //! Register Reset Value #define PTR_RTN_DW2_EP4_4_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_4_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_4_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_4_CPU_EGP_6 Register PTR_RTN_DW3_EP4_4_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_4_CPU_EGP_6 0x16124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_4_CPU_EGP_6 0x190D6124u //! Register Reset Value #define PTR_RTN_DW3_EP4_4_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_4_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_4_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_4_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_4_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_5_CPU_EGP_6 Register PTR_RTN_DW2_EP4_5_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_5_CPU_EGP_6 0x16128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_5_CPU_EGP_6 0x190D6128u //! Register Reset Value #define PTR_RTN_DW2_EP4_5_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_5_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_5_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_5_CPU_EGP_6 Register PTR_RTN_DW3_EP4_5_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_5_CPU_EGP_6 0x1612C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_5_CPU_EGP_6 0x190D612Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_5_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_5_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_5_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_5_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_5_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_6_CPU_EGP_6 Register PTR_RTN_DW2_EP4_6_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_6_CPU_EGP_6 0x16130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_6_CPU_EGP_6 0x190D6130u //! Register Reset Value #define PTR_RTN_DW2_EP4_6_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_6_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_6_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_6_CPU_EGP_6 Register PTR_RTN_DW3_EP4_6_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_6_CPU_EGP_6 0x16134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_6_CPU_EGP_6 0x190D6134u //! Register Reset Value #define PTR_RTN_DW3_EP4_6_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_6_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_6_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_6_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_6_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_7_CPU_EGP_6 Register PTR_RTN_DW2_EP4_7_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_7_CPU_EGP_6 0x16138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_7_CPU_EGP_6 0x190D6138u //! Register Reset Value #define PTR_RTN_DW2_EP4_7_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_7_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_7_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_7_CPU_EGP_6 Register PTR_RTN_DW3_EP4_7_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_7_CPU_EGP_6 0x1613C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_7_CPU_EGP_6 0x190D613Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_7_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_7_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_7_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_7_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_7_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_8_CPU_EGP_6 Register PTR_RTN_DW2_EP4_8_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_8_CPU_EGP_6 0x16140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_8_CPU_EGP_6 0x190D6140u //! Register Reset Value #define PTR_RTN_DW2_EP4_8_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_8_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_8_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_8_CPU_EGP_6 Register PTR_RTN_DW3_EP4_8_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_8_CPU_EGP_6 0x16144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_8_CPU_EGP_6 0x190D6144u //! Register Reset Value #define PTR_RTN_DW3_EP4_8_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_8_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_8_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_8_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_8_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_9_CPU_EGP_6 Register PTR_RTN_DW2_EP4_9_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_9_CPU_EGP_6 0x16148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_9_CPU_EGP_6 0x190D6148u //! Register Reset Value #define PTR_RTN_DW2_EP4_9_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_9_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_9_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_9_CPU_EGP_6 Register PTR_RTN_DW3_EP4_9_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_9_CPU_EGP_6 0x1614C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_9_CPU_EGP_6 0x190D614Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_9_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_9_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_9_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_9_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_9_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_10_CPU_EGP_6 Register PTR_RTN_DW2_EP4_10_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_10_CPU_EGP_6 0x16150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_10_CPU_EGP_6 0x190D6150u //! Register Reset Value #define PTR_RTN_DW2_EP4_10_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_10_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_10_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_10_CPU_EGP_6 Register PTR_RTN_DW3_EP4_10_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_10_CPU_EGP_6 0x16154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_10_CPU_EGP_6 0x190D6154u //! Register Reset Value #define PTR_RTN_DW3_EP4_10_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_10_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_10_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_10_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_10_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_11_CPU_EGP_6 Register PTR_RTN_DW2_EP4_11_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_11_CPU_EGP_6 0x16158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_11_CPU_EGP_6 0x190D6158u //! Register Reset Value #define PTR_RTN_DW2_EP4_11_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_11_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_11_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_11_CPU_EGP_6 Register PTR_RTN_DW3_EP4_11_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_11_CPU_EGP_6 0x1615C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_11_CPU_EGP_6 0x190D615Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_11_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_11_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_11_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_11_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_11_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_12_CPU_EGP_6 Register PTR_RTN_DW2_EP4_12_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_12_CPU_EGP_6 0x16160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_12_CPU_EGP_6 0x190D6160u //! Register Reset Value #define PTR_RTN_DW2_EP4_12_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_12_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_12_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_12_CPU_EGP_6 Register PTR_RTN_DW3_EP4_12_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_12_CPU_EGP_6 0x16164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_12_CPU_EGP_6 0x190D6164u //! Register Reset Value #define PTR_RTN_DW3_EP4_12_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_12_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_12_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_12_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_12_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_13_CPU_EGP_6 Register PTR_RTN_DW2_EP4_13_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_13_CPU_EGP_6 0x16168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_13_CPU_EGP_6 0x190D6168u //! Register Reset Value #define PTR_RTN_DW2_EP4_13_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_13_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_13_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_13_CPU_EGP_6 Register PTR_RTN_DW3_EP4_13_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_13_CPU_EGP_6 0x1616C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_13_CPU_EGP_6 0x190D616Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_13_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_13_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_13_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_13_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_13_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_14_CPU_EGP_6 Register PTR_RTN_DW2_EP4_14_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_14_CPU_EGP_6 0x16170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_14_CPU_EGP_6 0x190D6170u //! Register Reset Value #define PTR_RTN_DW2_EP4_14_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_14_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_14_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_14_CPU_EGP_6 Register PTR_RTN_DW3_EP4_14_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_14_CPU_EGP_6 0x16174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_14_CPU_EGP_6 0x190D6174u //! Register Reset Value #define PTR_RTN_DW3_EP4_14_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_14_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_14_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_14_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_14_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_15_CPU_EGP_6 Register PTR_RTN_DW2_EP4_15_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_15_CPU_EGP_6 0x16178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_15_CPU_EGP_6 0x190D6178u //! Register Reset Value #define PTR_RTN_DW2_EP4_15_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_15_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_15_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_15_CPU_EGP_6 Register PTR_RTN_DW3_EP4_15_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_15_CPU_EGP_6 0x1617C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_15_CPU_EGP_6 0x190D617Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_15_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_15_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_15_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_15_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_15_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_16_CPU_EGP_6 Register PTR_RTN_DW2_EP4_16_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_16_CPU_EGP_6 0x16180 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_16_CPU_EGP_6 0x190D6180u //! Register Reset Value #define PTR_RTN_DW2_EP4_16_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_16_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_16_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_16_CPU_EGP_6 Register PTR_RTN_DW3_EP4_16_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_16_CPU_EGP_6 0x16184 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_16_CPU_EGP_6 0x190D6184u //! Register Reset Value #define PTR_RTN_DW3_EP4_16_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_16_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_16_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_16_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_16_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_17_CPU_EGP_6 Register PTR_RTN_DW2_EP4_17_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_17_CPU_EGP_6 0x16188 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_17_CPU_EGP_6 0x190D6188u //! Register Reset Value #define PTR_RTN_DW2_EP4_17_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_17_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_17_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_17_CPU_EGP_6 Register PTR_RTN_DW3_EP4_17_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_17_CPU_EGP_6 0x1618C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_17_CPU_EGP_6 0x190D618Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_17_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_17_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_17_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_17_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_17_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_18_CPU_EGP_6 Register PTR_RTN_DW2_EP4_18_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_18_CPU_EGP_6 0x16190 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_18_CPU_EGP_6 0x190D6190u //! Register Reset Value #define PTR_RTN_DW2_EP4_18_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_18_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_18_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_18_CPU_EGP_6 Register PTR_RTN_DW3_EP4_18_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_18_CPU_EGP_6 0x16194 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_18_CPU_EGP_6 0x190D6194u //! Register Reset Value #define PTR_RTN_DW3_EP4_18_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_18_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_18_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_18_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_18_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_19_CPU_EGP_6 Register PTR_RTN_DW2_EP4_19_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_19_CPU_EGP_6 0x16198 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_19_CPU_EGP_6 0x190D6198u //! Register Reset Value #define PTR_RTN_DW2_EP4_19_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_19_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_19_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_19_CPU_EGP_6 Register PTR_RTN_DW3_EP4_19_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_19_CPU_EGP_6 0x1619C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_19_CPU_EGP_6 0x190D619Cu //! Register Reset Value #define PTR_RTN_DW3_EP4_19_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_19_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_19_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_19_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_19_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_20_CPU_EGP_6 Register PTR_RTN_DW2_EP4_20_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_20_CPU_EGP_6 0x161A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_20_CPU_EGP_6 0x190D61A0u //! Register Reset Value #define PTR_RTN_DW2_EP4_20_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_20_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_20_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_20_CPU_EGP_6 Register PTR_RTN_DW3_EP4_20_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_20_CPU_EGP_6 0x161A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_20_CPU_EGP_6 0x190D61A4u //! Register Reset Value #define PTR_RTN_DW3_EP4_20_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_20_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_20_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_20_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_20_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_21_CPU_EGP_6 Register PTR_RTN_DW2_EP4_21_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_21_CPU_EGP_6 0x161A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_21_CPU_EGP_6 0x190D61A8u //! Register Reset Value #define PTR_RTN_DW2_EP4_21_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_21_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_21_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_21_CPU_EGP_6 Register PTR_RTN_DW3_EP4_21_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_21_CPU_EGP_6 0x161AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_21_CPU_EGP_6 0x190D61ACu //! Register Reset Value #define PTR_RTN_DW3_EP4_21_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_21_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_21_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_21_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_21_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_22_CPU_EGP_6 Register PTR_RTN_DW2_EP4_22_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_22_CPU_EGP_6 0x161B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_22_CPU_EGP_6 0x190D61B0u //! Register Reset Value #define PTR_RTN_DW2_EP4_22_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_22_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_22_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_22_CPU_EGP_6 Register PTR_RTN_DW3_EP4_22_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_22_CPU_EGP_6 0x161B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_22_CPU_EGP_6 0x190D61B4u //! Register Reset Value #define PTR_RTN_DW3_EP4_22_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_22_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_22_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_22_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_22_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_23_CPU_EGP_6 Register PTR_RTN_DW2_EP4_23_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_23_CPU_EGP_6 0x161B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_23_CPU_EGP_6 0x190D61B8u //! Register Reset Value #define PTR_RTN_DW2_EP4_23_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_23_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_23_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_23_CPU_EGP_6 Register PTR_RTN_DW3_EP4_23_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_23_CPU_EGP_6 0x161BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_23_CPU_EGP_6 0x190D61BCu //! Register Reset Value #define PTR_RTN_DW3_EP4_23_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_23_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_23_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_23_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_23_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_24_CPU_EGP_6 Register PTR_RTN_DW2_EP4_24_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_24_CPU_EGP_6 0x161C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_24_CPU_EGP_6 0x190D61C0u //! Register Reset Value #define PTR_RTN_DW2_EP4_24_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_24_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_24_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_24_CPU_EGP_6 Register PTR_RTN_DW3_EP4_24_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_24_CPU_EGP_6 0x161C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_24_CPU_EGP_6 0x190D61C4u //! Register Reset Value #define PTR_RTN_DW3_EP4_24_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_24_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_24_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_24_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_24_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_25_CPU_EGP_6 Register PTR_RTN_DW2_EP4_25_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_25_CPU_EGP_6 0x161C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_25_CPU_EGP_6 0x190D61C8u //! Register Reset Value #define PTR_RTN_DW2_EP4_25_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_25_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_25_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_25_CPU_EGP_6 Register PTR_RTN_DW3_EP4_25_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_25_CPU_EGP_6 0x161CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_25_CPU_EGP_6 0x190D61CCu //! Register Reset Value #define PTR_RTN_DW3_EP4_25_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_25_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_25_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_25_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_25_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_26_CPU_EGP_6 Register PTR_RTN_DW2_EP4_26_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_26_CPU_EGP_6 0x161D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_26_CPU_EGP_6 0x190D61D0u //! Register Reset Value #define PTR_RTN_DW2_EP4_26_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_26_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_26_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_26_CPU_EGP_6 Register PTR_RTN_DW3_EP4_26_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_26_CPU_EGP_6 0x161D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_26_CPU_EGP_6 0x190D61D4u //! Register Reset Value #define PTR_RTN_DW3_EP4_26_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_26_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_26_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_26_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_26_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_27_CPU_EGP_6 Register PTR_RTN_DW2_EP4_27_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_27_CPU_EGP_6 0x161D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_27_CPU_EGP_6 0x190D61D8u //! Register Reset Value #define PTR_RTN_DW2_EP4_27_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_27_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_27_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_27_CPU_EGP_6 Register PTR_RTN_DW3_EP4_27_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_27_CPU_EGP_6 0x161DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_27_CPU_EGP_6 0x190D61DCu //! Register Reset Value #define PTR_RTN_DW3_EP4_27_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_27_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_27_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_27_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_27_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_28_CPU_EGP_6 Register PTR_RTN_DW2_EP4_28_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_28_CPU_EGP_6 0x161E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_28_CPU_EGP_6 0x190D61E0u //! Register Reset Value #define PTR_RTN_DW2_EP4_28_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_28_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_28_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_28_CPU_EGP_6 Register PTR_RTN_DW3_EP4_28_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_28_CPU_EGP_6 0x161E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_28_CPU_EGP_6 0x190D61E4u //! Register Reset Value #define PTR_RTN_DW3_EP4_28_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_28_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_28_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_28_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_28_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_29_CPU_EGP_6 Register PTR_RTN_DW2_EP4_29_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_29_CPU_EGP_6 0x161E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_29_CPU_EGP_6 0x190D61E8u //! Register Reset Value #define PTR_RTN_DW2_EP4_29_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_29_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_29_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_29_CPU_EGP_6 Register PTR_RTN_DW3_EP4_29_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_29_CPU_EGP_6 0x161EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_29_CPU_EGP_6 0x190D61ECu //! Register Reset Value #define PTR_RTN_DW3_EP4_29_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_29_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_29_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_29_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_29_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_30_CPU_EGP_6 Register PTR_RTN_DW2_EP4_30_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_30_CPU_EGP_6 0x161F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_30_CPU_EGP_6 0x190D61F0u //! Register Reset Value #define PTR_RTN_DW2_EP4_30_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_30_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_30_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_30_CPU_EGP_6 Register PTR_RTN_DW3_EP4_30_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_30_CPU_EGP_6 0x161F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_30_CPU_EGP_6 0x190D61F4u //! Register Reset Value #define PTR_RTN_DW3_EP4_30_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_30_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_30_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_30_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_30_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup PTR_RTN_DW2_EP4_31_CPU_EGP_6 Register PTR_RTN_DW2_EP4_31_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_DW2_EP4_31_CPU_EGP_6 0x161F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW2_EP4_31_CPU_EGP_6 0x190D61F8u //! Register Reset Value #define PTR_RTN_DW2_EP4_31_CPU_EGP_6_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_31_CPU_EGP_6_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_DW2_EP4_31_CPU_EGP_6_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_DW3_EP4_31_CPU_EGP_6 Register PTR_RTN_DW3_EP4_31_CPU_EGP_6 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_DW3_EP4_31_CPU_EGP_6 0x161FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_DW3_EP4_31_CPU_EGP_6 0x190D61FCu //! Register Reset Value #define PTR_RTN_DW3_EP4_31_CPU_EGP_6_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_31_CPU_EGP_6_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_31_CPU_EGP_6_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_31_CPU_EGP_6_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_DW3_EP4_31_CPU_EGP_6_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_EP6_0_CPU_EGP_6 Register DESC0_EP6_0_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_0_CPU_EGP_6 0x16200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_0_CPU_EGP_6 0x190D6200u //! Register Reset Value #define DESC0_EP6_0_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_0_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_0_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_0_CPU_EGP_6 Register DESC1_EP6_0_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_0_CPU_EGP_6 0x16204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_0_CPU_EGP_6 0x190D6204u //! Register Reset Value #define DESC1_EP6_0_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_0_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_0_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_0_CPU_EGP_6 Register DESC2_EP6_0_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_0_CPU_EGP_6 0x16208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_0_CPU_EGP_6 0x190D6208u //! Register Reset Value #define DESC2_EP6_0_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_0_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_0_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_0_CPU_EGP_6 Register DESC3_EP6_0_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_0_CPU_EGP_6 0x1620C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_0_CPU_EGP_6 0x190D620Cu //! Register Reset Value #define DESC3_EP6_0_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_0_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_0_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_1_CPU_EGP_6 Register DESC0_EP6_1_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_1_CPU_EGP_6 0x16210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_1_CPU_EGP_6 0x190D6210u //! Register Reset Value #define DESC0_EP6_1_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_1_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_1_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_1_CPU_EGP_6 Register DESC1_EP6_1_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_1_CPU_EGP_6 0x16214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_1_CPU_EGP_6 0x190D6214u //! Register Reset Value #define DESC1_EP6_1_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_1_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_1_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_1_CPU_EGP_6 Register DESC2_EP6_1_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_1_CPU_EGP_6 0x16218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_1_CPU_EGP_6 0x190D6218u //! Register Reset Value #define DESC2_EP6_1_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_1_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_1_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_1_CPU_EGP_6 Register DESC3_EP6_1_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_1_CPU_EGP_6 0x1621C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_1_CPU_EGP_6 0x190D621Cu //! Register Reset Value #define DESC3_EP6_1_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_1_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_1_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_2_CPU_EGP_6 Register DESC0_EP6_2_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_2_CPU_EGP_6 0x16220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_2_CPU_EGP_6 0x190D6220u //! Register Reset Value #define DESC0_EP6_2_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_2_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_2_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_2_CPU_EGP_6 Register DESC1_EP6_2_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_2_CPU_EGP_6 0x16224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_2_CPU_EGP_6 0x190D6224u //! Register Reset Value #define DESC1_EP6_2_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_2_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_2_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_2_CPU_EGP_6 Register DESC2_EP6_2_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_2_CPU_EGP_6 0x16228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_2_CPU_EGP_6 0x190D6228u //! Register Reset Value #define DESC2_EP6_2_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_2_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_2_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_2_CPU_EGP_6 Register DESC3_EP6_2_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_2_CPU_EGP_6 0x1622C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_2_CPU_EGP_6 0x190D622Cu //! Register Reset Value #define DESC3_EP6_2_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_2_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_2_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_3_CPU_EGP_6 Register DESC0_EP6_3_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_3_CPU_EGP_6 0x16230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_3_CPU_EGP_6 0x190D6230u //! Register Reset Value #define DESC0_EP6_3_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_3_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_3_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_3_CPU_EGP_6 Register DESC1_EP6_3_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_3_CPU_EGP_6 0x16234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_3_CPU_EGP_6 0x190D6234u //! Register Reset Value #define DESC1_EP6_3_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_3_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_3_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_3_CPU_EGP_6 Register DESC2_EP6_3_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_3_CPU_EGP_6 0x16238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_3_CPU_EGP_6 0x190D6238u //! Register Reset Value #define DESC2_EP6_3_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_3_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_3_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_3_CPU_EGP_6 Register DESC3_EP6_3_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_3_CPU_EGP_6 0x1623C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_3_CPU_EGP_6 0x190D623Cu //! Register Reset Value #define DESC3_EP6_3_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_3_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_3_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_4_CPU_EGP_6 Register DESC0_EP6_4_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_4_CPU_EGP_6 0x16240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_4_CPU_EGP_6 0x190D6240u //! Register Reset Value #define DESC0_EP6_4_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_4_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_4_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_4_CPU_EGP_6 Register DESC1_EP6_4_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_4_CPU_EGP_6 0x16244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_4_CPU_EGP_6 0x190D6244u //! Register Reset Value #define DESC1_EP6_4_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_4_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_4_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_4_CPU_EGP_6 Register DESC2_EP6_4_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_4_CPU_EGP_6 0x16248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_4_CPU_EGP_6 0x190D6248u //! Register Reset Value #define DESC2_EP6_4_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_4_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_4_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_4_CPU_EGP_6 Register DESC3_EP6_4_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_4_CPU_EGP_6 0x1624C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_4_CPU_EGP_6 0x190D624Cu //! Register Reset Value #define DESC3_EP6_4_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_4_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_4_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_5_CPU_EGP_6 Register DESC0_EP6_5_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_5_CPU_EGP_6 0x16250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_5_CPU_EGP_6 0x190D6250u //! Register Reset Value #define DESC0_EP6_5_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_5_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_5_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_5_CPU_EGP_6 Register DESC1_EP6_5_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_5_CPU_EGP_6 0x16254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_5_CPU_EGP_6 0x190D6254u //! Register Reset Value #define DESC1_EP6_5_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_5_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_5_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_5_CPU_EGP_6 Register DESC2_EP6_5_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_5_CPU_EGP_6 0x16258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_5_CPU_EGP_6 0x190D6258u //! Register Reset Value #define DESC2_EP6_5_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_5_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_5_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_5_CPU_EGP_6 Register DESC3_EP6_5_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_5_CPU_EGP_6 0x1625C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_5_CPU_EGP_6 0x190D625Cu //! Register Reset Value #define DESC3_EP6_5_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_5_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_5_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_6_CPU_EGP_6 Register DESC0_EP6_6_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_6_CPU_EGP_6 0x16260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_6_CPU_EGP_6 0x190D6260u //! Register Reset Value #define DESC0_EP6_6_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_6_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_6_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_6_CPU_EGP_6 Register DESC1_EP6_6_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_6_CPU_EGP_6 0x16264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_6_CPU_EGP_6 0x190D6264u //! Register Reset Value #define DESC1_EP6_6_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_6_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_6_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_6_CPU_EGP_6 Register DESC2_EP6_6_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_6_CPU_EGP_6 0x16268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_6_CPU_EGP_6 0x190D6268u //! Register Reset Value #define DESC2_EP6_6_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_6_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_6_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_6_CPU_EGP_6 Register DESC3_EP6_6_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_6_CPU_EGP_6 0x1626C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_6_CPU_EGP_6 0x190D626Cu //! Register Reset Value #define DESC3_EP6_6_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_6_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_6_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_7_CPU_EGP_6 Register DESC0_EP6_7_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_7_CPU_EGP_6 0x16270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_7_CPU_EGP_6 0x190D6270u //! Register Reset Value #define DESC0_EP6_7_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_7_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_7_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_7_CPU_EGP_6 Register DESC1_EP6_7_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_7_CPU_EGP_6 0x16274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_7_CPU_EGP_6 0x190D6274u //! Register Reset Value #define DESC1_EP6_7_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_7_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_7_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_7_CPU_EGP_6 Register DESC2_EP6_7_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_7_CPU_EGP_6 0x16278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_7_CPU_EGP_6 0x190D6278u //! Register Reset Value #define DESC2_EP6_7_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_7_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_7_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_7_CPU_EGP_6 Register DESC3_EP6_7_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_7_CPU_EGP_6 0x1627C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_7_CPU_EGP_6 0x190D627Cu //! Register Reset Value #define DESC3_EP6_7_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_7_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_7_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_8_CPU_EGP_6 Register DESC0_EP6_8_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_8_CPU_EGP_6 0x16280 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_8_CPU_EGP_6 0x190D6280u //! Register Reset Value #define DESC0_EP6_8_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_8_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_8_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_8_CPU_EGP_6 Register DESC1_EP6_8_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_8_CPU_EGP_6 0x16284 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_8_CPU_EGP_6 0x190D6284u //! Register Reset Value #define DESC1_EP6_8_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_8_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_8_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_8_CPU_EGP_6 Register DESC2_EP6_8_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_8_CPU_EGP_6 0x16288 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_8_CPU_EGP_6 0x190D6288u //! Register Reset Value #define DESC2_EP6_8_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_8_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_8_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_8_CPU_EGP_6 Register DESC3_EP6_8_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_8_CPU_EGP_6 0x1628C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_8_CPU_EGP_6 0x190D628Cu //! Register Reset Value #define DESC3_EP6_8_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_8_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_8_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_9_CPU_EGP_6 Register DESC0_EP6_9_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_9_CPU_EGP_6 0x16290 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_9_CPU_EGP_6 0x190D6290u //! Register Reset Value #define DESC0_EP6_9_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_9_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_9_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_9_CPU_EGP_6 Register DESC1_EP6_9_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_9_CPU_EGP_6 0x16294 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_9_CPU_EGP_6 0x190D6294u //! Register Reset Value #define DESC1_EP6_9_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_9_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_9_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_9_CPU_EGP_6 Register DESC2_EP6_9_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_9_CPU_EGP_6 0x16298 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_9_CPU_EGP_6 0x190D6298u //! Register Reset Value #define DESC2_EP6_9_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_9_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_9_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_9_CPU_EGP_6 Register DESC3_EP6_9_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_9_CPU_EGP_6 0x1629C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_9_CPU_EGP_6 0x190D629Cu //! Register Reset Value #define DESC3_EP6_9_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_9_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_9_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_10_CPU_EGP_6 Register DESC0_EP6_10_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_10_CPU_EGP_6 0x162A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_10_CPU_EGP_6 0x190D62A0u //! Register Reset Value #define DESC0_EP6_10_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_10_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_10_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_10_CPU_EGP_6 Register DESC1_EP6_10_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_10_CPU_EGP_6 0x162A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_10_CPU_EGP_6 0x190D62A4u //! Register Reset Value #define DESC1_EP6_10_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_10_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_10_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_10_CPU_EGP_6 Register DESC2_EP6_10_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_10_CPU_EGP_6 0x162A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_10_CPU_EGP_6 0x190D62A8u //! Register Reset Value #define DESC2_EP6_10_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_10_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_10_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_10_CPU_EGP_6 Register DESC3_EP6_10_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_10_CPU_EGP_6 0x162AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_10_CPU_EGP_6 0x190D62ACu //! Register Reset Value #define DESC3_EP6_10_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_10_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_10_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_11_CPU_EGP_6 Register DESC0_EP6_11_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_11_CPU_EGP_6 0x162B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_11_CPU_EGP_6 0x190D62B0u //! Register Reset Value #define DESC0_EP6_11_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_11_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_11_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_11_CPU_EGP_6 Register DESC1_EP6_11_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_11_CPU_EGP_6 0x162B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_11_CPU_EGP_6 0x190D62B4u //! Register Reset Value #define DESC1_EP6_11_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_11_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_11_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_11_CPU_EGP_6 Register DESC2_EP6_11_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_11_CPU_EGP_6 0x162B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_11_CPU_EGP_6 0x190D62B8u //! Register Reset Value #define DESC2_EP6_11_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_11_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_11_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_11_CPU_EGP_6 Register DESC3_EP6_11_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_11_CPU_EGP_6 0x162BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_11_CPU_EGP_6 0x190D62BCu //! Register Reset Value #define DESC3_EP6_11_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_11_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_11_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_12_CPU_EGP_6 Register DESC0_EP6_12_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_12_CPU_EGP_6 0x162C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_12_CPU_EGP_6 0x190D62C0u //! Register Reset Value #define DESC0_EP6_12_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_12_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_12_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_12_CPU_EGP_6 Register DESC1_EP6_12_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_12_CPU_EGP_6 0x162C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_12_CPU_EGP_6 0x190D62C4u //! Register Reset Value #define DESC1_EP6_12_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_12_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_12_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_12_CPU_EGP_6 Register DESC2_EP6_12_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_12_CPU_EGP_6 0x162C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_12_CPU_EGP_6 0x190D62C8u //! Register Reset Value #define DESC2_EP6_12_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_12_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_12_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_12_CPU_EGP_6 Register DESC3_EP6_12_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_12_CPU_EGP_6 0x162CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_12_CPU_EGP_6 0x190D62CCu //! Register Reset Value #define DESC3_EP6_12_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_12_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_12_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_13_CPU_EGP_6 Register DESC0_EP6_13_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_13_CPU_EGP_6 0x162D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_13_CPU_EGP_6 0x190D62D0u //! Register Reset Value #define DESC0_EP6_13_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_13_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_13_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_13_CPU_EGP_6 Register DESC1_EP6_13_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_13_CPU_EGP_6 0x162D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_13_CPU_EGP_6 0x190D62D4u //! Register Reset Value #define DESC1_EP6_13_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_13_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_13_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_13_CPU_EGP_6 Register DESC2_EP6_13_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_13_CPU_EGP_6 0x162D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_13_CPU_EGP_6 0x190D62D8u //! Register Reset Value #define DESC2_EP6_13_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_13_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_13_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_13_CPU_EGP_6 Register DESC3_EP6_13_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_13_CPU_EGP_6 0x162DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_13_CPU_EGP_6 0x190D62DCu //! Register Reset Value #define DESC3_EP6_13_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_13_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_13_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_14_CPU_EGP_6 Register DESC0_EP6_14_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_14_CPU_EGP_6 0x162E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_14_CPU_EGP_6 0x190D62E0u //! Register Reset Value #define DESC0_EP6_14_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_14_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_14_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_14_CPU_EGP_6 Register DESC1_EP6_14_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_14_CPU_EGP_6 0x162E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_14_CPU_EGP_6 0x190D62E4u //! Register Reset Value #define DESC1_EP6_14_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_14_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_14_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_14_CPU_EGP_6 Register DESC2_EP6_14_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_14_CPU_EGP_6 0x162E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_14_CPU_EGP_6 0x190D62E8u //! Register Reset Value #define DESC2_EP6_14_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_14_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_14_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_14_CPU_EGP_6 Register DESC3_EP6_14_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_14_CPU_EGP_6 0x162EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_14_CPU_EGP_6 0x190D62ECu //! Register Reset Value #define DESC3_EP6_14_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_14_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_14_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_15_CPU_EGP_6 Register DESC0_EP6_15_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_15_CPU_EGP_6 0x162F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_15_CPU_EGP_6 0x190D62F0u //! Register Reset Value #define DESC0_EP6_15_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_15_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_15_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_15_CPU_EGP_6 Register DESC1_EP6_15_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_15_CPU_EGP_6 0x162F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_15_CPU_EGP_6 0x190D62F4u //! Register Reset Value #define DESC1_EP6_15_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_15_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_15_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_15_CPU_EGP_6 Register DESC2_EP6_15_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_15_CPU_EGP_6 0x162F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_15_CPU_EGP_6 0x190D62F8u //! Register Reset Value #define DESC2_EP6_15_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_15_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_15_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_15_CPU_EGP_6 Register DESC3_EP6_15_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_15_CPU_EGP_6 0x162FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_15_CPU_EGP_6 0x190D62FCu //! Register Reset Value #define DESC3_EP6_15_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_15_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_15_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_16_CPU_EGP_6 Register DESC0_EP6_16_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_16_CPU_EGP_6 0x16300 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_16_CPU_EGP_6 0x190D6300u //! Register Reset Value #define DESC0_EP6_16_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_16_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_16_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_16_CPU_EGP_6 Register DESC1_EP6_16_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_16_CPU_EGP_6 0x16304 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_16_CPU_EGP_6 0x190D6304u //! Register Reset Value #define DESC1_EP6_16_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_16_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_16_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_16_CPU_EGP_6 Register DESC2_EP6_16_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_16_CPU_EGP_6 0x16308 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_16_CPU_EGP_6 0x190D6308u //! Register Reset Value #define DESC2_EP6_16_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_16_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_16_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_16_CPU_EGP_6 Register DESC3_EP6_16_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_16_CPU_EGP_6 0x1630C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_16_CPU_EGP_6 0x190D630Cu //! Register Reset Value #define DESC3_EP6_16_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_16_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_16_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_17_CPU_EGP_6 Register DESC0_EP6_17_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_17_CPU_EGP_6 0x16310 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_17_CPU_EGP_6 0x190D6310u //! Register Reset Value #define DESC0_EP6_17_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_17_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_17_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_17_CPU_EGP_6 Register DESC1_EP6_17_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_17_CPU_EGP_6 0x16314 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_17_CPU_EGP_6 0x190D6314u //! Register Reset Value #define DESC1_EP6_17_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_17_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_17_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_17_CPU_EGP_6 Register DESC2_EP6_17_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_17_CPU_EGP_6 0x16318 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_17_CPU_EGP_6 0x190D6318u //! Register Reset Value #define DESC2_EP6_17_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_17_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_17_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_17_CPU_EGP_6 Register DESC3_EP6_17_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_17_CPU_EGP_6 0x1631C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_17_CPU_EGP_6 0x190D631Cu //! Register Reset Value #define DESC3_EP6_17_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_17_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_17_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_18_CPU_EGP_6 Register DESC0_EP6_18_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_18_CPU_EGP_6 0x16320 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_18_CPU_EGP_6 0x190D6320u //! Register Reset Value #define DESC0_EP6_18_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_18_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_18_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_18_CPU_EGP_6 Register DESC1_EP6_18_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_18_CPU_EGP_6 0x16324 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_18_CPU_EGP_6 0x190D6324u //! Register Reset Value #define DESC1_EP6_18_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_18_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_18_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_18_CPU_EGP_6 Register DESC2_EP6_18_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_18_CPU_EGP_6 0x16328 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_18_CPU_EGP_6 0x190D6328u //! Register Reset Value #define DESC2_EP6_18_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_18_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_18_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_18_CPU_EGP_6 Register DESC3_EP6_18_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_18_CPU_EGP_6 0x1632C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_18_CPU_EGP_6 0x190D632Cu //! Register Reset Value #define DESC3_EP6_18_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_18_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_18_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_19_CPU_EGP_6 Register DESC0_EP6_19_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_19_CPU_EGP_6 0x16330 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_19_CPU_EGP_6 0x190D6330u //! Register Reset Value #define DESC0_EP6_19_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_19_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_19_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_19_CPU_EGP_6 Register DESC1_EP6_19_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_19_CPU_EGP_6 0x16334 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_19_CPU_EGP_6 0x190D6334u //! Register Reset Value #define DESC1_EP6_19_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_19_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_19_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_19_CPU_EGP_6 Register DESC2_EP6_19_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_19_CPU_EGP_6 0x16338 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_19_CPU_EGP_6 0x190D6338u //! Register Reset Value #define DESC2_EP6_19_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_19_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_19_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_19_CPU_EGP_6 Register DESC3_EP6_19_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_19_CPU_EGP_6 0x1633C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_19_CPU_EGP_6 0x190D633Cu //! Register Reset Value #define DESC3_EP6_19_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_19_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_19_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_20_CPU_EGP_6 Register DESC0_EP6_20_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_20_CPU_EGP_6 0x16340 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_20_CPU_EGP_6 0x190D6340u //! Register Reset Value #define DESC0_EP6_20_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_20_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_20_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_20_CPU_EGP_6 Register DESC1_EP6_20_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_20_CPU_EGP_6 0x16344 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_20_CPU_EGP_6 0x190D6344u //! Register Reset Value #define DESC1_EP6_20_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_20_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_20_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_20_CPU_EGP_6 Register DESC2_EP6_20_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_20_CPU_EGP_6 0x16348 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_20_CPU_EGP_6 0x190D6348u //! Register Reset Value #define DESC2_EP6_20_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_20_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_20_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_20_CPU_EGP_6 Register DESC3_EP6_20_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_20_CPU_EGP_6 0x1634C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_20_CPU_EGP_6 0x190D634Cu //! Register Reset Value #define DESC3_EP6_20_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_20_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_20_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_21_CPU_EGP_6 Register DESC0_EP6_21_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_21_CPU_EGP_6 0x16350 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_21_CPU_EGP_6 0x190D6350u //! Register Reset Value #define DESC0_EP6_21_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_21_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_21_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_21_CPU_EGP_6 Register DESC1_EP6_21_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_21_CPU_EGP_6 0x16354 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_21_CPU_EGP_6 0x190D6354u //! Register Reset Value #define DESC1_EP6_21_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_21_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_21_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_21_CPU_EGP_6 Register DESC2_EP6_21_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_21_CPU_EGP_6 0x16358 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_21_CPU_EGP_6 0x190D6358u //! Register Reset Value #define DESC2_EP6_21_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_21_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_21_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_21_CPU_EGP_6 Register DESC3_EP6_21_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_21_CPU_EGP_6 0x1635C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_21_CPU_EGP_6 0x190D635Cu //! Register Reset Value #define DESC3_EP6_21_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_21_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_21_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_22_CPU_EGP_6 Register DESC0_EP6_22_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_22_CPU_EGP_6 0x16360 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_22_CPU_EGP_6 0x190D6360u //! Register Reset Value #define DESC0_EP6_22_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_22_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_22_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_22_CPU_EGP_6 Register DESC1_EP6_22_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_22_CPU_EGP_6 0x16364 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_22_CPU_EGP_6 0x190D6364u //! Register Reset Value #define DESC1_EP6_22_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_22_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_22_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_22_CPU_EGP_6 Register DESC2_EP6_22_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_22_CPU_EGP_6 0x16368 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_22_CPU_EGP_6 0x190D6368u //! Register Reset Value #define DESC2_EP6_22_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_22_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_22_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_22_CPU_EGP_6 Register DESC3_EP6_22_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_22_CPU_EGP_6 0x1636C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_22_CPU_EGP_6 0x190D636Cu //! Register Reset Value #define DESC3_EP6_22_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_22_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_22_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_23_CPU_EGP_6 Register DESC0_EP6_23_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_23_CPU_EGP_6 0x16370 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_23_CPU_EGP_6 0x190D6370u //! Register Reset Value #define DESC0_EP6_23_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_23_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_23_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_23_CPU_EGP_6 Register DESC1_EP6_23_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_23_CPU_EGP_6 0x16374 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_23_CPU_EGP_6 0x190D6374u //! Register Reset Value #define DESC1_EP6_23_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_23_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_23_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_23_CPU_EGP_6 Register DESC2_EP6_23_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_23_CPU_EGP_6 0x16378 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_23_CPU_EGP_6 0x190D6378u //! Register Reset Value #define DESC2_EP6_23_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_23_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_23_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_23_CPU_EGP_6 Register DESC3_EP6_23_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_23_CPU_EGP_6 0x1637C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_23_CPU_EGP_6 0x190D637Cu //! Register Reset Value #define DESC3_EP6_23_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_23_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_23_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_24_CPU_EGP_6 Register DESC0_EP6_24_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_24_CPU_EGP_6 0x16380 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_24_CPU_EGP_6 0x190D6380u //! Register Reset Value #define DESC0_EP6_24_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_24_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_24_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_24_CPU_EGP_6 Register DESC1_EP6_24_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_24_CPU_EGP_6 0x16384 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_24_CPU_EGP_6 0x190D6384u //! Register Reset Value #define DESC1_EP6_24_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_24_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_24_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_24_CPU_EGP_6 Register DESC2_EP6_24_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_24_CPU_EGP_6 0x16388 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_24_CPU_EGP_6 0x190D6388u //! Register Reset Value #define DESC2_EP6_24_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_24_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_24_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_24_CPU_EGP_6 Register DESC3_EP6_24_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_24_CPU_EGP_6 0x1638C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_24_CPU_EGP_6 0x190D638Cu //! Register Reset Value #define DESC3_EP6_24_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_24_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_24_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_25_CPU_EGP_6 Register DESC0_EP6_25_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_25_CPU_EGP_6 0x16390 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_25_CPU_EGP_6 0x190D6390u //! Register Reset Value #define DESC0_EP6_25_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_25_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_25_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_25_CPU_EGP_6 Register DESC1_EP6_25_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_25_CPU_EGP_6 0x16394 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_25_CPU_EGP_6 0x190D6394u //! Register Reset Value #define DESC1_EP6_25_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_25_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_25_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_25_CPU_EGP_6 Register DESC2_EP6_25_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_25_CPU_EGP_6 0x16398 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_25_CPU_EGP_6 0x190D6398u //! Register Reset Value #define DESC2_EP6_25_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_25_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_25_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_25_CPU_EGP_6 Register DESC3_EP6_25_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_25_CPU_EGP_6 0x1639C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_25_CPU_EGP_6 0x190D639Cu //! Register Reset Value #define DESC3_EP6_25_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_25_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_25_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_26_CPU_EGP_6 Register DESC0_EP6_26_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_26_CPU_EGP_6 0x163A0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_26_CPU_EGP_6 0x190D63A0u //! Register Reset Value #define DESC0_EP6_26_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_26_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_26_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_26_CPU_EGP_6 Register DESC1_EP6_26_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_26_CPU_EGP_6 0x163A4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_26_CPU_EGP_6 0x190D63A4u //! Register Reset Value #define DESC1_EP6_26_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_26_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_26_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_26_CPU_EGP_6 Register DESC2_EP6_26_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_26_CPU_EGP_6 0x163A8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_26_CPU_EGP_6 0x190D63A8u //! Register Reset Value #define DESC2_EP6_26_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_26_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_26_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_26_CPU_EGP_6 Register DESC3_EP6_26_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_26_CPU_EGP_6 0x163AC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_26_CPU_EGP_6 0x190D63ACu //! Register Reset Value #define DESC3_EP6_26_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_26_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_26_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_27_CPU_EGP_6 Register DESC0_EP6_27_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_27_CPU_EGP_6 0x163B0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_27_CPU_EGP_6 0x190D63B0u //! Register Reset Value #define DESC0_EP6_27_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_27_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_27_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_27_CPU_EGP_6 Register DESC1_EP6_27_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_27_CPU_EGP_6 0x163B4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_27_CPU_EGP_6 0x190D63B4u //! Register Reset Value #define DESC1_EP6_27_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_27_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_27_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_27_CPU_EGP_6 Register DESC2_EP6_27_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_27_CPU_EGP_6 0x163B8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_27_CPU_EGP_6 0x190D63B8u //! Register Reset Value #define DESC2_EP6_27_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_27_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_27_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_27_CPU_EGP_6 Register DESC3_EP6_27_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_27_CPU_EGP_6 0x163BC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_27_CPU_EGP_6 0x190D63BCu //! Register Reset Value #define DESC3_EP6_27_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_27_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_27_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_28_CPU_EGP_6 Register DESC0_EP6_28_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_28_CPU_EGP_6 0x163C0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_28_CPU_EGP_6 0x190D63C0u //! Register Reset Value #define DESC0_EP6_28_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_28_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_28_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_28_CPU_EGP_6 Register DESC1_EP6_28_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_28_CPU_EGP_6 0x163C4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_28_CPU_EGP_6 0x190D63C4u //! Register Reset Value #define DESC1_EP6_28_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_28_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_28_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_28_CPU_EGP_6 Register DESC2_EP6_28_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_28_CPU_EGP_6 0x163C8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_28_CPU_EGP_6 0x190D63C8u //! Register Reset Value #define DESC2_EP6_28_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_28_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_28_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_28_CPU_EGP_6 Register DESC3_EP6_28_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_28_CPU_EGP_6 0x163CC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_28_CPU_EGP_6 0x190D63CCu //! Register Reset Value #define DESC3_EP6_28_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_28_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_28_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_29_CPU_EGP_6 Register DESC0_EP6_29_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_29_CPU_EGP_6 0x163D0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_29_CPU_EGP_6 0x190D63D0u //! Register Reset Value #define DESC0_EP6_29_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_29_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_29_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_29_CPU_EGP_6 Register DESC1_EP6_29_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_29_CPU_EGP_6 0x163D4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_29_CPU_EGP_6 0x190D63D4u //! Register Reset Value #define DESC1_EP6_29_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_29_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_29_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_29_CPU_EGP_6 Register DESC2_EP6_29_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_29_CPU_EGP_6 0x163D8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_29_CPU_EGP_6 0x190D63D8u //! Register Reset Value #define DESC2_EP6_29_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_29_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_29_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_29_CPU_EGP_6 Register DESC3_EP6_29_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_29_CPU_EGP_6 0x163DC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_29_CPU_EGP_6 0x190D63DCu //! Register Reset Value #define DESC3_EP6_29_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_29_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_29_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_30_CPU_EGP_6 Register DESC0_EP6_30_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_30_CPU_EGP_6 0x163E0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_30_CPU_EGP_6 0x190D63E0u //! Register Reset Value #define DESC0_EP6_30_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_30_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_30_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_30_CPU_EGP_6 Register DESC1_EP6_30_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_30_CPU_EGP_6 0x163E4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_30_CPU_EGP_6 0x190D63E4u //! Register Reset Value #define DESC1_EP6_30_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_30_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_30_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_30_CPU_EGP_6 Register DESC2_EP6_30_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_30_CPU_EGP_6 0x163E8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_30_CPU_EGP_6 0x190D63E8u //! Register Reset Value #define DESC2_EP6_30_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_30_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_30_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_30_CPU_EGP_6 Register DESC3_EP6_30_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_30_CPU_EGP_6 0x163EC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_30_CPU_EGP_6 0x190D63ECu //! Register Reset Value #define DESC3_EP6_30_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_30_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_30_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC0_EP6_31_CPU_EGP_6 Register DESC0_EP6_31_CPU_EGP_6 - Special CPU Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_EP6_31_CPU_EGP_6 0x163F0 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_EP6_31_CPU_EGP_6 0x190D63F0u //! Register Reset Value #define DESC0_EP6_31_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_31_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_EP6_31_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_EP6_31_CPU_EGP_6 Register DESC1_EP6_31_CPU_EGP_6 - Special CPU Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_EP6_31_CPU_EGP_6 0x163F4 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_EP6_31_CPU_EGP_6 0x190D63F4u //! Register Reset Value #define DESC1_EP6_31_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_31_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_EP6_31_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_EP6_31_CPU_EGP_6 Register DESC2_EP6_31_CPU_EGP_6 - Special CPU Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_EP6_31_CPU_EGP_6 0x163F8 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_EP6_31_CPU_EGP_6 0x190D63F8u //! Register Reset Value #define DESC2_EP6_31_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_31_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_EP6_31_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_EP6_31_CPU_EGP_6 Register DESC3_EP6_31_CPU_EGP_6 - Special CPU Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_EP6_31_CPU_EGP_6 0x163FC //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_EP6_31_CPU_EGP_6 0x190D63FCu //! Register Reset Value #define DESC3_EP6_31_CPU_EGP_6_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_31_CPU_EGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_EP6_31_CPU_EGP_6_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup CFG_DMA_EGP_7 Register CFG_DMA_EGP_7 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_7 0x17000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_7 0x190D7000u //! Register Reset Value #define CFG_DMA_EGP_7_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_7_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_7_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_7_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_7_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_7_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_7_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_7_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_7_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_7_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_7_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_7 Register DQPC_DMA_EGP_7 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_7 0x17004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_7 0x190D7004u //! Register Reset Value #define DQPC_DMA_EGP_7_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_7_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_7_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_7 Register IRNCR_DMA_EGP_7 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_7 0x17020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_7 0x190D7020u //! Register Reset Value #define IRNCR_DMA_EGP_7_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_7_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_7_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_7_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_7_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_7 Register IRNICR_DMA_EGP_7 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_7 0x17024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_7 0x190D7024u //! Register Reset Value #define IRNICR_DMA_EGP_7_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_7_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_7_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_7 Register IRNEN_DMA_EGP_7 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_7 0x17028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_7 0x190D7028u //! Register Reset Value #define IRNEN_DMA_EGP_7_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_7_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_7_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_7_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_7_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_7 Register DPTR_DMA_EGP_7 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_7 0x17030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_7 0x190D7030u //! Register Reset Value #define DPTR_DMA_EGP_7_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_7_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_7_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_7_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_7_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_8 Register CFG_DMA_EGP_8 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_8 0x18000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_8 0x190D8000u //! Register Reset Value #define CFG_DMA_EGP_8_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_8_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_8_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_8_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_8_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_8_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_8_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_8_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_8_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_8_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_8_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_8 Register DQPC_DMA_EGP_8 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_8 0x18004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_8 0x190D8004u //! Register Reset Value #define DQPC_DMA_EGP_8_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_8_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_8_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_8 Register IRNCR_DMA_EGP_8 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_8 0x18020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_8 0x190D8020u //! Register Reset Value #define IRNCR_DMA_EGP_8_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_8_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_8_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_8_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_8_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_8 Register IRNICR_DMA_EGP_8 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_8 0x18024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_8 0x190D8024u //! Register Reset Value #define IRNICR_DMA_EGP_8_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_8_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_8_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_8 Register IRNEN_DMA_EGP_8 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_8 0x18028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_8 0x190D8028u //! Register Reset Value #define IRNEN_DMA_EGP_8_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_8_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_8_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_8_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_8_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_8 Register DPTR_DMA_EGP_8 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_8 0x18030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_8 0x190D8030u //! Register Reset Value #define DPTR_DMA_EGP_8_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_8_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_8_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_8_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_8_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_9 Register CFG_DMA_EGP_9 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_9 0x19000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_9 0x190D9000u //! Register Reset Value #define CFG_DMA_EGP_9_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_9_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_9_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_9_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_9_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_9_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_9_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_9_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_9_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_9_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_9_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_9 Register DQPC_DMA_EGP_9 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_9 0x19004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_9 0x190D9004u //! Register Reset Value #define DQPC_DMA_EGP_9_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_9_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_9_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_9 Register IRNCR_DMA_EGP_9 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_9 0x19020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_9 0x190D9020u //! Register Reset Value #define IRNCR_DMA_EGP_9_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_9_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_9_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_9_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_9_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_9 Register IRNICR_DMA_EGP_9 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_9 0x19024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_9 0x190D9024u //! Register Reset Value #define IRNICR_DMA_EGP_9_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_9_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_9_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_9 Register IRNEN_DMA_EGP_9 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_9 0x19028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_9 0x190D9028u //! Register Reset Value #define IRNEN_DMA_EGP_9_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_9_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_9_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_9_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_9_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_9 Register DPTR_DMA_EGP_9 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_9 0x19030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_9 0x190D9030u //! Register Reset Value #define DPTR_DMA_EGP_9_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_9_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_9_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_9_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_9_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_10 Register CFG_DMA_EGP_10 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_10 0x1A000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_10 0x190DA000u //! Register Reset Value #define CFG_DMA_EGP_10_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_10_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_10_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_10_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_10_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_10_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_10_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_10_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_10_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_10_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_10_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_10 Register DQPC_DMA_EGP_10 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_10 0x1A004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_10 0x190DA004u //! Register Reset Value #define DQPC_DMA_EGP_10_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_10_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_10_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_10 Register IRNCR_DMA_EGP_10 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_10 0x1A020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_10 0x190DA020u //! Register Reset Value #define IRNCR_DMA_EGP_10_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_10_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_10_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_10_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_10_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_10 Register IRNICR_DMA_EGP_10 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_10 0x1A024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_10 0x190DA024u //! Register Reset Value #define IRNICR_DMA_EGP_10_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_10_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_10_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_10 Register IRNEN_DMA_EGP_10 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_10 0x1A028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_10 0x190DA028u //! Register Reset Value #define IRNEN_DMA_EGP_10_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_10_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_10_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_10_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_10_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_10 Register DPTR_DMA_EGP_10 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_10 0x1A030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_10 0x190DA030u //! Register Reset Value #define DPTR_DMA_EGP_10_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_10_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_10_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_10_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_10_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_11 Register CFG_DMA_EGP_11 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_11 0x1B000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_11 0x190DB000u //! Register Reset Value #define CFG_DMA_EGP_11_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_11_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_11_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_11_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_11_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_11_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_11_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_11_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_11_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_11_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_11_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_11 Register DQPC_DMA_EGP_11 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_11 0x1B004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_11 0x190DB004u //! Register Reset Value #define DQPC_DMA_EGP_11_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_11_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_11_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_11 Register IRNCR_DMA_EGP_11 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_11 0x1B020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_11 0x190DB020u //! Register Reset Value #define IRNCR_DMA_EGP_11_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_11_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_11_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_11_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_11_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_11 Register IRNICR_DMA_EGP_11 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_11 0x1B024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_11 0x190DB024u //! Register Reset Value #define IRNICR_DMA_EGP_11_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_11_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_11_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_11 Register IRNEN_DMA_EGP_11 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_11 0x1B028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_11 0x190DB028u //! Register Reset Value #define IRNEN_DMA_EGP_11_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_11_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_11_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_11_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_11_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_11 Register DPTR_DMA_EGP_11 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_11 0x1B030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_11 0x190DB030u //! Register Reset Value #define DPTR_DMA_EGP_11_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_11_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_11_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_11_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_11_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_12 Register CFG_DMA_EGP_12 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_12 0x1C000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_12 0x190DC000u //! Register Reset Value #define CFG_DMA_EGP_12_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_12_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_12_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_12_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_12_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_12_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_12_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_12_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_12_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_12_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_12_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_12 Register DQPC_DMA_EGP_12 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_12 0x1C004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_12 0x190DC004u //! Register Reset Value #define DQPC_DMA_EGP_12_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_12_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_12_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_12 Register IRNCR_DMA_EGP_12 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_12 0x1C020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_12 0x190DC020u //! Register Reset Value #define IRNCR_DMA_EGP_12_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_12_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_12_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_12_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_12_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_12 Register IRNICR_DMA_EGP_12 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_12 0x1C024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_12 0x190DC024u //! Register Reset Value #define IRNICR_DMA_EGP_12_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_12_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_12_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_12 Register IRNEN_DMA_EGP_12 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_12 0x1C028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_12 0x190DC028u //! Register Reset Value #define IRNEN_DMA_EGP_12_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_12_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_12_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_12_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_12_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_12 Register DPTR_DMA_EGP_12 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_12 0x1C030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_12 0x190DC030u //! Register Reset Value #define DPTR_DMA_EGP_12_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_12_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_12_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_12_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_12_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_13 Register CFG_DMA_EGP_13 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_13 0x1D000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_13 0x190DD000u //! Register Reset Value #define CFG_DMA_EGP_13_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_13_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_13_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_13_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_13_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_13_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_13_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_13_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_13_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_13_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_13_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_13 Register DQPC_DMA_EGP_13 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_13 0x1D004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_13 0x190DD004u //! Register Reset Value #define DQPC_DMA_EGP_13_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_13_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_13_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_13 Register IRNCR_DMA_EGP_13 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_13 0x1D020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_13 0x190DD020u //! Register Reset Value #define IRNCR_DMA_EGP_13_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_13_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_13_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_13_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_13_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_13 Register IRNICR_DMA_EGP_13 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_13 0x1D024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_13 0x190DD024u //! Register Reset Value #define IRNICR_DMA_EGP_13_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_13_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_13_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_13 Register IRNEN_DMA_EGP_13 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_13 0x1D028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_13 0x190DD028u //! Register Reset Value #define IRNEN_DMA_EGP_13_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_13_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_13_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_13_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_13_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_13 Register DPTR_DMA_EGP_13 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_13 0x1D030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_13 0x190DD030u //! Register Reset Value #define DPTR_DMA_EGP_13_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_13_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_13_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_13_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_13_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_14 Register CFG_DMA_EGP_14 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_14 0x1E000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_14 0x190DE000u //! Register Reset Value #define CFG_DMA_EGP_14_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_14_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_14_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_14_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_14_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_14_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_14_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_14_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_14_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_14_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_14_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_14 Register DQPC_DMA_EGP_14 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_14 0x1E004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_14 0x190DE004u //! Register Reset Value #define DQPC_DMA_EGP_14_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_14_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_14_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_14 Register IRNCR_DMA_EGP_14 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_14 0x1E020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_14 0x190DE020u //! Register Reset Value #define IRNCR_DMA_EGP_14_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_14_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_14_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_14_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_14_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_14 Register IRNICR_DMA_EGP_14 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_14 0x1E024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_14 0x190DE024u //! Register Reset Value #define IRNICR_DMA_EGP_14_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_14_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_14_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_14 Register IRNEN_DMA_EGP_14 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_14 0x1E028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_14 0x190DE028u //! Register Reset Value #define IRNEN_DMA_EGP_14_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_14_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_14_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_14_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_14_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_14 Register DPTR_DMA_EGP_14 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_14 0x1E030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_14 0x190DE030u //! Register Reset Value #define DPTR_DMA_EGP_14_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_14_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_14_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_14_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_14_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_15 Register CFG_DMA_EGP_15 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_15 0x1F000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_15 0x190DF000u //! Register Reset Value #define CFG_DMA_EGP_15_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_15_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_15_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_15_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_15_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_15_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_15_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_15_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_15_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_15_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_15_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_15 Register DQPC_DMA_EGP_15 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_15 0x1F004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_15 0x190DF004u //! Register Reset Value #define DQPC_DMA_EGP_15_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_15_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_15_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_15 Register IRNCR_DMA_EGP_15 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_15 0x1F020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_15 0x190DF020u //! Register Reset Value #define IRNCR_DMA_EGP_15_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_15_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_15_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_15_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_15_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_15 Register IRNICR_DMA_EGP_15 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_15 0x1F024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_15 0x190DF024u //! Register Reset Value #define IRNICR_DMA_EGP_15_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_15_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_15_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_15 Register IRNEN_DMA_EGP_15 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_15 0x1F028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_15 0x190DF028u //! Register Reset Value #define IRNEN_DMA_EGP_15_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_15_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_15_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_15_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_15_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_15 Register DPTR_DMA_EGP_15 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_15 0x1F030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_15 0x190DF030u //! Register Reset Value #define DPTR_DMA_EGP_15_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_15_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_15_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_15_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_15_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_16 Register CFG_DMA_EGP_16 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_16 0x20000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_16 0x190E0000u //! Register Reset Value #define CFG_DMA_EGP_16_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_16_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_16_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_16_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_16_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_16_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_16_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_16_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_16_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_16_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_16_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_16 Register DQPC_DMA_EGP_16 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_16 0x20004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_16 0x190E0004u //! Register Reset Value #define DQPC_DMA_EGP_16_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_16_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_16_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_16 Register IRNCR_DMA_EGP_16 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_16 0x20020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_16 0x190E0020u //! Register Reset Value #define IRNCR_DMA_EGP_16_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_16_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_16_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_16_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_16_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_16 Register IRNICR_DMA_EGP_16 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_16 0x20024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_16 0x190E0024u //! Register Reset Value #define IRNICR_DMA_EGP_16_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_16_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_16_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_16 Register IRNEN_DMA_EGP_16 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_16 0x20028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_16 0x190E0028u //! Register Reset Value #define IRNEN_DMA_EGP_16_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_16_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_16_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_16_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_16_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_16 Register DPTR_DMA_EGP_16 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_16 0x20030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_16 0x190E0030u //! Register Reset Value #define DPTR_DMA_EGP_16_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_16_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_16_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_16_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_16_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_17 Register CFG_DMA_EGP_17 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_17 0x21000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_17 0x190E1000u //! Register Reset Value #define CFG_DMA_EGP_17_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_17_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_17_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_17_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_17_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_17_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_17_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_17_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_17_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_17_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_17_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_17 Register DQPC_DMA_EGP_17 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_17 0x21004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_17 0x190E1004u //! Register Reset Value #define DQPC_DMA_EGP_17_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_17_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_17_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_17 Register IRNCR_DMA_EGP_17 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_17 0x21020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_17 0x190E1020u //! Register Reset Value #define IRNCR_DMA_EGP_17_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_17_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_17_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_17_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_17_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_17 Register IRNICR_DMA_EGP_17 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_17 0x21024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_17 0x190E1024u //! Register Reset Value #define IRNICR_DMA_EGP_17_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_17_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_17_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_17 Register IRNEN_DMA_EGP_17 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_17 0x21028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_17 0x190E1028u //! Register Reset Value #define IRNEN_DMA_EGP_17_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_17_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_17_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_17_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_17_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_17 Register DPTR_DMA_EGP_17 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_17 0x21030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_17 0x190E1030u //! Register Reset Value #define DPTR_DMA_EGP_17_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_17_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_17_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_17_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_17_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_18 Register CFG_DMA_EGP_18 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_18 0x22000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_18 0x190E2000u //! Register Reset Value #define CFG_DMA_EGP_18_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_18_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_18_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_18_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_18_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_18_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_18_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_18_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_18_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_18_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_18_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_18 Register DQPC_DMA_EGP_18 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_18 0x22004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_18 0x190E2004u //! Register Reset Value #define DQPC_DMA_EGP_18_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_18_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_18_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_18 Register IRNCR_DMA_EGP_18 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_18 0x22020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_18 0x190E2020u //! Register Reset Value #define IRNCR_DMA_EGP_18_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_18_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_18_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_18_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_18_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_18 Register IRNICR_DMA_EGP_18 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_18 0x22024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_18 0x190E2024u //! Register Reset Value #define IRNICR_DMA_EGP_18_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_18_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_18_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_18 Register IRNEN_DMA_EGP_18 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_18 0x22028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_18 0x190E2028u //! Register Reset Value #define IRNEN_DMA_EGP_18_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_18_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_18_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_18_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_18_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_18 Register DPTR_DMA_EGP_18 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_18 0x22030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_18 0x190E2030u //! Register Reset Value #define DPTR_DMA_EGP_18_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_18_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_18_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_18_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_18_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_19 Register CFG_DMA_EGP_19 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_19 0x23000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_19 0x190E3000u //! Register Reset Value #define CFG_DMA_EGP_19_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_19_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_19_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_19_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_19_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_19_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_19_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_19_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_19_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_19_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_19_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_19 Register DQPC_DMA_EGP_19 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_19 0x23004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_19 0x190E3004u //! Register Reset Value #define DQPC_DMA_EGP_19_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_19_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_19_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_19 Register IRNCR_DMA_EGP_19 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_19 0x23020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_19 0x190E3020u //! Register Reset Value #define IRNCR_DMA_EGP_19_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_19_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_19_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_19_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_19_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_19 Register IRNICR_DMA_EGP_19 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_19 0x23024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_19 0x190E3024u //! Register Reset Value #define IRNICR_DMA_EGP_19_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_19_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_19_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_19 Register IRNEN_DMA_EGP_19 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_19 0x23028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_19 0x190E3028u //! Register Reset Value #define IRNEN_DMA_EGP_19_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_19_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_19_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_19_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_19_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_19 Register DPTR_DMA_EGP_19 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_19 0x23030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_19 0x190E3030u //! Register Reset Value #define DPTR_DMA_EGP_19_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_19_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_19_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_19_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_19_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_20 Register CFG_DMA_EGP_20 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_20 0x24000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_20 0x190E4000u //! Register Reset Value #define CFG_DMA_EGP_20_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_20_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_20_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_20_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_20_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_20_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_20_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_20_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_20_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_20_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_20_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_20 Register DQPC_DMA_EGP_20 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_20 0x24004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_20 0x190E4004u //! Register Reset Value #define DQPC_DMA_EGP_20_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_20_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_20_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_20 Register IRNCR_DMA_EGP_20 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_20 0x24020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_20 0x190E4020u //! Register Reset Value #define IRNCR_DMA_EGP_20_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_20_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_20_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_20_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_20_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_20 Register IRNICR_DMA_EGP_20 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_20 0x24024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_20 0x190E4024u //! Register Reset Value #define IRNICR_DMA_EGP_20_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_20_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_20_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_20 Register IRNEN_DMA_EGP_20 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_20 0x24028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_20 0x190E4028u //! Register Reset Value #define IRNEN_DMA_EGP_20_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_20_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_20_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_20_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_20_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_20 Register DPTR_DMA_EGP_20 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_20 0x24030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_20 0x190E4030u //! Register Reset Value #define DPTR_DMA_EGP_20_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_20_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_20_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_20_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_20_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_21 Register CFG_DMA_EGP_21 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_21 0x25000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_21 0x190E5000u //! Register Reset Value #define CFG_DMA_EGP_21_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_21_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_21_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_21_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_21_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_21_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_21_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_21_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_21_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_21_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_21_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_21 Register DQPC_DMA_EGP_21 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_21 0x25004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_21 0x190E5004u //! Register Reset Value #define DQPC_DMA_EGP_21_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_21_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_21_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_21 Register IRNCR_DMA_EGP_21 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_21 0x25020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_21 0x190E5020u //! Register Reset Value #define IRNCR_DMA_EGP_21_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_21_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_21_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_21_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_21_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_21 Register IRNICR_DMA_EGP_21 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_21 0x25024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_21 0x190E5024u //! Register Reset Value #define IRNICR_DMA_EGP_21_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_21_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_21_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_21 Register IRNEN_DMA_EGP_21 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_21 0x25028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_21 0x190E5028u //! Register Reset Value #define IRNEN_DMA_EGP_21_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_21_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_21_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_21_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_21_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_21 Register DPTR_DMA_EGP_21 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_21 0x25030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_21 0x190E5030u //! Register Reset Value #define DPTR_DMA_EGP_21_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_21_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_21_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_21_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_21_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_22 Register CFG_DMA_EGP_22 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_22 0x26000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_22 0x190E6000u //! Register Reset Value #define CFG_DMA_EGP_22_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_22_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_22_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_22_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_22_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_22_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_22_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_22_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_22_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_22_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_22_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_22 Register DQPC_DMA_EGP_22 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_22 0x26004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_22 0x190E6004u //! Register Reset Value #define DQPC_DMA_EGP_22_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_22_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_22_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_22 Register IRNCR_DMA_EGP_22 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_22 0x26020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_22 0x190E6020u //! Register Reset Value #define IRNCR_DMA_EGP_22_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_22_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_22_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_22_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_22_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_22 Register IRNICR_DMA_EGP_22 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_22 0x26024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_22 0x190E6024u //! Register Reset Value #define IRNICR_DMA_EGP_22_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_22_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_22_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_22 Register IRNEN_DMA_EGP_22 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_22 0x26028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_22 0x190E6028u //! Register Reset Value #define IRNEN_DMA_EGP_22_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_22_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_22_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_22_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_22_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_22 Register DPTR_DMA_EGP_22 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_22 0x26030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_22 0x190E6030u //! Register Reset Value #define DPTR_DMA_EGP_22_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_22_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_22_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_22_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_22_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_23 Register CFG_DMA_EGP_23 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_23 0x27000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_23 0x190E7000u //! Register Reset Value #define CFG_DMA_EGP_23_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_23_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_23_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_23_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_23_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_23_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_23_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_23_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_23_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_23_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_23_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_23 Register DQPC_DMA_EGP_23 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_23 0x27004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_23 0x190E7004u //! Register Reset Value #define DQPC_DMA_EGP_23_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_23_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_23_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_23 Register IRNCR_DMA_EGP_23 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_23 0x27020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_23 0x190E7020u //! Register Reset Value #define IRNCR_DMA_EGP_23_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_23_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_23_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_23_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_23_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_23 Register IRNICR_DMA_EGP_23 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_23 0x27024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_23 0x190E7024u //! Register Reset Value #define IRNICR_DMA_EGP_23_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_23_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_23_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_23 Register IRNEN_DMA_EGP_23 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_23 0x27028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_23 0x190E7028u //! Register Reset Value #define IRNEN_DMA_EGP_23_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_23_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_23_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_23_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_23_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_23 Register DPTR_DMA_EGP_23 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_23 0x27030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_23 0x190E7030u //! Register Reset Value #define DPTR_DMA_EGP_23_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_23_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_23_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_23_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_23_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_24 Register CFG_DMA_EGP_24 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_24 0x28000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_24 0x190E8000u //! Register Reset Value #define CFG_DMA_EGP_24_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_24_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_24_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_24_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_24_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_24_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_24_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_24_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_24_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_24_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_24_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_24 Register DQPC_DMA_EGP_24 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_24 0x28004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_24 0x190E8004u //! Register Reset Value #define DQPC_DMA_EGP_24_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_24_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_24_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_24 Register IRNCR_DMA_EGP_24 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_24 0x28020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_24 0x190E8020u //! Register Reset Value #define IRNCR_DMA_EGP_24_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_24_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_24_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_24_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_24_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_24 Register IRNICR_DMA_EGP_24 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_24 0x28024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_24 0x190E8024u //! Register Reset Value #define IRNICR_DMA_EGP_24_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_24_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_24_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_24 Register IRNEN_DMA_EGP_24 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_24 0x28028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_24 0x190E8028u //! Register Reset Value #define IRNEN_DMA_EGP_24_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_24_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_24_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_24_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_24_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_24 Register DPTR_DMA_EGP_24 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_24 0x28030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_24 0x190E8030u //! Register Reset Value #define DPTR_DMA_EGP_24_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_24_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_24_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_24_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_24_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_DMA_EGP_25 Register CFG_DMA_EGP_25 - DMA Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_DMA_EGP_25 0x29000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_DMA_EGP_25 0x190E9000u //! Register Reset Value #define CFG_DMA_EGP_25_RST 0x00000000u //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_25_DQREQ_POS 0 //! Field DQREQ - Enable DMA Dequeue Request #define CFG_DMA_EGP_25_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_25_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_25_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_25_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_DMA_EGP_25_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_DMA_EGP_25_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_DMA_EGP_25_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_25_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_DMA_EGP_25_EPMAP_MASK 0x7F0000u //! @} //! \defgroup DQPC_DMA_EGP_25 Register DQPC_DMA_EGP_25 - DMA Egress Port dequeue packet counter //! @{ //! Register Offset (relative) #define DQPC_DMA_EGP_25 0x29004 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DQPC_DMA_EGP_25 0x190E9004u //! Register Reset Value #define DQPC_DMA_EGP_25_RST 0x00000000u //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_25_PC_POS 0 //! Field PC - Per Port Packet Counter #define DQPC_DMA_EGP_25_PC_MASK 0xFFFFFFFFu //! @} //! \defgroup IRNCR_DMA_EGP_25 Register IRNCR_DMA_EGP_25 - DMA Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_DMA_EGP_25 0x29020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_DMA_EGP_25 0x190E9020u //! Register Reset Value #define IRNCR_DMA_EGP_25_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_25_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_DMA_EGP_25_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_DMA_EGP_25_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_DMA_EGP_25_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_DMA_EGP_25 Register IRNICR_DMA_EGP_25 - DMA Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_DMA_EGP_25 0x29024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_DMA_EGP_25 0x190E9024u //! Register Reset Value #define IRNICR_DMA_EGP_25_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_25_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_DMA_EGP_25_DR_MASK 0x2u //! @} //! \defgroup IRNEN_DMA_EGP_25 Register IRNEN_DMA_EGP_25 - DMA Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_DMA_EGP_25 0x29028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_DMA_EGP_25 0x190E9028u //! Register Reset Value #define IRNEN_DMA_EGP_25_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_25_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_DMA_EGP_25_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_DMA_EGP_25_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_DMA_EGP_25_DR_EN 0x1 //! @} //! \defgroup DPTR_DMA_EGP_25 Register DPTR_DMA_EGP_25 - DMA Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_DMA_EGP_25 0x29030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_DMA_EGP_25 0x190E9030u //! Register Reset Value #define DPTR_DMA_EGP_25_RST 0x00000007u //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_25_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_DMA_EGP_25_ND_MASK 0x7u //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_25_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_DMA_EGP_25_DPTR_MASK 0x70000u //! @} //! \defgroup CFG_PON_EGP_26 Register CFG_PON_EGP_26 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_26 0x2A000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_26 0x190EA000u //! Register Reset Value #define CFG_PON_EGP_26_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_26_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_26_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_26_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_26_DQREQ_EN 0x1 //! Field BUFRTN - Enable PON Buffer Return #define CFG_PON_EGP_26_BUFRTN_POS 1 //! Field BUFRTN - Enable PON Buffer Return #define CFG_PON_EGP_26_BUFRTN_MASK 0x2u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_26_BUFRTN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_26_BUFRTN_EN 0x1 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_PON_EGP_26_BFBPEN_POS 2 //! Field BFBPEN - Buffer Return Back Pressure Enable #define CFG_PON_EGP_26_BFBPEN_MASK 0x4u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_26_BFBPEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_26_BFBPEN_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_26_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_26_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_26_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_26_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_26_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_26_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_26 Register IRNCR_PON_EGP_26 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_26 0x2A020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_26 0x190EA020u //! Register Reset Value #define IRNCR_PON_EGP_26_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_26_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_26_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_26_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_26_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_26 Register IRNICR_PON_EGP_26 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_26 0x2A024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_26 0x190EA024u //! Register Reset Value #define IRNICR_PON_EGP_26_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_26_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_26_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_26 Register IRNEN_PON_EGP_26 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_26 0x2A028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_26 0x190EA028u //! Register Reset Value #define IRNEN_PON_EGP_26_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_26_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_26_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_26_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_26_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_26 Register DPTR_PON_EGP_26 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_26 0x2A030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_26 0x190EA030u //! Register Reset Value #define DPTR_PON_EGP_26_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_26_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_26_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_26_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_26_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_26_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_26_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_26_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_26_SDPTR_MASK 0x7000000u //! @} //! \defgroup BPRC_PON_EGP Register BPRC_PON_EGP - Egress Port Buffer Pointer Return counter //! @{ //! Register Offset (relative) #define BPRC_PON_EGP 0x2A034 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_BPRC_PON_EGP 0x190EA034u //! Register Reset Value #define BPRC_PON_EGP_RST 0x00000000u //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_PON_EGP_BPRC_POS 0 //! Field BPRC - Per Port Buffer Pointer Return Counter #define BPRC_PON_EGP_BPRC_MASK 0xFFFFFFFFu //! @} //! \defgroup PTR_RTN_PON_DW2 Register PTR_RTN_PON_DW2 - CPU Egress Port Buffer Pointer Return DW2 //! @{ //! Register Offset (relative) #define PTR_RTN_PON_DW2 0x2A080 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_PON_DW2 0x190EA080u //! Register Reset Value #define PTR_RTN_PON_DW2_RST 0xFFFFFF80u //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_PON_DW2_BPTR_POS 7 //! Field BPTR - Buffer Pointer (DW2 of the Descriptor) #define PTR_RTN_PON_DW2_BPTR_MASK 0xFFFFFF80u //! @} //! \defgroup PTR_RTN_PON_DW3 Register PTR_RTN_PON_DW3 - CPU Egress Port Buffer Pointer Return DW3 //! @{ //! Register Offset (relative) #define PTR_RTN_PON_DW3 0x2A084 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_PTR_RTN_PON_DW3 0x190EA084u //! Register Reset Value #define PTR_RTN_PON_DW3_RST 0x00700000u //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_PON_DW3_POOL_POS 16 //! Field POOL - Pool ID of the buffer to be returned provided in DW2 #define PTR_RTN_PON_DW3_POOL_MASK 0x70000u //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_PON_DW3_POLICY_POS 20 //! Field POLICY - Policy ID of the buffer to be returned provided in DW2 #define PTR_RTN_PON_DW3_POLICY_MASK 0x700000u //! @} //! \defgroup DESC0_0_PON_EGP_26 Register DESC0_0_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_26 0x2A100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_26 0x190EA100u //! Register Reset Value #define DESC0_0_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_26 Register DESC1_0_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_26 0x2A104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_26 0x190EA104u //! Register Reset Value #define DESC1_0_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_26 Register DESC2_0_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_26 0x2A108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_26 0x190EA108u //! Register Reset Value #define DESC2_0_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_26 Register DESC3_0_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_26 0x2A10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_26 0x190EA10Cu //! Register Reset Value #define DESC3_0_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_26 Register DESC0_1_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_26 0x2A110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_26 0x190EA110u //! Register Reset Value #define DESC0_1_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_26 Register DESC1_1_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_26 0x2A114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_26 0x190EA114u //! Register Reset Value #define DESC1_1_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_26 Register DESC2_1_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_26 0x2A118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_26 0x190EA118u //! Register Reset Value #define DESC2_1_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_26 Register DESC3_1_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_26 0x2A11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_26 0x190EA11Cu //! Register Reset Value #define DESC3_1_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_26 Register DESC0_2_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_26 0x2A120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_26 0x190EA120u //! Register Reset Value #define DESC0_2_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_26 Register DESC1_2_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_26 0x2A124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_26 0x190EA124u //! Register Reset Value #define DESC1_2_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_26 Register DESC2_2_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_26 0x2A128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_26 0x190EA128u //! Register Reset Value #define DESC2_2_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_26 Register DESC3_2_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_26 0x2A12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_26 0x190EA12Cu //! Register Reset Value #define DESC3_2_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_26 Register DESC0_3_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_26 0x2A130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_26 0x190EA130u //! Register Reset Value #define DESC0_3_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_26 Register DESC1_3_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_26 0x2A134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_26 0x190EA134u //! Register Reset Value #define DESC1_3_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_26 Register DESC2_3_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_26 0x2A138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_26 0x190EA138u //! Register Reset Value #define DESC2_3_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_26 Register DESC3_3_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_26 0x2A13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_26 0x190EA13Cu //! Register Reset Value #define DESC3_3_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_26 Register DESC0_4_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_26 0x2A140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_26 0x190EA140u //! Register Reset Value #define DESC0_4_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_26 Register DESC1_4_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_26 0x2A144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_26 0x190EA144u //! Register Reset Value #define DESC1_4_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_26 Register DESC2_4_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_26 0x2A148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_26 0x190EA148u //! Register Reset Value #define DESC2_4_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_26 Register DESC3_4_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_26 0x2A14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_26 0x190EA14Cu //! Register Reset Value #define DESC3_4_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_26 Register DESC0_5_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_26 0x2A150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_26 0x190EA150u //! Register Reset Value #define DESC0_5_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_26 Register DESC1_5_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_26 0x2A154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_26 0x190EA154u //! Register Reset Value #define DESC1_5_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_26 Register DESC2_5_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_26 0x2A158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_26 0x190EA158u //! Register Reset Value #define DESC2_5_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_26 Register DESC3_5_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_26 0x2A15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_26 0x190EA15Cu //! Register Reset Value #define DESC3_5_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_26 Register DESC0_6_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_26 0x2A160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_26 0x190EA160u //! Register Reset Value #define DESC0_6_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_26 Register DESC1_6_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_26 0x2A164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_26 0x190EA164u //! Register Reset Value #define DESC1_6_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_26 Register DESC2_6_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_26 0x2A168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_26 0x190EA168u //! Register Reset Value #define DESC2_6_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_26 Register DESC3_6_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_26 0x2A16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_26 0x190EA16Cu //! Register Reset Value #define DESC3_6_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_26 Register DESC0_7_PON_EGP_26 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_26 0x2A170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_26 0x190EA170u //! Register Reset Value #define DESC0_7_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_26 Register DESC1_7_PON_EGP_26 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_26 0x2A174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_26 0x190EA174u //! Register Reset Value #define DESC1_7_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_26 Register DESC2_7_PON_EGP_26 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_26 0x2A178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_26 0x190EA178u //! Register Reset Value #define DESC2_7_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_26 Register DESC3_7_PON_EGP_26 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_26 0x2A17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_26 0x190EA17Cu //! Register Reset Value #define DESC3_7_PON_EGP_26_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_26_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_26_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_26 Register DESC0_0_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_26 0x2A200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_26 0x190EA200u //! Register Reset Value #define DESC0_0_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_26 Register DESC1_0_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_26 0x2A204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_26 0x190EA204u //! Register Reset Value #define DESC1_0_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_26 Register DESC2_0_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_26 0x2A208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_26 0x190EA208u //! Register Reset Value #define DESC2_0_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_26 Register DESC3_0_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_26 0x2A20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_26 0x190EA20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_26 Register DESC0_1_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_26 0x2A210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_26 0x190EA210u //! Register Reset Value #define DESC0_1_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_26 Register DESC1_1_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_26 0x2A214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_26 0x190EA214u //! Register Reset Value #define DESC1_1_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_26 Register DESC2_1_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_26 0x2A218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_26 0x190EA218u //! Register Reset Value #define DESC2_1_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_26 Register DESC3_1_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_26 0x2A21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_26 0x190EA21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_26 Register DESC0_2_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_26 0x2A220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_26 0x190EA220u //! Register Reset Value #define DESC0_2_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_26 Register DESC1_2_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_26 0x2A224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_26 0x190EA224u //! Register Reset Value #define DESC1_2_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_26 Register DESC2_2_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_26 0x2A228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_26 0x190EA228u //! Register Reset Value #define DESC2_2_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_26 Register DESC3_2_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_26 0x2A22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_26 0x190EA22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_26 Register DESC0_3_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_26 0x2A230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_26 0x190EA230u //! Register Reset Value #define DESC0_3_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_26 Register DESC1_3_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_26 0x2A234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_26 0x190EA234u //! Register Reset Value #define DESC1_3_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_26 Register DESC2_3_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_26 0x2A238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_26 0x190EA238u //! Register Reset Value #define DESC2_3_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_26 Register DESC3_3_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_26 0x2A23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_26 0x190EA23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_26 Register DESC0_4_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_26 0x2A240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_26 0x190EA240u //! Register Reset Value #define DESC0_4_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_26 Register DESC1_4_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_26 0x2A244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_26 0x190EA244u //! Register Reset Value #define DESC1_4_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_26 Register DESC2_4_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_26 0x2A248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_26 0x190EA248u //! Register Reset Value #define DESC2_4_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_26 Register DESC3_4_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_26 0x2A24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_26 0x190EA24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_26 Register DESC0_5_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_26 0x2A250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_26 0x190EA250u //! Register Reset Value #define DESC0_5_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_26 Register DESC1_5_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_26 0x2A254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_26 0x190EA254u //! Register Reset Value #define DESC1_5_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_26 Register DESC2_5_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_26 0x2A258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_26 0x190EA258u //! Register Reset Value #define DESC2_5_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_26 Register DESC3_5_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_26 0x2A25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_26 0x190EA25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_26 Register DESC0_6_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_26 0x2A260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_26 0x190EA260u //! Register Reset Value #define DESC0_6_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_26 Register DESC1_6_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_26 0x2A264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_26 0x190EA264u //! Register Reset Value #define DESC1_6_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_26 Register DESC2_6_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_26 0x2A268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_26 0x190EA268u //! Register Reset Value #define DESC2_6_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_26 Register DESC3_6_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_26 0x2A26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_26 0x190EA26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_26 Register DESC0_7_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_26 0x2A270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_26 0x190EA270u //! Register Reset Value #define DESC0_7_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_26 Register DESC1_7_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_26 0x2A274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_26 0x190EA274u //! Register Reset Value #define DESC1_7_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_26 Register DESC2_7_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_26 0x2A278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_26 0x190EA278u //! Register Reset Value #define DESC2_7_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_26_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_26 Register DESC3_7_PON_EGP_S_26 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_26 0x2A27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_26 0x190EA27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_26_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_26_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_26_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_26_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_26_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_27 Register CFG_PON_EGP_27 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_27 0x2A400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_27 0x190EA400u //! Register Reset Value #define CFG_PON_EGP_27_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_27_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_27_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_27_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_27_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_27_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_27_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_27_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_27_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_27_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_27_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_27 Register IRNCR_PON_EGP_27 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_27 0x2A420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_27 0x190EA420u //! Register Reset Value #define IRNCR_PON_EGP_27_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_27_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_27_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_27_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_27_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_27 Register IRNICR_PON_EGP_27 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_27 0x2A424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_27 0x190EA424u //! Register Reset Value #define IRNICR_PON_EGP_27_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_27_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_27_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_27 Register IRNEN_PON_EGP_27 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_27 0x2A428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_27 0x190EA428u //! Register Reset Value #define IRNEN_PON_EGP_27_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_27_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_27_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_27_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_27_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_27 Register DPTR_PON_EGP_27 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_27 0x2A430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_27 0x190EA430u //! Register Reset Value #define DPTR_PON_EGP_27_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_27_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_27_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_27_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_27_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_27_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_27_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_27_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_27_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_27 Register DESC0_0_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_27 0x2A500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_27 0x190EA500u //! Register Reset Value #define DESC0_0_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_27 Register DESC1_0_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_27 0x2A504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_27 0x190EA504u //! Register Reset Value #define DESC1_0_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_27 Register DESC2_0_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_27 0x2A508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_27 0x190EA508u //! Register Reset Value #define DESC2_0_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_27 Register DESC3_0_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_27 0x2A50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_27 0x190EA50Cu //! Register Reset Value #define DESC3_0_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_27 Register DESC0_1_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_27 0x2A510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_27 0x190EA510u //! Register Reset Value #define DESC0_1_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_27 Register DESC1_1_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_27 0x2A514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_27 0x190EA514u //! Register Reset Value #define DESC1_1_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_27 Register DESC2_1_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_27 0x2A518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_27 0x190EA518u //! Register Reset Value #define DESC2_1_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_27 Register DESC3_1_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_27 0x2A51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_27 0x190EA51Cu //! Register Reset Value #define DESC3_1_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_27 Register DESC0_2_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_27 0x2A520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_27 0x190EA520u //! Register Reset Value #define DESC0_2_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_27 Register DESC1_2_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_27 0x2A524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_27 0x190EA524u //! Register Reset Value #define DESC1_2_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_27 Register DESC2_2_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_27 0x2A528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_27 0x190EA528u //! Register Reset Value #define DESC2_2_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_27 Register DESC3_2_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_27 0x2A52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_27 0x190EA52Cu //! Register Reset Value #define DESC3_2_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_27 Register DESC0_3_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_27 0x2A530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_27 0x190EA530u //! Register Reset Value #define DESC0_3_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_27 Register DESC1_3_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_27 0x2A534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_27 0x190EA534u //! Register Reset Value #define DESC1_3_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_27 Register DESC2_3_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_27 0x2A538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_27 0x190EA538u //! Register Reset Value #define DESC2_3_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_27 Register DESC3_3_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_27 0x2A53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_27 0x190EA53Cu //! Register Reset Value #define DESC3_3_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_27 Register DESC0_4_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_27 0x2A540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_27 0x190EA540u //! Register Reset Value #define DESC0_4_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_27 Register DESC1_4_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_27 0x2A544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_27 0x190EA544u //! Register Reset Value #define DESC1_4_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_27 Register DESC2_4_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_27 0x2A548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_27 0x190EA548u //! Register Reset Value #define DESC2_4_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_27 Register DESC3_4_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_27 0x2A54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_27 0x190EA54Cu //! Register Reset Value #define DESC3_4_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_27 Register DESC0_5_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_27 0x2A550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_27 0x190EA550u //! Register Reset Value #define DESC0_5_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_27 Register DESC1_5_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_27 0x2A554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_27 0x190EA554u //! Register Reset Value #define DESC1_5_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_27 Register DESC2_5_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_27 0x2A558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_27 0x190EA558u //! Register Reset Value #define DESC2_5_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_27 Register DESC3_5_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_27 0x2A55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_27 0x190EA55Cu //! Register Reset Value #define DESC3_5_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_27 Register DESC0_6_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_27 0x2A560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_27 0x190EA560u //! Register Reset Value #define DESC0_6_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_27 Register DESC1_6_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_27 0x2A564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_27 0x190EA564u //! Register Reset Value #define DESC1_6_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_27 Register DESC2_6_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_27 0x2A568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_27 0x190EA568u //! Register Reset Value #define DESC2_6_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_27 Register DESC3_6_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_27 0x2A56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_27 0x190EA56Cu //! Register Reset Value #define DESC3_6_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_27 Register DESC0_7_PON_EGP_27 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_27 0x2A570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_27 0x190EA570u //! Register Reset Value #define DESC0_7_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_27 Register DESC1_7_PON_EGP_27 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_27 0x2A574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_27 0x190EA574u //! Register Reset Value #define DESC1_7_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_27 Register DESC2_7_PON_EGP_27 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_27 0x2A578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_27 0x190EA578u //! Register Reset Value #define DESC2_7_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_27 Register DESC3_7_PON_EGP_27 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_27 0x2A57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_27 0x190EA57Cu //! Register Reset Value #define DESC3_7_PON_EGP_27_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_27_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_27_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_27 Register DESC0_0_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_27 0x2A600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_27 0x190EA600u //! Register Reset Value #define DESC0_0_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_27 Register DESC1_0_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_27 0x2A604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_27 0x190EA604u //! Register Reset Value #define DESC1_0_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_27 Register DESC2_0_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_27 0x2A608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_27 0x190EA608u //! Register Reset Value #define DESC2_0_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_27 Register DESC3_0_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_27 0x2A60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_27 0x190EA60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_27 Register DESC0_1_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_27 0x2A610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_27 0x190EA610u //! Register Reset Value #define DESC0_1_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_27 Register DESC1_1_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_27 0x2A614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_27 0x190EA614u //! Register Reset Value #define DESC1_1_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_27 Register DESC2_1_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_27 0x2A618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_27 0x190EA618u //! Register Reset Value #define DESC2_1_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_27 Register DESC3_1_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_27 0x2A61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_27 0x190EA61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_27 Register DESC0_2_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_27 0x2A620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_27 0x190EA620u //! Register Reset Value #define DESC0_2_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_27 Register DESC1_2_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_27 0x2A624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_27 0x190EA624u //! Register Reset Value #define DESC1_2_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_27 Register DESC2_2_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_27 0x2A628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_27 0x190EA628u //! Register Reset Value #define DESC2_2_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_27 Register DESC3_2_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_27 0x2A62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_27 0x190EA62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_27 Register DESC0_3_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_27 0x2A630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_27 0x190EA630u //! Register Reset Value #define DESC0_3_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_27 Register DESC1_3_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_27 0x2A634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_27 0x190EA634u //! Register Reset Value #define DESC1_3_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_27 Register DESC2_3_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_27 0x2A638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_27 0x190EA638u //! Register Reset Value #define DESC2_3_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_27 Register DESC3_3_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_27 0x2A63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_27 0x190EA63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_27 Register DESC0_4_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_27 0x2A640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_27 0x190EA640u //! Register Reset Value #define DESC0_4_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_27 Register DESC1_4_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_27 0x2A644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_27 0x190EA644u //! Register Reset Value #define DESC1_4_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_27 Register DESC2_4_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_27 0x2A648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_27 0x190EA648u //! Register Reset Value #define DESC2_4_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_27 Register DESC3_4_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_27 0x2A64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_27 0x190EA64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_27 Register DESC0_5_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_27 0x2A650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_27 0x190EA650u //! Register Reset Value #define DESC0_5_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_27 Register DESC1_5_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_27 0x2A654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_27 0x190EA654u //! Register Reset Value #define DESC1_5_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_27 Register DESC2_5_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_27 0x2A658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_27 0x190EA658u //! Register Reset Value #define DESC2_5_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_27 Register DESC3_5_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_27 0x2A65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_27 0x190EA65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_27 Register DESC0_6_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_27 0x2A660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_27 0x190EA660u //! Register Reset Value #define DESC0_6_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_27 Register DESC1_6_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_27 0x2A664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_27 0x190EA664u //! Register Reset Value #define DESC1_6_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_27 Register DESC2_6_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_27 0x2A668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_27 0x190EA668u //! Register Reset Value #define DESC2_6_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_27 Register DESC3_6_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_27 0x2A66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_27 0x190EA66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_27 Register DESC0_7_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_27 0x2A670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_27 0x190EA670u //! Register Reset Value #define DESC0_7_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_27 Register DESC1_7_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_27 0x2A674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_27 0x190EA674u //! Register Reset Value #define DESC1_7_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_27 Register DESC2_7_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_27 0x2A678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_27 0x190EA678u //! Register Reset Value #define DESC2_7_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_27_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_27 Register DESC3_7_PON_EGP_S_27 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_27 0x2A67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_27 0x190EA67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_27_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_27_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_27_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_27_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_27_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_28 Register CFG_PON_EGP_28 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_28 0x2A800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_28 0x190EA800u //! Register Reset Value #define CFG_PON_EGP_28_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_28_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_28_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_28_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_28_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_28_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_28_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_28_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_28_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_28_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_28_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_28 Register IRNCR_PON_EGP_28 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_28 0x2A820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_28 0x190EA820u //! Register Reset Value #define IRNCR_PON_EGP_28_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_28_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_28_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_28_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_28_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_28 Register IRNICR_PON_EGP_28 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_28 0x2A824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_28 0x190EA824u //! Register Reset Value #define IRNICR_PON_EGP_28_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_28_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_28_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_28 Register IRNEN_PON_EGP_28 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_28 0x2A828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_28 0x190EA828u //! Register Reset Value #define IRNEN_PON_EGP_28_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_28_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_28_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_28_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_28_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_28 Register DPTR_PON_EGP_28 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_28 0x2A830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_28 0x190EA830u //! Register Reset Value #define DPTR_PON_EGP_28_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_28_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_28_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_28_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_28_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_28_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_28_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_28_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_28_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_28 Register DESC0_0_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_28 0x2A900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_28 0x190EA900u //! Register Reset Value #define DESC0_0_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_28 Register DESC1_0_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_28 0x2A904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_28 0x190EA904u //! Register Reset Value #define DESC1_0_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_28 Register DESC2_0_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_28 0x2A908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_28 0x190EA908u //! Register Reset Value #define DESC2_0_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_28 Register DESC3_0_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_28 0x2A90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_28 0x190EA90Cu //! Register Reset Value #define DESC3_0_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_28 Register DESC0_1_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_28 0x2A910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_28 0x190EA910u //! Register Reset Value #define DESC0_1_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_28 Register DESC1_1_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_28 0x2A914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_28 0x190EA914u //! Register Reset Value #define DESC1_1_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_28 Register DESC2_1_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_28 0x2A918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_28 0x190EA918u //! Register Reset Value #define DESC2_1_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_28 Register DESC3_1_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_28 0x2A91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_28 0x190EA91Cu //! Register Reset Value #define DESC3_1_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_28 Register DESC0_2_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_28 0x2A920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_28 0x190EA920u //! Register Reset Value #define DESC0_2_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_28 Register DESC1_2_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_28 0x2A924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_28 0x190EA924u //! Register Reset Value #define DESC1_2_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_28 Register DESC2_2_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_28 0x2A928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_28 0x190EA928u //! Register Reset Value #define DESC2_2_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_28 Register DESC3_2_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_28 0x2A92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_28 0x190EA92Cu //! Register Reset Value #define DESC3_2_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_28 Register DESC0_3_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_28 0x2A930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_28 0x190EA930u //! Register Reset Value #define DESC0_3_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_28 Register DESC1_3_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_28 0x2A934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_28 0x190EA934u //! Register Reset Value #define DESC1_3_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_28 Register DESC2_3_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_28 0x2A938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_28 0x190EA938u //! Register Reset Value #define DESC2_3_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_28 Register DESC3_3_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_28 0x2A93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_28 0x190EA93Cu //! Register Reset Value #define DESC3_3_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_28 Register DESC0_4_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_28 0x2A940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_28 0x190EA940u //! Register Reset Value #define DESC0_4_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_28 Register DESC1_4_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_28 0x2A944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_28 0x190EA944u //! Register Reset Value #define DESC1_4_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_28 Register DESC2_4_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_28 0x2A948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_28 0x190EA948u //! Register Reset Value #define DESC2_4_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_28 Register DESC3_4_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_28 0x2A94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_28 0x190EA94Cu //! Register Reset Value #define DESC3_4_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_28 Register DESC0_5_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_28 0x2A950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_28 0x190EA950u //! Register Reset Value #define DESC0_5_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_28 Register DESC1_5_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_28 0x2A954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_28 0x190EA954u //! Register Reset Value #define DESC1_5_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_28 Register DESC2_5_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_28 0x2A958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_28 0x190EA958u //! Register Reset Value #define DESC2_5_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_28 Register DESC3_5_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_28 0x2A95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_28 0x190EA95Cu //! Register Reset Value #define DESC3_5_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_28 Register DESC0_6_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_28 0x2A960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_28 0x190EA960u //! Register Reset Value #define DESC0_6_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_28 Register DESC1_6_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_28 0x2A964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_28 0x190EA964u //! Register Reset Value #define DESC1_6_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_28 Register DESC2_6_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_28 0x2A968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_28 0x190EA968u //! Register Reset Value #define DESC2_6_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_28 Register DESC3_6_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_28 0x2A96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_28 0x190EA96Cu //! Register Reset Value #define DESC3_6_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_28 Register DESC0_7_PON_EGP_28 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_28 0x2A970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_28 0x190EA970u //! Register Reset Value #define DESC0_7_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_28 Register DESC1_7_PON_EGP_28 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_28 0x2A974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_28 0x190EA974u //! Register Reset Value #define DESC1_7_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_28 Register DESC2_7_PON_EGP_28 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_28 0x2A978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_28 0x190EA978u //! Register Reset Value #define DESC2_7_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_28 Register DESC3_7_PON_EGP_28 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_28 0x2A97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_28 0x190EA97Cu //! Register Reset Value #define DESC3_7_PON_EGP_28_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_28_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_28_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_28 Register DESC0_0_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_28 0x2AA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_28 0x190EAA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_28 Register DESC1_0_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_28 0x2AA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_28 0x190EAA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_28 Register DESC2_0_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_28 0x2AA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_28 0x190EAA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_28 Register DESC3_0_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_28 0x2AA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_28 0x190EAA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_28 Register DESC0_1_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_28 0x2AA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_28 0x190EAA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_28 Register DESC1_1_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_28 0x2AA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_28 0x190EAA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_28 Register DESC2_1_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_28 0x2AA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_28 0x190EAA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_28 Register DESC3_1_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_28 0x2AA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_28 0x190EAA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_28 Register DESC0_2_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_28 0x2AA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_28 0x190EAA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_28 Register DESC1_2_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_28 0x2AA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_28 0x190EAA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_28 Register DESC2_2_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_28 0x2AA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_28 0x190EAA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_28 Register DESC3_2_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_28 0x2AA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_28 0x190EAA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_28 Register DESC0_3_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_28 0x2AA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_28 0x190EAA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_28 Register DESC1_3_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_28 0x2AA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_28 0x190EAA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_28 Register DESC2_3_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_28 0x2AA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_28 0x190EAA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_28 Register DESC3_3_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_28 0x2AA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_28 0x190EAA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_28 Register DESC0_4_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_28 0x2AA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_28 0x190EAA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_28 Register DESC1_4_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_28 0x2AA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_28 0x190EAA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_28 Register DESC2_4_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_28 0x2AA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_28 0x190EAA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_28 Register DESC3_4_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_28 0x2AA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_28 0x190EAA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_28 Register DESC0_5_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_28 0x2AA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_28 0x190EAA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_28 Register DESC1_5_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_28 0x2AA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_28 0x190EAA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_28 Register DESC2_5_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_28 0x2AA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_28 0x190EAA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_28 Register DESC3_5_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_28 0x2AA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_28 0x190EAA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_28 Register DESC0_6_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_28 0x2AA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_28 0x190EAA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_28 Register DESC1_6_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_28 0x2AA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_28 0x190EAA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_28 Register DESC2_6_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_28 0x2AA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_28 0x190EAA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_28 Register DESC3_6_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_28 0x2AA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_28 0x190EAA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_28 Register DESC0_7_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_28 0x2AA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_28 0x190EAA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_28 Register DESC1_7_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_28 0x2AA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_28 0x190EAA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_28 Register DESC2_7_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_28 0x2AA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_28 0x190EAA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_28_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_28 Register DESC3_7_PON_EGP_S_28 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_28 0x2AA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_28 0x190EAA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_28_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_28_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_28_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_28_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_28_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_29 Register CFG_PON_EGP_29 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_29 0x2AC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_29 0x190EAC00u //! Register Reset Value #define CFG_PON_EGP_29_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_29_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_29_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_29_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_29_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_29_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_29_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_29_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_29_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_29_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_29_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_29 Register IRNCR_PON_EGP_29 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_29 0x2AC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_29 0x190EAC20u //! Register Reset Value #define IRNCR_PON_EGP_29_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_29_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_29_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_29_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_29_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_29 Register IRNICR_PON_EGP_29 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_29 0x2AC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_29 0x190EAC24u //! Register Reset Value #define IRNICR_PON_EGP_29_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_29_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_29_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_29 Register IRNEN_PON_EGP_29 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_29 0x2AC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_29 0x190EAC28u //! Register Reset Value #define IRNEN_PON_EGP_29_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_29_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_29_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_29_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_29_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_29 Register DPTR_PON_EGP_29 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_29 0x2AC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_29 0x190EAC30u //! Register Reset Value #define DPTR_PON_EGP_29_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_29_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_29_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_29_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_29_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_29_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_29_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_29_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_29_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_29 Register DESC0_0_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_29 0x2AD00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_29 0x190EAD00u //! Register Reset Value #define DESC0_0_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_29 Register DESC1_0_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_29 0x2AD04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_29 0x190EAD04u //! Register Reset Value #define DESC1_0_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_29 Register DESC2_0_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_29 0x2AD08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_29 0x190EAD08u //! Register Reset Value #define DESC2_0_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_29 Register DESC3_0_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_29 0x2AD0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_29 0x190EAD0Cu //! Register Reset Value #define DESC3_0_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_29 Register DESC0_1_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_29 0x2AD10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_29 0x190EAD10u //! Register Reset Value #define DESC0_1_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_29 Register DESC1_1_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_29 0x2AD14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_29 0x190EAD14u //! Register Reset Value #define DESC1_1_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_29 Register DESC2_1_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_29 0x2AD18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_29 0x190EAD18u //! Register Reset Value #define DESC2_1_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_29 Register DESC3_1_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_29 0x2AD1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_29 0x190EAD1Cu //! Register Reset Value #define DESC3_1_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_29 Register DESC0_2_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_29 0x2AD20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_29 0x190EAD20u //! Register Reset Value #define DESC0_2_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_29 Register DESC1_2_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_29 0x2AD24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_29 0x190EAD24u //! Register Reset Value #define DESC1_2_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_29 Register DESC2_2_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_29 0x2AD28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_29 0x190EAD28u //! Register Reset Value #define DESC2_2_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_29 Register DESC3_2_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_29 0x2AD2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_29 0x190EAD2Cu //! Register Reset Value #define DESC3_2_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_29 Register DESC0_3_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_29 0x2AD30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_29 0x190EAD30u //! Register Reset Value #define DESC0_3_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_29 Register DESC1_3_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_29 0x2AD34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_29 0x190EAD34u //! Register Reset Value #define DESC1_3_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_29 Register DESC2_3_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_29 0x2AD38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_29 0x190EAD38u //! Register Reset Value #define DESC2_3_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_29 Register DESC3_3_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_29 0x2AD3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_29 0x190EAD3Cu //! Register Reset Value #define DESC3_3_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_29 Register DESC0_4_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_29 0x2AD40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_29 0x190EAD40u //! Register Reset Value #define DESC0_4_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_29 Register DESC1_4_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_29 0x2AD44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_29 0x190EAD44u //! Register Reset Value #define DESC1_4_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_29 Register DESC2_4_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_29 0x2AD48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_29 0x190EAD48u //! Register Reset Value #define DESC2_4_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_29 Register DESC3_4_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_29 0x2AD4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_29 0x190EAD4Cu //! Register Reset Value #define DESC3_4_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_29 Register DESC0_5_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_29 0x2AD50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_29 0x190EAD50u //! Register Reset Value #define DESC0_5_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_29 Register DESC1_5_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_29 0x2AD54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_29 0x190EAD54u //! Register Reset Value #define DESC1_5_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_29 Register DESC2_5_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_29 0x2AD58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_29 0x190EAD58u //! Register Reset Value #define DESC2_5_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_29 Register DESC3_5_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_29 0x2AD5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_29 0x190EAD5Cu //! Register Reset Value #define DESC3_5_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_29 Register DESC0_6_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_29 0x2AD60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_29 0x190EAD60u //! Register Reset Value #define DESC0_6_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_29 Register DESC1_6_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_29 0x2AD64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_29 0x190EAD64u //! Register Reset Value #define DESC1_6_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_29 Register DESC2_6_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_29 0x2AD68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_29 0x190EAD68u //! Register Reset Value #define DESC2_6_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_29 Register DESC3_6_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_29 0x2AD6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_29 0x190EAD6Cu //! Register Reset Value #define DESC3_6_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_29 Register DESC0_7_PON_EGP_29 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_29 0x2AD70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_29 0x190EAD70u //! Register Reset Value #define DESC0_7_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_29 Register DESC1_7_PON_EGP_29 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_29 0x2AD74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_29 0x190EAD74u //! Register Reset Value #define DESC1_7_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_29 Register DESC2_7_PON_EGP_29 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_29 0x2AD78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_29 0x190EAD78u //! Register Reset Value #define DESC2_7_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_29 Register DESC3_7_PON_EGP_29 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_29 0x2AD7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_29 0x190EAD7Cu //! Register Reset Value #define DESC3_7_PON_EGP_29_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_29_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_29_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_29 Register DESC0_0_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_29 0x2AE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_29 0x190EAE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_29 Register DESC1_0_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_29 0x2AE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_29 0x190EAE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_29 Register DESC2_0_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_29 0x2AE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_29 0x190EAE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_29 Register DESC3_0_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_29 0x2AE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_29 0x190EAE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_29 Register DESC0_1_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_29 0x2AE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_29 0x190EAE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_29 Register DESC1_1_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_29 0x2AE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_29 0x190EAE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_29 Register DESC2_1_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_29 0x2AE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_29 0x190EAE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_29 Register DESC3_1_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_29 0x2AE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_29 0x190EAE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_29 Register DESC0_2_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_29 0x2AE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_29 0x190EAE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_29 Register DESC1_2_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_29 0x2AE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_29 0x190EAE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_29 Register DESC2_2_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_29 0x2AE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_29 0x190EAE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_29 Register DESC3_2_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_29 0x2AE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_29 0x190EAE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_29 Register DESC0_3_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_29 0x2AE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_29 0x190EAE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_29 Register DESC1_3_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_29 0x2AE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_29 0x190EAE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_29 Register DESC2_3_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_29 0x2AE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_29 0x190EAE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_29 Register DESC3_3_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_29 0x2AE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_29 0x190EAE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_29 Register DESC0_4_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_29 0x2AE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_29 0x190EAE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_29 Register DESC1_4_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_29 0x2AE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_29 0x190EAE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_29 Register DESC2_4_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_29 0x2AE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_29 0x190EAE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_29 Register DESC3_4_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_29 0x2AE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_29 0x190EAE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_29 Register DESC0_5_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_29 0x2AE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_29 0x190EAE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_29 Register DESC1_5_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_29 0x2AE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_29 0x190EAE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_29 Register DESC2_5_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_29 0x2AE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_29 0x190EAE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_29 Register DESC3_5_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_29 0x2AE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_29 0x190EAE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_29 Register DESC0_6_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_29 0x2AE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_29 0x190EAE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_29 Register DESC1_6_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_29 0x2AE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_29 0x190EAE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_29 Register DESC2_6_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_29 0x2AE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_29 0x190EAE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_29 Register DESC3_6_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_29 0x2AE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_29 0x190EAE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_29 Register DESC0_7_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_29 0x2AE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_29 0x190EAE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_29 Register DESC1_7_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_29 0x2AE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_29 0x190EAE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_29 Register DESC2_7_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_29 0x2AE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_29 0x190EAE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_29_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_29 Register DESC3_7_PON_EGP_S_29 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_29 0x2AE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_29 0x190EAE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_29_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_29_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_29_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_29_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_29_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_30 Register CFG_PON_EGP_30 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_30 0x2B000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_30 0x190EB000u //! Register Reset Value #define CFG_PON_EGP_30_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_30_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_30_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_30_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_30_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_30_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_30_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_30_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_30_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_30_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_30_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_30 Register IRNCR_PON_EGP_30 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_30 0x2B020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_30 0x190EB020u //! Register Reset Value #define IRNCR_PON_EGP_30_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_30_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_30_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_30_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_30_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_30 Register IRNICR_PON_EGP_30 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_30 0x2B024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_30 0x190EB024u //! Register Reset Value #define IRNICR_PON_EGP_30_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_30_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_30_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_30 Register IRNEN_PON_EGP_30 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_30 0x2B028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_30 0x190EB028u //! Register Reset Value #define IRNEN_PON_EGP_30_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_30_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_30_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_30_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_30_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_30 Register DPTR_PON_EGP_30 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_30 0x2B030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_30 0x190EB030u //! Register Reset Value #define DPTR_PON_EGP_30_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_30_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_30_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_30_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_30_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_30_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_30_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_30_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_30_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_30 Register DESC0_0_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_30 0x2B100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_30 0x190EB100u //! Register Reset Value #define DESC0_0_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_30 Register DESC1_0_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_30 0x2B104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_30 0x190EB104u //! Register Reset Value #define DESC1_0_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_30 Register DESC2_0_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_30 0x2B108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_30 0x190EB108u //! Register Reset Value #define DESC2_0_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_30 Register DESC3_0_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_30 0x2B10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_30 0x190EB10Cu //! Register Reset Value #define DESC3_0_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_30 Register DESC0_1_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_30 0x2B110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_30 0x190EB110u //! Register Reset Value #define DESC0_1_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_30 Register DESC1_1_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_30 0x2B114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_30 0x190EB114u //! Register Reset Value #define DESC1_1_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_30 Register DESC2_1_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_30 0x2B118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_30 0x190EB118u //! Register Reset Value #define DESC2_1_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_30 Register DESC3_1_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_30 0x2B11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_30 0x190EB11Cu //! Register Reset Value #define DESC3_1_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_30 Register DESC0_2_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_30 0x2B120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_30 0x190EB120u //! Register Reset Value #define DESC0_2_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_30 Register DESC1_2_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_30 0x2B124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_30 0x190EB124u //! Register Reset Value #define DESC1_2_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_30 Register DESC2_2_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_30 0x2B128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_30 0x190EB128u //! Register Reset Value #define DESC2_2_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_30 Register DESC3_2_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_30 0x2B12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_30 0x190EB12Cu //! Register Reset Value #define DESC3_2_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_30 Register DESC0_3_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_30 0x2B130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_30 0x190EB130u //! Register Reset Value #define DESC0_3_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_30 Register DESC1_3_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_30 0x2B134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_30 0x190EB134u //! Register Reset Value #define DESC1_3_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_30 Register DESC2_3_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_30 0x2B138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_30 0x190EB138u //! Register Reset Value #define DESC2_3_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_30 Register DESC3_3_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_30 0x2B13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_30 0x190EB13Cu //! Register Reset Value #define DESC3_3_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_30 Register DESC0_4_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_30 0x2B140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_30 0x190EB140u //! Register Reset Value #define DESC0_4_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_30 Register DESC1_4_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_30 0x2B144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_30 0x190EB144u //! Register Reset Value #define DESC1_4_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_30 Register DESC2_4_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_30 0x2B148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_30 0x190EB148u //! Register Reset Value #define DESC2_4_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_30 Register DESC3_4_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_30 0x2B14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_30 0x190EB14Cu //! Register Reset Value #define DESC3_4_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_30 Register DESC0_5_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_30 0x2B150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_30 0x190EB150u //! Register Reset Value #define DESC0_5_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_30 Register DESC1_5_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_30 0x2B154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_30 0x190EB154u //! Register Reset Value #define DESC1_5_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_30 Register DESC2_5_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_30 0x2B158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_30 0x190EB158u //! Register Reset Value #define DESC2_5_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_30 Register DESC3_5_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_30 0x2B15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_30 0x190EB15Cu //! Register Reset Value #define DESC3_5_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_30 Register DESC0_6_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_30 0x2B160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_30 0x190EB160u //! Register Reset Value #define DESC0_6_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_30 Register DESC1_6_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_30 0x2B164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_30 0x190EB164u //! Register Reset Value #define DESC1_6_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_30 Register DESC2_6_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_30 0x2B168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_30 0x190EB168u //! Register Reset Value #define DESC2_6_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_30 Register DESC3_6_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_30 0x2B16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_30 0x190EB16Cu //! Register Reset Value #define DESC3_6_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_30 Register DESC0_7_PON_EGP_30 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_30 0x2B170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_30 0x190EB170u //! Register Reset Value #define DESC0_7_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_30 Register DESC1_7_PON_EGP_30 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_30 0x2B174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_30 0x190EB174u //! Register Reset Value #define DESC1_7_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_30 Register DESC2_7_PON_EGP_30 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_30 0x2B178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_30 0x190EB178u //! Register Reset Value #define DESC2_7_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_30 Register DESC3_7_PON_EGP_30 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_30 0x2B17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_30 0x190EB17Cu //! Register Reset Value #define DESC3_7_PON_EGP_30_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_30_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_30_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_30 Register DESC0_0_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_30 0x2B200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_30 0x190EB200u //! Register Reset Value #define DESC0_0_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_30 Register DESC1_0_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_30 0x2B204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_30 0x190EB204u //! Register Reset Value #define DESC1_0_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_30 Register DESC2_0_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_30 0x2B208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_30 0x190EB208u //! Register Reset Value #define DESC2_0_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_30 Register DESC3_0_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_30 0x2B20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_30 0x190EB20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_30 Register DESC0_1_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_30 0x2B210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_30 0x190EB210u //! Register Reset Value #define DESC0_1_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_30 Register DESC1_1_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_30 0x2B214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_30 0x190EB214u //! Register Reset Value #define DESC1_1_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_30 Register DESC2_1_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_30 0x2B218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_30 0x190EB218u //! Register Reset Value #define DESC2_1_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_30 Register DESC3_1_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_30 0x2B21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_30 0x190EB21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_30 Register DESC0_2_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_30 0x2B220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_30 0x190EB220u //! Register Reset Value #define DESC0_2_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_30 Register DESC1_2_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_30 0x2B224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_30 0x190EB224u //! Register Reset Value #define DESC1_2_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_30 Register DESC2_2_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_30 0x2B228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_30 0x190EB228u //! Register Reset Value #define DESC2_2_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_30 Register DESC3_2_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_30 0x2B22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_30 0x190EB22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_30 Register DESC0_3_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_30 0x2B230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_30 0x190EB230u //! Register Reset Value #define DESC0_3_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_30 Register DESC1_3_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_30 0x2B234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_30 0x190EB234u //! Register Reset Value #define DESC1_3_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_30 Register DESC2_3_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_30 0x2B238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_30 0x190EB238u //! Register Reset Value #define DESC2_3_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_30 Register DESC3_3_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_30 0x2B23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_30 0x190EB23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_30 Register DESC0_4_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_30 0x2B240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_30 0x190EB240u //! Register Reset Value #define DESC0_4_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_30 Register DESC1_4_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_30 0x2B244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_30 0x190EB244u //! Register Reset Value #define DESC1_4_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_30 Register DESC2_4_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_30 0x2B248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_30 0x190EB248u //! Register Reset Value #define DESC2_4_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_30 Register DESC3_4_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_30 0x2B24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_30 0x190EB24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_30 Register DESC0_5_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_30 0x2B250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_30 0x190EB250u //! Register Reset Value #define DESC0_5_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_30 Register DESC1_5_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_30 0x2B254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_30 0x190EB254u //! Register Reset Value #define DESC1_5_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_30 Register DESC2_5_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_30 0x2B258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_30 0x190EB258u //! Register Reset Value #define DESC2_5_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_30 Register DESC3_5_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_30 0x2B25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_30 0x190EB25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_30 Register DESC0_6_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_30 0x2B260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_30 0x190EB260u //! Register Reset Value #define DESC0_6_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_30 Register DESC1_6_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_30 0x2B264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_30 0x190EB264u //! Register Reset Value #define DESC1_6_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_30 Register DESC2_6_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_30 0x2B268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_30 0x190EB268u //! Register Reset Value #define DESC2_6_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_30 Register DESC3_6_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_30 0x2B26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_30 0x190EB26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_30 Register DESC0_7_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_30 0x2B270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_30 0x190EB270u //! Register Reset Value #define DESC0_7_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_30 Register DESC1_7_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_30 0x2B274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_30 0x190EB274u //! Register Reset Value #define DESC1_7_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_30 Register DESC2_7_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_30 0x2B278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_30 0x190EB278u //! Register Reset Value #define DESC2_7_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_30_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_30 Register DESC3_7_PON_EGP_S_30 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_30 0x2B27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_30 0x190EB27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_30_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_30_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_30_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_30_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_30_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_31 Register CFG_PON_EGP_31 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_31 0x2B400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_31 0x190EB400u //! Register Reset Value #define CFG_PON_EGP_31_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_31_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_31_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_31_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_31_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_31_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_31_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_31_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_31_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_31_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_31_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_31 Register IRNCR_PON_EGP_31 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_31 0x2B420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_31 0x190EB420u //! Register Reset Value #define IRNCR_PON_EGP_31_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_31_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_31_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_31_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_31_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_31 Register IRNICR_PON_EGP_31 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_31 0x2B424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_31 0x190EB424u //! Register Reset Value #define IRNICR_PON_EGP_31_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_31_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_31_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_31 Register IRNEN_PON_EGP_31 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_31 0x2B428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_31 0x190EB428u //! Register Reset Value #define IRNEN_PON_EGP_31_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_31_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_31_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_31_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_31_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_31 Register DPTR_PON_EGP_31 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_31 0x2B430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_31 0x190EB430u //! Register Reset Value #define DPTR_PON_EGP_31_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_31_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_31_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_31_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_31_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_31_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_31_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_31_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_31_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_31 Register DESC0_0_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_31 0x2B500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_31 0x190EB500u //! Register Reset Value #define DESC0_0_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_31 Register DESC1_0_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_31 0x2B504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_31 0x190EB504u //! Register Reset Value #define DESC1_0_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_31 Register DESC2_0_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_31 0x2B508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_31 0x190EB508u //! Register Reset Value #define DESC2_0_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_31 Register DESC3_0_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_31 0x2B50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_31 0x190EB50Cu //! Register Reset Value #define DESC3_0_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_31 Register DESC0_1_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_31 0x2B510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_31 0x190EB510u //! Register Reset Value #define DESC0_1_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_31 Register DESC1_1_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_31 0x2B514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_31 0x190EB514u //! Register Reset Value #define DESC1_1_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_31 Register DESC2_1_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_31 0x2B518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_31 0x190EB518u //! Register Reset Value #define DESC2_1_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_31 Register DESC3_1_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_31 0x2B51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_31 0x190EB51Cu //! Register Reset Value #define DESC3_1_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_31 Register DESC0_2_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_31 0x2B520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_31 0x190EB520u //! Register Reset Value #define DESC0_2_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_31 Register DESC1_2_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_31 0x2B524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_31 0x190EB524u //! Register Reset Value #define DESC1_2_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_31 Register DESC2_2_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_31 0x2B528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_31 0x190EB528u //! Register Reset Value #define DESC2_2_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_31 Register DESC3_2_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_31 0x2B52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_31 0x190EB52Cu //! Register Reset Value #define DESC3_2_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_31 Register DESC0_3_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_31 0x2B530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_31 0x190EB530u //! Register Reset Value #define DESC0_3_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_31 Register DESC1_3_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_31 0x2B534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_31 0x190EB534u //! Register Reset Value #define DESC1_3_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_31 Register DESC2_3_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_31 0x2B538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_31 0x190EB538u //! Register Reset Value #define DESC2_3_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_31 Register DESC3_3_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_31 0x2B53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_31 0x190EB53Cu //! Register Reset Value #define DESC3_3_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_31 Register DESC0_4_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_31 0x2B540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_31 0x190EB540u //! Register Reset Value #define DESC0_4_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_31 Register DESC1_4_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_31 0x2B544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_31 0x190EB544u //! Register Reset Value #define DESC1_4_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_31 Register DESC2_4_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_31 0x2B548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_31 0x190EB548u //! Register Reset Value #define DESC2_4_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_31 Register DESC3_4_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_31 0x2B54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_31 0x190EB54Cu //! Register Reset Value #define DESC3_4_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_31 Register DESC0_5_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_31 0x2B550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_31 0x190EB550u //! Register Reset Value #define DESC0_5_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_31 Register DESC1_5_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_31 0x2B554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_31 0x190EB554u //! Register Reset Value #define DESC1_5_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_31 Register DESC2_5_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_31 0x2B558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_31 0x190EB558u //! Register Reset Value #define DESC2_5_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_31 Register DESC3_5_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_31 0x2B55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_31 0x190EB55Cu //! Register Reset Value #define DESC3_5_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_31 Register DESC0_6_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_31 0x2B560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_31 0x190EB560u //! Register Reset Value #define DESC0_6_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_31 Register DESC1_6_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_31 0x2B564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_31 0x190EB564u //! Register Reset Value #define DESC1_6_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_31 Register DESC2_6_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_31 0x2B568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_31 0x190EB568u //! Register Reset Value #define DESC2_6_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_31 Register DESC3_6_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_31 0x2B56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_31 0x190EB56Cu //! Register Reset Value #define DESC3_6_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_31 Register DESC0_7_PON_EGP_31 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_31 0x2B570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_31 0x190EB570u //! Register Reset Value #define DESC0_7_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_31 Register DESC1_7_PON_EGP_31 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_31 0x2B574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_31 0x190EB574u //! Register Reset Value #define DESC1_7_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_31 Register DESC2_7_PON_EGP_31 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_31 0x2B578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_31 0x190EB578u //! Register Reset Value #define DESC2_7_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_31 Register DESC3_7_PON_EGP_31 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_31 0x2B57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_31 0x190EB57Cu //! Register Reset Value #define DESC3_7_PON_EGP_31_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_31_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_31_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_31 Register DESC0_0_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_31 0x2B600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_31 0x190EB600u //! Register Reset Value #define DESC0_0_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_31 Register DESC1_0_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_31 0x2B604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_31 0x190EB604u //! Register Reset Value #define DESC1_0_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_31 Register DESC2_0_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_31 0x2B608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_31 0x190EB608u //! Register Reset Value #define DESC2_0_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_31 Register DESC3_0_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_31 0x2B60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_31 0x190EB60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_31 Register DESC0_1_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_31 0x2B610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_31 0x190EB610u //! Register Reset Value #define DESC0_1_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_31 Register DESC1_1_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_31 0x2B614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_31 0x190EB614u //! Register Reset Value #define DESC1_1_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_31 Register DESC2_1_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_31 0x2B618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_31 0x190EB618u //! Register Reset Value #define DESC2_1_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_31 Register DESC3_1_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_31 0x2B61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_31 0x190EB61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_31 Register DESC0_2_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_31 0x2B620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_31 0x190EB620u //! Register Reset Value #define DESC0_2_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_31 Register DESC1_2_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_31 0x2B624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_31 0x190EB624u //! Register Reset Value #define DESC1_2_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_31 Register DESC2_2_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_31 0x2B628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_31 0x190EB628u //! Register Reset Value #define DESC2_2_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_31 Register DESC3_2_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_31 0x2B62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_31 0x190EB62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_31 Register DESC0_3_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_31 0x2B630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_31 0x190EB630u //! Register Reset Value #define DESC0_3_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_31 Register DESC1_3_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_31 0x2B634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_31 0x190EB634u //! Register Reset Value #define DESC1_3_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_31 Register DESC2_3_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_31 0x2B638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_31 0x190EB638u //! Register Reset Value #define DESC2_3_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_31 Register DESC3_3_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_31 0x2B63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_31 0x190EB63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_31 Register DESC0_4_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_31 0x2B640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_31 0x190EB640u //! Register Reset Value #define DESC0_4_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_31 Register DESC1_4_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_31 0x2B644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_31 0x190EB644u //! Register Reset Value #define DESC1_4_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_31 Register DESC2_4_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_31 0x2B648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_31 0x190EB648u //! Register Reset Value #define DESC2_4_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_31 Register DESC3_4_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_31 0x2B64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_31 0x190EB64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_31 Register DESC0_5_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_31 0x2B650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_31 0x190EB650u //! Register Reset Value #define DESC0_5_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_31 Register DESC1_5_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_31 0x2B654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_31 0x190EB654u //! Register Reset Value #define DESC1_5_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_31 Register DESC2_5_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_31 0x2B658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_31 0x190EB658u //! Register Reset Value #define DESC2_5_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_31 Register DESC3_5_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_31 0x2B65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_31 0x190EB65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_31 Register DESC0_6_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_31 0x2B660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_31 0x190EB660u //! Register Reset Value #define DESC0_6_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_31 Register DESC1_6_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_31 0x2B664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_31 0x190EB664u //! Register Reset Value #define DESC1_6_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_31 Register DESC2_6_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_31 0x2B668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_31 0x190EB668u //! Register Reset Value #define DESC2_6_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_31 Register DESC3_6_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_31 0x2B66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_31 0x190EB66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_31 Register DESC0_7_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_31 0x2B670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_31 0x190EB670u //! Register Reset Value #define DESC0_7_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_31 Register DESC1_7_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_31 0x2B674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_31 0x190EB674u //! Register Reset Value #define DESC1_7_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_31 Register DESC2_7_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_31 0x2B678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_31 0x190EB678u //! Register Reset Value #define DESC2_7_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_31_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_31 Register DESC3_7_PON_EGP_S_31 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_31 0x2B67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_31 0x190EB67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_31_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_31_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_31_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_31_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_31_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_32 Register CFG_PON_EGP_32 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_32 0x2B800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_32 0x190EB800u //! Register Reset Value #define CFG_PON_EGP_32_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_32_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_32_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_32_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_32_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_32_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_32_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_32_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_32_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_32_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_32_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_32 Register IRNCR_PON_EGP_32 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_32 0x2B820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_32 0x190EB820u //! Register Reset Value #define IRNCR_PON_EGP_32_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_32_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_32_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_32_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_32_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_32 Register IRNICR_PON_EGP_32 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_32 0x2B824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_32 0x190EB824u //! Register Reset Value #define IRNICR_PON_EGP_32_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_32_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_32_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_32 Register IRNEN_PON_EGP_32 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_32 0x2B828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_32 0x190EB828u //! Register Reset Value #define IRNEN_PON_EGP_32_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_32_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_32_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_32_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_32_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_32 Register DPTR_PON_EGP_32 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_32 0x2B830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_32 0x190EB830u //! Register Reset Value #define DPTR_PON_EGP_32_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_32_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_32_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_32_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_32_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_32_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_32_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_32_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_32_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_32 Register DESC0_0_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_32 0x2B900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_32 0x190EB900u //! Register Reset Value #define DESC0_0_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_32 Register DESC1_0_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_32 0x2B904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_32 0x190EB904u //! Register Reset Value #define DESC1_0_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_32 Register DESC2_0_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_32 0x2B908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_32 0x190EB908u //! Register Reset Value #define DESC2_0_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_32 Register DESC3_0_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_32 0x2B90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_32 0x190EB90Cu //! Register Reset Value #define DESC3_0_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_32 Register DESC0_1_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_32 0x2B910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_32 0x190EB910u //! Register Reset Value #define DESC0_1_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_32 Register DESC1_1_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_32 0x2B914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_32 0x190EB914u //! Register Reset Value #define DESC1_1_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_32 Register DESC2_1_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_32 0x2B918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_32 0x190EB918u //! Register Reset Value #define DESC2_1_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_32 Register DESC3_1_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_32 0x2B91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_32 0x190EB91Cu //! Register Reset Value #define DESC3_1_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_32 Register DESC0_2_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_32 0x2B920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_32 0x190EB920u //! Register Reset Value #define DESC0_2_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_32 Register DESC1_2_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_32 0x2B924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_32 0x190EB924u //! Register Reset Value #define DESC1_2_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_32 Register DESC2_2_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_32 0x2B928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_32 0x190EB928u //! Register Reset Value #define DESC2_2_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_32 Register DESC3_2_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_32 0x2B92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_32 0x190EB92Cu //! Register Reset Value #define DESC3_2_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_32 Register DESC0_3_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_32 0x2B930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_32 0x190EB930u //! Register Reset Value #define DESC0_3_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_32 Register DESC1_3_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_32 0x2B934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_32 0x190EB934u //! Register Reset Value #define DESC1_3_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_32 Register DESC2_3_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_32 0x2B938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_32 0x190EB938u //! Register Reset Value #define DESC2_3_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_32 Register DESC3_3_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_32 0x2B93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_32 0x190EB93Cu //! Register Reset Value #define DESC3_3_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_32 Register DESC0_4_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_32 0x2B940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_32 0x190EB940u //! Register Reset Value #define DESC0_4_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_32 Register DESC1_4_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_32 0x2B944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_32 0x190EB944u //! Register Reset Value #define DESC1_4_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_32 Register DESC2_4_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_32 0x2B948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_32 0x190EB948u //! Register Reset Value #define DESC2_4_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_32 Register DESC3_4_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_32 0x2B94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_32 0x190EB94Cu //! Register Reset Value #define DESC3_4_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_32 Register DESC0_5_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_32 0x2B950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_32 0x190EB950u //! Register Reset Value #define DESC0_5_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_32 Register DESC1_5_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_32 0x2B954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_32 0x190EB954u //! Register Reset Value #define DESC1_5_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_32 Register DESC2_5_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_32 0x2B958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_32 0x190EB958u //! Register Reset Value #define DESC2_5_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_32 Register DESC3_5_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_32 0x2B95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_32 0x190EB95Cu //! Register Reset Value #define DESC3_5_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_32 Register DESC0_6_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_32 0x2B960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_32 0x190EB960u //! Register Reset Value #define DESC0_6_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_32 Register DESC1_6_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_32 0x2B964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_32 0x190EB964u //! Register Reset Value #define DESC1_6_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_32 Register DESC2_6_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_32 0x2B968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_32 0x190EB968u //! Register Reset Value #define DESC2_6_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_32 Register DESC3_6_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_32 0x2B96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_32 0x190EB96Cu //! Register Reset Value #define DESC3_6_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_32 Register DESC0_7_PON_EGP_32 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_32 0x2B970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_32 0x190EB970u //! Register Reset Value #define DESC0_7_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_32 Register DESC1_7_PON_EGP_32 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_32 0x2B974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_32 0x190EB974u //! Register Reset Value #define DESC1_7_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_32 Register DESC2_7_PON_EGP_32 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_32 0x2B978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_32 0x190EB978u //! Register Reset Value #define DESC2_7_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_32 Register DESC3_7_PON_EGP_32 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_32 0x2B97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_32 0x190EB97Cu //! Register Reset Value #define DESC3_7_PON_EGP_32_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_32_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_32_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_32 Register DESC0_0_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_32 0x2BA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_32 0x190EBA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_32 Register DESC1_0_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_32 0x2BA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_32 0x190EBA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_32 Register DESC2_0_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_32 0x2BA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_32 0x190EBA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_32 Register DESC3_0_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_32 0x2BA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_32 0x190EBA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_32 Register DESC0_1_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_32 0x2BA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_32 0x190EBA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_32 Register DESC1_1_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_32 0x2BA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_32 0x190EBA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_32 Register DESC2_1_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_32 0x2BA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_32 0x190EBA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_32 Register DESC3_1_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_32 0x2BA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_32 0x190EBA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_32 Register DESC0_2_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_32 0x2BA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_32 0x190EBA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_32 Register DESC1_2_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_32 0x2BA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_32 0x190EBA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_32 Register DESC2_2_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_32 0x2BA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_32 0x190EBA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_32 Register DESC3_2_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_32 0x2BA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_32 0x190EBA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_32 Register DESC0_3_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_32 0x2BA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_32 0x190EBA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_32 Register DESC1_3_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_32 0x2BA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_32 0x190EBA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_32 Register DESC2_3_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_32 0x2BA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_32 0x190EBA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_32 Register DESC3_3_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_32 0x2BA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_32 0x190EBA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_32 Register DESC0_4_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_32 0x2BA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_32 0x190EBA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_32 Register DESC1_4_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_32 0x2BA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_32 0x190EBA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_32 Register DESC2_4_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_32 0x2BA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_32 0x190EBA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_32 Register DESC3_4_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_32 0x2BA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_32 0x190EBA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_32 Register DESC0_5_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_32 0x2BA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_32 0x190EBA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_32 Register DESC1_5_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_32 0x2BA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_32 0x190EBA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_32 Register DESC2_5_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_32 0x2BA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_32 0x190EBA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_32 Register DESC3_5_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_32 0x2BA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_32 0x190EBA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_32 Register DESC0_6_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_32 0x2BA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_32 0x190EBA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_32 Register DESC1_6_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_32 0x2BA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_32 0x190EBA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_32 Register DESC2_6_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_32 0x2BA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_32 0x190EBA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_32 Register DESC3_6_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_32 0x2BA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_32 0x190EBA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_32 Register DESC0_7_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_32 0x2BA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_32 0x190EBA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_32 Register DESC1_7_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_32 0x2BA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_32 0x190EBA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_32 Register DESC2_7_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_32 0x2BA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_32 0x190EBA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_32_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_32 Register DESC3_7_PON_EGP_S_32 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_32 0x2BA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_32 0x190EBA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_32_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_32_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_32_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_32_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_32_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_33 Register CFG_PON_EGP_33 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_33 0x2BC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_33 0x190EBC00u //! Register Reset Value #define CFG_PON_EGP_33_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_33_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_33_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_33_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_33_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_33_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_33_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_33_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_33_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_33_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_33_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_33 Register IRNCR_PON_EGP_33 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_33 0x2BC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_33 0x190EBC20u //! Register Reset Value #define IRNCR_PON_EGP_33_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_33_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_33_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_33_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_33_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_33 Register IRNICR_PON_EGP_33 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_33 0x2BC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_33 0x190EBC24u //! Register Reset Value #define IRNICR_PON_EGP_33_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_33_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_33_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_33 Register IRNEN_PON_EGP_33 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_33 0x2BC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_33 0x190EBC28u //! Register Reset Value #define IRNEN_PON_EGP_33_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_33_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_33_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_33_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_33_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_33 Register DPTR_PON_EGP_33 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_33 0x2BC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_33 0x190EBC30u //! Register Reset Value #define DPTR_PON_EGP_33_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_33_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_33_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_33_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_33_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_33_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_33_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_33_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_33_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_33 Register DESC0_0_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_33 0x2BD00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_33 0x190EBD00u //! Register Reset Value #define DESC0_0_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_33 Register DESC1_0_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_33 0x2BD04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_33 0x190EBD04u //! Register Reset Value #define DESC1_0_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_33 Register DESC2_0_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_33 0x2BD08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_33 0x190EBD08u //! Register Reset Value #define DESC2_0_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_33 Register DESC3_0_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_33 0x2BD0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_33 0x190EBD0Cu //! Register Reset Value #define DESC3_0_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_33 Register DESC0_1_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_33 0x2BD10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_33 0x190EBD10u //! Register Reset Value #define DESC0_1_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_33 Register DESC1_1_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_33 0x2BD14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_33 0x190EBD14u //! Register Reset Value #define DESC1_1_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_33 Register DESC2_1_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_33 0x2BD18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_33 0x190EBD18u //! Register Reset Value #define DESC2_1_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_33 Register DESC3_1_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_33 0x2BD1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_33 0x190EBD1Cu //! Register Reset Value #define DESC3_1_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_33 Register DESC0_2_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_33 0x2BD20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_33 0x190EBD20u //! Register Reset Value #define DESC0_2_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_33 Register DESC1_2_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_33 0x2BD24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_33 0x190EBD24u //! Register Reset Value #define DESC1_2_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_33 Register DESC2_2_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_33 0x2BD28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_33 0x190EBD28u //! Register Reset Value #define DESC2_2_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_33 Register DESC3_2_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_33 0x2BD2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_33 0x190EBD2Cu //! Register Reset Value #define DESC3_2_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_33 Register DESC0_3_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_33 0x2BD30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_33 0x190EBD30u //! Register Reset Value #define DESC0_3_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_33 Register DESC1_3_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_33 0x2BD34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_33 0x190EBD34u //! Register Reset Value #define DESC1_3_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_33 Register DESC2_3_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_33 0x2BD38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_33 0x190EBD38u //! Register Reset Value #define DESC2_3_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_33 Register DESC3_3_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_33 0x2BD3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_33 0x190EBD3Cu //! Register Reset Value #define DESC3_3_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_33 Register DESC0_4_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_33 0x2BD40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_33 0x190EBD40u //! Register Reset Value #define DESC0_4_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_33 Register DESC1_4_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_33 0x2BD44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_33 0x190EBD44u //! Register Reset Value #define DESC1_4_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_33 Register DESC2_4_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_33 0x2BD48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_33 0x190EBD48u //! Register Reset Value #define DESC2_4_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_33 Register DESC3_4_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_33 0x2BD4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_33 0x190EBD4Cu //! Register Reset Value #define DESC3_4_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_33 Register DESC0_5_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_33 0x2BD50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_33 0x190EBD50u //! Register Reset Value #define DESC0_5_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_33 Register DESC1_5_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_33 0x2BD54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_33 0x190EBD54u //! Register Reset Value #define DESC1_5_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_33 Register DESC2_5_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_33 0x2BD58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_33 0x190EBD58u //! Register Reset Value #define DESC2_5_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_33 Register DESC3_5_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_33 0x2BD5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_33 0x190EBD5Cu //! Register Reset Value #define DESC3_5_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_33 Register DESC0_6_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_33 0x2BD60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_33 0x190EBD60u //! Register Reset Value #define DESC0_6_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_33 Register DESC1_6_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_33 0x2BD64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_33 0x190EBD64u //! Register Reset Value #define DESC1_6_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_33 Register DESC2_6_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_33 0x2BD68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_33 0x190EBD68u //! Register Reset Value #define DESC2_6_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_33 Register DESC3_6_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_33 0x2BD6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_33 0x190EBD6Cu //! Register Reset Value #define DESC3_6_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_33 Register DESC0_7_PON_EGP_33 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_33 0x2BD70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_33 0x190EBD70u //! Register Reset Value #define DESC0_7_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_33 Register DESC1_7_PON_EGP_33 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_33 0x2BD74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_33 0x190EBD74u //! Register Reset Value #define DESC1_7_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_33 Register DESC2_7_PON_EGP_33 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_33 0x2BD78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_33 0x190EBD78u //! Register Reset Value #define DESC2_7_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_33 Register DESC3_7_PON_EGP_33 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_33 0x2BD7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_33 0x190EBD7Cu //! Register Reset Value #define DESC3_7_PON_EGP_33_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_33_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_33_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_33 Register DESC0_0_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_33 0x2BE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_33 0x190EBE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_33 Register DESC1_0_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_33 0x2BE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_33 0x190EBE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_33 Register DESC2_0_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_33 0x2BE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_33 0x190EBE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_33 Register DESC3_0_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_33 0x2BE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_33 0x190EBE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_33 Register DESC0_1_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_33 0x2BE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_33 0x190EBE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_33 Register DESC1_1_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_33 0x2BE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_33 0x190EBE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_33 Register DESC2_1_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_33 0x2BE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_33 0x190EBE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_33 Register DESC3_1_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_33 0x2BE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_33 0x190EBE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_33 Register DESC0_2_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_33 0x2BE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_33 0x190EBE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_33 Register DESC1_2_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_33 0x2BE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_33 0x190EBE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_33 Register DESC2_2_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_33 0x2BE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_33 0x190EBE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_33 Register DESC3_2_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_33 0x2BE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_33 0x190EBE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_33 Register DESC0_3_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_33 0x2BE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_33 0x190EBE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_33 Register DESC1_3_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_33 0x2BE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_33 0x190EBE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_33 Register DESC2_3_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_33 0x2BE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_33 0x190EBE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_33 Register DESC3_3_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_33 0x2BE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_33 0x190EBE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_33 Register DESC0_4_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_33 0x2BE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_33 0x190EBE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_33 Register DESC1_4_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_33 0x2BE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_33 0x190EBE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_33 Register DESC2_4_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_33 0x2BE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_33 0x190EBE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_33 Register DESC3_4_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_33 0x2BE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_33 0x190EBE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_33 Register DESC0_5_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_33 0x2BE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_33 0x190EBE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_33 Register DESC1_5_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_33 0x2BE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_33 0x190EBE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_33 Register DESC2_5_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_33 0x2BE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_33 0x190EBE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_33 Register DESC3_5_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_33 0x2BE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_33 0x190EBE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_33 Register DESC0_6_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_33 0x2BE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_33 0x190EBE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_33 Register DESC1_6_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_33 0x2BE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_33 0x190EBE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_33 Register DESC2_6_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_33 0x2BE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_33 0x190EBE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_33 Register DESC3_6_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_33 0x2BE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_33 0x190EBE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_33 Register DESC0_7_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_33 0x2BE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_33 0x190EBE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_33 Register DESC1_7_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_33 0x2BE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_33 0x190EBE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_33 Register DESC2_7_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_33 0x2BE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_33 0x190EBE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_33_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_33 Register DESC3_7_PON_EGP_S_33 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_33 0x2BE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_33 0x190EBE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_33_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_33_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_33_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_33_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_33_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_34 Register CFG_PON_EGP_34 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_34 0x2C000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_34 0x190EC000u //! Register Reset Value #define CFG_PON_EGP_34_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_34_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_34_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_34_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_34_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_34_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_34_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_34_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_34_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_34_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_34_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_34 Register IRNCR_PON_EGP_34 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_34 0x2C020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_34 0x190EC020u //! Register Reset Value #define IRNCR_PON_EGP_34_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_34_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_34_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_34_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_34_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_34 Register IRNICR_PON_EGP_34 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_34 0x2C024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_34 0x190EC024u //! Register Reset Value #define IRNICR_PON_EGP_34_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_34_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_34_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_34 Register IRNEN_PON_EGP_34 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_34 0x2C028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_34 0x190EC028u //! Register Reset Value #define IRNEN_PON_EGP_34_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_34_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_34_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_34_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_34_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_34 Register DPTR_PON_EGP_34 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_34 0x2C030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_34 0x190EC030u //! Register Reset Value #define DPTR_PON_EGP_34_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_34_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_34_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_34_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_34_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_34_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_34_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_34_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_34_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_34 Register DESC0_0_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_34 0x2C100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_34 0x190EC100u //! Register Reset Value #define DESC0_0_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_34 Register DESC1_0_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_34 0x2C104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_34 0x190EC104u //! Register Reset Value #define DESC1_0_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_34 Register DESC2_0_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_34 0x2C108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_34 0x190EC108u //! Register Reset Value #define DESC2_0_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_34 Register DESC3_0_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_34 0x2C10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_34 0x190EC10Cu //! Register Reset Value #define DESC3_0_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_34 Register DESC0_1_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_34 0x2C110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_34 0x190EC110u //! Register Reset Value #define DESC0_1_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_34 Register DESC1_1_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_34 0x2C114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_34 0x190EC114u //! Register Reset Value #define DESC1_1_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_34 Register DESC2_1_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_34 0x2C118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_34 0x190EC118u //! Register Reset Value #define DESC2_1_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_34 Register DESC3_1_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_34 0x2C11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_34 0x190EC11Cu //! Register Reset Value #define DESC3_1_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_34 Register DESC0_2_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_34 0x2C120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_34 0x190EC120u //! Register Reset Value #define DESC0_2_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_34 Register DESC1_2_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_34 0x2C124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_34 0x190EC124u //! Register Reset Value #define DESC1_2_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_34 Register DESC2_2_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_34 0x2C128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_34 0x190EC128u //! Register Reset Value #define DESC2_2_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_34 Register DESC3_2_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_34 0x2C12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_34 0x190EC12Cu //! Register Reset Value #define DESC3_2_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_34 Register DESC0_3_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_34 0x2C130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_34 0x190EC130u //! Register Reset Value #define DESC0_3_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_34 Register DESC1_3_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_34 0x2C134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_34 0x190EC134u //! Register Reset Value #define DESC1_3_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_34 Register DESC2_3_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_34 0x2C138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_34 0x190EC138u //! Register Reset Value #define DESC2_3_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_34 Register DESC3_3_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_34 0x2C13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_34 0x190EC13Cu //! Register Reset Value #define DESC3_3_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_34 Register DESC0_4_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_34 0x2C140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_34 0x190EC140u //! Register Reset Value #define DESC0_4_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_34 Register DESC1_4_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_34 0x2C144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_34 0x190EC144u //! Register Reset Value #define DESC1_4_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_34 Register DESC2_4_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_34 0x2C148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_34 0x190EC148u //! Register Reset Value #define DESC2_4_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_34 Register DESC3_4_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_34 0x2C14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_34 0x190EC14Cu //! Register Reset Value #define DESC3_4_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_34 Register DESC0_5_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_34 0x2C150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_34 0x190EC150u //! Register Reset Value #define DESC0_5_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_34 Register DESC1_5_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_34 0x2C154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_34 0x190EC154u //! Register Reset Value #define DESC1_5_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_34 Register DESC2_5_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_34 0x2C158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_34 0x190EC158u //! Register Reset Value #define DESC2_5_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_34 Register DESC3_5_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_34 0x2C15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_34 0x190EC15Cu //! Register Reset Value #define DESC3_5_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_34 Register DESC0_6_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_34 0x2C160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_34 0x190EC160u //! Register Reset Value #define DESC0_6_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_34 Register DESC1_6_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_34 0x2C164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_34 0x190EC164u //! Register Reset Value #define DESC1_6_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_34 Register DESC2_6_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_34 0x2C168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_34 0x190EC168u //! Register Reset Value #define DESC2_6_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_34 Register DESC3_6_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_34 0x2C16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_34 0x190EC16Cu //! Register Reset Value #define DESC3_6_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_34 Register DESC0_7_PON_EGP_34 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_34 0x2C170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_34 0x190EC170u //! Register Reset Value #define DESC0_7_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_34 Register DESC1_7_PON_EGP_34 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_34 0x2C174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_34 0x190EC174u //! Register Reset Value #define DESC1_7_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_34 Register DESC2_7_PON_EGP_34 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_34 0x2C178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_34 0x190EC178u //! Register Reset Value #define DESC2_7_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_34 Register DESC3_7_PON_EGP_34 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_34 0x2C17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_34 0x190EC17Cu //! Register Reset Value #define DESC3_7_PON_EGP_34_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_34_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_34_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_34 Register DESC0_0_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_34 0x2C200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_34 0x190EC200u //! Register Reset Value #define DESC0_0_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_34 Register DESC1_0_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_34 0x2C204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_34 0x190EC204u //! Register Reset Value #define DESC1_0_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_34 Register DESC2_0_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_34 0x2C208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_34 0x190EC208u //! Register Reset Value #define DESC2_0_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_34 Register DESC3_0_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_34 0x2C20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_34 0x190EC20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_34 Register DESC0_1_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_34 0x2C210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_34 0x190EC210u //! Register Reset Value #define DESC0_1_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_34 Register DESC1_1_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_34 0x2C214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_34 0x190EC214u //! Register Reset Value #define DESC1_1_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_34 Register DESC2_1_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_34 0x2C218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_34 0x190EC218u //! Register Reset Value #define DESC2_1_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_34 Register DESC3_1_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_34 0x2C21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_34 0x190EC21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_34 Register DESC0_2_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_34 0x2C220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_34 0x190EC220u //! Register Reset Value #define DESC0_2_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_34 Register DESC1_2_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_34 0x2C224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_34 0x190EC224u //! Register Reset Value #define DESC1_2_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_34 Register DESC2_2_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_34 0x2C228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_34 0x190EC228u //! Register Reset Value #define DESC2_2_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_34 Register DESC3_2_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_34 0x2C22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_34 0x190EC22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_34 Register DESC0_3_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_34 0x2C230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_34 0x190EC230u //! Register Reset Value #define DESC0_3_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_34 Register DESC1_3_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_34 0x2C234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_34 0x190EC234u //! Register Reset Value #define DESC1_3_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_34 Register DESC2_3_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_34 0x2C238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_34 0x190EC238u //! Register Reset Value #define DESC2_3_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_34 Register DESC3_3_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_34 0x2C23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_34 0x190EC23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_34 Register DESC0_4_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_34 0x2C240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_34 0x190EC240u //! Register Reset Value #define DESC0_4_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_34 Register DESC1_4_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_34 0x2C244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_34 0x190EC244u //! Register Reset Value #define DESC1_4_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_34 Register DESC2_4_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_34 0x2C248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_34 0x190EC248u //! Register Reset Value #define DESC2_4_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_34 Register DESC3_4_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_34 0x2C24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_34 0x190EC24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_34 Register DESC0_5_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_34 0x2C250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_34 0x190EC250u //! Register Reset Value #define DESC0_5_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_34 Register DESC1_5_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_34 0x2C254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_34 0x190EC254u //! Register Reset Value #define DESC1_5_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_34 Register DESC2_5_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_34 0x2C258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_34 0x190EC258u //! Register Reset Value #define DESC2_5_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_34 Register DESC3_5_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_34 0x2C25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_34 0x190EC25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_34 Register DESC0_6_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_34 0x2C260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_34 0x190EC260u //! Register Reset Value #define DESC0_6_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_34 Register DESC1_6_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_34 0x2C264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_34 0x190EC264u //! Register Reset Value #define DESC1_6_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_34 Register DESC2_6_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_34 0x2C268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_34 0x190EC268u //! Register Reset Value #define DESC2_6_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_34 Register DESC3_6_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_34 0x2C26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_34 0x190EC26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_34 Register DESC0_7_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_34 0x2C270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_34 0x190EC270u //! Register Reset Value #define DESC0_7_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_34 Register DESC1_7_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_34 0x2C274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_34 0x190EC274u //! Register Reset Value #define DESC1_7_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_34 Register DESC2_7_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_34 0x2C278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_34 0x190EC278u //! Register Reset Value #define DESC2_7_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_34_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_34 Register DESC3_7_PON_EGP_S_34 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_34 0x2C27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_34 0x190EC27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_34_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_34_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_34_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_34_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_34_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_35 Register CFG_PON_EGP_35 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_35 0x2C400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_35 0x190EC400u //! Register Reset Value #define CFG_PON_EGP_35_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_35_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_35_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_35_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_35_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_35_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_35_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_35_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_35_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_35_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_35_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_35 Register IRNCR_PON_EGP_35 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_35 0x2C420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_35 0x190EC420u //! Register Reset Value #define IRNCR_PON_EGP_35_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_35_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_35_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_35_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_35_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_35 Register IRNICR_PON_EGP_35 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_35 0x2C424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_35 0x190EC424u //! Register Reset Value #define IRNICR_PON_EGP_35_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_35_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_35_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_35 Register IRNEN_PON_EGP_35 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_35 0x2C428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_35 0x190EC428u //! Register Reset Value #define IRNEN_PON_EGP_35_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_35_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_35_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_35_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_35_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_35 Register DPTR_PON_EGP_35 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_35 0x2C430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_35 0x190EC430u //! Register Reset Value #define DPTR_PON_EGP_35_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_35_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_35_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_35_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_35_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_35_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_35_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_35_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_35_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_35 Register DESC0_0_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_35 0x2C500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_35 0x190EC500u //! Register Reset Value #define DESC0_0_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_35 Register DESC1_0_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_35 0x2C504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_35 0x190EC504u //! Register Reset Value #define DESC1_0_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_35 Register DESC2_0_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_35 0x2C508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_35 0x190EC508u //! Register Reset Value #define DESC2_0_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_35 Register DESC3_0_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_35 0x2C50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_35 0x190EC50Cu //! Register Reset Value #define DESC3_0_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_35 Register DESC0_1_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_35 0x2C510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_35 0x190EC510u //! Register Reset Value #define DESC0_1_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_35 Register DESC1_1_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_35 0x2C514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_35 0x190EC514u //! Register Reset Value #define DESC1_1_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_35 Register DESC2_1_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_35 0x2C518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_35 0x190EC518u //! Register Reset Value #define DESC2_1_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_35 Register DESC3_1_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_35 0x2C51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_35 0x190EC51Cu //! Register Reset Value #define DESC3_1_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_35 Register DESC0_2_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_35 0x2C520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_35 0x190EC520u //! Register Reset Value #define DESC0_2_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_35 Register DESC1_2_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_35 0x2C524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_35 0x190EC524u //! Register Reset Value #define DESC1_2_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_35 Register DESC2_2_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_35 0x2C528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_35 0x190EC528u //! Register Reset Value #define DESC2_2_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_35 Register DESC3_2_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_35 0x2C52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_35 0x190EC52Cu //! Register Reset Value #define DESC3_2_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_35 Register DESC0_3_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_35 0x2C530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_35 0x190EC530u //! Register Reset Value #define DESC0_3_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_35 Register DESC1_3_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_35 0x2C534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_35 0x190EC534u //! Register Reset Value #define DESC1_3_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_35 Register DESC2_3_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_35 0x2C538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_35 0x190EC538u //! Register Reset Value #define DESC2_3_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_35 Register DESC3_3_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_35 0x2C53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_35 0x190EC53Cu //! Register Reset Value #define DESC3_3_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_35 Register DESC0_4_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_35 0x2C540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_35 0x190EC540u //! Register Reset Value #define DESC0_4_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_35 Register DESC1_4_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_35 0x2C544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_35 0x190EC544u //! Register Reset Value #define DESC1_4_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_35 Register DESC2_4_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_35 0x2C548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_35 0x190EC548u //! Register Reset Value #define DESC2_4_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_35 Register DESC3_4_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_35 0x2C54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_35 0x190EC54Cu //! Register Reset Value #define DESC3_4_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_35 Register DESC0_5_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_35 0x2C550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_35 0x190EC550u //! Register Reset Value #define DESC0_5_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_35 Register DESC1_5_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_35 0x2C554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_35 0x190EC554u //! Register Reset Value #define DESC1_5_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_35 Register DESC2_5_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_35 0x2C558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_35 0x190EC558u //! Register Reset Value #define DESC2_5_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_35 Register DESC3_5_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_35 0x2C55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_35 0x190EC55Cu //! Register Reset Value #define DESC3_5_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_35 Register DESC0_6_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_35 0x2C560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_35 0x190EC560u //! Register Reset Value #define DESC0_6_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_35 Register DESC1_6_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_35 0x2C564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_35 0x190EC564u //! Register Reset Value #define DESC1_6_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_35 Register DESC2_6_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_35 0x2C568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_35 0x190EC568u //! Register Reset Value #define DESC2_6_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_35 Register DESC3_6_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_35 0x2C56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_35 0x190EC56Cu //! Register Reset Value #define DESC3_6_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_35 Register DESC0_7_PON_EGP_35 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_35 0x2C570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_35 0x190EC570u //! Register Reset Value #define DESC0_7_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_35 Register DESC1_7_PON_EGP_35 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_35 0x2C574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_35 0x190EC574u //! Register Reset Value #define DESC1_7_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_35 Register DESC2_7_PON_EGP_35 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_35 0x2C578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_35 0x190EC578u //! Register Reset Value #define DESC2_7_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_35 Register DESC3_7_PON_EGP_35 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_35 0x2C57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_35 0x190EC57Cu //! Register Reset Value #define DESC3_7_PON_EGP_35_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_35_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_35_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_35 Register DESC0_0_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_35 0x2C600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_35 0x190EC600u //! Register Reset Value #define DESC0_0_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_35 Register DESC1_0_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_35 0x2C604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_35 0x190EC604u //! Register Reset Value #define DESC1_0_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_35 Register DESC2_0_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_35 0x2C608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_35 0x190EC608u //! Register Reset Value #define DESC2_0_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_35 Register DESC3_0_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_35 0x2C60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_35 0x190EC60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_35 Register DESC0_1_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_35 0x2C610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_35 0x190EC610u //! Register Reset Value #define DESC0_1_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_35 Register DESC1_1_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_35 0x2C614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_35 0x190EC614u //! Register Reset Value #define DESC1_1_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_35 Register DESC2_1_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_35 0x2C618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_35 0x190EC618u //! Register Reset Value #define DESC2_1_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_35 Register DESC3_1_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_35 0x2C61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_35 0x190EC61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_35 Register DESC0_2_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_35 0x2C620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_35 0x190EC620u //! Register Reset Value #define DESC0_2_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_35 Register DESC1_2_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_35 0x2C624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_35 0x190EC624u //! Register Reset Value #define DESC1_2_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_35 Register DESC2_2_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_35 0x2C628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_35 0x190EC628u //! Register Reset Value #define DESC2_2_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_35 Register DESC3_2_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_35 0x2C62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_35 0x190EC62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_35 Register DESC0_3_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_35 0x2C630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_35 0x190EC630u //! Register Reset Value #define DESC0_3_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_35 Register DESC1_3_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_35 0x2C634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_35 0x190EC634u //! Register Reset Value #define DESC1_3_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_35 Register DESC2_3_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_35 0x2C638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_35 0x190EC638u //! Register Reset Value #define DESC2_3_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_35 Register DESC3_3_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_35 0x2C63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_35 0x190EC63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_35 Register DESC0_4_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_35 0x2C640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_35 0x190EC640u //! Register Reset Value #define DESC0_4_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_35 Register DESC1_4_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_35 0x2C644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_35 0x190EC644u //! Register Reset Value #define DESC1_4_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_35 Register DESC2_4_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_35 0x2C648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_35 0x190EC648u //! Register Reset Value #define DESC2_4_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_35 Register DESC3_4_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_35 0x2C64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_35 0x190EC64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_35 Register DESC0_5_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_35 0x2C650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_35 0x190EC650u //! Register Reset Value #define DESC0_5_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_35 Register DESC1_5_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_35 0x2C654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_35 0x190EC654u //! Register Reset Value #define DESC1_5_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_35 Register DESC2_5_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_35 0x2C658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_35 0x190EC658u //! Register Reset Value #define DESC2_5_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_35 Register DESC3_5_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_35 0x2C65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_35 0x190EC65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_35 Register DESC0_6_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_35 0x2C660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_35 0x190EC660u //! Register Reset Value #define DESC0_6_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_35 Register DESC1_6_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_35 0x2C664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_35 0x190EC664u //! Register Reset Value #define DESC1_6_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_35 Register DESC2_6_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_35 0x2C668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_35 0x190EC668u //! Register Reset Value #define DESC2_6_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_35 Register DESC3_6_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_35 0x2C66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_35 0x190EC66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_35 Register DESC0_7_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_35 0x2C670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_35 0x190EC670u //! Register Reset Value #define DESC0_7_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_35 Register DESC1_7_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_35 0x2C674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_35 0x190EC674u //! Register Reset Value #define DESC1_7_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_35 Register DESC2_7_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_35 0x2C678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_35 0x190EC678u //! Register Reset Value #define DESC2_7_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_35_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_35 Register DESC3_7_PON_EGP_S_35 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_35 0x2C67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_35 0x190EC67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_35_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_35_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_35_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_35_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_35_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_36 Register CFG_PON_EGP_36 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_36 0x2C800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_36 0x190EC800u //! Register Reset Value #define CFG_PON_EGP_36_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_36_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_36_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_36_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_36_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_36_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_36_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_36_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_36_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_36_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_36_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_36 Register IRNCR_PON_EGP_36 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_36 0x2C820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_36 0x190EC820u //! Register Reset Value #define IRNCR_PON_EGP_36_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_36_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_36_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_36_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_36_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_36 Register IRNICR_PON_EGP_36 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_36 0x2C824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_36 0x190EC824u //! Register Reset Value #define IRNICR_PON_EGP_36_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_36_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_36_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_36 Register IRNEN_PON_EGP_36 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_36 0x2C828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_36 0x190EC828u //! Register Reset Value #define IRNEN_PON_EGP_36_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_36_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_36_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_36_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_36_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_36 Register DPTR_PON_EGP_36 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_36 0x2C830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_36 0x190EC830u //! Register Reset Value #define DPTR_PON_EGP_36_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_36_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_36_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_36_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_36_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_36_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_36_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_36_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_36_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_36 Register DESC0_0_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_36 0x2C900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_36 0x190EC900u //! Register Reset Value #define DESC0_0_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_36 Register DESC1_0_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_36 0x2C904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_36 0x190EC904u //! Register Reset Value #define DESC1_0_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_36 Register DESC2_0_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_36 0x2C908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_36 0x190EC908u //! Register Reset Value #define DESC2_0_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_36 Register DESC3_0_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_36 0x2C90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_36 0x190EC90Cu //! Register Reset Value #define DESC3_0_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_36 Register DESC0_1_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_36 0x2C910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_36 0x190EC910u //! Register Reset Value #define DESC0_1_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_36 Register DESC1_1_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_36 0x2C914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_36 0x190EC914u //! Register Reset Value #define DESC1_1_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_36 Register DESC2_1_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_36 0x2C918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_36 0x190EC918u //! Register Reset Value #define DESC2_1_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_36 Register DESC3_1_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_36 0x2C91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_36 0x190EC91Cu //! Register Reset Value #define DESC3_1_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_36 Register DESC0_2_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_36 0x2C920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_36 0x190EC920u //! Register Reset Value #define DESC0_2_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_36 Register DESC1_2_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_36 0x2C924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_36 0x190EC924u //! Register Reset Value #define DESC1_2_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_36 Register DESC2_2_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_36 0x2C928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_36 0x190EC928u //! Register Reset Value #define DESC2_2_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_36 Register DESC3_2_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_36 0x2C92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_36 0x190EC92Cu //! Register Reset Value #define DESC3_2_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_36 Register DESC0_3_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_36 0x2C930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_36 0x190EC930u //! Register Reset Value #define DESC0_3_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_36 Register DESC1_3_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_36 0x2C934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_36 0x190EC934u //! Register Reset Value #define DESC1_3_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_36 Register DESC2_3_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_36 0x2C938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_36 0x190EC938u //! Register Reset Value #define DESC2_3_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_36 Register DESC3_3_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_36 0x2C93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_36 0x190EC93Cu //! Register Reset Value #define DESC3_3_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_36 Register DESC0_4_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_36 0x2C940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_36 0x190EC940u //! Register Reset Value #define DESC0_4_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_36 Register DESC1_4_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_36 0x2C944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_36 0x190EC944u //! Register Reset Value #define DESC1_4_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_36 Register DESC2_4_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_36 0x2C948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_36 0x190EC948u //! Register Reset Value #define DESC2_4_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_36 Register DESC3_4_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_36 0x2C94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_36 0x190EC94Cu //! Register Reset Value #define DESC3_4_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_36 Register DESC0_5_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_36 0x2C950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_36 0x190EC950u //! Register Reset Value #define DESC0_5_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_36 Register DESC1_5_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_36 0x2C954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_36 0x190EC954u //! Register Reset Value #define DESC1_5_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_36 Register DESC2_5_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_36 0x2C958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_36 0x190EC958u //! Register Reset Value #define DESC2_5_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_36 Register DESC3_5_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_36 0x2C95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_36 0x190EC95Cu //! Register Reset Value #define DESC3_5_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_36 Register DESC0_6_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_36 0x2C960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_36 0x190EC960u //! Register Reset Value #define DESC0_6_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_36 Register DESC1_6_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_36 0x2C964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_36 0x190EC964u //! Register Reset Value #define DESC1_6_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_36 Register DESC2_6_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_36 0x2C968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_36 0x190EC968u //! Register Reset Value #define DESC2_6_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_36 Register DESC3_6_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_36 0x2C96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_36 0x190EC96Cu //! Register Reset Value #define DESC3_6_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_36 Register DESC0_7_PON_EGP_36 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_36 0x2C970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_36 0x190EC970u //! Register Reset Value #define DESC0_7_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_36 Register DESC1_7_PON_EGP_36 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_36 0x2C974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_36 0x190EC974u //! Register Reset Value #define DESC1_7_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_36 Register DESC2_7_PON_EGP_36 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_36 0x2C978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_36 0x190EC978u //! Register Reset Value #define DESC2_7_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_36 Register DESC3_7_PON_EGP_36 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_36 0x2C97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_36 0x190EC97Cu //! Register Reset Value #define DESC3_7_PON_EGP_36_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_36_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_36_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_36 Register DESC0_0_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_36 0x2CA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_36 0x190ECA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_36 Register DESC1_0_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_36 0x2CA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_36 0x190ECA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_36 Register DESC2_0_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_36 0x2CA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_36 0x190ECA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_36 Register DESC3_0_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_36 0x2CA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_36 0x190ECA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_36 Register DESC0_1_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_36 0x2CA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_36 0x190ECA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_36 Register DESC1_1_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_36 0x2CA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_36 0x190ECA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_36 Register DESC2_1_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_36 0x2CA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_36 0x190ECA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_36 Register DESC3_1_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_36 0x2CA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_36 0x190ECA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_36 Register DESC0_2_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_36 0x2CA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_36 0x190ECA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_36 Register DESC1_2_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_36 0x2CA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_36 0x190ECA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_36 Register DESC2_2_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_36 0x2CA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_36 0x190ECA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_36 Register DESC3_2_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_36 0x2CA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_36 0x190ECA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_36 Register DESC0_3_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_36 0x2CA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_36 0x190ECA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_36 Register DESC1_3_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_36 0x2CA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_36 0x190ECA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_36 Register DESC2_3_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_36 0x2CA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_36 0x190ECA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_36 Register DESC3_3_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_36 0x2CA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_36 0x190ECA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_36 Register DESC0_4_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_36 0x2CA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_36 0x190ECA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_36 Register DESC1_4_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_36 0x2CA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_36 0x190ECA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_36 Register DESC2_4_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_36 0x2CA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_36 0x190ECA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_36 Register DESC3_4_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_36 0x2CA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_36 0x190ECA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_36 Register DESC0_5_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_36 0x2CA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_36 0x190ECA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_36 Register DESC1_5_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_36 0x2CA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_36 0x190ECA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_36 Register DESC2_5_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_36 0x2CA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_36 0x190ECA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_36 Register DESC3_5_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_36 0x2CA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_36 0x190ECA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_36 Register DESC0_6_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_36 0x2CA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_36 0x190ECA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_36 Register DESC1_6_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_36 0x2CA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_36 0x190ECA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_36 Register DESC2_6_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_36 0x2CA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_36 0x190ECA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_36 Register DESC3_6_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_36 0x2CA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_36 0x190ECA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_36 Register DESC0_7_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_36 0x2CA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_36 0x190ECA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_36 Register DESC1_7_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_36 0x2CA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_36 0x190ECA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_36 Register DESC2_7_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_36 0x2CA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_36 0x190ECA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_36_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_36 Register DESC3_7_PON_EGP_S_36 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_36 0x2CA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_36 0x190ECA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_36_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_36_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_36_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_36_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_36_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_37 Register CFG_PON_EGP_37 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_37 0x2CC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_37 0x190ECC00u //! Register Reset Value #define CFG_PON_EGP_37_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_37_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_37_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_37_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_37_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_37_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_37_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_37_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_37_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_37_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_37_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_37 Register IRNCR_PON_EGP_37 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_37 0x2CC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_37 0x190ECC20u //! Register Reset Value #define IRNCR_PON_EGP_37_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_37_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_37_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_37_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_37_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_37 Register IRNICR_PON_EGP_37 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_37 0x2CC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_37 0x190ECC24u //! Register Reset Value #define IRNICR_PON_EGP_37_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_37_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_37_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_37 Register IRNEN_PON_EGP_37 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_37 0x2CC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_37 0x190ECC28u //! Register Reset Value #define IRNEN_PON_EGP_37_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_37_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_37_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_37_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_37_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_37 Register DPTR_PON_EGP_37 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_37 0x2CC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_37 0x190ECC30u //! Register Reset Value #define DPTR_PON_EGP_37_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_37_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_37_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_37_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_37_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_37_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_37_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_37_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_37_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_37 Register DESC0_0_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_37 0x2CD00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_37 0x190ECD00u //! Register Reset Value #define DESC0_0_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_37 Register DESC1_0_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_37 0x2CD04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_37 0x190ECD04u //! Register Reset Value #define DESC1_0_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_37 Register DESC2_0_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_37 0x2CD08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_37 0x190ECD08u //! Register Reset Value #define DESC2_0_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_37 Register DESC3_0_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_37 0x2CD0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_37 0x190ECD0Cu //! Register Reset Value #define DESC3_0_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_37 Register DESC0_1_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_37 0x2CD10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_37 0x190ECD10u //! Register Reset Value #define DESC0_1_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_37 Register DESC1_1_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_37 0x2CD14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_37 0x190ECD14u //! Register Reset Value #define DESC1_1_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_37 Register DESC2_1_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_37 0x2CD18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_37 0x190ECD18u //! Register Reset Value #define DESC2_1_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_37 Register DESC3_1_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_37 0x2CD1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_37 0x190ECD1Cu //! Register Reset Value #define DESC3_1_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_37 Register DESC0_2_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_37 0x2CD20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_37 0x190ECD20u //! Register Reset Value #define DESC0_2_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_37 Register DESC1_2_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_37 0x2CD24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_37 0x190ECD24u //! Register Reset Value #define DESC1_2_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_37 Register DESC2_2_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_37 0x2CD28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_37 0x190ECD28u //! Register Reset Value #define DESC2_2_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_37 Register DESC3_2_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_37 0x2CD2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_37 0x190ECD2Cu //! Register Reset Value #define DESC3_2_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_37 Register DESC0_3_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_37 0x2CD30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_37 0x190ECD30u //! Register Reset Value #define DESC0_3_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_37 Register DESC1_3_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_37 0x2CD34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_37 0x190ECD34u //! Register Reset Value #define DESC1_3_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_37 Register DESC2_3_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_37 0x2CD38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_37 0x190ECD38u //! Register Reset Value #define DESC2_3_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_37 Register DESC3_3_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_37 0x2CD3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_37 0x190ECD3Cu //! Register Reset Value #define DESC3_3_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_37 Register DESC0_4_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_37 0x2CD40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_37 0x190ECD40u //! Register Reset Value #define DESC0_4_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_37 Register DESC1_4_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_37 0x2CD44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_37 0x190ECD44u //! Register Reset Value #define DESC1_4_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_37 Register DESC2_4_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_37 0x2CD48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_37 0x190ECD48u //! Register Reset Value #define DESC2_4_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_37 Register DESC3_4_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_37 0x2CD4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_37 0x190ECD4Cu //! Register Reset Value #define DESC3_4_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_37 Register DESC0_5_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_37 0x2CD50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_37 0x190ECD50u //! Register Reset Value #define DESC0_5_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_37 Register DESC1_5_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_37 0x2CD54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_37 0x190ECD54u //! Register Reset Value #define DESC1_5_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_37 Register DESC2_5_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_37 0x2CD58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_37 0x190ECD58u //! Register Reset Value #define DESC2_5_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_37 Register DESC3_5_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_37 0x2CD5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_37 0x190ECD5Cu //! Register Reset Value #define DESC3_5_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_37 Register DESC0_6_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_37 0x2CD60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_37 0x190ECD60u //! Register Reset Value #define DESC0_6_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_37 Register DESC1_6_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_37 0x2CD64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_37 0x190ECD64u //! Register Reset Value #define DESC1_6_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_37 Register DESC2_6_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_37 0x2CD68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_37 0x190ECD68u //! Register Reset Value #define DESC2_6_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_37 Register DESC3_6_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_37 0x2CD6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_37 0x190ECD6Cu //! Register Reset Value #define DESC3_6_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_37 Register DESC0_7_PON_EGP_37 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_37 0x2CD70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_37 0x190ECD70u //! Register Reset Value #define DESC0_7_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_37 Register DESC1_7_PON_EGP_37 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_37 0x2CD74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_37 0x190ECD74u //! Register Reset Value #define DESC1_7_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_37 Register DESC2_7_PON_EGP_37 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_37 0x2CD78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_37 0x190ECD78u //! Register Reset Value #define DESC2_7_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_37 Register DESC3_7_PON_EGP_37 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_37 0x2CD7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_37 0x190ECD7Cu //! Register Reset Value #define DESC3_7_PON_EGP_37_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_37_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_37_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_37 Register DESC0_0_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_37 0x2CE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_37 0x190ECE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_37 Register DESC1_0_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_37 0x2CE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_37 0x190ECE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_37 Register DESC2_0_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_37 0x2CE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_37 0x190ECE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_37 Register DESC3_0_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_37 0x2CE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_37 0x190ECE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_37 Register DESC0_1_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_37 0x2CE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_37 0x190ECE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_37 Register DESC1_1_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_37 0x2CE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_37 0x190ECE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_37 Register DESC2_1_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_37 0x2CE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_37 0x190ECE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_37 Register DESC3_1_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_37 0x2CE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_37 0x190ECE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_37 Register DESC0_2_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_37 0x2CE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_37 0x190ECE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_37 Register DESC1_2_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_37 0x2CE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_37 0x190ECE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_37 Register DESC2_2_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_37 0x2CE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_37 0x190ECE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_37 Register DESC3_2_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_37 0x2CE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_37 0x190ECE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_37 Register DESC0_3_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_37 0x2CE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_37 0x190ECE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_37 Register DESC1_3_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_37 0x2CE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_37 0x190ECE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_37 Register DESC2_3_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_37 0x2CE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_37 0x190ECE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_37 Register DESC3_3_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_37 0x2CE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_37 0x190ECE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_37 Register DESC0_4_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_37 0x2CE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_37 0x190ECE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_37 Register DESC1_4_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_37 0x2CE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_37 0x190ECE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_37 Register DESC2_4_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_37 0x2CE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_37 0x190ECE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_37 Register DESC3_4_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_37 0x2CE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_37 0x190ECE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_37 Register DESC0_5_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_37 0x2CE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_37 0x190ECE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_37 Register DESC1_5_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_37 0x2CE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_37 0x190ECE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_37 Register DESC2_5_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_37 0x2CE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_37 0x190ECE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_37 Register DESC3_5_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_37 0x2CE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_37 0x190ECE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_37 Register DESC0_6_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_37 0x2CE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_37 0x190ECE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_37 Register DESC1_6_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_37 0x2CE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_37 0x190ECE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_37 Register DESC2_6_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_37 0x2CE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_37 0x190ECE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_37 Register DESC3_6_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_37 0x2CE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_37 0x190ECE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_37 Register DESC0_7_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_37 0x2CE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_37 0x190ECE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_37 Register DESC1_7_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_37 0x2CE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_37 0x190ECE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_37 Register DESC2_7_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_37 0x2CE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_37 0x190ECE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_37_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_37 Register DESC3_7_PON_EGP_S_37 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_37 0x2CE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_37 0x190ECE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_37_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_37_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_37_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_37_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_37_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_38 Register CFG_PON_EGP_38 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_38 0x2D000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_38 0x190ED000u //! Register Reset Value #define CFG_PON_EGP_38_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_38_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_38_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_38_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_38_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_38_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_38_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_38_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_38_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_38_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_38_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_38 Register IRNCR_PON_EGP_38 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_38 0x2D020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_38 0x190ED020u //! Register Reset Value #define IRNCR_PON_EGP_38_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_38_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_38_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_38_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_38_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_38 Register IRNICR_PON_EGP_38 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_38 0x2D024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_38 0x190ED024u //! Register Reset Value #define IRNICR_PON_EGP_38_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_38_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_38_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_38 Register IRNEN_PON_EGP_38 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_38 0x2D028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_38 0x190ED028u //! Register Reset Value #define IRNEN_PON_EGP_38_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_38_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_38_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_38_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_38_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_38 Register DPTR_PON_EGP_38 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_38 0x2D030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_38 0x190ED030u //! Register Reset Value #define DPTR_PON_EGP_38_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_38_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_38_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_38_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_38_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_38_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_38_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_38_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_38_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_38 Register DESC0_0_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_38 0x2D100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_38 0x190ED100u //! Register Reset Value #define DESC0_0_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_38 Register DESC1_0_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_38 0x2D104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_38 0x190ED104u //! Register Reset Value #define DESC1_0_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_38 Register DESC2_0_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_38 0x2D108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_38 0x190ED108u //! Register Reset Value #define DESC2_0_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_38 Register DESC3_0_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_38 0x2D10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_38 0x190ED10Cu //! Register Reset Value #define DESC3_0_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_38 Register DESC0_1_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_38 0x2D110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_38 0x190ED110u //! Register Reset Value #define DESC0_1_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_38 Register DESC1_1_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_38 0x2D114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_38 0x190ED114u //! Register Reset Value #define DESC1_1_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_38 Register DESC2_1_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_38 0x2D118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_38 0x190ED118u //! Register Reset Value #define DESC2_1_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_38 Register DESC3_1_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_38 0x2D11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_38 0x190ED11Cu //! Register Reset Value #define DESC3_1_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_38 Register DESC0_2_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_38 0x2D120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_38 0x190ED120u //! Register Reset Value #define DESC0_2_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_38 Register DESC1_2_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_38 0x2D124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_38 0x190ED124u //! Register Reset Value #define DESC1_2_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_38 Register DESC2_2_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_38 0x2D128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_38 0x190ED128u //! Register Reset Value #define DESC2_2_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_38 Register DESC3_2_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_38 0x2D12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_38 0x190ED12Cu //! Register Reset Value #define DESC3_2_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_38 Register DESC0_3_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_38 0x2D130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_38 0x190ED130u //! Register Reset Value #define DESC0_3_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_38 Register DESC1_3_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_38 0x2D134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_38 0x190ED134u //! Register Reset Value #define DESC1_3_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_38 Register DESC2_3_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_38 0x2D138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_38 0x190ED138u //! Register Reset Value #define DESC2_3_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_38 Register DESC3_3_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_38 0x2D13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_38 0x190ED13Cu //! Register Reset Value #define DESC3_3_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_38 Register DESC0_4_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_38 0x2D140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_38 0x190ED140u //! Register Reset Value #define DESC0_4_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_38 Register DESC1_4_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_38 0x2D144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_38 0x190ED144u //! Register Reset Value #define DESC1_4_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_38 Register DESC2_4_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_38 0x2D148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_38 0x190ED148u //! Register Reset Value #define DESC2_4_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_38 Register DESC3_4_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_38 0x2D14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_38 0x190ED14Cu //! Register Reset Value #define DESC3_4_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_38 Register DESC0_5_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_38 0x2D150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_38 0x190ED150u //! Register Reset Value #define DESC0_5_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_38 Register DESC1_5_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_38 0x2D154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_38 0x190ED154u //! Register Reset Value #define DESC1_5_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_38 Register DESC2_5_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_38 0x2D158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_38 0x190ED158u //! Register Reset Value #define DESC2_5_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_38 Register DESC3_5_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_38 0x2D15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_38 0x190ED15Cu //! Register Reset Value #define DESC3_5_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_38 Register DESC0_6_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_38 0x2D160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_38 0x190ED160u //! Register Reset Value #define DESC0_6_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_38 Register DESC1_6_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_38 0x2D164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_38 0x190ED164u //! Register Reset Value #define DESC1_6_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_38 Register DESC2_6_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_38 0x2D168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_38 0x190ED168u //! Register Reset Value #define DESC2_6_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_38 Register DESC3_6_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_38 0x2D16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_38 0x190ED16Cu //! Register Reset Value #define DESC3_6_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_38 Register DESC0_7_PON_EGP_38 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_38 0x2D170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_38 0x190ED170u //! Register Reset Value #define DESC0_7_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_38 Register DESC1_7_PON_EGP_38 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_38 0x2D174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_38 0x190ED174u //! Register Reset Value #define DESC1_7_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_38 Register DESC2_7_PON_EGP_38 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_38 0x2D178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_38 0x190ED178u //! Register Reset Value #define DESC2_7_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_38 Register DESC3_7_PON_EGP_38 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_38 0x2D17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_38 0x190ED17Cu //! Register Reset Value #define DESC3_7_PON_EGP_38_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_38_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_38_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_38 Register DESC0_0_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_38 0x2D200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_38 0x190ED200u //! Register Reset Value #define DESC0_0_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_38 Register DESC1_0_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_38 0x2D204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_38 0x190ED204u //! Register Reset Value #define DESC1_0_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_38 Register DESC2_0_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_38 0x2D208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_38 0x190ED208u //! Register Reset Value #define DESC2_0_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_38 Register DESC3_0_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_38 0x2D20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_38 0x190ED20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_38 Register DESC0_1_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_38 0x2D210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_38 0x190ED210u //! Register Reset Value #define DESC0_1_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_38 Register DESC1_1_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_38 0x2D214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_38 0x190ED214u //! Register Reset Value #define DESC1_1_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_38 Register DESC2_1_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_38 0x2D218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_38 0x190ED218u //! Register Reset Value #define DESC2_1_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_38 Register DESC3_1_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_38 0x2D21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_38 0x190ED21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_38 Register DESC0_2_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_38 0x2D220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_38 0x190ED220u //! Register Reset Value #define DESC0_2_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_38 Register DESC1_2_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_38 0x2D224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_38 0x190ED224u //! Register Reset Value #define DESC1_2_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_38 Register DESC2_2_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_38 0x2D228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_38 0x190ED228u //! Register Reset Value #define DESC2_2_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_38 Register DESC3_2_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_38 0x2D22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_38 0x190ED22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_38 Register DESC0_3_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_38 0x2D230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_38 0x190ED230u //! Register Reset Value #define DESC0_3_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_38 Register DESC1_3_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_38 0x2D234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_38 0x190ED234u //! Register Reset Value #define DESC1_3_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_38 Register DESC2_3_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_38 0x2D238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_38 0x190ED238u //! Register Reset Value #define DESC2_3_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_38 Register DESC3_3_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_38 0x2D23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_38 0x190ED23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_38 Register DESC0_4_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_38 0x2D240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_38 0x190ED240u //! Register Reset Value #define DESC0_4_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_38 Register DESC1_4_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_38 0x2D244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_38 0x190ED244u //! Register Reset Value #define DESC1_4_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_38 Register DESC2_4_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_38 0x2D248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_38 0x190ED248u //! Register Reset Value #define DESC2_4_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_38 Register DESC3_4_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_38 0x2D24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_38 0x190ED24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_38 Register DESC0_5_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_38 0x2D250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_38 0x190ED250u //! Register Reset Value #define DESC0_5_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_38 Register DESC1_5_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_38 0x2D254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_38 0x190ED254u //! Register Reset Value #define DESC1_5_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_38 Register DESC2_5_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_38 0x2D258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_38 0x190ED258u //! Register Reset Value #define DESC2_5_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_38 Register DESC3_5_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_38 0x2D25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_38 0x190ED25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_38 Register DESC0_6_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_38 0x2D260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_38 0x190ED260u //! Register Reset Value #define DESC0_6_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_38 Register DESC1_6_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_38 0x2D264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_38 0x190ED264u //! Register Reset Value #define DESC1_6_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_38 Register DESC2_6_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_38 0x2D268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_38 0x190ED268u //! Register Reset Value #define DESC2_6_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_38 Register DESC3_6_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_38 0x2D26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_38 0x190ED26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_38 Register DESC0_7_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_38 0x2D270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_38 0x190ED270u //! Register Reset Value #define DESC0_7_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_38 Register DESC1_7_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_38 0x2D274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_38 0x190ED274u //! Register Reset Value #define DESC1_7_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_38 Register DESC2_7_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_38 0x2D278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_38 0x190ED278u //! Register Reset Value #define DESC2_7_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_38_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_38 Register DESC3_7_PON_EGP_S_38 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_38 0x2D27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_38 0x190ED27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_38_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_38_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_38_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_38_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_38_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_39 Register CFG_PON_EGP_39 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_39 0x2D400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_39 0x190ED400u //! Register Reset Value #define CFG_PON_EGP_39_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_39_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_39_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_39_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_39_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_39_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_39_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_39_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_39_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_39_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_39_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_39 Register IRNCR_PON_EGP_39 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_39 0x2D420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_39 0x190ED420u //! Register Reset Value #define IRNCR_PON_EGP_39_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_39_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_39_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_39_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_39_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_39 Register IRNICR_PON_EGP_39 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_39 0x2D424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_39 0x190ED424u //! Register Reset Value #define IRNICR_PON_EGP_39_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_39_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_39_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_39 Register IRNEN_PON_EGP_39 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_39 0x2D428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_39 0x190ED428u //! Register Reset Value #define IRNEN_PON_EGP_39_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_39_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_39_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_39_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_39_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_39 Register DPTR_PON_EGP_39 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_39 0x2D430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_39 0x190ED430u //! Register Reset Value #define DPTR_PON_EGP_39_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_39_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_39_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_39_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_39_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_39_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_39_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_39_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_39_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_39 Register DESC0_0_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_39 0x2D500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_39 0x190ED500u //! Register Reset Value #define DESC0_0_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_39 Register DESC1_0_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_39 0x2D504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_39 0x190ED504u //! Register Reset Value #define DESC1_0_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_39 Register DESC2_0_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_39 0x2D508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_39 0x190ED508u //! Register Reset Value #define DESC2_0_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_39 Register DESC3_0_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_39 0x2D50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_39 0x190ED50Cu //! Register Reset Value #define DESC3_0_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_39 Register DESC0_1_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_39 0x2D510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_39 0x190ED510u //! Register Reset Value #define DESC0_1_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_39 Register DESC1_1_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_39 0x2D514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_39 0x190ED514u //! Register Reset Value #define DESC1_1_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_39 Register DESC2_1_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_39 0x2D518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_39 0x190ED518u //! Register Reset Value #define DESC2_1_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_39 Register DESC3_1_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_39 0x2D51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_39 0x190ED51Cu //! Register Reset Value #define DESC3_1_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_39 Register DESC0_2_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_39 0x2D520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_39 0x190ED520u //! Register Reset Value #define DESC0_2_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_39 Register DESC1_2_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_39 0x2D524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_39 0x190ED524u //! Register Reset Value #define DESC1_2_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_39 Register DESC2_2_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_39 0x2D528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_39 0x190ED528u //! Register Reset Value #define DESC2_2_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_39 Register DESC3_2_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_39 0x2D52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_39 0x190ED52Cu //! Register Reset Value #define DESC3_2_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_39 Register DESC0_3_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_39 0x2D530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_39 0x190ED530u //! Register Reset Value #define DESC0_3_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_39 Register DESC1_3_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_39 0x2D534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_39 0x190ED534u //! Register Reset Value #define DESC1_3_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_39 Register DESC2_3_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_39 0x2D538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_39 0x190ED538u //! Register Reset Value #define DESC2_3_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_39 Register DESC3_3_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_39 0x2D53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_39 0x190ED53Cu //! Register Reset Value #define DESC3_3_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_39 Register DESC0_4_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_39 0x2D540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_39 0x190ED540u //! Register Reset Value #define DESC0_4_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_39 Register DESC1_4_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_39 0x2D544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_39 0x190ED544u //! Register Reset Value #define DESC1_4_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_39 Register DESC2_4_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_39 0x2D548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_39 0x190ED548u //! Register Reset Value #define DESC2_4_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_39 Register DESC3_4_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_39 0x2D54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_39 0x190ED54Cu //! Register Reset Value #define DESC3_4_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_39 Register DESC0_5_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_39 0x2D550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_39 0x190ED550u //! Register Reset Value #define DESC0_5_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_39 Register DESC1_5_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_39 0x2D554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_39 0x190ED554u //! Register Reset Value #define DESC1_5_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_39 Register DESC2_5_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_39 0x2D558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_39 0x190ED558u //! Register Reset Value #define DESC2_5_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_39 Register DESC3_5_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_39 0x2D55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_39 0x190ED55Cu //! Register Reset Value #define DESC3_5_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_39 Register DESC0_6_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_39 0x2D560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_39 0x190ED560u //! Register Reset Value #define DESC0_6_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_39 Register DESC1_6_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_39 0x2D564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_39 0x190ED564u //! Register Reset Value #define DESC1_6_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_39 Register DESC2_6_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_39 0x2D568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_39 0x190ED568u //! Register Reset Value #define DESC2_6_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_39 Register DESC3_6_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_39 0x2D56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_39 0x190ED56Cu //! Register Reset Value #define DESC3_6_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_39 Register DESC0_7_PON_EGP_39 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_39 0x2D570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_39 0x190ED570u //! Register Reset Value #define DESC0_7_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_39 Register DESC1_7_PON_EGP_39 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_39 0x2D574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_39 0x190ED574u //! Register Reset Value #define DESC1_7_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_39 Register DESC2_7_PON_EGP_39 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_39 0x2D578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_39 0x190ED578u //! Register Reset Value #define DESC2_7_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_39 Register DESC3_7_PON_EGP_39 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_39 0x2D57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_39 0x190ED57Cu //! Register Reset Value #define DESC3_7_PON_EGP_39_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_39_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_39_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_39 Register DESC0_0_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_39 0x2D600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_39 0x190ED600u //! Register Reset Value #define DESC0_0_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_39 Register DESC1_0_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_39 0x2D604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_39 0x190ED604u //! Register Reset Value #define DESC1_0_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_39 Register DESC2_0_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_39 0x2D608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_39 0x190ED608u //! Register Reset Value #define DESC2_0_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_39 Register DESC3_0_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_39 0x2D60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_39 0x190ED60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_39 Register DESC0_1_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_39 0x2D610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_39 0x190ED610u //! Register Reset Value #define DESC0_1_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_39 Register DESC1_1_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_39 0x2D614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_39 0x190ED614u //! Register Reset Value #define DESC1_1_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_39 Register DESC2_1_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_39 0x2D618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_39 0x190ED618u //! Register Reset Value #define DESC2_1_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_39 Register DESC3_1_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_39 0x2D61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_39 0x190ED61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_39 Register DESC0_2_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_39 0x2D620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_39 0x190ED620u //! Register Reset Value #define DESC0_2_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_39 Register DESC1_2_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_39 0x2D624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_39 0x190ED624u //! Register Reset Value #define DESC1_2_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_39 Register DESC2_2_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_39 0x2D628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_39 0x190ED628u //! Register Reset Value #define DESC2_2_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_39 Register DESC3_2_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_39 0x2D62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_39 0x190ED62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_39 Register DESC0_3_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_39 0x2D630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_39 0x190ED630u //! Register Reset Value #define DESC0_3_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_39 Register DESC1_3_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_39 0x2D634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_39 0x190ED634u //! Register Reset Value #define DESC1_3_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_39 Register DESC2_3_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_39 0x2D638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_39 0x190ED638u //! Register Reset Value #define DESC2_3_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_39 Register DESC3_3_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_39 0x2D63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_39 0x190ED63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_39 Register DESC0_4_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_39 0x2D640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_39 0x190ED640u //! Register Reset Value #define DESC0_4_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_39 Register DESC1_4_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_39 0x2D644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_39 0x190ED644u //! Register Reset Value #define DESC1_4_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_39 Register DESC2_4_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_39 0x2D648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_39 0x190ED648u //! Register Reset Value #define DESC2_4_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_39 Register DESC3_4_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_39 0x2D64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_39 0x190ED64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_39 Register DESC0_5_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_39 0x2D650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_39 0x190ED650u //! Register Reset Value #define DESC0_5_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_39 Register DESC1_5_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_39 0x2D654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_39 0x190ED654u //! Register Reset Value #define DESC1_5_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_39 Register DESC2_5_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_39 0x2D658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_39 0x190ED658u //! Register Reset Value #define DESC2_5_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_39 Register DESC3_5_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_39 0x2D65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_39 0x190ED65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_39 Register DESC0_6_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_39 0x2D660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_39 0x190ED660u //! Register Reset Value #define DESC0_6_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_39 Register DESC1_6_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_39 0x2D664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_39 0x190ED664u //! Register Reset Value #define DESC1_6_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_39 Register DESC2_6_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_39 0x2D668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_39 0x190ED668u //! Register Reset Value #define DESC2_6_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_39 Register DESC3_6_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_39 0x2D66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_39 0x190ED66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_39 Register DESC0_7_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_39 0x2D670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_39 0x190ED670u //! Register Reset Value #define DESC0_7_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_39 Register DESC1_7_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_39 0x2D674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_39 0x190ED674u //! Register Reset Value #define DESC1_7_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_39 Register DESC2_7_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_39 0x2D678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_39 0x190ED678u //! Register Reset Value #define DESC2_7_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_39_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_39 Register DESC3_7_PON_EGP_S_39 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_39 0x2D67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_39 0x190ED67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_39_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_39_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_39_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_39_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_39_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_40 Register CFG_PON_EGP_40 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_40 0x2D800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_40 0x190ED800u //! Register Reset Value #define CFG_PON_EGP_40_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_40_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_40_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_40_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_40_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_40_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_40_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_40_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_40_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_40_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_40_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_40 Register IRNCR_PON_EGP_40 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_40 0x2D820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_40 0x190ED820u //! Register Reset Value #define IRNCR_PON_EGP_40_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_40_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_40_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_40_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_40_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_40 Register IRNICR_PON_EGP_40 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_40 0x2D824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_40 0x190ED824u //! Register Reset Value #define IRNICR_PON_EGP_40_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_40_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_40_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_40 Register IRNEN_PON_EGP_40 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_40 0x2D828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_40 0x190ED828u //! Register Reset Value #define IRNEN_PON_EGP_40_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_40_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_40_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_40_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_40_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_40 Register DPTR_PON_EGP_40 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_40 0x2D830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_40 0x190ED830u //! Register Reset Value #define DPTR_PON_EGP_40_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_40_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_40_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_40_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_40_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_40_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_40_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_40_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_40_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_40 Register DESC0_0_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_40 0x2D900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_40 0x190ED900u //! Register Reset Value #define DESC0_0_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_40 Register DESC1_0_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_40 0x2D904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_40 0x190ED904u //! Register Reset Value #define DESC1_0_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_40 Register DESC2_0_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_40 0x2D908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_40 0x190ED908u //! Register Reset Value #define DESC2_0_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_40 Register DESC3_0_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_40 0x2D90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_40 0x190ED90Cu //! Register Reset Value #define DESC3_0_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_40 Register DESC0_1_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_40 0x2D910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_40 0x190ED910u //! Register Reset Value #define DESC0_1_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_40 Register DESC1_1_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_40 0x2D914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_40 0x190ED914u //! Register Reset Value #define DESC1_1_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_40 Register DESC2_1_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_40 0x2D918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_40 0x190ED918u //! Register Reset Value #define DESC2_1_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_40 Register DESC3_1_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_40 0x2D91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_40 0x190ED91Cu //! Register Reset Value #define DESC3_1_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_40 Register DESC0_2_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_40 0x2D920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_40 0x190ED920u //! Register Reset Value #define DESC0_2_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_40 Register DESC1_2_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_40 0x2D924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_40 0x190ED924u //! Register Reset Value #define DESC1_2_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_40 Register DESC2_2_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_40 0x2D928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_40 0x190ED928u //! Register Reset Value #define DESC2_2_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_40 Register DESC3_2_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_40 0x2D92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_40 0x190ED92Cu //! Register Reset Value #define DESC3_2_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_40 Register DESC0_3_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_40 0x2D930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_40 0x190ED930u //! Register Reset Value #define DESC0_3_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_40 Register DESC1_3_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_40 0x2D934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_40 0x190ED934u //! Register Reset Value #define DESC1_3_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_40 Register DESC2_3_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_40 0x2D938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_40 0x190ED938u //! Register Reset Value #define DESC2_3_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_40 Register DESC3_3_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_40 0x2D93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_40 0x190ED93Cu //! Register Reset Value #define DESC3_3_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_40 Register DESC0_4_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_40 0x2D940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_40 0x190ED940u //! Register Reset Value #define DESC0_4_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_40 Register DESC1_4_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_40 0x2D944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_40 0x190ED944u //! Register Reset Value #define DESC1_4_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_40 Register DESC2_4_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_40 0x2D948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_40 0x190ED948u //! Register Reset Value #define DESC2_4_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_40 Register DESC3_4_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_40 0x2D94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_40 0x190ED94Cu //! Register Reset Value #define DESC3_4_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_40 Register DESC0_5_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_40 0x2D950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_40 0x190ED950u //! Register Reset Value #define DESC0_5_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_40 Register DESC1_5_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_40 0x2D954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_40 0x190ED954u //! Register Reset Value #define DESC1_5_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_40 Register DESC2_5_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_40 0x2D958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_40 0x190ED958u //! Register Reset Value #define DESC2_5_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_40 Register DESC3_5_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_40 0x2D95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_40 0x190ED95Cu //! Register Reset Value #define DESC3_5_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_40 Register DESC0_6_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_40 0x2D960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_40 0x190ED960u //! Register Reset Value #define DESC0_6_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_40 Register DESC1_6_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_40 0x2D964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_40 0x190ED964u //! Register Reset Value #define DESC1_6_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_40 Register DESC2_6_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_40 0x2D968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_40 0x190ED968u //! Register Reset Value #define DESC2_6_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_40 Register DESC3_6_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_40 0x2D96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_40 0x190ED96Cu //! Register Reset Value #define DESC3_6_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_40 Register DESC0_7_PON_EGP_40 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_40 0x2D970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_40 0x190ED970u //! Register Reset Value #define DESC0_7_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_40 Register DESC1_7_PON_EGP_40 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_40 0x2D974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_40 0x190ED974u //! Register Reset Value #define DESC1_7_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_40 Register DESC2_7_PON_EGP_40 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_40 0x2D978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_40 0x190ED978u //! Register Reset Value #define DESC2_7_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_40 Register DESC3_7_PON_EGP_40 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_40 0x2D97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_40 0x190ED97Cu //! Register Reset Value #define DESC3_7_PON_EGP_40_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_40_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_40_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_40 Register DESC0_0_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_40 0x2DA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_40 0x190EDA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_40 Register DESC1_0_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_40 0x2DA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_40 0x190EDA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_40 Register DESC2_0_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_40 0x2DA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_40 0x190EDA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_40 Register DESC3_0_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_40 0x2DA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_40 0x190EDA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_40 Register DESC0_1_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_40 0x2DA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_40 0x190EDA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_40 Register DESC1_1_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_40 0x2DA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_40 0x190EDA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_40 Register DESC2_1_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_40 0x2DA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_40 0x190EDA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_40 Register DESC3_1_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_40 0x2DA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_40 0x190EDA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_40 Register DESC0_2_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_40 0x2DA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_40 0x190EDA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_40 Register DESC1_2_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_40 0x2DA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_40 0x190EDA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_40 Register DESC2_2_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_40 0x2DA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_40 0x190EDA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_40 Register DESC3_2_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_40 0x2DA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_40 0x190EDA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_40 Register DESC0_3_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_40 0x2DA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_40 0x190EDA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_40 Register DESC1_3_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_40 0x2DA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_40 0x190EDA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_40 Register DESC2_3_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_40 0x2DA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_40 0x190EDA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_40 Register DESC3_3_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_40 0x2DA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_40 0x190EDA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_40 Register DESC0_4_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_40 0x2DA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_40 0x190EDA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_40 Register DESC1_4_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_40 0x2DA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_40 0x190EDA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_40 Register DESC2_4_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_40 0x2DA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_40 0x190EDA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_40 Register DESC3_4_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_40 0x2DA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_40 0x190EDA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_40 Register DESC0_5_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_40 0x2DA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_40 0x190EDA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_40 Register DESC1_5_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_40 0x2DA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_40 0x190EDA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_40 Register DESC2_5_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_40 0x2DA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_40 0x190EDA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_40 Register DESC3_5_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_40 0x2DA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_40 0x190EDA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_40 Register DESC0_6_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_40 0x2DA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_40 0x190EDA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_40 Register DESC1_6_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_40 0x2DA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_40 0x190EDA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_40 Register DESC2_6_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_40 0x2DA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_40 0x190EDA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_40 Register DESC3_6_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_40 0x2DA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_40 0x190EDA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_40 Register DESC0_7_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_40 0x2DA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_40 0x190EDA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_40 Register DESC1_7_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_40 0x2DA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_40 0x190EDA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_40 Register DESC2_7_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_40 0x2DA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_40 0x190EDA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_40_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_40 Register DESC3_7_PON_EGP_S_40 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_40 0x2DA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_40 0x190EDA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_40_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_40_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_40_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_40_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_40_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_41 Register CFG_PON_EGP_41 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_41 0x2DC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_41 0x190EDC00u //! Register Reset Value #define CFG_PON_EGP_41_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_41_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_41_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_41_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_41_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_41_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_41_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_41_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_41_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_41_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_41_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_41 Register IRNCR_PON_EGP_41 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_41 0x2DC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_41 0x190EDC20u //! Register Reset Value #define IRNCR_PON_EGP_41_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_41_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_41_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_41_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_41_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_41 Register IRNICR_PON_EGP_41 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_41 0x2DC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_41 0x190EDC24u //! Register Reset Value #define IRNICR_PON_EGP_41_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_41_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_41_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_41 Register IRNEN_PON_EGP_41 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_41 0x2DC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_41 0x190EDC28u //! Register Reset Value #define IRNEN_PON_EGP_41_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_41_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_41_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_41_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_41_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_41 Register DPTR_PON_EGP_41 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_41 0x2DC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_41 0x190EDC30u //! Register Reset Value #define DPTR_PON_EGP_41_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_41_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_41_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_41_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_41_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_41_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_41_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_41_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_41_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_41 Register DESC0_0_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_41 0x2DD00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_41 0x190EDD00u //! Register Reset Value #define DESC0_0_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_41 Register DESC1_0_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_41 0x2DD04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_41 0x190EDD04u //! Register Reset Value #define DESC1_0_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_41 Register DESC2_0_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_41 0x2DD08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_41 0x190EDD08u //! Register Reset Value #define DESC2_0_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_41 Register DESC3_0_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_41 0x2DD0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_41 0x190EDD0Cu //! Register Reset Value #define DESC3_0_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_41 Register DESC0_1_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_41 0x2DD10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_41 0x190EDD10u //! Register Reset Value #define DESC0_1_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_41 Register DESC1_1_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_41 0x2DD14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_41 0x190EDD14u //! Register Reset Value #define DESC1_1_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_41 Register DESC2_1_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_41 0x2DD18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_41 0x190EDD18u //! Register Reset Value #define DESC2_1_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_41 Register DESC3_1_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_41 0x2DD1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_41 0x190EDD1Cu //! Register Reset Value #define DESC3_1_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_41 Register DESC0_2_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_41 0x2DD20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_41 0x190EDD20u //! Register Reset Value #define DESC0_2_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_41 Register DESC1_2_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_41 0x2DD24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_41 0x190EDD24u //! Register Reset Value #define DESC1_2_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_41 Register DESC2_2_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_41 0x2DD28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_41 0x190EDD28u //! Register Reset Value #define DESC2_2_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_41 Register DESC3_2_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_41 0x2DD2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_41 0x190EDD2Cu //! Register Reset Value #define DESC3_2_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_41 Register DESC0_3_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_41 0x2DD30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_41 0x190EDD30u //! Register Reset Value #define DESC0_3_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_41 Register DESC1_3_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_41 0x2DD34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_41 0x190EDD34u //! Register Reset Value #define DESC1_3_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_41 Register DESC2_3_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_41 0x2DD38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_41 0x190EDD38u //! Register Reset Value #define DESC2_3_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_41 Register DESC3_3_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_41 0x2DD3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_41 0x190EDD3Cu //! Register Reset Value #define DESC3_3_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_41 Register DESC0_4_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_41 0x2DD40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_41 0x190EDD40u //! Register Reset Value #define DESC0_4_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_41 Register DESC1_4_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_41 0x2DD44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_41 0x190EDD44u //! Register Reset Value #define DESC1_4_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_41 Register DESC2_4_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_41 0x2DD48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_41 0x190EDD48u //! Register Reset Value #define DESC2_4_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_41 Register DESC3_4_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_41 0x2DD4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_41 0x190EDD4Cu //! Register Reset Value #define DESC3_4_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_41 Register DESC0_5_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_41 0x2DD50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_41 0x190EDD50u //! Register Reset Value #define DESC0_5_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_41 Register DESC1_5_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_41 0x2DD54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_41 0x190EDD54u //! Register Reset Value #define DESC1_5_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_41 Register DESC2_5_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_41 0x2DD58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_41 0x190EDD58u //! Register Reset Value #define DESC2_5_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_41 Register DESC3_5_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_41 0x2DD5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_41 0x190EDD5Cu //! Register Reset Value #define DESC3_5_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_41 Register DESC0_6_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_41 0x2DD60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_41 0x190EDD60u //! Register Reset Value #define DESC0_6_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_41 Register DESC1_6_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_41 0x2DD64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_41 0x190EDD64u //! Register Reset Value #define DESC1_6_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_41 Register DESC2_6_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_41 0x2DD68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_41 0x190EDD68u //! Register Reset Value #define DESC2_6_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_41 Register DESC3_6_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_41 0x2DD6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_41 0x190EDD6Cu //! Register Reset Value #define DESC3_6_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_41 Register DESC0_7_PON_EGP_41 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_41 0x2DD70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_41 0x190EDD70u //! Register Reset Value #define DESC0_7_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_41 Register DESC1_7_PON_EGP_41 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_41 0x2DD74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_41 0x190EDD74u //! Register Reset Value #define DESC1_7_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_41 Register DESC2_7_PON_EGP_41 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_41 0x2DD78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_41 0x190EDD78u //! Register Reset Value #define DESC2_7_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_41 Register DESC3_7_PON_EGP_41 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_41 0x2DD7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_41 0x190EDD7Cu //! Register Reset Value #define DESC3_7_PON_EGP_41_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_41_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_41_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_41 Register DESC0_0_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_41 0x2DE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_41 0x190EDE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_41 Register DESC1_0_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_41 0x2DE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_41 0x190EDE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_41 Register DESC2_0_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_41 0x2DE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_41 0x190EDE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_41 Register DESC3_0_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_41 0x2DE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_41 0x190EDE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_41 Register DESC0_1_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_41 0x2DE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_41 0x190EDE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_41 Register DESC1_1_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_41 0x2DE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_41 0x190EDE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_41 Register DESC2_1_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_41 0x2DE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_41 0x190EDE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_41 Register DESC3_1_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_41 0x2DE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_41 0x190EDE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_41 Register DESC0_2_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_41 0x2DE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_41 0x190EDE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_41 Register DESC1_2_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_41 0x2DE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_41 0x190EDE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_41 Register DESC2_2_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_41 0x2DE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_41 0x190EDE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_41 Register DESC3_2_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_41 0x2DE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_41 0x190EDE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_41 Register DESC0_3_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_41 0x2DE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_41 0x190EDE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_41 Register DESC1_3_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_41 0x2DE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_41 0x190EDE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_41 Register DESC2_3_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_41 0x2DE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_41 0x190EDE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_41 Register DESC3_3_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_41 0x2DE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_41 0x190EDE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_41 Register DESC0_4_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_41 0x2DE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_41 0x190EDE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_41 Register DESC1_4_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_41 0x2DE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_41 0x190EDE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_41 Register DESC2_4_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_41 0x2DE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_41 0x190EDE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_41 Register DESC3_4_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_41 0x2DE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_41 0x190EDE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_41 Register DESC0_5_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_41 0x2DE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_41 0x190EDE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_41 Register DESC1_5_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_41 0x2DE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_41 0x190EDE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_41 Register DESC2_5_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_41 0x2DE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_41 0x190EDE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_41 Register DESC3_5_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_41 0x2DE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_41 0x190EDE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_41 Register DESC0_6_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_41 0x2DE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_41 0x190EDE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_41 Register DESC1_6_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_41 0x2DE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_41 0x190EDE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_41 Register DESC2_6_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_41 0x2DE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_41 0x190EDE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_41 Register DESC3_6_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_41 0x2DE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_41 0x190EDE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_41 Register DESC0_7_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_41 0x2DE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_41 0x190EDE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_41 Register DESC1_7_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_41 0x2DE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_41 0x190EDE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_41 Register DESC2_7_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_41 0x2DE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_41 0x190EDE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_41_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_41 Register DESC3_7_PON_EGP_S_41 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_41 0x2DE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_41 0x190EDE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_41_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_41_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_41_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_41_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_41_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_42 Register CFG_PON_EGP_42 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_42 0x2E000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_42 0x190EE000u //! Register Reset Value #define CFG_PON_EGP_42_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_42_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_42_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_42_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_42_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_42_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_42_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_42_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_42_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_42_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_42_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_42 Register IRNCR_PON_EGP_42 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_42 0x2E020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_42 0x190EE020u //! Register Reset Value #define IRNCR_PON_EGP_42_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_42_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_42_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_42_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_42_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_42 Register IRNICR_PON_EGP_42 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_42 0x2E024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_42 0x190EE024u //! Register Reset Value #define IRNICR_PON_EGP_42_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_42_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_42_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_42 Register IRNEN_PON_EGP_42 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_42 0x2E028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_42 0x190EE028u //! Register Reset Value #define IRNEN_PON_EGP_42_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_42_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_42_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_42_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_42_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_42 Register DPTR_PON_EGP_42 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_42 0x2E030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_42 0x190EE030u //! Register Reset Value #define DPTR_PON_EGP_42_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_42_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_42_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_42_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_42_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_42_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_42_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_42_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_42_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_42 Register DESC0_0_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_42 0x2E100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_42 0x190EE100u //! Register Reset Value #define DESC0_0_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_42 Register DESC1_0_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_42 0x2E104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_42 0x190EE104u //! Register Reset Value #define DESC1_0_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_42 Register DESC2_0_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_42 0x2E108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_42 0x190EE108u //! Register Reset Value #define DESC2_0_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_42 Register DESC3_0_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_42 0x2E10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_42 0x190EE10Cu //! Register Reset Value #define DESC3_0_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_42 Register DESC0_1_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_42 0x2E110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_42 0x190EE110u //! Register Reset Value #define DESC0_1_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_42 Register DESC1_1_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_42 0x2E114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_42 0x190EE114u //! Register Reset Value #define DESC1_1_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_42 Register DESC2_1_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_42 0x2E118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_42 0x190EE118u //! Register Reset Value #define DESC2_1_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_42 Register DESC3_1_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_42 0x2E11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_42 0x190EE11Cu //! Register Reset Value #define DESC3_1_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_42 Register DESC0_2_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_42 0x2E120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_42 0x190EE120u //! Register Reset Value #define DESC0_2_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_42 Register DESC1_2_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_42 0x2E124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_42 0x190EE124u //! Register Reset Value #define DESC1_2_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_42 Register DESC2_2_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_42 0x2E128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_42 0x190EE128u //! Register Reset Value #define DESC2_2_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_42 Register DESC3_2_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_42 0x2E12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_42 0x190EE12Cu //! Register Reset Value #define DESC3_2_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_42 Register DESC0_3_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_42 0x2E130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_42 0x190EE130u //! Register Reset Value #define DESC0_3_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_42 Register DESC1_3_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_42 0x2E134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_42 0x190EE134u //! Register Reset Value #define DESC1_3_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_42 Register DESC2_3_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_42 0x2E138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_42 0x190EE138u //! Register Reset Value #define DESC2_3_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_42 Register DESC3_3_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_42 0x2E13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_42 0x190EE13Cu //! Register Reset Value #define DESC3_3_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_42 Register DESC0_4_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_42 0x2E140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_42 0x190EE140u //! Register Reset Value #define DESC0_4_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_42 Register DESC1_4_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_42 0x2E144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_42 0x190EE144u //! Register Reset Value #define DESC1_4_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_42 Register DESC2_4_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_42 0x2E148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_42 0x190EE148u //! Register Reset Value #define DESC2_4_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_42 Register DESC3_4_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_42 0x2E14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_42 0x190EE14Cu //! Register Reset Value #define DESC3_4_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_42 Register DESC0_5_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_42 0x2E150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_42 0x190EE150u //! Register Reset Value #define DESC0_5_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_42 Register DESC1_5_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_42 0x2E154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_42 0x190EE154u //! Register Reset Value #define DESC1_5_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_42 Register DESC2_5_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_42 0x2E158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_42 0x190EE158u //! Register Reset Value #define DESC2_5_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_42 Register DESC3_5_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_42 0x2E15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_42 0x190EE15Cu //! Register Reset Value #define DESC3_5_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_42 Register DESC0_6_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_42 0x2E160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_42 0x190EE160u //! Register Reset Value #define DESC0_6_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_42 Register DESC1_6_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_42 0x2E164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_42 0x190EE164u //! Register Reset Value #define DESC1_6_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_42 Register DESC2_6_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_42 0x2E168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_42 0x190EE168u //! Register Reset Value #define DESC2_6_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_42 Register DESC3_6_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_42 0x2E16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_42 0x190EE16Cu //! Register Reset Value #define DESC3_6_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_42 Register DESC0_7_PON_EGP_42 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_42 0x2E170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_42 0x190EE170u //! Register Reset Value #define DESC0_7_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_42 Register DESC1_7_PON_EGP_42 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_42 0x2E174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_42 0x190EE174u //! Register Reset Value #define DESC1_7_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_42 Register DESC2_7_PON_EGP_42 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_42 0x2E178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_42 0x190EE178u //! Register Reset Value #define DESC2_7_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_42 Register DESC3_7_PON_EGP_42 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_42 0x2E17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_42 0x190EE17Cu //! Register Reset Value #define DESC3_7_PON_EGP_42_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_42_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_42_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_42 Register DESC0_0_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_42 0x2E200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_42 0x190EE200u //! Register Reset Value #define DESC0_0_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_42 Register DESC1_0_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_42 0x2E204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_42 0x190EE204u //! Register Reset Value #define DESC1_0_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_42 Register DESC2_0_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_42 0x2E208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_42 0x190EE208u //! Register Reset Value #define DESC2_0_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_42 Register DESC3_0_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_42 0x2E20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_42 0x190EE20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_42 Register DESC0_1_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_42 0x2E210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_42 0x190EE210u //! Register Reset Value #define DESC0_1_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_42 Register DESC1_1_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_42 0x2E214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_42 0x190EE214u //! Register Reset Value #define DESC1_1_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_42 Register DESC2_1_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_42 0x2E218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_42 0x190EE218u //! Register Reset Value #define DESC2_1_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_42 Register DESC3_1_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_42 0x2E21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_42 0x190EE21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_42 Register DESC0_2_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_42 0x2E220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_42 0x190EE220u //! Register Reset Value #define DESC0_2_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_42 Register DESC1_2_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_42 0x2E224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_42 0x190EE224u //! Register Reset Value #define DESC1_2_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_42 Register DESC2_2_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_42 0x2E228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_42 0x190EE228u //! Register Reset Value #define DESC2_2_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_42 Register DESC3_2_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_42 0x2E22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_42 0x190EE22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_42 Register DESC0_3_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_42 0x2E230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_42 0x190EE230u //! Register Reset Value #define DESC0_3_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_42 Register DESC1_3_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_42 0x2E234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_42 0x190EE234u //! Register Reset Value #define DESC1_3_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_42 Register DESC2_3_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_42 0x2E238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_42 0x190EE238u //! Register Reset Value #define DESC2_3_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_42 Register DESC3_3_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_42 0x2E23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_42 0x190EE23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_42 Register DESC0_4_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_42 0x2E240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_42 0x190EE240u //! Register Reset Value #define DESC0_4_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_42 Register DESC1_4_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_42 0x2E244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_42 0x190EE244u //! Register Reset Value #define DESC1_4_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_42 Register DESC2_4_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_42 0x2E248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_42 0x190EE248u //! Register Reset Value #define DESC2_4_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_42 Register DESC3_4_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_42 0x2E24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_42 0x190EE24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_42 Register DESC0_5_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_42 0x2E250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_42 0x190EE250u //! Register Reset Value #define DESC0_5_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_42 Register DESC1_5_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_42 0x2E254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_42 0x190EE254u //! Register Reset Value #define DESC1_5_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_42 Register DESC2_5_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_42 0x2E258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_42 0x190EE258u //! Register Reset Value #define DESC2_5_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_42 Register DESC3_5_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_42 0x2E25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_42 0x190EE25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_42 Register DESC0_6_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_42 0x2E260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_42 0x190EE260u //! Register Reset Value #define DESC0_6_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_42 Register DESC1_6_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_42 0x2E264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_42 0x190EE264u //! Register Reset Value #define DESC1_6_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_42 Register DESC2_6_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_42 0x2E268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_42 0x190EE268u //! Register Reset Value #define DESC2_6_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_42 Register DESC3_6_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_42 0x2E26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_42 0x190EE26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_42 Register DESC0_7_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_42 0x2E270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_42 0x190EE270u //! Register Reset Value #define DESC0_7_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_42 Register DESC1_7_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_42 0x2E274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_42 0x190EE274u //! Register Reset Value #define DESC1_7_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_42 Register DESC2_7_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_42 0x2E278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_42 0x190EE278u //! Register Reset Value #define DESC2_7_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_42_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_42 Register DESC3_7_PON_EGP_S_42 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_42 0x2E27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_42 0x190EE27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_42_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_42_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_42_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_42_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_42_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_43 Register CFG_PON_EGP_43 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_43 0x2E400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_43 0x190EE400u //! Register Reset Value #define CFG_PON_EGP_43_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_43_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_43_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_43_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_43_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_43_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_43_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_43_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_43_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_43_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_43_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_43 Register IRNCR_PON_EGP_43 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_43 0x2E420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_43 0x190EE420u //! Register Reset Value #define IRNCR_PON_EGP_43_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_43_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_43_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_43_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_43_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_43 Register IRNICR_PON_EGP_43 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_43 0x2E424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_43 0x190EE424u //! Register Reset Value #define IRNICR_PON_EGP_43_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_43_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_43_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_43 Register IRNEN_PON_EGP_43 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_43 0x2E428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_43 0x190EE428u //! Register Reset Value #define IRNEN_PON_EGP_43_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_43_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_43_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_43_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_43_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_43 Register DPTR_PON_EGP_43 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_43 0x2E430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_43 0x190EE430u //! Register Reset Value #define DPTR_PON_EGP_43_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_43_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_43_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_43_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_43_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_43_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_43_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_43_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_43_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_43 Register DESC0_0_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_43 0x2E500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_43 0x190EE500u //! Register Reset Value #define DESC0_0_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_43 Register DESC1_0_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_43 0x2E504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_43 0x190EE504u //! Register Reset Value #define DESC1_0_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_43 Register DESC2_0_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_43 0x2E508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_43 0x190EE508u //! Register Reset Value #define DESC2_0_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_43 Register DESC3_0_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_43 0x2E50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_43 0x190EE50Cu //! Register Reset Value #define DESC3_0_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_43 Register DESC0_1_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_43 0x2E510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_43 0x190EE510u //! Register Reset Value #define DESC0_1_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_43 Register DESC1_1_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_43 0x2E514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_43 0x190EE514u //! Register Reset Value #define DESC1_1_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_43 Register DESC2_1_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_43 0x2E518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_43 0x190EE518u //! Register Reset Value #define DESC2_1_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_43 Register DESC3_1_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_43 0x2E51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_43 0x190EE51Cu //! Register Reset Value #define DESC3_1_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_43 Register DESC0_2_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_43 0x2E520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_43 0x190EE520u //! Register Reset Value #define DESC0_2_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_43 Register DESC1_2_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_43 0x2E524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_43 0x190EE524u //! Register Reset Value #define DESC1_2_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_43 Register DESC2_2_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_43 0x2E528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_43 0x190EE528u //! Register Reset Value #define DESC2_2_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_43 Register DESC3_2_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_43 0x2E52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_43 0x190EE52Cu //! Register Reset Value #define DESC3_2_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_43 Register DESC0_3_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_43 0x2E530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_43 0x190EE530u //! Register Reset Value #define DESC0_3_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_43 Register DESC1_3_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_43 0x2E534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_43 0x190EE534u //! Register Reset Value #define DESC1_3_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_43 Register DESC2_3_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_43 0x2E538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_43 0x190EE538u //! Register Reset Value #define DESC2_3_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_43 Register DESC3_3_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_43 0x2E53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_43 0x190EE53Cu //! Register Reset Value #define DESC3_3_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_43 Register DESC0_4_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_43 0x2E540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_43 0x190EE540u //! Register Reset Value #define DESC0_4_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_43 Register DESC1_4_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_43 0x2E544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_43 0x190EE544u //! Register Reset Value #define DESC1_4_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_43 Register DESC2_4_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_43 0x2E548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_43 0x190EE548u //! Register Reset Value #define DESC2_4_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_43 Register DESC3_4_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_43 0x2E54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_43 0x190EE54Cu //! Register Reset Value #define DESC3_4_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_43 Register DESC0_5_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_43 0x2E550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_43 0x190EE550u //! Register Reset Value #define DESC0_5_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_43 Register DESC1_5_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_43 0x2E554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_43 0x190EE554u //! Register Reset Value #define DESC1_5_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_43 Register DESC2_5_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_43 0x2E558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_43 0x190EE558u //! Register Reset Value #define DESC2_5_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_43 Register DESC3_5_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_43 0x2E55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_43 0x190EE55Cu //! Register Reset Value #define DESC3_5_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_43 Register DESC0_6_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_43 0x2E560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_43 0x190EE560u //! Register Reset Value #define DESC0_6_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_43 Register DESC1_6_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_43 0x2E564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_43 0x190EE564u //! Register Reset Value #define DESC1_6_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_43 Register DESC2_6_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_43 0x2E568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_43 0x190EE568u //! Register Reset Value #define DESC2_6_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_43 Register DESC3_6_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_43 0x2E56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_43 0x190EE56Cu //! Register Reset Value #define DESC3_6_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_43 Register DESC0_7_PON_EGP_43 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_43 0x2E570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_43 0x190EE570u //! Register Reset Value #define DESC0_7_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_43 Register DESC1_7_PON_EGP_43 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_43 0x2E574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_43 0x190EE574u //! Register Reset Value #define DESC1_7_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_43 Register DESC2_7_PON_EGP_43 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_43 0x2E578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_43 0x190EE578u //! Register Reset Value #define DESC2_7_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_43 Register DESC3_7_PON_EGP_43 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_43 0x2E57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_43 0x190EE57Cu //! Register Reset Value #define DESC3_7_PON_EGP_43_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_43_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_43_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_43 Register DESC0_0_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_43 0x2E600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_43 0x190EE600u //! Register Reset Value #define DESC0_0_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_43 Register DESC1_0_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_43 0x2E604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_43 0x190EE604u //! Register Reset Value #define DESC1_0_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_43 Register DESC2_0_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_43 0x2E608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_43 0x190EE608u //! Register Reset Value #define DESC2_0_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_43 Register DESC3_0_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_43 0x2E60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_43 0x190EE60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_43 Register DESC0_1_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_43 0x2E610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_43 0x190EE610u //! Register Reset Value #define DESC0_1_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_43 Register DESC1_1_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_43 0x2E614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_43 0x190EE614u //! Register Reset Value #define DESC1_1_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_43 Register DESC2_1_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_43 0x2E618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_43 0x190EE618u //! Register Reset Value #define DESC2_1_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_43 Register DESC3_1_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_43 0x2E61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_43 0x190EE61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_43 Register DESC0_2_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_43 0x2E620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_43 0x190EE620u //! Register Reset Value #define DESC0_2_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_43 Register DESC1_2_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_43 0x2E624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_43 0x190EE624u //! Register Reset Value #define DESC1_2_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_43 Register DESC2_2_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_43 0x2E628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_43 0x190EE628u //! Register Reset Value #define DESC2_2_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_43 Register DESC3_2_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_43 0x2E62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_43 0x190EE62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_43 Register DESC0_3_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_43 0x2E630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_43 0x190EE630u //! Register Reset Value #define DESC0_3_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_43 Register DESC1_3_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_43 0x2E634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_43 0x190EE634u //! Register Reset Value #define DESC1_3_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_43 Register DESC2_3_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_43 0x2E638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_43 0x190EE638u //! Register Reset Value #define DESC2_3_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_43 Register DESC3_3_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_43 0x2E63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_43 0x190EE63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_43 Register DESC0_4_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_43 0x2E640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_43 0x190EE640u //! Register Reset Value #define DESC0_4_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_43 Register DESC1_4_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_43 0x2E644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_43 0x190EE644u //! Register Reset Value #define DESC1_4_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_43 Register DESC2_4_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_43 0x2E648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_43 0x190EE648u //! Register Reset Value #define DESC2_4_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_43 Register DESC3_4_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_43 0x2E64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_43 0x190EE64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_43 Register DESC0_5_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_43 0x2E650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_43 0x190EE650u //! Register Reset Value #define DESC0_5_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_43 Register DESC1_5_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_43 0x2E654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_43 0x190EE654u //! Register Reset Value #define DESC1_5_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_43 Register DESC2_5_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_43 0x2E658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_43 0x190EE658u //! Register Reset Value #define DESC2_5_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_43 Register DESC3_5_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_43 0x2E65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_43 0x190EE65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_43 Register DESC0_6_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_43 0x2E660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_43 0x190EE660u //! Register Reset Value #define DESC0_6_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_43 Register DESC1_6_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_43 0x2E664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_43 0x190EE664u //! Register Reset Value #define DESC1_6_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_43 Register DESC2_6_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_43 0x2E668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_43 0x190EE668u //! Register Reset Value #define DESC2_6_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_43 Register DESC3_6_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_43 0x2E66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_43 0x190EE66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_43 Register DESC0_7_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_43 0x2E670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_43 0x190EE670u //! Register Reset Value #define DESC0_7_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_43 Register DESC1_7_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_43 0x2E674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_43 0x190EE674u //! Register Reset Value #define DESC1_7_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_43 Register DESC2_7_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_43 0x2E678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_43 0x190EE678u //! Register Reset Value #define DESC2_7_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_43_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_43 Register DESC3_7_PON_EGP_S_43 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_43 0x2E67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_43 0x190EE67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_43_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_43_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_43_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_43_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_43_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_44 Register CFG_PON_EGP_44 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_44 0x2E800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_44 0x190EE800u //! Register Reset Value #define CFG_PON_EGP_44_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_44_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_44_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_44_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_44_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_44_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_44_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_44_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_44_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_44_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_44_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_44 Register IRNCR_PON_EGP_44 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_44 0x2E820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_44 0x190EE820u //! Register Reset Value #define IRNCR_PON_EGP_44_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_44_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_44_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_44_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_44_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_44 Register IRNICR_PON_EGP_44 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_44 0x2E824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_44 0x190EE824u //! Register Reset Value #define IRNICR_PON_EGP_44_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_44_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_44_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_44 Register IRNEN_PON_EGP_44 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_44 0x2E828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_44 0x190EE828u //! Register Reset Value #define IRNEN_PON_EGP_44_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_44_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_44_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_44_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_44_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_44 Register DPTR_PON_EGP_44 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_44 0x2E830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_44 0x190EE830u //! Register Reset Value #define DPTR_PON_EGP_44_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_44_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_44_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_44_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_44_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_44_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_44_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_44_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_44_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_44 Register DESC0_0_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_44 0x2E900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_44 0x190EE900u //! Register Reset Value #define DESC0_0_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_44 Register DESC1_0_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_44 0x2E904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_44 0x190EE904u //! Register Reset Value #define DESC1_0_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_44 Register DESC2_0_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_44 0x2E908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_44 0x190EE908u //! Register Reset Value #define DESC2_0_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_44 Register DESC3_0_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_44 0x2E90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_44 0x190EE90Cu //! Register Reset Value #define DESC3_0_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_44 Register DESC0_1_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_44 0x2E910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_44 0x190EE910u //! Register Reset Value #define DESC0_1_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_44 Register DESC1_1_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_44 0x2E914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_44 0x190EE914u //! Register Reset Value #define DESC1_1_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_44 Register DESC2_1_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_44 0x2E918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_44 0x190EE918u //! Register Reset Value #define DESC2_1_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_44 Register DESC3_1_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_44 0x2E91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_44 0x190EE91Cu //! Register Reset Value #define DESC3_1_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_44 Register DESC0_2_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_44 0x2E920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_44 0x190EE920u //! Register Reset Value #define DESC0_2_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_44 Register DESC1_2_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_44 0x2E924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_44 0x190EE924u //! Register Reset Value #define DESC1_2_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_44 Register DESC2_2_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_44 0x2E928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_44 0x190EE928u //! Register Reset Value #define DESC2_2_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_44 Register DESC3_2_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_44 0x2E92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_44 0x190EE92Cu //! Register Reset Value #define DESC3_2_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_44 Register DESC0_3_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_44 0x2E930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_44 0x190EE930u //! Register Reset Value #define DESC0_3_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_44 Register DESC1_3_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_44 0x2E934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_44 0x190EE934u //! Register Reset Value #define DESC1_3_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_44 Register DESC2_3_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_44 0x2E938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_44 0x190EE938u //! Register Reset Value #define DESC2_3_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_44 Register DESC3_3_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_44 0x2E93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_44 0x190EE93Cu //! Register Reset Value #define DESC3_3_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_44 Register DESC0_4_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_44 0x2E940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_44 0x190EE940u //! Register Reset Value #define DESC0_4_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_44 Register DESC1_4_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_44 0x2E944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_44 0x190EE944u //! Register Reset Value #define DESC1_4_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_44 Register DESC2_4_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_44 0x2E948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_44 0x190EE948u //! Register Reset Value #define DESC2_4_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_44 Register DESC3_4_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_44 0x2E94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_44 0x190EE94Cu //! Register Reset Value #define DESC3_4_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_44 Register DESC0_5_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_44 0x2E950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_44 0x190EE950u //! Register Reset Value #define DESC0_5_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_44 Register DESC1_5_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_44 0x2E954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_44 0x190EE954u //! Register Reset Value #define DESC1_5_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_44 Register DESC2_5_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_44 0x2E958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_44 0x190EE958u //! Register Reset Value #define DESC2_5_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_44 Register DESC3_5_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_44 0x2E95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_44 0x190EE95Cu //! Register Reset Value #define DESC3_5_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_44 Register DESC0_6_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_44 0x2E960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_44 0x190EE960u //! Register Reset Value #define DESC0_6_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_44 Register DESC1_6_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_44 0x2E964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_44 0x190EE964u //! Register Reset Value #define DESC1_6_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_44 Register DESC2_6_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_44 0x2E968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_44 0x190EE968u //! Register Reset Value #define DESC2_6_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_44 Register DESC3_6_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_44 0x2E96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_44 0x190EE96Cu //! Register Reset Value #define DESC3_6_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_44 Register DESC0_7_PON_EGP_44 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_44 0x2E970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_44 0x190EE970u //! Register Reset Value #define DESC0_7_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_44 Register DESC1_7_PON_EGP_44 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_44 0x2E974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_44 0x190EE974u //! Register Reset Value #define DESC1_7_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_44 Register DESC2_7_PON_EGP_44 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_44 0x2E978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_44 0x190EE978u //! Register Reset Value #define DESC2_7_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_44 Register DESC3_7_PON_EGP_44 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_44 0x2E97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_44 0x190EE97Cu //! Register Reset Value #define DESC3_7_PON_EGP_44_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_44_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_44_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_44 Register DESC0_0_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_44 0x2EA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_44 0x190EEA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_44 Register DESC1_0_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_44 0x2EA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_44 0x190EEA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_44 Register DESC2_0_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_44 0x2EA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_44 0x190EEA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_44 Register DESC3_0_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_44 0x2EA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_44 0x190EEA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_44 Register DESC0_1_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_44 0x2EA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_44 0x190EEA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_44 Register DESC1_1_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_44 0x2EA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_44 0x190EEA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_44 Register DESC2_1_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_44 0x2EA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_44 0x190EEA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_44 Register DESC3_1_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_44 0x2EA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_44 0x190EEA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_44 Register DESC0_2_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_44 0x2EA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_44 0x190EEA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_44 Register DESC1_2_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_44 0x2EA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_44 0x190EEA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_44 Register DESC2_2_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_44 0x2EA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_44 0x190EEA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_44 Register DESC3_2_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_44 0x2EA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_44 0x190EEA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_44 Register DESC0_3_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_44 0x2EA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_44 0x190EEA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_44 Register DESC1_3_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_44 0x2EA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_44 0x190EEA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_44 Register DESC2_3_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_44 0x2EA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_44 0x190EEA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_44 Register DESC3_3_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_44 0x2EA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_44 0x190EEA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_44 Register DESC0_4_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_44 0x2EA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_44 0x190EEA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_44 Register DESC1_4_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_44 0x2EA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_44 0x190EEA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_44 Register DESC2_4_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_44 0x2EA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_44 0x190EEA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_44 Register DESC3_4_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_44 0x2EA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_44 0x190EEA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_44 Register DESC0_5_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_44 0x2EA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_44 0x190EEA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_44 Register DESC1_5_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_44 0x2EA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_44 0x190EEA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_44 Register DESC2_5_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_44 0x2EA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_44 0x190EEA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_44 Register DESC3_5_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_44 0x2EA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_44 0x190EEA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_44 Register DESC0_6_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_44 0x2EA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_44 0x190EEA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_44 Register DESC1_6_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_44 0x2EA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_44 0x190EEA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_44 Register DESC2_6_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_44 0x2EA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_44 0x190EEA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_44 Register DESC3_6_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_44 0x2EA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_44 0x190EEA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_44 Register DESC0_7_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_44 0x2EA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_44 0x190EEA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_44 Register DESC1_7_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_44 0x2EA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_44 0x190EEA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_44 Register DESC2_7_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_44 0x2EA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_44 0x190EEA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_44_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_44 Register DESC3_7_PON_EGP_S_44 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_44 0x2EA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_44 0x190EEA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_44_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_44_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_44_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_44_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_44_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_45 Register CFG_PON_EGP_45 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_45 0x2EC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_45 0x190EEC00u //! Register Reset Value #define CFG_PON_EGP_45_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_45_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_45_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_45_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_45_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_45_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_45_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_45_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_45_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_45_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_45_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_45 Register IRNCR_PON_EGP_45 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_45 0x2EC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_45 0x190EEC20u //! Register Reset Value #define IRNCR_PON_EGP_45_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_45_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_45_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_45_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_45_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_45 Register IRNICR_PON_EGP_45 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_45 0x2EC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_45 0x190EEC24u //! Register Reset Value #define IRNICR_PON_EGP_45_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_45_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_45_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_45 Register IRNEN_PON_EGP_45 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_45 0x2EC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_45 0x190EEC28u //! Register Reset Value #define IRNEN_PON_EGP_45_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_45_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_45_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_45_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_45_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_45 Register DPTR_PON_EGP_45 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_45 0x2EC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_45 0x190EEC30u //! Register Reset Value #define DPTR_PON_EGP_45_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_45_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_45_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_45_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_45_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_45_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_45_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_45_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_45_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_45 Register DESC0_0_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_45 0x2ED00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_45 0x190EED00u //! Register Reset Value #define DESC0_0_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_45 Register DESC1_0_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_45 0x2ED04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_45 0x190EED04u //! Register Reset Value #define DESC1_0_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_45 Register DESC2_0_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_45 0x2ED08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_45 0x190EED08u //! Register Reset Value #define DESC2_0_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_45 Register DESC3_0_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_45 0x2ED0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_45 0x190EED0Cu //! Register Reset Value #define DESC3_0_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_45 Register DESC0_1_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_45 0x2ED10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_45 0x190EED10u //! Register Reset Value #define DESC0_1_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_45 Register DESC1_1_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_45 0x2ED14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_45 0x190EED14u //! Register Reset Value #define DESC1_1_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_45 Register DESC2_1_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_45 0x2ED18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_45 0x190EED18u //! Register Reset Value #define DESC2_1_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_45 Register DESC3_1_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_45 0x2ED1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_45 0x190EED1Cu //! Register Reset Value #define DESC3_1_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_45 Register DESC0_2_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_45 0x2ED20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_45 0x190EED20u //! Register Reset Value #define DESC0_2_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_45 Register DESC1_2_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_45 0x2ED24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_45 0x190EED24u //! Register Reset Value #define DESC1_2_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_45 Register DESC2_2_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_45 0x2ED28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_45 0x190EED28u //! Register Reset Value #define DESC2_2_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_45 Register DESC3_2_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_45 0x2ED2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_45 0x190EED2Cu //! Register Reset Value #define DESC3_2_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_45 Register DESC0_3_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_45 0x2ED30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_45 0x190EED30u //! Register Reset Value #define DESC0_3_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_45 Register DESC1_3_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_45 0x2ED34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_45 0x190EED34u //! Register Reset Value #define DESC1_3_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_45 Register DESC2_3_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_45 0x2ED38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_45 0x190EED38u //! Register Reset Value #define DESC2_3_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_45 Register DESC3_3_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_45 0x2ED3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_45 0x190EED3Cu //! Register Reset Value #define DESC3_3_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_45 Register DESC0_4_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_45 0x2ED40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_45 0x190EED40u //! Register Reset Value #define DESC0_4_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_45 Register DESC1_4_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_45 0x2ED44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_45 0x190EED44u //! Register Reset Value #define DESC1_4_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_45 Register DESC2_4_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_45 0x2ED48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_45 0x190EED48u //! Register Reset Value #define DESC2_4_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_45 Register DESC3_4_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_45 0x2ED4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_45 0x190EED4Cu //! Register Reset Value #define DESC3_4_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_45 Register DESC0_5_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_45 0x2ED50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_45 0x190EED50u //! Register Reset Value #define DESC0_5_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_45 Register DESC1_5_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_45 0x2ED54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_45 0x190EED54u //! Register Reset Value #define DESC1_5_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_45 Register DESC2_5_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_45 0x2ED58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_45 0x190EED58u //! Register Reset Value #define DESC2_5_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_45 Register DESC3_5_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_45 0x2ED5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_45 0x190EED5Cu //! Register Reset Value #define DESC3_5_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_45 Register DESC0_6_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_45 0x2ED60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_45 0x190EED60u //! Register Reset Value #define DESC0_6_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_45 Register DESC1_6_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_45 0x2ED64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_45 0x190EED64u //! Register Reset Value #define DESC1_6_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_45 Register DESC2_6_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_45 0x2ED68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_45 0x190EED68u //! Register Reset Value #define DESC2_6_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_45 Register DESC3_6_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_45 0x2ED6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_45 0x190EED6Cu //! Register Reset Value #define DESC3_6_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_45 Register DESC0_7_PON_EGP_45 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_45 0x2ED70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_45 0x190EED70u //! Register Reset Value #define DESC0_7_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_45 Register DESC1_7_PON_EGP_45 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_45 0x2ED74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_45 0x190EED74u //! Register Reset Value #define DESC1_7_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_45 Register DESC2_7_PON_EGP_45 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_45 0x2ED78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_45 0x190EED78u //! Register Reset Value #define DESC2_7_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_45 Register DESC3_7_PON_EGP_45 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_45 0x2ED7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_45 0x190EED7Cu //! Register Reset Value #define DESC3_7_PON_EGP_45_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_45_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_45_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_45 Register DESC0_0_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_45 0x2EE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_45 0x190EEE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_45 Register DESC1_0_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_45 0x2EE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_45 0x190EEE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_45 Register DESC2_0_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_45 0x2EE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_45 0x190EEE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_45 Register DESC3_0_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_45 0x2EE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_45 0x190EEE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_45 Register DESC0_1_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_45 0x2EE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_45 0x190EEE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_45 Register DESC1_1_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_45 0x2EE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_45 0x190EEE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_45 Register DESC2_1_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_45 0x2EE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_45 0x190EEE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_45 Register DESC3_1_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_45 0x2EE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_45 0x190EEE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_45 Register DESC0_2_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_45 0x2EE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_45 0x190EEE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_45 Register DESC1_2_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_45 0x2EE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_45 0x190EEE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_45 Register DESC2_2_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_45 0x2EE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_45 0x190EEE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_45 Register DESC3_2_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_45 0x2EE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_45 0x190EEE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_45 Register DESC0_3_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_45 0x2EE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_45 0x190EEE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_45 Register DESC1_3_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_45 0x2EE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_45 0x190EEE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_45 Register DESC2_3_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_45 0x2EE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_45 0x190EEE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_45 Register DESC3_3_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_45 0x2EE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_45 0x190EEE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_45 Register DESC0_4_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_45 0x2EE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_45 0x190EEE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_45 Register DESC1_4_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_45 0x2EE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_45 0x190EEE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_45 Register DESC2_4_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_45 0x2EE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_45 0x190EEE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_45 Register DESC3_4_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_45 0x2EE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_45 0x190EEE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_45 Register DESC0_5_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_45 0x2EE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_45 0x190EEE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_45 Register DESC1_5_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_45 0x2EE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_45 0x190EEE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_45 Register DESC2_5_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_45 0x2EE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_45 0x190EEE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_45 Register DESC3_5_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_45 0x2EE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_45 0x190EEE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_45 Register DESC0_6_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_45 0x2EE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_45 0x190EEE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_45 Register DESC1_6_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_45 0x2EE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_45 0x190EEE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_45 Register DESC2_6_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_45 0x2EE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_45 0x190EEE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_45 Register DESC3_6_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_45 0x2EE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_45 0x190EEE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_45 Register DESC0_7_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_45 0x2EE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_45 0x190EEE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_45 Register DESC1_7_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_45 0x2EE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_45 0x190EEE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_45 Register DESC2_7_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_45 0x2EE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_45 0x190EEE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_45_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_45 Register DESC3_7_PON_EGP_S_45 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_45 0x2EE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_45 0x190EEE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_45_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_45_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_45_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_45_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_45_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_46 Register CFG_PON_EGP_46 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_46 0x2F000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_46 0x190EF000u //! Register Reset Value #define CFG_PON_EGP_46_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_46_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_46_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_46_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_46_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_46_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_46_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_46_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_46_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_46_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_46_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_46 Register IRNCR_PON_EGP_46 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_46 0x2F020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_46 0x190EF020u //! Register Reset Value #define IRNCR_PON_EGP_46_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_46_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_46_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_46_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_46_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_46 Register IRNICR_PON_EGP_46 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_46 0x2F024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_46 0x190EF024u //! Register Reset Value #define IRNICR_PON_EGP_46_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_46_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_46_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_46 Register IRNEN_PON_EGP_46 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_46 0x2F028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_46 0x190EF028u //! Register Reset Value #define IRNEN_PON_EGP_46_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_46_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_46_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_46_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_46_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_46 Register DPTR_PON_EGP_46 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_46 0x2F030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_46 0x190EF030u //! Register Reset Value #define DPTR_PON_EGP_46_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_46_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_46_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_46_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_46_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_46_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_46_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_46_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_46_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_46 Register DESC0_0_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_46 0x2F100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_46 0x190EF100u //! Register Reset Value #define DESC0_0_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_46 Register DESC1_0_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_46 0x2F104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_46 0x190EF104u //! Register Reset Value #define DESC1_0_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_46 Register DESC2_0_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_46 0x2F108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_46 0x190EF108u //! Register Reset Value #define DESC2_0_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_46 Register DESC3_0_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_46 0x2F10C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_46 0x190EF10Cu //! Register Reset Value #define DESC3_0_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_46 Register DESC0_1_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_46 0x2F110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_46 0x190EF110u //! Register Reset Value #define DESC0_1_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_46 Register DESC1_1_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_46 0x2F114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_46 0x190EF114u //! Register Reset Value #define DESC1_1_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_46 Register DESC2_1_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_46 0x2F118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_46 0x190EF118u //! Register Reset Value #define DESC2_1_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_46 Register DESC3_1_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_46 0x2F11C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_46 0x190EF11Cu //! Register Reset Value #define DESC3_1_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_46 Register DESC0_2_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_46 0x2F120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_46 0x190EF120u //! Register Reset Value #define DESC0_2_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_46 Register DESC1_2_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_46 0x2F124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_46 0x190EF124u //! Register Reset Value #define DESC1_2_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_46 Register DESC2_2_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_46 0x2F128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_46 0x190EF128u //! Register Reset Value #define DESC2_2_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_46 Register DESC3_2_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_46 0x2F12C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_46 0x190EF12Cu //! Register Reset Value #define DESC3_2_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_46 Register DESC0_3_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_46 0x2F130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_46 0x190EF130u //! Register Reset Value #define DESC0_3_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_46 Register DESC1_3_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_46 0x2F134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_46 0x190EF134u //! Register Reset Value #define DESC1_3_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_46 Register DESC2_3_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_46 0x2F138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_46 0x190EF138u //! Register Reset Value #define DESC2_3_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_46 Register DESC3_3_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_46 0x2F13C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_46 0x190EF13Cu //! Register Reset Value #define DESC3_3_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_46 Register DESC0_4_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_46 0x2F140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_46 0x190EF140u //! Register Reset Value #define DESC0_4_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_46 Register DESC1_4_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_46 0x2F144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_46 0x190EF144u //! Register Reset Value #define DESC1_4_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_46 Register DESC2_4_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_46 0x2F148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_46 0x190EF148u //! Register Reset Value #define DESC2_4_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_46 Register DESC3_4_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_46 0x2F14C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_46 0x190EF14Cu //! Register Reset Value #define DESC3_4_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_46 Register DESC0_5_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_46 0x2F150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_46 0x190EF150u //! Register Reset Value #define DESC0_5_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_46 Register DESC1_5_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_46 0x2F154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_46 0x190EF154u //! Register Reset Value #define DESC1_5_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_46 Register DESC2_5_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_46 0x2F158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_46 0x190EF158u //! Register Reset Value #define DESC2_5_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_46 Register DESC3_5_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_46 0x2F15C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_46 0x190EF15Cu //! Register Reset Value #define DESC3_5_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_46 Register DESC0_6_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_46 0x2F160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_46 0x190EF160u //! Register Reset Value #define DESC0_6_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_46 Register DESC1_6_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_46 0x2F164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_46 0x190EF164u //! Register Reset Value #define DESC1_6_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_46 Register DESC2_6_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_46 0x2F168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_46 0x190EF168u //! Register Reset Value #define DESC2_6_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_46 Register DESC3_6_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_46 0x2F16C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_46 0x190EF16Cu //! Register Reset Value #define DESC3_6_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_46 Register DESC0_7_PON_EGP_46 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_46 0x2F170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_46 0x190EF170u //! Register Reset Value #define DESC0_7_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_46 Register DESC1_7_PON_EGP_46 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_46 0x2F174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_46 0x190EF174u //! Register Reset Value #define DESC1_7_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_46 Register DESC2_7_PON_EGP_46 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_46 0x2F178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_46 0x190EF178u //! Register Reset Value #define DESC2_7_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_46 Register DESC3_7_PON_EGP_46 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_46 0x2F17C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_46 0x190EF17Cu //! Register Reset Value #define DESC3_7_PON_EGP_46_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_46_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_46_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_46 Register DESC0_0_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_46 0x2F200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_46 0x190EF200u //! Register Reset Value #define DESC0_0_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_46 Register DESC1_0_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_46 0x2F204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_46 0x190EF204u //! Register Reset Value #define DESC1_0_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_46 Register DESC2_0_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_46 0x2F208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_46 0x190EF208u //! Register Reset Value #define DESC2_0_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_46 Register DESC3_0_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_46 0x2F20C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_46 0x190EF20Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_46 Register DESC0_1_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_46 0x2F210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_46 0x190EF210u //! Register Reset Value #define DESC0_1_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_46 Register DESC1_1_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_46 0x2F214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_46 0x190EF214u //! Register Reset Value #define DESC1_1_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_46 Register DESC2_1_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_46 0x2F218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_46 0x190EF218u //! Register Reset Value #define DESC2_1_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_46 Register DESC3_1_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_46 0x2F21C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_46 0x190EF21Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_46 Register DESC0_2_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_46 0x2F220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_46 0x190EF220u //! Register Reset Value #define DESC0_2_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_46 Register DESC1_2_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_46 0x2F224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_46 0x190EF224u //! Register Reset Value #define DESC1_2_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_46 Register DESC2_2_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_46 0x2F228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_46 0x190EF228u //! Register Reset Value #define DESC2_2_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_46 Register DESC3_2_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_46 0x2F22C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_46 0x190EF22Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_46 Register DESC0_3_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_46 0x2F230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_46 0x190EF230u //! Register Reset Value #define DESC0_3_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_46 Register DESC1_3_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_46 0x2F234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_46 0x190EF234u //! Register Reset Value #define DESC1_3_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_46 Register DESC2_3_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_46 0x2F238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_46 0x190EF238u //! Register Reset Value #define DESC2_3_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_46 Register DESC3_3_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_46 0x2F23C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_46 0x190EF23Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_46 Register DESC0_4_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_46 0x2F240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_46 0x190EF240u //! Register Reset Value #define DESC0_4_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_46 Register DESC1_4_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_46 0x2F244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_46 0x190EF244u //! Register Reset Value #define DESC1_4_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_46 Register DESC2_4_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_46 0x2F248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_46 0x190EF248u //! Register Reset Value #define DESC2_4_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_46 Register DESC3_4_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_46 0x2F24C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_46 0x190EF24Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_46 Register DESC0_5_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_46 0x2F250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_46 0x190EF250u //! Register Reset Value #define DESC0_5_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_46 Register DESC1_5_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_46 0x2F254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_46 0x190EF254u //! Register Reset Value #define DESC1_5_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_46 Register DESC2_5_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_46 0x2F258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_46 0x190EF258u //! Register Reset Value #define DESC2_5_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_46 Register DESC3_5_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_46 0x2F25C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_46 0x190EF25Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_46 Register DESC0_6_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_46 0x2F260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_46 0x190EF260u //! Register Reset Value #define DESC0_6_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_46 Register DESC1_6_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_46 0x2F264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_46 0x190EF264u //! Register Reset Value #define DESC1_6_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_46 Register DESC2_6_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_46 0x2F268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_46 0x190EF268u //! Register Reset Value #define DESC2_6_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_46 Register DESC3_6_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_46 0x2F26C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_46 0x190EF26Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_46 Register DESC0_7_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_46 0x2F270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_46 0x190EF270u //! Register Reset Value #define DESC0_7_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_46 Register DESC1_7_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_46 0x2F274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_46 0x190EF274u //! Register Reset Value #define DESC1_7_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_46 Register DESC2_7_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_46 0x2F278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_46 0x190EF278u //! Register Reset Value #define DESC2_7_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_46_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_46 Register DESC3_7_PON_EGP_S_46 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_46 0x2F27C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_46 0x190EF27Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_46_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_46_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_46_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_46_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_46_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_47 Register CFG_PON_EGP_47 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_47 0x2F400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_47 0x190EF400u //! Register Reset Value #define CFG_PON_EGP_47_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_47_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_47_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_47_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_47_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_47_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_47_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_47_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_47_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_47_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_47_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_47 Register IRNCR_PON_EGP_47 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_47 0x2F420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_47 0x190EF420u //! Register Reset Value #define IRNCR_PON_EGP_47_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_47_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_47_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_47_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_47_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_47 Register IRNICR_PON_EGP_47 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_47 0x2F424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_47 0x190EF424u //! Register Reset Value #define IRNICR_PON_EGP_47_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_47_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_47_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_47 Register IRNEN_PON_EGP_47 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_47 0x2F428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_47 0x190EF428u //! Register Reset Value #define IRNEN_PON_EGP_47_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_47_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_47_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_47_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_47_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_47 Register DPTR_PON_EGP_47 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_47 0x2F430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_47 0x190EF430u //! Register Reset Value #define DPTR_PON_EGP_47_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_47_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_47_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_47_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_47_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_47_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_47_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_47_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_47_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_47 Register DESC0_0_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_47 0x2F500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_47 0x190EF500u //! Register Reset Value #define DESC0_0_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_47 Register DESC1_0_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_47 0x2F504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_47 0x190EF504u //! Register Reset Value #define DESC1_0_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_47 Register DESC2_0_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_47 0x2F508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_47 0x190EF508u //! Register Reset Value #define DESC2_0_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_47 Register DESC3_0_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_47 0x2F50C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_47 0x190EF50Cu //! Register Reset Value #define DESC3_0_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_47 Register DESC0_1_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_47 0x2F510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_47 0x190EF510u //! Register Reset Value #define DESC0_1_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_47 Register DESC1_1_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_47 0x2F514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_47 0x190EF514u //! Register Reset Value #define DESC1_1_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_47 Register DESC2_1_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_47 0x2F518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_47 0x190EF518u //! Register Reset Value #define DESC2_1_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_47 Register DESC3_1_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_47 0x2F51C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_47 0x190EF51Cu //! Register Reset Value #define DESC3_1_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_47 Register DESC0_2_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_47 0x2F520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_47 0x190EF520u //! Register Reset Value #define DESC0_2_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_47 Register DESC1_2_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_47 0x2F524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_47 0x190EF524u //! Register Reset Value #define DESC1_2_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_47 Register DESC2_2_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_47 0x2F528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_47 0x190EF528u //! Register Reset Value #define DESC2_2_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_47 Register DESC3_2_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_47 0x2F52C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_47 0x190EF52Cu //! Register Reset Value #define DESC3_2_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_47 Register DESC0_3_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_47 0x2F530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_47 0x190EF530u //! Register Reset Value #define DESC0_3_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_47 Register DESC1_3_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_47 0x2F534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_47 0x190EF534u //! Register Reset Value #define DESC1_3_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_47 Register DESC2_3_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_47 0x2F538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_47 0x190EF538u //! Register Reset Value #define DESC2_3_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_47 Register DESC3_3_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_47 0x2F53C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_47 0x190EF53Cu //! Register Reset Value #define DESC3_3_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_47 Register DESC0_4_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_47 0x2F540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_47 0x190EF540u //! Register Reset Value #define DESC0_4_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_47 Register DESC1_4_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_47 0x2F544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_47 0x190EF544u //! Register Reset Value #define DESC1_4_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_47 Register DESC2_4_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_47 0x2F548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_47 0x190EF548u //! Register Reset Value #define DESC2_4_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_47 Register DESC3_4_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_47 0x2F54C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_47 0x190EF54Cu //! Register Reset Value #define DESC3_4_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_47 Register DESC0_5_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_47 0x2F550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_47 0x190EF550u //! Register Reset Value #define DESC0_5_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_47 Register DESC1_5_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_47 0x2F554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_47 0x190EF554u //! Register Reset Value #define DESC1_5_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_47 Register DESC2_5_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_47 0x2F558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_47 0x190EF558u //! Register Reset Value #define DESC2_5_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_47 Register DESC3_5_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_47 0x2F55C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_47 0x190EF55Cu //! Register Reset Value #define DESC3_5_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_47 Register DESC0_6_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_47 0x2F560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_47 0x190EF560u //! Register Reset Value #define DESC0_6_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_47 Register DESC1_6_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_47 0x2F564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_47 0x190EF564u //! Register Reset Value #define DESC1_6_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_47 Register DESC2_6_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_47 0x2F568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_47 0x190EF568u //! Register Reset Value #define DESC2_6_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_47 Register DESC3_6_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_47 0x2F56C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_47 0x190EF56Cu //! Register Reset Value #define DESC3_6_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_47 Register DESC0_7_PON_EGP_47 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_47 0x2F570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_47 0x190EF570u //! Register Reset Value #define DESC0_7_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_47 Register DESC1_7_PON_EGP_47 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_47 0x2F574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_47 0x190EF574u //! Register Reset Value #define DESC1_7_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_47 Register DESC2_7_PON_EGP_47 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_47 0x2F578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_47 0x190EF578u //! Register Reset Value #define DESC2_7_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_47 Register DESC3_7_PON_EGP_47 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_47 0x2F57C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_47 0x190EF57Cu //! Register Reset Value #define DESC3_7_PON_EGP_47_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_47_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_47_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_47 Register DESC0_0_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_47 0x2F600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_47 0x190EF600u //! Register Reset Value #define DESC0_0_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_47 Register DESC1_0_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_47 0x2F604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_47 0x190EF604u //! Register Reset Value #define DESC1_0_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_47 Register DESC2_0_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_47 0x2F608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_47 0x190EF608u //! Register Reset Value #define DESC2_0_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_47 Register DESC3_0_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_47 0x2F60C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_47 0x190EF60Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_47 Register DESC0_1_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_47 0x2F610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_47 0x190EF610u //! Register Reset Value #define DESC0_1_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_47 Register DESC1_1_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_47 0x2F614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_47 0x190EF614u //! Register Reset Value #define DESC1_1_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_47 Register DESC2_1_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_47 0x2F618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_47 0x190EF618u //! Register Reset Value #define DESC2_1_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_47 Register DESC3_1_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_47 0x2F61C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_47 0x190EF61Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_47 Register DESC0_2_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_47 0x2F620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_47 0x190EF620u //! Register Reset Value #define DESC0_2_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_47 Register DESC1_2_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_47 0x2F624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_47 0x190EF624u //! Register Reset Value #define DESC1_2_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_47 Register DESC2_2_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_47 0x2F628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_47 0x190EF628u //! Register Reset Value #define DESC2_2_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_47 Register DESC3_2_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_47 0x2F62C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_47 0x190EF62Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_47 Register DESC0_3_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_47 0x2F630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_47 0x190EF630u //! Register Reset Value #define DESC0_3_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_47 Register DESC1_3_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_47 0x2F634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_47 0x190EF634u //! Register Reset Value #define DESC1_3_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_47 Register DESC2_3_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_47 0x2F638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_47 0x190EF638u //! Register Reset Value #define DESC2_3_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_47 Register DESC3_3_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_47 0x2F63C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_47 0x190EF63Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_47 Register DESC0_4_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_47 0x2F640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_47 0x190EF640u //! Register Reset Value #define DESC0_4_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_47 Register DESC1_4_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_47 0x2F644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_47 0x190EF644u //! Register Reset Value #define DESC1_4_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_47 Register DESC2_4_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_47 0x2F648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_47 0x190EF648u //! Register Reset Value #define DESC2_4_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_47 Register DESC3_4_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_47 0x2F64C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_47 0x190EF64Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_47 Register DESC0_5_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_47 0x2F650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_47 0x190EF650u //! Register Reset Value #define DESC0_5_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_47 Register DESC1_5_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_47 0x2F654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_47 0x190EF654u //! Register Reset Value #define DESC1_5_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_47 Register DESC2_5_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_47 0x2F658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_47 0x190EF658u //! Register Reset Value #define DESC2_5_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_47 Register DESC3_5_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_47 0x2F65C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_47 0x190EF65Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_47 Register DESC0_6_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_47 0x2F660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_47 0x190EF660u //! Register Reset Value #define DESC0_6_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_47 Register DESC1_6_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_47 0x2F664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_47 0x190EF664u //! Register Reset Value #define DESC1_6_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_47 Register DESC2_6_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_47 0x2F668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_47 0x190EF668u //! Register Reset Value #define DESC2_6_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_47 Register DESC3_6_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_47 0x2F66C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_47 0x190EF66Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_47 Register DESC0_7_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_47 0x2F670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_47 0x190EF670u //! Register Reset Value #define DESC0_7_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_47 Register DESC1_7_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_47 0x2F674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_47 0x190EF674u //! Register Reset Value #define DESC1_7_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_47 Register DESC2_7_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_47 0x2F678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_47 0x190EF678u //! Register Reset Value #define DESC2_7_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_47_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_47 Register DESC3_7_PON_EGP_S_47 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_47 0x2F67C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_47 0x190EF67Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_47_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_47_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_47_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_47_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_47_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_48 Register CFG_PON_EGP_48 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_48 0x2F800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_48 0x190EF800u //! Register Reset Value #define CFG_PON_EGP_48_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_48_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_48_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_48_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_48_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_48_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_48_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_48_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_48_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_48_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_48_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_48 Register IRNCR_PON_EGP_48 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_48 0x2F820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_48 0x190EF820u //! Register Reset Value #define IRNCR_PON_EGP_48_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_48_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_48_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_48_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_48_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_48 Register IRNICR_PON_EGP_48 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_48 0x2F824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_48 0x190EF824u //! Register Reset Value #define IRNICR_PON_EGP_48_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_48_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_48_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_48 Register IRNEN_PON_EGP_48 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_48 0x2F828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_48 0x190EF828u //! Register Reset Value #define IRNEN_PON_EGP_48_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_48_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_48_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_48_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_48_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_48 Register DPTR_PON_EGP_48 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_48 0x2F830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_48 0x190EF830u //! Register Reset Value #define DPTR_PON_EGP_48_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_48_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_48_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_48_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_48_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_48_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_48_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_48_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_48_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_48 Register DESC0_0_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_48 0x2F900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_48 0x190EF900u //! Register Reset Value #define DESC0_0_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_48 Register DESC1_0_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_48 0x2F904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_48 0x190EF904u //! Register Reset Value #define DESC1_0_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_48 Register DESC2_0_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_48 0x2F908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_48 0x190EF908u //! Register Reset Value #define DESC2_0_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_48 Register DESC3_0_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_48 0x2F90C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_48 0x190EF90Cu //! Register Reset Value #define DESC3_0_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_48 Register DESC0_1_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_48 0x2F910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_48 0x190EF910u //! Register Reset Value #define DESC0_1_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_48 Register DESC1_1_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_48 0x2F914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_48 0x190EF914u //! Register Reset Value #define DESC1_1_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_48 Register DESC2_1_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_48 0x2F918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_48 0x190EF918u //! Register Reset Value #define DESC2_1_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_48 Register DESC3_1_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_48 0x2F91C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_48 0x190EF91Cu //! Register Reset Value #define DESC3_1_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_48 Register DESC0_2_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_48 0x2F920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_48 0x190EF920u //! Register Reset Value #define DESC0_2_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_48 Register DESC1_2_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_48 0x2F924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_48 0x190EF924u //! Register Reset Value #define DESC1_2_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_48 Register DESC2_2_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_48 0x2F928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_48 0x190EF928u //! Register Reset Value #define DESC2_2_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_48 Register DESC3_2_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_48 0x2F92C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_48 0x190EF92Cu //! Register Reset Value #define DESC3_2_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_48 Register DESC0_3_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_48 0x2F930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_48 0x190EF930u //! Register Reset Value #define DESC0_3_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_48 Register DESC1_3_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_48 0x2F934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_48 0x190EF934u //! Register Reset Value #define DESC1_3_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_48 Register DESC2_3_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_48 0x2F938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_48 0x190EF938u //! Register Reset Value #define DESC2_3_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_48 Register DESC3_3_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_48 0x2F93C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_48 0x190EF93Cu //! Register Reset Value #define DESC3_3_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_48 Register DESC0_4_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_48 0x2F940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_48 0x190EF940u //! Register Reset Value #define DESC0_4_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_48 Register DESC1_4_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_48 0x2F944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_48 0x190EF944u //! Register Reset Value #define DESC1_4_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_48 Register DESC2_4_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_48 0x2F948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_48 0x190EF948u //! Register Reset Value #define DESC2_4_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_48 Register DESC3_4_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_48 0x2F94C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_48 0x190EF94Cu //! Register Reset Value #define DESC3_4_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_48 Register DESC0_5_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_48 0x2F950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_48 0x190EF950u //! Register Reset Value #define DESC0_5_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_48 Register DESC1_5_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_48 0x2F954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_48 0x190EF954u //! Register Reset Value #define DESC1_5_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_48 Register DESC2_5_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_48 0x2F958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_48 0x190EF958u //! Register Reset Value #define DESC2_5_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_48 Register DESC3_5_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_48 0x2F95C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_48 0x190EF95Cu //! Register Reset Value #define DESC3_5_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_48 Register DESC0_6_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_48 0x2F960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_48 0x190EF960u //! Register Reset Value #define DESC0_6_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_48 Register DESC1_6_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_48 0x2F964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_48 0x190EF964u //! Register Reset Value #define DESC1_6_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_48 Register DESC2_6_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_48 0x2F968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_48 0x190EF968u //! Register Reset Value #define DESC2_6_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_48 Register DESC3_6_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_48 0x2F96C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_48 0x190EF96Cu //! Register Reset Value #define DESC3_6_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_48 Register DESC0_7_PON_EGP_48 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_48 0x2F970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_48 0x190EF970u //! Register Reset Value #define DESC0_7_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_48 Register DESC1_7_PON_EGP_48 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_48 0x2F974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_48 0x190EF974u //! Register Reset Value #define DESC1_7_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_48 Register DESC2_7_PON_EGP_48 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_48 0x2F978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_48 0x190EF978u //! Register Reset Value #define DESC2_7_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_48 Register DESC3_7_PON_EGP_48 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_48 0x2F97C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_48 0x190EF97Cu //! Register Reset Value #define DESC3_7_PON_EGP_48_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_48_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_48_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_48 Register DESC0_0_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_48 0x2FA00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_48 0x190EFA00u //! Register Reset Value #define DESC0_0_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_48 Register DESC1_0_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_48 0x2FA04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_48 0x190EFA04u //! Register Reset Value #define DESC1_0_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_48 Register DESC2_0_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_48 0x2FA08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_48 0x190EFA08u //! Register Reset Value #define DESC2_0_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_48 Register DESC3_0_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_48 0x2FA0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_48 0x190EFA0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_48 Register DESC0_1_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_48 0x2FA10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_48 0x190EFA10u //! Register Reset Value #define DESC0_1_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_48 Register DESC1_1_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_48 0x2FA14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_48 0x190EFA14u //! Register Reset Value #define DESC1_1_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_48 Register DESC2_1_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_48 0x2FA18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_48 0x190EFA18u //! Register Reset Value #define DESC2_1_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_48 Register DESC3_1_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_48 0x2FA1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_48 0x190EFA1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_48 Register DESC0_2_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_48 0x2FA20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_48 0x190EFA20u //! Register Reset Value #define DESC0_2_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_48 Register DESC1_2_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_48 0x2FA24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_48 0x190EFA24u //! Register Reset Value #define DESC1_2_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_48 Register DESC2_2_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_48 0x2FA28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_48 0x190EFA28u //! Register Reset Value #define DESC2_2_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_48 Register DESC3_2_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_48 0x2FA2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_48 0x190EFA2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_48 Register DESC0_3_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_48 0x2FA30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_48 0x190EFA30u //! Register Reset Value #define DESC0_3_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_48 Register DESC1_3_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_48 0x2FA34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_48 0x190EFA34u //! Register Reset Value #define DESC1_3_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_48 Register DESC2_3_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_48 0x2FA38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_48 0x190EFA38u //! Register Reset Value #define DESC2_3_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_48 Register DESC3_3_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_48 0x2FA3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_48 0x190EFA3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_48 Register DESC0_4_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_48 0x2FA40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_48 0x190EFA40u //! Register Reset Value #define DESC0_4_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_48 Register DESC1_4_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_48 0x2FA44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_48 0x190EFA44u //! Register Reset Value #define DESC1_4_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_48 Register DESC2_4_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_48 0x2FA48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_48 0x190EFA48u //! Register Reset Value #define DESC2_4_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_48 Register DESC3_4_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_48 0x2FA4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_48 0x190EFA4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_48 Register DESC0_5_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_48 0x2FA50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_48 0x190EFA50u //! Register Reset Value #define DESC0_5_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_48 Register DESC1_5_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_48 0x2FA54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_48 0x190EFA54u //! Register Reset Value #define DESC1_5_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_48 Register DESC2_5_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_48 0x2FA58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_48 0x190EFA58u //! Register Reset Value #define DESC2_5_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_48 Register DESC3_5_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_48 0x2FA5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_48 0x190EFA5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_48 Register DESC0_6_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_48 0x2FA60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_48 0x190EFA60u //! Register Reset Value #define DESC0_6_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_48 Register DESC1_6_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_48 0x2FA64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_48 0x190EFA64u //! Register Reset Value #define DESC1_6_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_48 Register DESC2_6_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_48 0x2FA68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_48 0x190EFA68u //! Register Reset Value #define DESC2_6_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_48 Register DESC3_6_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_48 0x2FA6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_48 0x190EFA6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_48 Register DESC0_7_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_48 0x2FA70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_48 0x190EFA70u //! Register Reset Value #define DESC0_7_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_48 Register DESC1_7_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_48 0x2FA74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_48 0x190EFA74u //! Register Reset Value #define DESC1_7_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_48 Register DESC2_7_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_48 0x2FA78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_48 0x190EFA78u //! Register Reset Value #define DESC2_7_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_48_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_48 Register DESC3_7_PON_EGP_S_48 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_48 0x2FA7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_48 0x190EFA7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_48_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_48_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_48_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_48_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_48_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_49 Register CFG_PON_EGP_49 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_49 0x2FC00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_49 0x190EFC00u //! Register Reset Value #define CFG_PON_EGP_49_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_49_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_49_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_49_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_49_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_49_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_49_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_49_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_49_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_49_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_49_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_49 Register IRNCR_PON_EGP_49 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_49 0x2FC20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_49 0x190EFC20u //! Register Reset Value #define IRNCR_PON_EGP_49_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_49_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_49_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_49_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_49_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_49 Register IRNICR_PON_EGP_49 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_49 0x2FC24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_49 0x190EFC24u //! Register Reset Value #define IRNICR_PON_EGP_49_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_49_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_49_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_49 Register IRNEN_PON_EGP_49 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_49 0x2FC28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_49 0x190EFC28u //! Register Reset Value #define IRNEN_PON_EGP_49_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_49_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_49_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_49_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_49_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_49 Register DPTR_PON_EGP_49 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_49 0x2FC30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_49 0x190EFC30u //! Register Reset Value #define DPTR_PON_EGP_49_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_49_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_49_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_49_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_49_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_49_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_49_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_49_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_49_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_49 Register DESC0_0_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_49 0x2FD00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_49 0x190EFD00u //! Register Reset Value #define DESC0_0_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_49 Register DESC1_0_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_49 0x2FD04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_49 0x190EFD04u //! Register Reset Value #define DESC1_0_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_49 Register DESC2_0_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_49 0x2FD08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_49 0x190EFD08u //! Register Reset Value #define DESC2_0_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_49 Register DESC3_0_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_49 0x2FD0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_49 0x190EFD0Cu //! Register Reset Value #define DESC3_0_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_49 Register DESC0_1_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_49 0x2FD10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_49 0x190EFD10u //! Register Reset Value #define DESC0_1_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_49 Register DESC1_1_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_49 0x2FD14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_49 0x190EFD14u //! Register Reset Value #define DESC1_1_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_49 Register DESC2_1_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_49 0x2FD18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_49 0x190EFD18u //! Register Reset Value #define DESC2_1_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_49 Register DESC3_1_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_49 0x2FD1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_49 0x190EFD1Cu //! Register Reset Value #define DESC3_1_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_49 Register DESC0_2_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_49 0x2FD20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_49 0x190EFD20u //! Register Reset Value #define DESC0_2_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_49 Register DESC1_2_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_49 0x2FD24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_49 0x190EFD24u //! Register Reset Value #define DESC1_2_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_49 Register DESC2_2_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_49 0x2FD28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_49 0x190EFD28u //! Register Reset Value #define DESC2_2_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_49 Register DESC3_2_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_49 0x2FD2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_49 0x190EFD2Cu //! Register Reset Value #define DESC3_2_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_49 Register DESC0_3_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_49 0x2FD30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_49 0x190EFD30u //! Register Reset Value #define DESC0_3_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_49 Register DESC1_3_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_49 0x2FD34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_49 0x190EFD34u //! Register Reset Value #define DESC1_3_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_49 Register DESC2_3_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_49 0x2FD38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_49 0x190EFD38u //! Register Reset Value #define DESC2_3_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_49 Register DESC3_3_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_49 0x2FD3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_49 0x190EFD3Cu //! Register Reset Value #define DESC3_3_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_49 Register DESC0_4_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_49 0x2FD40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_49 0x190EFD40u //! Register Reset Value #define DESC0_4_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_49 Register DESC1_4_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_49 0x2FD44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_49 0x190EFD44u //! Register Reset Value #define DESC1_4_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_49 Register DESC2_4_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_49 0x2FD48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_49 0x190EFD48u //! Register Reset Value #define DESC2_4_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_49 Register DESC3_4_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_49 0x2FD4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_49 0x190EFD4Cu //! Register Reset Value #define DESC3_4_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_49 Register DESC0_5_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_49 0x2FD50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_49 0x190EFD50u //! Register Reset Value #define DESC0_5_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_49 Register DESC1_5_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_49 0x2FD54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_49 0x190EFD54u //! Register Reset Value #define DESC1_5_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_49 Register DESC2_5_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_49 0x2FD58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_49 0x190EFD58u //! Register Reset Value #define DESC2_5_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_49 Register DESC3_5_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_49 0x2FD5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_49 0x190EFD5Cu //! Register Reset Value #define DESC3_5_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_49 Register DESC0_6_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_49 0x2FD60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_49 0x190EFD60u //! Register Reset Value #define DESC0_6_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_49 Register DESC1_6_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_49 0x2FD64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_49 0x190EFD64u //! Register Reset Value #define DESC1_6_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_49 Register DESC2_6_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_49 0x2FD68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_49 0x190EFD68u //! Register Reset Value #define DESC2_6_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_49 Register DESC3_6_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_49 0x2FD6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_49 0x190EFD6Cu //! Register Reset Value #define DESC3_6_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_49 Register DESC0_7_PON_EGP_49 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_49 0x2FD70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_49 0x190EFD70u //! Register Reset Value #define DESC0_7_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_49 Register DESC1_7_PON_EGP_49 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_49 0x2FD74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_49 0x190EFD74u //! Register Reset Value #define DESC1_7_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_49 Register DESC2_7_PON_EGP_49 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_49 0x2FD78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_49 0x190EFD78u //! Register Reset Value #define DESC2_7_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_49 Register DESC3_7_PON_EGP_49 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_49 0x2FD7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_49 0x190EFD7Cu //! Register Reset Value #define DESC3_7_PON_EGP_49_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_49_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_49_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_49 Register DESC0_0_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_49 0x2FE00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_49 0x190EFE00u //! Register Reset Value #define DESC0_0_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_49 Register DESC1_0_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_49 0x2FE04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_49 0x190EFE04u //! Register Reset Value #define DESC1_0_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_49 Register DESC2_0_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_49 0x2FE08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_49 0x190EFE08u //! Register Reset Value #define DESC2_0_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_49 Register DESC3_0_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_49 0x2FE0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_49 0x190EFE0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_49 Register DESC0_1_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_49 0x2FE10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_49 0x190EFE10u //! Register Reset Value #define DESC0_1_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_49 Register DESC1_1_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_49 0x2FE14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_49 0x190EFE14u //! Register Reset Value #define DESC1_1_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_49 Register DESC2_1_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_49 0x2FE18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_49 0x190EFE18u //! Register Reset Value #define DESC2_1_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_49 Register DESC3_1_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_49 0x2FE1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_49 0x190EFE1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_49 Register DESC0_2_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_49 0x2FE20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_49 0x190EFE20u //! Register Reset Value #define DESC0_2_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_49 Register DESC1_2_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_49 0x2FE24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_49 0x190EFE24u //! Register Reset Value #define DESC1_2_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_49 Register DESC2_2_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_49 0x2FE28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_49 0x190EFE28u //! Register Reset Value #define DESC2_2_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_49 Register DESC3_2_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_49 0x2FE2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_49 0x190EFE2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_49 Register DESC0_3_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_49 0x2FE30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_49 0x190EFE30u //! Register Reset Value #define DESC0_3_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_49 Register DESC1_3_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_49 0x2FE34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_49 0x190EFE34u //! Register Reset Value #define DESC1_3_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_49 Register DESC2_3_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_49 0x2FE38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_49 0x190EFE38u //! Register Reset Value #define DESC2_3_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_49 Register DESC3_3_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_49 0x2FE3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_49 0x190EFE3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_49 Register DESC0_4_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_49 0x2FE40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_49 0x190EFE40u //! Register Reset Value #define DESC0_4_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_49 Register DESC1_4_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_49 0x2FE44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_49 0x190EFE44u //! Register Reset Value #define DESC1_4_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_49 Register DESC2_4_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_49 0x2FE48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_49 0x190EFE48u //! Register Reset Value #define DESC2_4_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_49 Register DESC3_4_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_49 0x2FE4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_49 0x190EFE4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_49 Register DESC0_5_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_49 0x2FE50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_49 0x190EFE50u //! Register Reset Value #define DESC0_5_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_49 Register DESC1_5_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_49 0x2FE54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_49 0x190EFE54u //! Register Reset Value #define DESC1_5_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_49 Register DESC2_5_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_49 0x2FE58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_49 0x190EFE58u //! Register Reset Value #define DESC2_5_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_49 Register DESC3_5_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_49 0x2FE5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_49 0x190EFE5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_49 Register DESC0_6_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_49 0x2FE60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_49 0x190EFE60u //! Register Reset Value #define DESC0_6_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_49 Register DESC1_6_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_49 0x2FE64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_49 0x190EFE64u //! Register Reset Value #define DESC1_6_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_49 Register DESC2_6_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_49 0x2FE68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_49 0x190EFE68u //! Register Reset Value #define DESC2_6_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_49 Register DESC3_6_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_49 0x2FE6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_49 0x190EFE6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_49 Register DESC0_7_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_49 0x2FE70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_49 0x190EFE70u //! Register Reset Value #define DESC0_7_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_49 Register DESC1_7_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_49 0x2FE74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_49 0x190EFE74u //! Register Reset Value #define DESC1_7_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_49 Register DESC2_7_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_49 0x2FE78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_49 0x190EFE78u //! Register Reset Value #define DESC2_7_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_49_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_49 Register DESC3_7_PON_EGP_S_49 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_49 0x2FE7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_49 0x190EFE7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_49_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_49_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_49_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_49_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_49_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_50 Register CFG_PON_EGP_50 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_50 0x30000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_50 0x190F0000u //! Register Reset Value #define CFG_PON_EGP_50_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_50_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_50_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_50_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_50_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_50_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_50_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_50_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_50_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_50_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_50_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_50 Register IRNCR_PON_EGP_50 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_50 0x30020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_50 0x190F0020u //! Register Reset Value #define IRNCR_PON_EGP_50_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_50_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_50_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_50_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_50_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_50 Register IRNICR_PON_EGP_50 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_50 0x30024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_50 0x190F0024u //! Register Reset Value #define IRNICR_PON_EGP_50_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_50_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_50_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_50 Register IRNEN_PON_EGP_50 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_50 0x30028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_50 0x190F0028u //! Register Reset Value #define IRNEN_PON_EGP_50_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_50_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_50_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_50_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_50_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_50 Register DPTR_PON_EGP_50 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_50 0x30030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_50 0x190F0030u //! Register Reset Value #define DPTR_PON_EGP_50_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_50_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_50_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_50_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_50_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_50_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_50_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_50_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_50_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_50 Register DESC0_0_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_50 0x30100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_50 0x190F0100u //! Register Reset Value #define DESC0_0_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_50 Register DESC1_0_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_50 0x30104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_50 0x190F0104u //! Register Reset Value #define DESC1_0_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_50 Register DESC2_0_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_50 0x30108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_50 0x190F0108u //! Register Reset Value #define DESC2_0_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_50 Register DESC3_0_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_50 0x3010C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_50 0x190F010Cu //! Register Reset Value #define DESC3_0_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_50 Register DESC0_1_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_50 0x30110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_50 0x190F0110u //! Register Reset Value #define DESC0_1_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_50 Register DESC1_1_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_50 0x30114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_50 0x190F0114u //! Register Reset Value #define DESC1_1_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_50 Register DESC2_1_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_50 0x30118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_50 0x190F0118u //! Register Reset Value #define DESC2_1_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_50 Register DESC3_1_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_50 0x3011C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_50 0x190F011Cu //! Register Reset Value #define DESC3_1_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_50 Register DESC0_2_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_50 0x30120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_50 0x190F0120u //! Register Reset Value #define DESC0_2_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_50 Register DESC1_2_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_50 0x30124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_50 0x190F0124u //! Register Reset Value #define DESC1_2_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_50 Register DESC2_2_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_50 0x30128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_50 0x190F0128u //! Register Reset Value #define DESC2_2_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_50 Register DESC3_2_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_50 0x3012C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_50 0x190F012Cu //! Register Reset Value #define DESC3_2_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_50 Register DESC0_3_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_50 0x30130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_50 0x190F0130u //! Register Reset Value #define DESC0_3_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_50 Register DESC1_3_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_50 0x30134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_50 0x190F0134u //! Register Reset Value #define DESC1_3_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_50 Register DESC2_3_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_50 0x30138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_50 0x190F0138u //! Register Reset Value #define DESC2_3_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_50 Register DESC3_3_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_50 0x3013C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_50 0x190F013Cu //! Register Reset Value #define DESC3_3_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_50 Register DESC0_4_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_50 0x30140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_50 0x190F0140u //! Register Reset Value #define DESC0_4_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_50 Register DESC1_4_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_50 0x30144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_50 0x190F0144u //! Register Reset Value #define DESC1_4_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_50 Register DESC2_4_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_50 0x30148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_50 0x190F0148u //! Register Reset Value #define DESC2_4_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_50 Register DESC3_4_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_50 0x3014C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_50 0x190F014Cu //! Register Reset Value #define DESC3_4_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_50 Register DESC0_5_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_50 0x30150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_50 0x190F0150u //! Register Reset Value #define DESC0_5_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_50 Register DESC1_5_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_50 0x30154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_50 0x190F0154u //! Register Reset Value #define DESC1_5_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_50 Register DESC2_5_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_50 0x30158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_50 0x190F0158u //! Register Reset Value #define DESC2_5_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_50 Register DESC3_5_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_50 0x3015C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_50 0x190F015Cu //! Register Reset Value #define DESC3_5_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_50 Register DESC0_6_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_50 0x30160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_50 0x190F0160u //! Register Reset Value #define DESC0_6_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_50 Register DESC1_6_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_50 0x30164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_50 0x190F0164u //! Register Reset Value #define DESC1_6_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_50 Register DESC2_6_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_50 0x30168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_50 0x190F0168u //! Register Reset Value #define DESC2_6_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_50 Register DESC3_6_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_50 0x3016C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_50 0x190F016Cu //! Register Reset Value #define DESC3_6_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_50 Register DESC0_7_PON_EGP_50 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_50 0x30170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_50 0x190F0170u //! Register Reset Value #define DESC0_7_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_50 Register DESC1_7_PON_EGP_50 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_50 0x30174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_50 0x190F0174u //! Register Reset Value #define DESC1_7_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_50 Register DESC2_7_PON_EGP_50 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_50 0x30178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_50 0x190F0178u //! Register Reset Value #define DESC2_7_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_50 Register DESC3_7_PON_EGP_50 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_50 0x3017C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_50 0x190F017Cu //! Register Reset Value #define DESC3_7_PON_EGP_50_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_50_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_50_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_50 Register DESC0_0_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_50 0x30200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_50 0x190F0200u //! Register Reset Value #define DESC0_0_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_50 Register DESC1_0_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_50 0x30204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_50 0x190F0204u //! Register Reset Value #define DESC1_0_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_50 Register DESC2_0_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_50 0x30208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_50 0x190F0208u //! Register Reset Value #define DESC2_0_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_50 Register DESC3_0_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_50 0x3020C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_50 0x190F020Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_50 Register DESC0_1_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_50 0x30210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_50 0x190F0210u //! Register Reset Value #define DESC0_1_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_50 Register DESC1_1_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_50 0x30214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_50 0x190F0214u //! Register Reset Value #define DESC1_1_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_50 Register DESC2_1_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_50 0x30218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_50 0x190F0218u //! Register Reset Value #define DESC2_1_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_50 Register DESC3_1_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_50 0x3021C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_50 0x190F021Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_50 Register DESC0_2_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_50 0x30220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_50 0x190F0220u //! Register Reset Value #define DESC0_2_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_50 Register DESC1_2_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_50 0x30224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_50 0x190F0224u //! Register Reset Value #define DESC1_2_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_50 Register DESC2_2_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_50 0x30228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_50 0x190F0228u //! Register Reset Value #define DESC2_2_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_50 Register DESC3_2_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_50 0x3022C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_50 0x190F022Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_50 Register DESC0_3_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_50 0x30230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_50 0x190F0230u //! Register Reset Value #define DESC0_3_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_50 Register DESC1_3_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_50 0x30234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_50 0x190F0234u //! Register Reset Value #define DESC1_3_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_50 Register DESC2_3_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_50 0x30238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_50 0x190F0238u //! Register Reset Value #define DESC2_3_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_50 Register DESC3_3_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_50 0x3023C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_50 0x190F023Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_50 Register DESC0_4_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_50 0x30240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_50 0x190F0240u //! Register Reset Value #define DESC0_4_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_50 Register DESC1_4_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_50 0x30244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_50 0x190F0244u //! Register Reset Value #define DESC1_4_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_50 Register DESC2_4_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_50 0x30248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_50 0x190F0248u //! Register Reset Value #define DESC2_4_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_50 Register DESC3_4_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_50 0x3024C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_50 0x190F024Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_50 Register DESC0_5_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_50 0x30250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_50 0x190F0250u //! Register Reset Value #define DESC0_5_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_50 Register DESC1_5_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_50 0x30254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_50 0x190F0254u //! Register Reset Value #define DESC1_5_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_50 Register DESC2_5_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_50 0x30258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_50 0x190F0258u //! Register Reset Value #define DESC2_5_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_50 Register DESC3_5_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_50 0x3025C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_50 0x190F025Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_50 Register DESC0_6_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_50 0x30260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_50 0x190F0260u //! Register Reset Value #define DESC0_6_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_50 Register DESC1_6_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_50 0x30264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_50 0x190F0264u //! Register Reset Value #define DESC1_6_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_50 Register DESC2_6_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_50 0x30268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_50 0x190F0268u //! Register Reset Value #define DESC2_6_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_50 Register DESC3_6_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_50 0x3026C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_50 0x190F026Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_50 Register DESC0_7_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_50 0x30270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_50 0x190F0270u //! Register Reset Value #define DESC0_7_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_50 Register DESC1_7_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_50 0x30274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_50 0x190F0274u //! Register Reset Value #define DESC1_7_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_50 Register DESC2_7_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_50 0x30278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_50 0x190F0278u //! Register Reset Value #define DESC2_7_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_50_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_50 Register DESC3_7_PON_EGP_S_50 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_50 0x3027C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_50 0x190F027Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_50_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_50_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_50_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_50_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_50_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_51 Register CFG_PON_EGP_51 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_51 0x30400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_51 0x190F0400u //! Register Reset Value #define CFG_PON_EGP_51_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_51_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_51_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_51_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_51_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_51_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_51_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_51_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_51_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_51_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_51_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_51 Register IRNCR_PON_EGP_51 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_51 0x30420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_51 0x190F0420u //! Register Reset Value #define IRNCR_PON_EGP_51_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_51_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_51_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_51_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_51_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_51 Register IRNICR_PON_EGP_51 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_51 0x30424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_51 0x190F0424u //! Register Reset Value #define IRNICR_PON_EGP_51_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_51_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_51_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_51 Register IRNEN_PON_EGP_51 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_51 0x30428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_51 0x190F0428u //! Register Reset Value #define IRNEN_PON_EGP_51_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_51_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_51_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_51_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_51_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_51 Register DPTR_PON_EGP_51 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_51 0x30430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_51 0x190F0430u //! Register Reset Value #define DPTR_PON_EGP_51_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_51_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_51_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_51_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_51_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_51_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_51_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_51_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_51_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_51 Register DESC0_0_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_51 0x30500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_51 0x190F0500u //! Register Reset Value #define DESC0_0_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_51 Register DESC1_0_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_51 0x30504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_51 0x190F0504u //! Register Reset Value #define DESC1_0_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_51 Register DESC2_0_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_51 0x30508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_51 0x190F0508u //! Register Reset Value #define DESC2_0_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_51 Register DESC3_0_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_51 0x3050C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_51 0x190F050Cu //! Register Reset Value #define DESC3_0_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_51 Register DESC0_1_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_51 0x30510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_51 0x190F0510u //! Register Reset Value #define DESC0_1_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_51 Register DESC1_1_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_51 0x30514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_51 0x190F0514u //! Register Reset Value #define DESC1_1_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_51 Register DESC2_1_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_51 0x30518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_51 0x190F0518u //! Register Reset Value #define DESC2_1_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_51 Register DESC3_1_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_51 0x3051C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_51 0x190F051Cu //! Register Reset Value #define DESC3_1_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_51 Register DESC0_2_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_51 0x30520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_51 0x190F0520u //! Register Reset Value #define DESC0_2_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_51 Register DESC1_2_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_51 0x30524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_51 0x190F0524u //! Register Reset Value #define DESC1_2_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_51 Register DESC2_2_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_51 0x30528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_51 0x190F0528u //! Register Reset Value #define DESC2_2_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_51 Register DESC3_2_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_51 0x3052C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_51 0x190F052Cu //! Register Reset Value #define DESC3_2_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_51 Register DESC0_3_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_51 0x30530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_51 0x190F0530u //! Register Reset Value #define DESC0_3_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_51 Register DESC1_3_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_51 0x30534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_51 0x190F0534u //! Register Reset Value #define DESC1_3_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_51 Register DESC2_3_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_51 0x30538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_51 0x190F0538u //! Register Reset Value #define DESC2_3_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_51 Register DESC3_3_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_51 0x3053C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_51 0x190F053Cu //! Register Reset Value #define DESC3_3_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_51 Register DESC0_4_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_51 0x30540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_51 0x190F0540u //! Register Reset Value #define DESC0_4_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_51 Register DESC1_4_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_51 0x30544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_51 0x190F0544u //! Register Reset Value #define DESC1_4_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_51 Register DESC2_4_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_51 0x30548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_51 0x190F0548u //! Register Reset Value #define DESC2_4_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_51 Register DESC3_4_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_51 0x3054C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_51 0x190F054Cu //! Register Reset Value #define DESC3_4_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_51 Register DESC0_5_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_51 0x30550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_51 0x190F0550u //! Register Reset Value #define DESC0_5_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_51 Register DESC1_5_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_51 0x30554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_51 0x190F0554u //! Register Reset Value #define DESC1_5_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_51 Register DESC2_5_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_51 0x30558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_51 0x190F0558u //! Register Reset Value #define DESC2_5_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_51 Register DESC3_5_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_51 0x3055C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_51 0x190F055Cu //! Register Reset Value #define DESC3_5_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_51 Register DESC0_6_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_51 0x30560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_51 0x190F0560u //! Register Reset Value #define DESC0_6_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_51 Register DESC1_6_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_51 0x30564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_51 0x190F0564u //! Register Reset Value #define DESC1_6_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_51 Register DESC2_6_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_51 0x30568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_51 0x190F0568u //! Register Reset Value #define DESC2_6_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_51 Register DESC3_6_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_51 0x3056C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_51 0x190F056Cu //! Register Reset Value #define DESC3_6_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_51 Register DESC0_7_PON_EGP_51 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_51 0x30570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_51 0x190F0570u //! Register Reset Value #define DESC0_7_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_51 Register DESC1_7_PON_EGP_51 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_51 0x30574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_51 0x190F0574u //! Register Reset Value #define DESC1_7_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_51 Register DESC2_7_PON_EGP_51 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_51 0x30578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_51 0x190F0578u //! Register Reset Value #define DESC2_7_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_51 Register DESC3_7_PON_EGP_51 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_51 0x3057C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_51 0x190F057Cu //! Register Reset Value #define DESC3_7_PON_EGP_51_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_51_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_51_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_51 Register DESC0_0_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_51 0x30600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_51 0x190F0600u //! Register Reset Value #define DESC0_0_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_51 Register DESC1_0_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_51 0x30604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_51 0x190F0604u //! Register Reset Value #define DESC1_0_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_51 Register DESC2_0_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_51 0x30608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_51 0x190F0608u //! Register Reset Value #define DESC2_0_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_51 Register DESC3_0_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_51 0x3060C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_51 0x190F060Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_51 Register DESC0_1_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_51 0x30610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_51 0x190F0610u //! Register Reset Value #define DESC0_1_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_51 Register DESC1_1_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_51 0x30614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_51 0x190F0614u //! Register Reset Value #define DESC1_1_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_51 Register DESC2_1_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_51 0x30618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_51 0x190F0618u //! Register Reset Value #define DESC2_1_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_51 Register DESC3_1_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_51 0x3061C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_51 0x190F061Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_51 Register DESC0_2_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_51 0x30620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_51 0x190F0620u //! Register Reset Value #define DESC0_2_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_51 Register DESC1_2_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_51 0x30624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_51 0x190F0624u //! Register Reset Value #define DESC1_2_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_51 Register DESC2_2_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_51 0x30628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_51 0x190F0628u //! Register Reset Value #define DESC2_2_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_51 Register DESC3_2_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_51 0x3062C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_51 0x190F062Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_51 Register DESC0_3_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_51 0x30630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_51 0x190F0630u //! Register Reset Value #define DESC0_3_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_51 Register DESC1_3_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_51 0x30634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_51 0x190F0634u //! Register Reset Value #define DESC1_3_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_51 Register DESC2_3_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_51 0x30638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_51 0x190F0638u //! Register Reset Value #define DESC2_3_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_51 Register DESC3_3_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_51 0x3063C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_51 0x190F063Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_51 Register DESC0_4_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_51 0x30640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_51 0x190F0640u //! Register Reset Value #define DESC0_4_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_51 Register DESC1_4_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_51 0x30644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_51 0x190F0644u //! Register Reset Value #define DESC1_4_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_51 Register DESC2_4_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_51 0x30648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_51 0x190F0648u //! Register Reset Value #define DESC2_4_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_51 Register DESC3_4_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_51 0x3064C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_51 0x190F064Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_51 Register DESC0_5_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_51 0x30650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_51 0x190F0650u //! Register Reset Value #define DESC0_5_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_51 Register DESC1_5_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_51 0x30654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_51 0x190F0654u //! Register Reset Value #define DESC1_5_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_51 Register DESC2_5_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_51 0x30658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_51 0x190F0658u //! Register Reset Value #define DESC2_5_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_51 Register DESC3_5_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_51 0x3065C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_51 0x190F065Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_51 Register DESC0_6_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_51 0x30660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_51 0x190F0660u //! Register Reset Value #define DESC0_6_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_51 Register DESC1_6_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_51 0x30664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_51 0x190F0664u //! Register Reset Value #define DESC1_6_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_51 Register DESC2_6_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_51 0x30668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_51 0x190F0668u //! Register Reset Value #define DESC2_6_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_51 Register DESC3_6_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_51 0x3066C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_51 0x190F066Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_51 Register DESC0_7_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_51 0x30670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_51 0x190F0670u //! Register Reset Value #define DESC0_7_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_51 Register DESC1_7_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_51 0x30674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_51 0x190F0674u //! Register Reset Value #define DESC1_7_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_51 Register DESC2_7_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_51 0x30678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_51 0x190F0678u //! Register Reset Value #define DESC2_7_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_51_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_51 Register DESC3_7_PON_EGP_S_51 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_51 0x3067C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_51 0x190F067Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_51_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_51_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_51_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_51_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_51_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_52 Register CFG_PON_EGP_52 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_52 0x30800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_52 0x190F0800u //! Register Reset Value #define CFG_PON_EGP_52_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_52_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_52_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_52_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_52_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_52_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_52_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_52_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_52_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_52_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_52_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_52 Register IRNCR_PON_EGP_52 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_52 0x30820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_52 0x190F0820u //! Register Reset Value #define IRNCR_PON_EGP_52_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_52_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_52_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_52_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_52_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_52 Register IRNICR_PON_EGP_52 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_52 0x30824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_52 0x190F0824u //! Register Reset Value #define IRNICR_PON_EGP_52_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_52_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_52_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_52 Register IRNEN_PON_EGP_52 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_52 0x30828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_52 0x190F0828u //! Register Reset Value #define IRNEN_PON_EGP_52_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_52_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_52_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_52_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_52_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_52 Register DPTR_PON_EGP_52 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_52 0x30830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_52 0x190F0830u //! Register Reset Value #define DPTR_PON_EGP_52_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_52_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_52_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_52_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_52_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_52_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_52_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_52_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_52_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_52 Register DESC0_0_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_52 0x30900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_52 0x190F0900u //! Register Reset Value #define DESC0_0_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_52 Register DESC1_0_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_52 0x30904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_52 0x190F0904u //! Register Reset Value #define DESC1_0_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_52 Register DESC2_0_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_52 0x30908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_52 0x190F0908u //! Register Reset Value #define DESC2_0_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_52 Register DESC3_0_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_52 0x3090C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_52 0x190F090Cu //! Register Reset Value #define DESC3_0_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_52 Register DESC0_1_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_52 0x30910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_52 0x190F0910u //! Register Reset Value #define DESC0_1_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_52 Register DESC1_1_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_52 0x30914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_52 0x190F0914u //! Register Reset Value #define DESC1_1_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_52 Register DESC2_1_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_52 0x30918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_52 0x190F0918u //! Register Reset Value #define DESC2_1_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_52 Register DESC3_1_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_52 0x3091C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_52 0x190F091Cu //! Register Reset Value #define DESC3_1_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_52 Register DESC0_2_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_52 0x30920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_52 0x190F0920u //! Register Reset Value #define DESC0_2_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_52 Register DESC1_2_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_52 0x30924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_52 0x190F0924u //! Register Reset Value #define DESC1_2_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_52 Register DESC2_2_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_52 0x30928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_52 0x190F0928u //! Register Reset Value #define DESC2_2_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_52 Register DESC3_2_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_52 0x3092C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_52 0x190F092Cu //! Register Reset Value #define DESC3_2_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_52 Register DESC0_3_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_52 0x30930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_52 0x190F0930u //! Register Reset Value #define DESC0_3_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_52 Register DESC1_3_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_52 0x30934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_52 0x190F0934u //! Register Reset Value #define DESC1_3_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_52 Register DESC2_3_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_52 0x30938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_52 0x190F0938u //! Register Reset Value #define DESC2_3_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_52 Register DESC3_3_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_52 0x3093C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_52 0x190F093Cu //! Register Reset Value #define DESC3_3_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_52 Register DESC0_4_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_52 0x30940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_52 0x190F0940u //! Register Reset Value #define DESC0_4_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_52 Register DESC1_4_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_52 0x30944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_52 0x190F0944u //! Register Reset Value #define DESC1_4_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_52 Register DESC2_4_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_52 0x30948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_52 0x190F0948u //! Register Reset Value #define DESC2_4_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_52 Register DESC3_4_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_52 0x3094C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_52 0x190F094Cu //! Register Reset Value #define DESC3_4_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_52 Register DESC0_5_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_52 0x30950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_52 0x190F0950u //! Register Reset Value #define DESC0_5_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_52 Register DESC1_5_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_52 0x30954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_52 0x190F0954u //! Register Reset Value #define DESC1_5_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_52 Register DESC2_5_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_52 0x30958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_52 0x190F0958u //! Register Reset Value #define DESC2_5_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_52 Register DESC3_5_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_52 0x3095C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_52 0x190F095Cu //! Register Reset Value #define DESC3_5_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_52 Register DESC0_6_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_52 0x30960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_52 0x190F0960u //! Register Reset Value #define DESC0_6_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_52 Register DESC1_6_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_52 0x30964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_52 0x190F0964u //! Register Reset Value #define DESC1_6_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_52 Register DESC2_6_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_52 0x30968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_52 0x190F0968u //! Register Reset Value #define DESC2_6_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_52 Register DESC3_6_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_52 0x3096C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_52 0x190F096Cu //! Register Reset Value #define DESC3_6_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_52 Register DESC0_7_PON_EGP_52 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_52 0x30970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_52 0x190F0970u //! Register Reset Value #define DESC0_7_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_52 Register DESC1_7_PON_EGP_52 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_52 0x30974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_52 0x190F0974u //! Register Reset Value #define DESC1_7_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_52 Register DESC2_7_PON_EGP_52 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_52 0x30978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_52 0x190F0978u //! Register Reset Value #define DESC2_7_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_52 Register DESC3_7_PON_EGP_52 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_52 0x3097C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_52 0x190F097Cu //! Register Reset Value #define DESC3_7_PON_EGP_52_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_52_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_52_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_52 Register DESC0_0_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_52 0x30A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_52 0x190F0A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_52 Register DESC1_0_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_52 0x30A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_52 0x190F0A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_52 Register DESC2_0_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_52 0x30A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_52 0x190F0A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_52 Register DESC3_0_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_52 0x30A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_52 0x190F0A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_52 Register DESC0_1_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_52 0x30A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_52 0x190F0A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_52 Register DESC1_1_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_52 0x30A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_52 0x190F0A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_52 Register DESC2_1_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_52 0x30A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_52 0x190F0A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_52 Register DESC3_1_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_52 0x30A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_52 0x190F0A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_52 Register DESC0_2_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_52 0x30A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_52 0x190F0A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_52 Register DESC1_2_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_52 0x30A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_52 0x190F0A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_52 Register DESC2_2_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_52 0x30A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_52 0x190F0A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_52 Register DESC3_2_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_52 0x30A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_52 0x190F0A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_52 Register DESC0_3_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_52 0x30A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_52 0x190F0A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_52 Register DESC1_3_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_52 0x30A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_52 0x190F0A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_52 Register DESC2_3_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_52 0x30A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_52 0x190F0A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_52 Register DESC3_3_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_52 0x30A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_52 0x190F0A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_52 Register DESC0_4_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_52 0x30A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_52 0x190F0A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_52 Register DESC1_4_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_52 0x30A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_52 0x190F0A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_52 Register DESC2_4_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_52 0x30A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_52 0x190F0A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_52 Register DESC3_4_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_52 0x30A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_52 0x190F0A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_52 Register DESC0_5_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_52 0x30A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_52 0x190F0A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_52 Register DESC1_5_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_52 0x30A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_52 0x190F0A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_52 Register DESC2_5_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_52 0x30A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_52 0x190F0A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_52 Register DESC3_5_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_52 0x30A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_52 0x190F0A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_52 Register DESC0_6_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_52 0x30A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_52 0x190F0A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_52 Register DESC1_6_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_52 0x30A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_52 0x190F0A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_52 Register DESC2_6_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_52 0x30A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_52 0x190F0A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_52 Register DESC3_6_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_52 0x30A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_52 0x190F0A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_52 Register DESC0_7_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_52 0x30A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_52 0x190F0A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_52 Register DESC1_7_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_52 0x30A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_52 0x190F0A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_52 Register DESC2_7_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_52 0x30A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_52 0x190F0A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_52_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_52 Register DESC3_7_PON_EGP_S_52 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_52 0x30A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_52 0x190F0A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_52_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_52_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_52_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_52_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_52_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_53 Register CFG_PON_EGP_53 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_53 0x30C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_53 0x190F0C00u //! Register Reset Value #define CFG_PON_EGP_53_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_53_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_53_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_53_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_53_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_53_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_53_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_53_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_53_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_53_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_53_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_53 Register IRNCR_PON_EGP_53 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_53 0x30C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_53 0x190F0C20u //! Register Reset Value #define IRNCR_PON_EGP_53_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_53_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_53_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_53_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_53_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_53 Register IRNICR_PON_EGP_53 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_53 0x30C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_53 0x190F0C24u //! Register Reset Value #define IRNICR_PON_EGP_53_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_53_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_53_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_53 Register IRNEN_PON_EGP_53 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_53 0x30C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_53 0x190F0C28u //! Register Reset Value #define IRNEN_PON_EGP_53_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_53_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_53_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_53_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_53_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_53 Register DPTR_PON_EGP_53 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_53 0x30C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_53 0x190F0C30u //! Register Reset Value #define DPTR_PON_EGP_53_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_53_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_53_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_53_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_53_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_53_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_53_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_53_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_53_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_53 Register DESC0_0_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_53 0x30D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_53 0x190F0D00u //! Register Reset Value #define DESC0_0_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_53 Register DESC1_0_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_53 0x30D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_53 0x190F0D04u //! Register Reset Value #define DESC1_0_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_53 Register DESC2_0_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_53 0x30D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_53 0x190F0D08u //! Register Reset Value #define DESC2_0_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_53 Register DESC3_0_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_53 0x30D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_53 0x190F0D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_53 Register DESC0_1_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_53 0x30D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_53 0x190F0D10u //! Register Reset Value #define DESC0_1_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_53 Register DESC1_1_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_53 0x30D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_53 0x190F0D14u //! Register Reset Value #define DESC1_1_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_53 Register DESC2_1_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_53 0x30D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_53 0x190F0D18u //! Register Reset Value #define DESC2_1_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_53 Register DESC3_1_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_53 0x30D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_53 0x190F0D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_53 Register DESC0_2_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_53 0x30D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_53 0x190F0D20u //! Register Reset Value #define DESC0_2_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_53 Register DESC1_2_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_53 0x30D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_53 0x190F0D24u //! Register Reset Value #define DESC1_2_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_53 Register DESC2_2_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_53 0x30D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_53 0x190F0D28u //! Register Reset Value #define DESC2_2_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_53 Register DESC3_2_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_53 0x30D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_53 0x190F0D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_53 Register DESC0_3_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_53 0x30D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_53 0x190F0D30u //! Register Reset Value #define DESC0_3_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_53 Register DESC1_3_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_53 0x30D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_53 0x190F0D34u //! Register Reset Value #define DESC1_3_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_53 Register DESC2_3_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_53 0x30D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_53 0x190F0D38u //! Register Reset Value #define DESC2_3_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_53 Register DESC3_3_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_53 0x30D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_53 0x190F0D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_53 Register DESC0_4_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_53 0x30D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_53 0x190F0D40u //! Register Reset Value #define DESC0_4_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_53 Register DESC1_4_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_53 0x30D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_53 0x190F0D44u //! Register Reset Value #define DESC1_4_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_53 Register DESC2_4_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_53 0x30D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_53 0x190F0D48u //! Register Reset Value #define DESC2_4_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_53 Register DESC3_4_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_53 0x30D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_53 0x190F0D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_53 Register DESC0_5_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_53 0x30D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_53 0x190F0D50u //! Register Reset Value #define DESC0_5_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_53 Register DESC1_5_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_53 0x30D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_53 0x190F0D54u //! Register Reset Value #define DESC1_5_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_53 Register DESC2_5_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_53 0x30D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_53 0x190F0D58u //! Register Reset Value #define DESC2_5_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_53 Register DESC3_5_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_53 0x30D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_53 0x190F0D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_53 Register DESC0_6_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_53 0x30D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_53 0x190F0D60u //! Register Reset Value #define DESC0_6_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_53 Register DESC1_6_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_53 0x30D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_53 0x190F0D64u //! Register Reset Value #define DESC1_6_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_53 Register DESC2_6_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_53 0x30D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_53 0x190F0D68u //! Register Reset Value #define DESC2_6_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_53 Register DESC3_6_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_53 0x30D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_53 0x190F0D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_53 Register DESC0_7_PON_EGP_53 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_53 0x30D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_53 0x190F0D70u //! Register Reset Value #define DESC0_7_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_53 Register DESC1_7_PON_EGP_53 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_53 0x30D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_53 0x190F0D74u //! Register Reset Value #define DESC1_7_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_53 Register DESC2_7_PON_EGP_53 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_53 0x30D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_53 0x190F0D78u //! Register Reset Value #define DESC2_7_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_53 Register DESC3_7_PON_EGP_53 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_53 0x30D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_53 0x190F0D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_53_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_53_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_53_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_53 Register DESC0_0_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_53 0x30E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_53 0x190F0E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_53 Register DESC1_0_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_53 0x30E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_53 0x190F0E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_53 Register DESC2_0_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_53 0x30E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_53 0x190F0E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_53 Register DESC3_0_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_53 0x30E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_53 0x190F0E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_53 Register DESC0_1_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_53 0x30E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_53 0x190F0E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_53 Register DESC1_1_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_53 0x30E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_53 0x190F0E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_53 Register DESC2_1_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_53 0x30E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_53 0x190F0E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_53 Register DESC3_1_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_53 0x30E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_53 0x190F0E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_53 Register DESC0_2_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_53 0x30E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_53 0x190F0E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_53 Register DESC1_2_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_53 0x30E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_53 0x190F0E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_53 Register DESC2_2_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_53 0x30E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_53 0x190F0E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_53 Register DESC3_2_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_53 0x30E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_53 0x190F0E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_53 Register DESC0_3_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_53 0x30E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_53 0x190F0E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_53 Register DESC1_3_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_53 0x30E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_53 0x190F0E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_53 Register DESC2_3_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_53 0x30E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_53 0x190F0E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_53 Register DESC3_3_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_53 0x30E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_53 0x190F0E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_53 Register DESC0_4_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_53 0x30E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_53 0x190F0E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_53 Register DESC1_4_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_53 0x30E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_53 0x190F0E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_53 Register DESC2_4_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_53 0x30E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_53 0x190F0E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_53 Register DESC3_4_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_53 0x30E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_53 0x190F0E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_53 Register DESC0_5_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_53 0x30E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_53 0x190F0E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_53 Register DESC1_5_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_53 0x30E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_53 0x190F0E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_53 Register DESC2_5_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_53 0x30E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_53 0x190F0E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_53 Register DESC3_5_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_53 0x30E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_53 0x190F0E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_53 Register DESC0_6_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_53 0x30E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_53 0x190F0E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_53 Register DESC1_6_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_53 0x30E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_53 0x190F0E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_53 Register DESC2_6_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_53 0x30E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_53 0x190F0E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_53 Register DESC3_6_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_53 0x30E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_53 0x190F0E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_53 Register DESC0_7_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_53 0x30E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_53 0x190F0E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_53 Register DESC1_7_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_53 0x30E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_53 0x190F0E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_53 Register DESC2_7_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_53 0x30E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_53 0x190F0E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_53_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_53 Register DESC3_7_PON_EGP_S_53 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_53 0x30E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_53 0x190F0E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_53_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_53_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_53_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_53_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_53_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_54 Register CFG_PON_EGP_54 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_54 0x31000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_54 0x190F1000u //! Register Reset Value #define CFG_PON_EGP_54_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_54_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_54_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_54_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_54_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_54_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_54_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_54_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_54_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_54_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_54_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_54 Register IRNCR_PON_EGP_54 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_54 0x31020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_54 0x190F1020u //! Register Reset Value #define IRNCR_PON_EGP_54_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_54_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_54_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_54_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_54_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_54 Register IRNICR_PON_EGP_54 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_54 0x31024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_54 0x190F1024u //! Register Reset Value #define IRNICR_PON_EGP_54_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_54_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_54_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_54 Register IRNEN_PON_EGP_54 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_54 0x31028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_54 0x190F1028u //! Register Reset Value #define IRNEN_PON_EGP_54_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_54_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_54_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_54_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_54_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_54 Register DPTR_PON_EGP_54 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_54 0x31030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_54 0x190F1030u //! Register Reset Value #define DPTR_PON_EGP_54_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_54_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_54_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_54_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_54_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_54_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_54_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_54_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_54_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_54 Register DESC0_0_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_54 0x31100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_54 0x190F1100u //! Register Reset Value #define DESC0_0_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_54 Register DESC1_0_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_54 0x31104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_54 0x190F1104u //! Register Reset Value #define DESC1_0_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_54 Register DESC2_0_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_54 0x31108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_54 0x190F1108u //! Register Reset Value #define DESC2_0_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_54 Register DESC3_0_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_54 0x3110C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_54 0x190F110Cu //! Register Reset Value #define DESC3_0_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_54 Register DESC0_1_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_54 0x31110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_54 0x190F1110u //! Register Reset Value #define DESC0_1_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_54 Register DESC1_1_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_54 0x31114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_54 0x190F1114u //! Register Reset Value #define DESC1_1_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_54 Register DESC2_1_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_54 0x31118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_54 0x190F1118u //! Register Reset Value #define DESC2_1_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_54 Register DESC3_1_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_54 0x3111C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_54 0x190F111Cu //! Register Reset Value #define DESC3_1_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_54 Register DESC0_2_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_54 0x31120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_54 0x190F1120u //! Register Reset Value #define DESC0_2_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_54 Register DESC1_2_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_54 0x31124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_54 0x190F1124u //! Register Reset Value #define DESC1_2_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_54 Register DESC2_2_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_54 0x31128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_54 0x190F1128u //! Register Reset Value #define DESC2_2_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_54 Register DESC3_2_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_54 0x3112C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_54 0x190F112Cu //! Register Reset Value #define DESC3_2_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_54 Register DESC0_3_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_54 0x31130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_54 0x190F1130u //! Register Reset Value #define DESC0_3_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_54 Register DESC1_3_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_54 0x31134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_54 0x190F1134u //! Register Reset Value #define DESC1_3_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_54 Register DESC2_3_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_54 0x31138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_54 0x190F1138u //! Register Reset Value #define DESC2_3_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_54 Register DESC3_3_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_54 0x3113C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_54 0x190F113Cu //! Register Reset Value #define DESC3_3_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_54 Register DESC0_4_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_54 0x31140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_54 0x190F1140u //! Register Reset Value #define DESC0_4_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_54 Register DESC1_4_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_54 0x31144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_54 0x190F1144u //! Register Reset Value #define DESC1_4_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_54 Register DESC2_4_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_54 0x31148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_54 0x190F1148u //! Register Reset Value #define DESC2_4_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_54 Register DESC3_4_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_54 0x3114C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_54 0x190F114Cu //! Register Reset Value #define DESC3_4_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_54 Register DESC0_5_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_54 0x31150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_54 0x190F1150u //! Register Reset Value #define DESC0_5_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_54 Register DESC1_5_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_54 0x31154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_54 0x190F1154u //! Register Reset Value #define DESC1_5_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_54 Register DESC2_5_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_54 0x31158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_54 0x190F1158u //! Register Reset Value #define DESC2_5_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_54 Register DESC3_5_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_54 0x3115C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_54 0x190F115Cu //! Register Reset Value #define DESC3_5_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_54 Register DESC0_6_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_54 0x31160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_54 0x190F1160u //! Register Reset Value #define DESC0_6_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_54 Register DESC1_6_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_54 0x31164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_54 0x190F1164u //! Register Reset Value #define DESC1_6_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_54 Register DESC2_6_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_54 0x31168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_54 0x190F1168u //! Register Reset Value #define DESC2_6_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_54 Register DESC3_6_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_54 0x3116C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_54 0x190F116Cu //! Register Reset Value #define DESC3_6_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_54 Register DESC0_7_PON_EGP_54 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_54 0x31170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_54 0x190F1170u //! Register Reset Value #define DESC0_7_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_54 Register DESC1_7_PON_EGP_54 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_54 0x31174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_54 0x190F1174u //! Register Reset Value #define DESC1_7_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_54 Register DESC2_7_PON_EGP_54 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_54 0x31178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_54 0x190F1178u //! Register Reset Value #define DESC2_7_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_54 Register DESC3_7_PON_EGP_54 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_54 0x3117C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_54 0x190F117Cu //! Register Reset Value #define DESC3_7_PON_EGP_54_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_54_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_54_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_54 Register DESC0_0_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_54 0x31200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_54 0x190F1200u //! Register Reset Value #define DESC0_0_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_54 Register DESC1_0_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_54 0x31204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_54 0x190F1204u //! Register Reset Value #define DESC1_0_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_54 Register DESC2_0_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_54 0x31208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_54 0x190F1208u //! Register Reset Value #define DESC2_0_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_54 Register DESC3_0_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_54 0x3120C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_54 0x190F120Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_54 Register DESC0_1_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_54 0x31210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_54 0x190F1210u //! Register Reset Value #define DESC0_1_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_54 Register DESC1_1_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_54 0x31214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_54 0x190F1214u //! Register Reset Value #define DESC1_1_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_54 Register DESC2_1_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_54 0x31218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_54 0x190F1218u //! Register Reset Value #define DESC2_1_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_54 Register DESC3_1_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_54 0x3121C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_54 0x190F121Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_54 Register DESC0_2_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_54 0x31220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_54 0x190F1220u //! Register Reset Value #define DESC0_2_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_54 Register DESC1_2_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_54 0x31224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_54 0x190F1224u //! Register Reset Value #define DESC1_2_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_54 Register DESC2_2_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_54 0x31228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_54 0x190F1228u //! Register Reset Value #define DESC2_2_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_54 Register DESC3_2_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_54 0x3122C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_54 0x190F122Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_54 Register DESC0_3_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_54 0x31230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_54 0x190F1230u //! Register Reset Value #define DESC0_3_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_54 Register DESC1_3_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_54 0x31234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_54 0x190F1234u //! Register Reset Value #define DESC1_3_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_54 Register DESC2_3_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_54 0x31238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_54 0x190F1238u //! Register Reset Value #define DESC2_3_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_54 Register DESC3_3_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_54 0x3123C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_54 0x190F123Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_54 Register DESC0_4_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_54 0x31240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_54 0x190F1240u //! Register Reset Value #define DESC0_4_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_54 Register DESC1_4_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_54 0x31244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_54 0x190F1244u //! Register Reset Value #define DESC1_4_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_54 Register DESC2_4_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_54 0x31248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_54 0x190F1248u //! Register Reset Value #define DESC2_4_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_54 Register DESC3_4_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_54 0x3124C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_54 0x190F124Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_54 Register DESC0_5_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_54 0x31250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_54 0x190F1250u //! Register Reset Value #define DESC0_5_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_54 Register DESC1_5_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_54 0x31254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_54 0x190F1254u //! Register Reset Value #define DESC1_5_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_54 Register DESC2_5_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_54 0x31258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_54 0x190F1258u //! Register Reset Value #define DESC2_5_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_54 Register DESC3_5_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_54 0x3125C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_54 0x190F125Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_54 Register DESC0_6_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_54 0x31260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_54 0x190F1260u //! Register Reset Value #define DESC0_6_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_54 Register DESC1_6_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_54 0x31264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_54 0x190F1264u //! Register Reset Value #define DESC1_6_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_54 Register DESC2_6_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_54 0x31268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_54 0x190F1268u //! Register Reset Value #define DESC2_6_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_54 Register DESC3_6_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_54 0x3126C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_54 0x190F126Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_54 Register DESC0_7_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_54 0x31270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_54 0x190F1270u //! Register Reset Value #define DESC0_7_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_54 Register DESC1_7_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_54 0x31274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_54 0x190F1274u //! Register Reset Value #define DESC1_7_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_54 Register DESC2_7_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_54 0x31278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_54 0x190F1278u //! Register Reset Value #define DESC2_7_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_54_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_54 Register DESC3_7_PON_EGP_S_54 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_54 0x3127C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_54 0x190F127Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_54_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_54_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_54_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_54_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_54_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_55 Register CFG_PON_EGP_55 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_55 0x31400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_55 0x190F1400u //! Register Reset Value #define CFG_PON_EGP_55_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_55_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_55_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_55_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_55_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_55_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_55_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_55_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_55_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_55_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_55_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_55 Register IRNCR_PON_EGP_55 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_55 0x31420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_55 0x190F1420u //! Register Reset Value #define IRNCR_PON_EGP_55_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_55_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_55_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_55_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_55_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_55 Register IRNICR_PON_EGP_55 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_55 0x31424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_55 0x190F1424u //! Register Reset Value #define IRNICR_PON_EGP_55_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_55_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_55_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_55 Register IRNEN_PON_EGP_55 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_55 0x31428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_55 0x190F1428u //! Register Reset Value #define IRNEN_PON_EGP_55_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_55_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_55_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_55_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_55_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_55 Register DPTR_PON_EGP_55 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_55 0x31430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_55 0x190F1430u //! Register Reset Value #define DPTR_PON_EGP_55_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_55_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_55_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_55_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_55_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_55_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_55_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_55_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_55_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_55 Register DESC0_0_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_55 0x31500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_55 0x190F1500u //! Register Reset Value #define DESC0_0_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_55 Register DESC1_0_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_55 0x31504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_55 0x190F1504u //! Register Reset Value #define DESC1_0_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_55 Register DESC2_0_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_55 0x31508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_55 0x190F1508u //! Register Reset Value #define DESC2_0_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_55 Register DESC3_0_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_55 0x3150C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_55 0x190F150Cu //! Register Reset Value #define DESC3_0_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_55 Register DESC0_1_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_55 0x31510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_55 0x190F1510u //! Register Reset Value #define DESC0_1_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_55 Register DESC1_1_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_55 0x31514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_55 0x190F1514u //! Register Reset Value #define DESC1_1_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_55 Register DESC2_1_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_55 0x31518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_55 0x190F1518u //! Register Reset Value #define DESC2_1_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_55 Register DESC3_1_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_55 0x3151C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_55 0x190F151Cu //! Register Reset Value #define DESC3_1_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_55 Register DESC0_2_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_55 0x31520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_55 0x190F1520u //! Register Reset Value #define DESC0_2_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_55 Register DESC1_2_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_55 0x31524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_55 0x190F1524u //! Register Reset Value #define DESC1_2_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_55 Register DESC2_2_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_55 0x31528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_55 0x190F1528u //! Register Reset Value #define DESC2_2_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_55 Register DESC3_2_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_55 0x3152C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_55 0x190F152Cu //! Register Reset Value #define DESC3_2_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_55 Register DESC0_3_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_55 0x31530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_55 0x190F1530u //! Register Reset Value #define DESC0_3_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_55 Register DESC1_3_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_55 0x31534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_55 0x190F1534u //! Register Reset Value #define DESC1_3_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_55 Register DESC2_3_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_55 0x31538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_55 0x190F1538u //! Register Reset Value #define DESC2_3_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_55 Register DESC3_3_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_55 0x3153C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_55 0x190F153Cu //! Register Reset Value #define DESC3_3_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_55 Register DESC0_4_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_55 0x31540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_55 0x190F1540u //! Register Reset Value #define DESC0_4_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_55 Register DESC1_4_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_55 0x31544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_55 0x190F1544u //! Register Reset Value #define DESC1_4_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_55 Register DESC2_4_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_55 0x31548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_55 0x190F1548u //! Register Reset Value #define DESC2_4_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_55 Register DESC3_4_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_55 0x3154C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_55 0x190F154Cu //! Register Reset Value #define DESC3_4_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_55 Register DESC0_5_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_55 0x31550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_55 0x190F1550u //! Register Reset Value #define DESC0_5_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_55 Register DESC1_5_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_55 0x31554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_55 0x190F1554u //! Register Reset Value #define DESC1_5_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_55 Register DESC2_5_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_55 0x31558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_55 0x190F1558u //! Register Reset Value #define DESC2_5_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_55 Register DESC3_5_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_55 0x3155C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_55 0x190F155Cu //! Register Reset Value #define DESC3_5_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_55 Register DESC0_6_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_55 0x31560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_55 0x190F1560u //! Register Reset Value #define DESC0_6_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_55 Register DESC1_6_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_55 0x31564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_55 0x190F1564u //! Register Reset Value #define DESC1_6_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_55 Register DESC2_6_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_55 0x31568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_55 0x190F1568u //! Register Reset Value #define DESC2_6_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_55 Register DESC3_6_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_55 0x3156C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_55 0x190F156Cu //! Register Reset Value #define DESC3_6_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_55 Register DESC0_7_PON_EGP_55 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_55 0x31570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_55 0x190F1570u //! Register Reset Value #define DESC0_7_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_55 Register DESC1_7_PON_EGP_55 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_55 0x31574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_55 0x190F1574u //! Register Reset Value #define DESC1_7_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_55 Register DESC2_7_PON_EGP_55 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_55 0x31578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_55 0x190F1578u //! Register Reset Value #define DESC2_7_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_55 Register DESC3_7_PON_EGP_55 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_55 0x3157C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_55 0x190F157Cu //! Register Reset Value #define DESC3_7_PON_EGP_55_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_55_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_55_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_55 Register DESC0_0_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_55 0x31600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_55 0x190F1600u //! Register Reset Value #define DESC0_0_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_55 Register DESC1_0_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_55 0x31604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_55 0x190F1604u //! Register Reset Value #define DESC1_0_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_55 Register DESC2_0_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_55 0x31608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_55 0x190F1608u //! Register Reset Value #define DESC2_0_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_55 Register DESC3_0_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_55 0x3160C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_55 0x190F160Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_55 Register DESC0_1_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_55 0x31610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_55 0x190F1610u //! Register Reset Value #define DESC0_1_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_55 Register DESC1_1_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_55 0x31614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_55 0x190F1614u //! Register Reset Value #define DESC1_1_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_55 Register DESC2_1_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_55 0x31618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_55 0x190F1618u //! Register Reset Value #define DESC2_1_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_55 Register DESC3_1_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_55 0x3161C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_55 0x190F161Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_55 Register DESC0_2_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_55 0x31620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_55 0x190F1620u //! Register Reset Value #define DESC0_2_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_55 Register DESC1_2_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_55 0x31624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_55 0x190F1624u //! Register Reset Value #define DESC1_2_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_55 Register DESC2_2_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_55 0x31628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_55 0x190F1628u //! Register Reset Value #define DESC2_2_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_55 Register DESC3_2_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_55 0x3162C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_55 0x190F162Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_55 Register DESC0_3_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_55 0x31630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_55 0x190F1630u //! Register Reset Value #define DESC0_3_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_55 Register DESC1_3_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_55 0x31634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_55 0x190F1634u //! Register Reset Value #define DESC1_3_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_55 Register DESC2_3_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_55 0x31638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_55 0x190F1638u //! Register Reset Value #define DESC2_3_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_55 Register DESC3_3_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_55 0x3163C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_55 0x190F163Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_55 Register DESC0_4_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_55 0x31640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_55 0x190F1640u //! Register Reset Value #define DESC0_4_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_55 Register DESC1_4_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_55 0x31644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_55 0x190F1644u //! Register Reset Value #define DESC1_4_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_55 Register DESC2_4_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_55 0x31648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_55 0x190F1648u //! Register Reset Value #define DESC2_4_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_55 Register DESC3_4_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_55 0x3164C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_55 0x190F164Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_55 Register DESC0_5_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_55 0x31650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_55 0x190F1650u //! Register Reset Value #define DESC0_5_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_55 Register DESC1_5_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_55 0x31654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_55 0x190F1654u //! Register Reset Value #define DESC1_5_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_55 Register DESC2_5_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_55 0x31658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_55 0x190F1658u //! Register Reset Value #define DESC2_5_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_55 Register DESC3_5_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_55 0x3165C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_55 0x190F165Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_55 Register DESC0_6_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_55 0x31660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_55 0x190F1660u //! Register Reset Value #define DESC0_6_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_55 Register DESC1_6_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_55 0x31664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_55 0x190F1664u //! Register Reset Value #define DESC1_6_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_55 Register DESC2_6_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_55 0x31668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_55 0x190F1668u //! Register Reset Value #define DESC2_6_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_55 Register DESC3_6_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_55 0x3166C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_55 0x190F166Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_55 Register DESC0_7_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_55 0x31670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_55 0x190F1670u //! Register Reset Value #define DESC0_7_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_55 Register DESC1_7_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_55 0x31674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_55 0x190F1674u //! Register Reset Value #define DESC1_7_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_55 Register DESC2_7_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_55 0x31678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_55 0x190F1678u //! Register Reset Value #define DESC2_7_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_55_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_55 Register DESC3_7_PON_EGP_S_55 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_55 0x3167C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_55 0x190F167Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_55_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_55_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_55_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_55_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_55_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_56 Register CFG_PON_EGP_56 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_56 0x31800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_56 0x190F1800u //! Register Reset Value #define CFG_PON_EGP_56_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_56_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_56_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_56_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_56_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_56_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_56_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_56_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_56_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_56_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_56_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_56 Register IRNCR_PON_EGP_56 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_56 0x31820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_56 0x190F1820u //! Register Reset Value #define IRNCR_PON_EGP_56_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_56_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_56_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_56_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_56_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_56 Register IRNICR_PON_EGP_56 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_56 0x31824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_56 0x190F1824u //! Register Reset Value #define IRNICR_PON_EGP_56_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_56_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_56_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_56 Register IRNEN_PON_EGP_56 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_56 0x31828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_56 0x190F1828u //! Register Reset Value #define IRNEN_PON_EGP_56_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_56_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_56_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_56_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_56_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_56 Register DPTR_PON_EGP_56 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_56 0x31830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_56 0x190F1830u //! Register Reset Value #define DPTR_PON_EGP_56_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_56_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_56_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_56_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_56_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_56_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_56_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_56_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_56_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_56 Register DESC0_0_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_56 0x31900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_56 0x190F1900u //! Register Reset Value #define DESC0_0_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_56 Register DESC1_0_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_56 0x31904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_56 0x190F1904u //! Register Reset Value #define DESC1_0_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_56 Register DESC2_0_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_56 0x31908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_56 0x190F1908u //! Register Reset Value #define DESC2_0_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_56 Register DESC3_0_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_56 0x3190C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_56 0x190F190Cu //! Register Reset Value #define DESC3_0_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_56 Register DESC0_1_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_56 0x31910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_56 0x190F1910u //! Register Reset Value #define DESC0_1_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_56 Register DESC1_1_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_56 0x31914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_56 0x190F1914u //! Register Reset Value #define DESC1_1_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_56 Register DESC2_1_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_56 0x31918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_56 0x190F1918u //! Register Reset Value #define DESC2_1_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_56 Register DESC3_1_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_56 0x3191C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_56 0x190F191Cu //! Register Reset Value #define DESC3_1_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_56 Register DESC0_2_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_56 0x31920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_56 0x190F1920u //! Register Reset Value #define DESC0_2_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_56 Register DESC1_2_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_56 0x31924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_56 0x190F1924u //! Register Reset Value #define DESC1_2_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_56 Register DESC2_2_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_56 0x31928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_56 0x190F1928u //! Register Reset Value #define DESC2_2_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_56 Register DESC3_2_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_56 0x3192C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_56 0x190F192Cu //! Register Reset Value #define DESC3_2_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_56 Register DESC0_3_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_56 0x31930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_56 0x190F1930u //! Register Reset Value #define DESC0_3_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_56 Register DESC1_3_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_56 0x31934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_56 0x190F1934u //! Register Reset Value #define DESC1_3_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_56 Register DESC2_3_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_56 0x31938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_56 0x190F1938u //! Register Reset Value #define DESC2_3_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_56 Register DESC3_3_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_56 0x3193C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_56 0x190F193Cu //! Register Reset Value #define DESC3_3_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_56 Register DESC0_4_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_56 0x31940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_56 0x190F1940u //! Register Reset Value #define DESC0_4_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_56 Register DESC1_4_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_56 0x31944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_56 0x190F1944u //! Register Reset Value #define DESC1_4_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_56 Register DESC2_4_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_56 0x31948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_56 0x190F1948u //! Register Reset Value #define DESC2_4_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_56 Register DESC3_4_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_56 0x3194C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_56 0x190F194Cu //! Register Reset Value #define DESC3_4_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_56 Register DESC0_5_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_56 0x31950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_56 0x190F1950u //! Register Reset Value #define DESC0_5_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_56 Register DESC1_5_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_56 0x31954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_56 0x190F1954u //! Register Reset Value #define DESC1_5_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_56 Register DESC2_5_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_56 0x31958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_56 0x190F1958u //! Register Reset Value #define DESC2_5_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_56 Register DESC3_5_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_56 0x3195C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_56 0x190F195Cu //! Register Reset Value #define DESC3_5_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_56 Register DESC0_6_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_56 0x31960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_56 0x190F1960u //! Register Reset Value #define DESC0_6_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_56 Register DESC1_6_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_56 0x31964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_56 0x190F1964u //! Register Reset Value #define DESC1_6_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_56 Register DESC2_6_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_56 0x31968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_56 0x190F1968u //! Register Reset Value #define DESC2_6_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_56 Register DESC3_6_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_56 0x3196C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_56 0x190F196Cu //! Register Reset Value #define DESC3_6_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_56 Register DESC0_7_PON_EGP_56 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_56 0x31970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_56 0x190F1970u //! Register Reset Value #define DESC0_7_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_56 Register DESC1_7_PON_EGP_56 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_56 0x31974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_56 0x190F1974u //! Register Reset Value #define DESC1_7_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_56 Register DESC2_7_PON_EGP_56 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_56 0x31978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_56 0x190F1978u //! Register Reset Value #define DESC2_7_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_56 Register DESC3_7_PON_EGP_56 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_56 0x3197C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_56 0x190F197Cu //! Register Reset Value #define DESC3_7_PON_EGP_56_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_56_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_56_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_56 Register DESC0_0_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_56 0x31A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_56 0x190F1A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_56 Register DESC1_0_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_56 0x31A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_56 0x190F1A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_56 Register DESC2_0_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_56 0x31A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_56 0x190F1A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_56 Register DESC3_0_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_56 0x31A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_56 0x190F1A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_56 Register DESC0_1_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_56 0x31A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_56 0x190F1A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_56 Register DESC1_1_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_56 0x31A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_56 0x190F1A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_56 Register DESC2_1_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_56 0x31A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_56 0x190F1A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_56 Register DESC3_1_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_56 0x31A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_56 0x190F1A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_56 Register DESC0_2_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_56 0x31A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_56 0x190F1A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_56 Register DESC1_2_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_56 0x31A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_56 0x190F1A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_56 Register DESC2_2_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_56 0x31A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_56 0x190F1A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_56 Register DESC3_2_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_56 0x31A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_56 0x190F1A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_56 Register DESC0_3_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_56 0x31A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_56 0x190F1A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_56 Register DESC1_3_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_56 0x31A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_56 0x190F1A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_56 Register DESC2_3_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_56 0x31A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_56 0x190F1A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_56 Register DESC3_3_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_56 0x31A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_56 0x190F1A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_56 Register DESC0_4_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_56 0x31A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_56 0x190F1A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_56 Register DESC1_4_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_56 0x31A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_56 0x190F1A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_56 Register DESC2_4_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_56 0x31A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_56 0x190F1A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_56 Register DESC3_4_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_56 0x31A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_56 0x190F1A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_56 Register DESC0_5_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_56 0x31A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_56 0x190F1A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_56 Register DESC1_5_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_56 0x31A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_56 0x190F1A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_56 Register DESC2_5_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_56 0x31A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_56 0x190F1A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_56 Register DESC3_5_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_56 0x31A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_56 0x190F1A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_56 Register DESC0_6_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_56 0x31A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_56 0x190F1A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_56 Register DESC1_6_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_56 0x31A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_56 0x190F1A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_56 Register DESC2_6_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_56 0x31A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_56 0x190F1A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_56 Register DESC3_6_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_56 0x31A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_56 0x190F1A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_56 Register DESC0_7_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_56 0x31A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_56 0x190F1A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_56 Register DESC1_7_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_56 0x31A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_56 0x190F1A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_56 Register DESC2_7_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_56 0x31A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_56 0x190F1A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_56_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_56 Register DESC3_7_PON_EGP_S_56 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_56 0x31A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_56 0x190F1A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_56_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_56_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_56_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_56_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_56_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_57 Register CFG_PON_EGP_57 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_57 0x31C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_57 0x190F1C00u //! Register Reset Value #define CFG_PON_EGP_57_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_57_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_57_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_57_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_57_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_57_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_57_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_57_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_57_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_57_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_57_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_57 Register IRNCR_PON_EGP_57 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_57 0x31C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_57 0x190F1C20u //! Register Reset Value #define IRNCR_PON_EGP_57_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_57_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_57_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_57_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_57_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_57 Register IRNICR_PON_EGP_57 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_57 0x31C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_57 0x190F1C24u //! Register Reset Value #define IRNICR_PON_EGP_57_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_57_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_57_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_57 Register IRNEN_PON_EGP_57 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_57 0x31C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_57 0x190F1C28u //! Register Reset Value #define IRNEN_PON_EGP_57_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_57_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_57_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_57_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_57_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_57 Register DPTR_PON_EGP_57 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_57 0x31C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_57 0x190F1C30u //! Register Reset Value #define DPTR_PON_EGP_57_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_57_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_57_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_57_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_57_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_57_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_57_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_57_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_57_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_57 Register DESC0_0_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_57 0x31D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_57 0x190F1D00u //! Register Reset Value #define DESC0_0_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_57 Register DESC1_0_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_57 0x31D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_57 0x190F1D04u //! Register Reset Value #define DESC1_0_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_57 Register DESC2_0_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_57 0x31D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_57 0x190F1D08u //! Register Reset Value #define DESC2_0_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_57 Register DESC3_0_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_57 0x31D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_57 0x190F1D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_57 Register DESC0_1_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_57 0x31D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_57 0x190F1D10u //! Register Reset Value #define DESC0_1_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_57 Register DESC1_1_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_57 0x31D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_57 0x190F1D14u //! Register Reset Value #define DESC1_1_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_57 Register DESC2_1_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_57 0x31D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_57 0x190F1D18u //! Register Reset Value #define DESC2_1_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_57 Register DESC3_1_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_57 0x31D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_57 0x190F1D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_57 Register DESC0_2_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_57 0x31D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_57 0x190F1D20u //! Register Reset Value #define DESC0_2_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_57 Register DESC1_2_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_57 0x31D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_57 0x190F1D24u //! Register Reset Value #define DESC1_2_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_57 Register DESC2_2_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_57 0x31D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_57 0x190F1D28u //! Register Reset Value #define DESC2_2_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_57 Register DESC3_2_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_57 0x31D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_57 0x190F1D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_57 Register DESC0_3_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_57 0x31D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_57 0x190F1D30u //! Register Reset Value #define DESC0_3_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_57 Register DESC1_3_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_57 0x31D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_57 0x190F1D34u //! Register Reset Value #define DESC1_3_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_57 Register DESC2_3_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_57 0x31D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_57 0x190F1D38u //! Register Reset Value #define DESC2_3_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_57 Register DESC3_3_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_57 0x31D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_57 0x190F1D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_57 Register DESC0_4_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_57 0x31D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_57 0x190F1D40u //! Register Reset Value #define DESC0_4_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_57 Register DESC1_4_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_57 0x31D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_57 0x190F1D44u //! Register Reset Value #define DESC1_4_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_57 Register DESC2_4_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_57 0x31D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_57 0x190F1D48u //! Register Reset Value #define DESC2_4_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_57 Register DESC3_4_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_57 0x31D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_57 0x190F1D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_57 Register DESC0_5_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_57 0x31D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_57 0x190F1D50u //! Register Reset Value #define DESC0_5_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_57 Register DESC1_5_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_57 0x31D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_57 0x190F1D54u //! Register Reset Value #define DESC1_5_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_57 Register DESC2_5_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_57 0x31D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_57 0x190F1D58u //! Register Reset Value #define DESC2_5_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_57 Register DESC3_5_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_57 0x31D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_57 0x190F1D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_57 Register DESC0_6_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_57 0x31D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_57 0x190F1D60u //! Register Reset Value #define DESC0_6_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_57 Register DESC1_6_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_57 0x31D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_57 0x190F1D64u //! Register Reset Value #define DESC1_6_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_57 Register DESC2_6_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_57 0x31D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_57 0x190F1D68u //! Register Reset Value #define DESC2_6_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_57 Register DESC3_6_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_57 0x31D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_57 0x190F1D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_57 Register DESC0_7_PON_EGP_57 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_57 0x31D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_57 0x190F1D70u //! Register Reset Value #define DESC0_7_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_57 Register DESC1_7_PON_EGP_57 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_57 0x31D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_57 0x190F1D74u //! Register Reset Value #define DESC1_7_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_57 Register DESC2_7_PON_EGP_57 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_57 0x31D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_57 0x190F1D78u //! Register Reset Value #define DESC2_7_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_57 Register DESC3_7_PON_EGP_57 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_57 0x31D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_57 0x190F1D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_57_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_57_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_57_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_57 Register DESC0_0_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_57 0x31E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_57 0x190F1E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_57 Register DESC1_0_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_57 0x31E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_57 0x190F1E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_57 Register DESC2_0_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_57 0x31E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_57 0x190F1E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_57 Register DESC3_0_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_57 0x31E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_57 0x190F1E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_57 Register DESC0_1_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_57 0x31E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_57 0x190F1E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_57 Register DESC1_1_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_57 0x31E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_57 0x190F1E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_57 Register DESC2_1_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_57 0x31E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_57 0x190F1E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_57 Register DESC3_1_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_57 0x31E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_57 0x190F1E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_57 Register DESC0_2_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_57 0x31E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_57 0x190F1E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_57 Register DESC1_2_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_57 0x31E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_57 0x190F1E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_57 Register DESC2_2_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_57 0x31E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_57 0x190F1E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_57 Register DESC3_2_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_57 0x31E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_57 0x190F1E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_57 Register DESC0_3_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_57 0x31E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_57 0x190F1E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_57 Register DESC1_3_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_57 0x31E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_57 0x190F1E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_57 Register DESC2_3_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_57 0x31E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_57 0x190F1E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_57 Register DESC3_3_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_57 0x31E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_57 0x190F1E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_57 Register DESC0_4_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_57 0x31E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_57 0x190F1E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_57 Register DESC1_4_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_57 0x31E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_57 0x190F1E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_57 Register DESC2_4_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_57 0x31E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_57 0x190F1E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_57 Register DESC3_4_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_57 0x31E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_57 0x190F1E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_57 Register DESC0_5_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_57 0x31E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_57 0x190F1E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_57 Register DESC1_5_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_57 0x31E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_57 0x190F1E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_57 Register DESC2_5_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_57 0x31E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_57 0x190F1E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_57 Register DESC3_5_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_57 0x31E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_57 0x190F1E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_57 Register DESC0_6_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_57 0x31E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_57 0x190F1E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_57 Register DESC1_6_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_57 0x31E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_57 0x190F1E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_57 Register DESC2_6_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_57 0x31E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_57 0x190F1E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_57 Register DESC3_6_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_57 0x31E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_57 0x190F1E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_57 Register DESC0_7_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_57 0x31E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_57 0x190F1E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_57 Register DESC1_7_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_57 0x31E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_57 0x190F1E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_57 Register DESC2_7_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_57 0x31E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_57 0x190F1E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_57_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_57 Register DESC3_7_PON_EGP_S_57 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_57 0x31E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_57 0x190F1E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_57_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_57_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_57_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_57_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_57_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_58 Register CFG_PON_EGP_58 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_58 0x32000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_58 0x190F2000u //! Register Reset Value #define CFG_PON_EGP_58_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_58_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_58_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_58_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_58_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_58_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_58_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_58_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_58_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_58_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_58_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_58 Register IRNCR_PON_EGP_58 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_58 0x32020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_58 0x190F2020u //! Register Reset Value #define IRNCR_PON_EGP_58_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_58_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_58_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_58_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_58_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_58 Register IRNICR_PON_EGP_58 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_58 0x32024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_58 0x190F2024u //! Register Reset Value #define IRNICR_PON_EGP_58_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_58_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_58_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_58 Register IRNEN_PON_EGP_58 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_58 0x32028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_58 0x190F2028u //! Register Reset Value #define IRNEN_PON_EGP_58_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_58_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_58_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_58_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_58_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_58 Register DPTR_PON_EGP_58 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_58 0x32030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_58 0x190F2030u //! Register Reset Value #define DPTR_PON_EGP_58_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_58_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_58_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_58_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_58_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_58_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_58_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_58_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_58_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_58 Register DESC0_0_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_58 0x32100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_58 0x190F2100u //! Register Reset Value #define DESC0_0_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_58 Register DESC1_0_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_58 0x32104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_58 0x190F2104u //! Register Reset Value #define DESC1_0_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_58 Register DESC2_0_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_58 0x32108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_58 0x190F2108u //! Register Reset Value #define DESC2_0_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_58 Register DESC3_0_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_58 0x3210C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_58 0x190F210Cu //! Register Reset Value #define DESC3_0_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_58 Register DESC0_1_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_58 0x32110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_58 0x190F2110u //! Register Reset Value #define DESC0_1_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_58 Register DESC1_1_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_58 0x32114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_58 0x190F2114u //! Register Reset Value #define DESC1_1_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_58 Register DESC2_1_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_58 0x32118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_58 0x190F2118u //! Register Reset Value #define DESC2_1_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_58 Register DESC3_1_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_58 0x3211C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_58 0x190F211Cu //! Register Reset Value #define DESC3_1_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_58 Register DESC0_2_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_58 0x32120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_58 0x190F2120u //! Register Reset Value #define DESC0_2_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_58 Register DESC1_2_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_58 0x32124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_58 0x190F2124u //! Register Reset Value #define DESC1_2_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_58 Register DESC2_2_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_58 0x32128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_58 0x190F2128u //! Register Reset Value #define DESC2_2_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_58 Register DESC3_2_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_58 0x3212C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_58 0x190F212Cu //! Register Reset Value #define DESC3_2_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_58 Register DESC0_3_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_58 0x32130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_58 0x190F2130u //! Register Reset Value #define DESC0_3_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_58 Register DESC1_3_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_58 0x32134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_58 0x190F2134u //! Register Reset Value #define DESC1_3_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_58 Register DESC2_3_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_58 0x32138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_58 0x190F2138u //! Register Reset Value #define DESC2_3_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_58 Register DESC3_3_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_58 0x3213C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_58 0x190F213Cu //! Register Reset Value #define DESC3_3_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_58 Register DESC0_4_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_58 0x32140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_58 0x190F2140u //! Register Reset Value #define DESC0_4_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_58 Register DESC1_4_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_58 0x32144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_58 0x190F2144u //! Register Reset Value #define DESC1_4_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_58 Register DESC2_4_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_58 0x32148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_58 0x190F2148u //! Register Reset Value #define DESC2_4_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_58 Register DESC3_4_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_58 0x3214C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_58 0x190F214Cu //! Register Reset Value #define DESC3_4_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_58 Register DESC0_5_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_58 0x32150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_58 0x190F2150u //! Register Reset Value #define DESC0_5_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_58 Register DESC1_5_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_58 0x32154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_58 0x190F2154u //! Register Reset Value #define DESC1_5_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_58 Register DESC2_5_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_58 0x32158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_58 0x190F2158u //! Register Reset Value #define DESC2_5_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_58 Register DESC3_5_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_58 0x3215C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_58 0x190F215Cu //! Register Reset Value #define DESC3_5_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_58 Register DESC0_6_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_58 0x32160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_58 0x190F2160u //! Register Reset Value #define DESC0_6_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_58 Register DESC1_6_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_58 0x32164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_58 0x190F2164u //! Register Reset Value #define DESC1_6_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_58 Register DESC2_6_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_58 0x32168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_58 0x190F2168u //! Register Reset Value #define DESC2_6_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_58 Register DESC3_6_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_58 0x3216C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_58 0x190F216Cu //! Register Reset Value #define DESC3_6_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_58 Register DESC0_7_PON_EGP_58 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_58 0x32170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_58 0x190F2170u //! Register Reset Value #define DESC0_7_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_58 Register DESC1_7_PON_EGP_58 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_58 0x32174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_58 0x190F2174u //! Register Reset Value #define DESC1_7_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_58 Register DESC2_7_PON_EGP_58 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_58 0x32178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_58 0x190F2178u //! Register Reset Value #define DESC2_7_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_58 Register DESC3_7_PON_EGP_58 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_58 0x3217C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_58 0x190F217Cu //! Register Reset Value #define DESC3_7_PON_EGP_58_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_58_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_58_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_58 Register DESC0_0_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_58 0x32200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_58 0x190F2200u //! Register Reset Value #define DESC0_0_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_58 Register DESC1_0_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_58 0x32204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_58 0x190F2204u //! Register Reset Value #define DESC1_0_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_58 Register DESC2_0_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_58 0x32208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_58 0x190F2208u //! Register Reset Value #define DESC2_0_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_58 Register DESC3_0_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_58 0x3220C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_58 0x190F220Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_58 Register DESC0_1_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_58 0x32210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_58 0x190F2210u //! Register Reset Value #define DESC0_1_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_58 Register DESC1_1_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_58 0x32214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_58 0x190F2214u //! Register Reset Value #define DESC1_1_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_58 Register DESC2_1_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_58 0x32218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_58 0x190F2218u //! Register Reset Value #define DESC2_1_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_58 Register DESC3_1_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_58 0x3221C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_58 0x190F221Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_58 Register DESC0_2_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_58 0x32220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_58 0x190F2220u //! Register Reset Value #define DESC0_2_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_58 Register DESC1_2_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_58 0x32224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_58 0x190F2224u //! Register Reset Value #define DESC1_2_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_58 Register DESC2_2_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_58 0x32228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_58 0x190F2228u //! Register Reset Value #define DESC2_2_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_58 Register DESC3_2_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_58 0x3222C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_58 0x190F222Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_58 Register DESC0_3_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_58 0x32230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_58 0x190F2230u //! Register Reset Value #define DESC0_3_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_58 Register DESC1_3_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_58 0x32234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_58 0x190F2234u //! Register Reset Value #define DESC1_3_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_58 Register DESC2_3_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_58 0x32238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_58 0x190F2238u //! Register Reset Value #define DESC2_3_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_58 Register DESC3_3_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_58 0x3223C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_58 0x190F223Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_58 Register DESC0_4_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_58 0x32240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_58 0x190F2240u //! Register Reset Value #define DESC0_4_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_58 Register DESC1_4_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_58 0x32244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_58 0x190F2244u //! Register Reset Value #define DESC1_4_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_58 Register DESC2_4_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_58 0x32248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_58 0x190F2248u //! Register Reset Value #define DESC2_4_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_58 Register DESC3_4_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_58 0x3224C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_58 0x190F224Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_58 Register DESC0_5_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_58 0x32250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_58 0x190F2250u //! Register Reset Value #define DESC0_5_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_58 Register DESC1_5_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_58 0x32254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_58 0x190F2254u //! Register Reset Value #define DESC1_5_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_58 Register DESC2_5_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_58 0x32258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_58 0x190F2258u //! Register Reset Value #define DESC2_5_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_58 Register DESC3_5_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_58 0x3225C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_58 0x190F225Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_58 Register DESC0_6_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_58 0x32260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_58 0x190F2260u //! Register Reset Value #define DESC0_6_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_58 Register DESC1_6_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_58 0x32264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_58 0x190F2264u //! Register Reset Value #define DESC1_6_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_58 Register DESC2_6_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_58 0x32268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_58 0x190F2268u //! Register Reset Value #define DESC2_6_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_58 Register DESC3_6_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_58 0x3226C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_58 0x190F226Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_58 Register DESC0_7_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_58 0x32270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_58 0x190F2270u //! Register Reset Value #define DESC0_7_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_58 Register DESC1_7_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_58 0x32274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_58 0x190F2274u //! Register Reset Value #define DESC1_7_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_58 Register DESC2_7_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_58 0x32278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_58 0x190F2278u //! Register Reset Value #define DESC2_7_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_58_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_58 Register DESC3_7_PON_EGP_S_58 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_58 0x3227C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_58 0x190F227Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_58_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_58_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_58_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_58_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_58_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_59 Register CFG_PON_EGP_59 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_59 0x32400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_59 0x190F2400u //! Register Reset Value #define CFG_PON_EGP_59_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_59_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_59_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_59_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_59_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_59_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_59_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_59_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_59_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_59_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_59_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_59 Register IRNCR_PON_EGP_59 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_59 0x32420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_59 0x190F2420u //! Register Reset Value #define IRNCR_PON_EGP_59_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_59_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_59_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_59_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_59_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_59 Register IRNICR_PON_EGP_59 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_59 0x32424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_59 0x190F2424u //! Register Reset Value #define IRNICR_PON_EGP_59_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_59_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_59_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_59 Register IRNEN_PON_EGP_59 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_59 0x32428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_59 0x190F2428u //! Register Reset Value #define IRNEN_PON_EGP_59_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_59_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_59_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_59_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_59_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_59 Register DPTR_PON_EGP_59 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_59 0x32430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_59 0x190F2430u //! Register Reset Value #define DPTR_PON_EGP_59_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_59_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_59_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_59_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_59_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_59_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_59_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_59_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_59_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_59 Register DESC0_0_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_59 0x32500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_59 0x190F2500u //! Register Reset Value #define DESC0_0_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_59 Register DESC1_0_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_59 0x32504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_59 0x190F2504u //! Register Reset Value #define DESC1_0_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_59 Register DESC2_0_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_59 0x32508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_59 0x190F2508u //! Register Reset Value #define DESC2_0_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_59 Register DESC3_0_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_59 0x3250C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_59 0x190F250Cu //! Register Reset Value #define DESC3_0_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_59 Register DESC0_1_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_59 0x32510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_59 0x190F2510u //! Register Reset Value #define DESC0_1_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_59 Register DESC1_1_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_59 0x32514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_59 0x190F2514u //! Register Reset Value #define DESC1_1_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_59 Register DESC2_1_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_59 0x32518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_59 0x190F2518u //! Register Reset Value #define DESC2_1_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_59 Register DESC3_1_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_59 0x3251C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_59 0x190F251Cu //! Register Reset Value #define DESC3_1_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_59 Register DESC0_2_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_59 0x32520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_59 0x190F2520u //! Register Reset Value #define DESC0_2_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_59 Register DESC1_2_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_59 0x32524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_59 0x190F2524u //! Register Reset Value #define DESC1_2_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_59 Register DESC2_2_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_59 0x32528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_59 0x190F2528u //! Register Reset Value #define DESC2_2_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_59 Register DESC3_2_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_59 0x3252C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_59 0x190F252Cu //! Register Reset Value #define DESC3_2_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_59 Register DESC0_3_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_59 0x32530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_59 0x190F2530u //! Register Reset Value #define DESC0_3_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_59 Register DESC1_3_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_59 0x32534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_59 0x190F2534u //! Register Reset Value #define DESC1_3_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_59 Register DESC2_3_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_59 0x32538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_59 0x190F2538u //! Register Reset Value #define DESC2_3_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_59 Register DESC3_3_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_59 0x3253C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_59 0x190F253Cu //! Register Reset Value #define DESC3_3_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_59 Register DESC0_4_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_59 0x32540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_59 0x190F2540u //! Register Reset Value #define DESC0_4_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_59 Register DESC1_4_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_59 0x32544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_59 0x190F2544u //! Register Reset Value #define DESC1_4_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_59 Register DESC2_4_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_59 0x32548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_59 0x190F2548u //! Register Reset Value #define DESC2_4_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_59 Register DESC3_4_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_59 0x3254C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_59 0x190F254Cu //! Register Reset Value #define DESC3_4_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_59 Register DESC0_5_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_59 0x32550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_59 0x190F2550u //! Register Reset Value #define DESC0_5_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_59 Register DESC1_5_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_59 0x32554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_59 0x190F2554u //! Register Reset Value #define DESC1_5_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_59 Register DESC2_5_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_59 0x32558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_59 0x190F2558u //! Register Reset Value #define DESC2_5_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_59 Register DESC3_5_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_59 0x3255C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_59 0x190F255Cu //! Register Reset Value #define DESC3_5_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_59 Register DESC0_6_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_59 0x32560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_59 0x190F2560u //! Register Reset Value #define DESC0_6_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_59 Register DESC1_6_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_59 0x32564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_59 0x190F2564u //! Register Reset Value #define DESC1_6_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_59 Register DESC2_6_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_59 0x32568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_59 0x190F2568u //! Register Reset Value #define DESC2_6_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_59 Register DESC3_6_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_59 0x3256C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_59 0x190F256Cu //! Register Reset Value #define DESC3_6_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_59 Register DESC0_7_PON_EGP_59 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_59 0x32570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_59 0x190F2570u //! Register Reset Value #define DESC0_7_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_59 Register DESC1_7_PON_EGP_59 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_59 0x32574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_59 0x190F2574u //! Register Reset Value #define DESC1_7_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_59 Register DESC2_7_PON_EGP_59 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_59 0x32578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_59 0x190F2578u //! Register Reset Value #define DESC2_7_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_59 Register DESC3_7_PON_EGP_59 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_59 0x3257C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_59 0x190F257Cu //! Register Reset Value #define DESC3_7_PON_EGP_59_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_59_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_59_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_59 Register DESC0_0_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_59 0x32600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_59 0x190F2600u //! Register Reset Value #define DESC0_0_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_59 Register DESC1_0_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_59 0x32604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_59 0x190F2604u //! Register Reset Value #define DESC1_0_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_59 Register DESC2_0_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_59 0x32608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_59 0x190F2608u //! Register Reset Value #define DESC2_0_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_59 Register DESC3_0_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_59 0x3260C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_59 0x190F260Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_59 Register DESC0_1_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_59 0x32610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_59 0x190F2610u //! Register Reset Value #define DESC0_1_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_59 Register DESC1_1_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_59 0x32614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_59 0x190F2614u //! Register Reset Value #define DESC1_1_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_59 Register DESC2_1_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_59 0x32618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_59 0x190F2618u //! Register Reset Value #define DESC2_1_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_59 Register DESC3_1_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_59 0x3261C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_59 0x190F261Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_59 Register DESC0_2_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_59 0x32620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_59 0x190F2620u //! Register Reset Value #define DESC0_2_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_59 Register DESC1_2_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_59 0x32624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_59 0x190F2624u //! Register Reset Value #define DESC1_2_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_59 Register DESC2_2_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_59 0x32628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_59 0x190F2628u //! Register Reset Value #define DESC2_2_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_59 Register DESC3_2_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_59 0x3262C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_59 0x190F262Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_59 Register DESC0_3_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_59 0x32630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_59 0x190F2630u //! Register Reset Value #define DESC0_3_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_59 Register DESC1_3_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_59 0x32634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_59 0x190F2634u //! Register Reset Value #define DESC1_3_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_59 Register DESC2_3_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_59 0x32638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_59 0x190F2638u //! Register Reset Value #define DESC2_3_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_59 Register DESC3_3_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_59 0x3263C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_59 0x190F263Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_59 Register DESC0_4_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_59 0x32640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_59 0x190F2640u //! Register Reset Value #define DESC0_4_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_59 Register DESC1_4_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_59 0x32644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_59 0x190F2644u //! Register Reset Value #define DESC1_4_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_59 Register DESC2_4_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_59 0x32648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_59 0x190F2648u //! Register Reset Value #define DESC2_4_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_59 Register DESC3_4_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_59 0x3264C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_59 0x190F264Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_59 Register DESC0_5_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_59 0x32650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_59 0x190F2650u //! Register Reset Value #define DESC0_5_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_59 Register DESC1_5_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_59 0x32654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_59 0x190F2654u //! Register Reset Value #define DESC1_5_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_59 Register DESC2_5_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_59 0x32658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_59 0x190F2658u //! Register Reset Value #define DESC2_5_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_59 Register DESC3_5_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_59 0x3265C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_59 0x190F265Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_59 Register DESC0_6_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_59 0x32660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_59 0x190F2660u //! Register Reset Value #define DESC0_6_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_59 Register DESC1_6_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_59 0x32664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_59 0x190F2664u //! Register Reset Value #define DESC1_6_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_59 Register DESC2_6_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_59 0x32668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_59 0x190F2668u //! Register Reset Value #define DESC2_6_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_59 Register DESC3_6_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_59 0x3266C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_59 0x190F266Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_59 Register DESC0_7_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_59 0x32670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_59 0x190F2670u //! Register Reset Value #define DESC0_7_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_59 Register DESC1_7_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_59 0x32674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_59 0x190F2674u //! Register Reset Value #define DESC1_7_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_59 Register DESC2_7_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_59 0x32678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_59 0x190F2678u //! Register Reset Value #define DESC2_7_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_59_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_59 Register DESC3_7_PON_EGP_S_59 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_59 0x3267C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_59 0x190F267Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_59_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_59_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_59_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_59_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_59_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_60 Register CFG_PON_EGP_60 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_60 0x32800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_60 0x190F2800u //! Register Reset Value #define CFG_PON_EGP_60_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_60_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_60_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_60_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_60_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_60_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_60_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_60_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_60_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_60_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_60_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_60 Register IRNCR_PON_EGP_60 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_60 0x32820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_60 0x190F2820u //! Register Reset Value #define IRNCR_PON_EGP_60_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_60_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_60_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_60_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_60_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_60 Register IRNICR_PON_EGP_60 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_60 0x32824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_60 0x190F2824u //! Register Reset Value #define IRNICR_PON_EGP_60_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_60_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_60_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_60 Register IRNEN_PON_EGP_60 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_60 0x32828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_60 0x190F2828u //! Register Reset Value #define IRNEN_PON_EGP_60_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_60_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_60_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_60_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_60_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_60 Register DPTR_PON_EGP_60 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_60 0x32830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_60 0x190F2830u //! Register Reset Value #define DPTR_PON_EGP_60_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_60_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_60_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_60_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_60_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_60_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_60_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_60_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_60_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_60 Register DESC0_0_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_60 0x32900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_60 0x190F2900u //! Register Reset Value #define DESC0_0_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_60 Register DESC1_0_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_60 0x32904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_60 0x190F2904u //! Register Reset Value #define DESC1_0_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_60 Register DESC2_0_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_60 0x32908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_60 0x190F2908u //! Register Reset Value #define DESC2_0_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_60 Register DESC3_0_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_60 0x3290C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_60 0x190F290Cu //! Register Reset Value #define DESC3_0_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_60 Register DESC0_1_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_60 0x32910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_60 0x190F2910u //! Register Reset Value #define DESC0_1_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_60 Register DESC1_1_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_60 0x32914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_60 0x190F2914u //! Register Reset Value #define DESC1_1_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_60 Register DESC2_1_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_60 0x32918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_60 0x190F2918u //! Register Reset Value #define DESC2_1_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_60 Register DESC3_1_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_60 0x3291C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_60 0x190F291Cu //! Register Reset Value #define DESC3_1_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_60 Register DESC0_2_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_60 0x32920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_60 0x190F2920u //! Register Reset Value #define DESC0_2_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_60 Register DESC1_2_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_60 0x32924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_60 0x190F2924u //! Register Reset Value #define DESC1_2_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_60 Register DESC2_2_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_60 0x32928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_60 0x190F2928u //! Register Reset Value #define DESC2_2_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_60 Register DESC3_2_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_60 0x3292C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_60 0x190F292Cu //! Register Reset Value #define DESC3_2_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_60 Register DESC0_3_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_60 0x32930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_60 0x190F2930u //! Register Reset Value #define DESC0_3_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_60 Register DESC1_3_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_60 0x32934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_60 0x190F2934u //! Register Reset Value #define DESC1_3_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_60 Register DESC2_3_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_60 0x32938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_60 0x190F2938u //! Register Reset Value #define DESC2_3_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_60 Register DESC3_3_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_60 0x3293C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_60 0x190F293Cu //! Register Reset Value #define DESC3_3_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_60 Register DESC0_4_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_60 0x32940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_60 0x190F2940u //! Register Reset Value #define DESC0_4_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_60 Register DESC1_4_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_60 0x32944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_60 0x190F2944u //! Register Reset Value #define DESC1_4_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_60 Register DESC2_4_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_60 0x32948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_60 0x190F2948u //! Register Reset Value #define DESC2_4_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_60 Register DESC3_4_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_60 0x3294C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_60 0x190F294Cu //! Register Reset Value #define DESC3_4_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_60 Register DESC0_5_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_60 0x32950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_60 0x190F2950u //! Register Reset Value #define DESC0_5_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_60 Register DESC1_5_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_60 0x32954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_60 0x190F2954u //! Register Reset Value #define DESC1_5_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_60 Register DESC2_5_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_60 0x32958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_60 0x190F2958u //! Register Reset Value #define DESC2_5_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_60 Register DESC3_5_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_60 0x3295C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_60 0x190F295Cu //! Register Reset Value #define DESC3_5_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_60 Register DESC0_6_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_60 0x32960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_60 0x190F2960u //! Register Reset Value #define DESC0_6_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_60 Register DESC1_6_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_60 0x32964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_60 0x190F2964u //! Register Reset Value #define DESC1_6_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_60 Register DESC2_6_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_60 0x32968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_60 0x190F2968u //! Register Reset Value #define DESC2_6_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_60 Register DESC3_6_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_60 0x3296C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_60 0x190F296Cu //! Register Reset Value #define DESC3_6_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_60 Register DESC0_7_PON_EGP_60 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_60 0x32970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_60 0x190F2970u //! Register Reset Value #define DESC0_7_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_60 Register DESC1_7_PON_EGP_60 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_60 0x32974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_60 0x190F2974u //! Register Reset Value #define DESC1_7_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_60 Register DESC2_7_PON_EGP_60 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_60 0x32978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_60 0x190F2978u //! Register Reset Value #define DESC2_7_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_60 Register DESC3_7_PON_EGP_60 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_60 0x3297C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_60 0x190F297Cu //! Register Reset Value #define DESC3_7_PON_EGP_60_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_60_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_60_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_60 Register DESC0_0_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_60 0x32A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_60 0x190F2A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_60 Register DESC1_0_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_60 0x32A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_60 0x190F2A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_60 Register DESC2_0_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_60 0x32A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_60 0x190F2A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_60 Register DESC3_0_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_60 0x32A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_60 0x190F2A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_60 Register DESC0_1_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_60 0x32A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_60 0x190F2A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_60 Register DESC1_1_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_60 0x32A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_60 0x190F2A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_60 Register DESC2_1_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_60 0x32A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_60 0x190F2A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_60 Register DESC3_1_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_60 0x32A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_60 0x190F2A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_60 Register DESC0_2_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_60 0x32A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_60 0x190F2A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_60 Register DESC1_2_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_60 0x32A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_60 0x190F2A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_60 Register DESC2_2_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_60 0x32A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_60 0x190F2A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_60 Register DESC3_2_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_60 0x32A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_60 0x190F2A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_60 Register DESC0_3_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_60 0x32A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_60 0x190F2A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_60 Register DESC1_3_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_60 0x32A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_60 0x190F2A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_60 Register DESC2_3_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_60 0x32A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_60 0x190F2A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_60 Register DESC3_3_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_60 0x32A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_60 0x190F2A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_60 Register DESC0_4_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_60 0x32A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_60 0x190F2A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_60 Register DESC1_4_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_60 0x32A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_60 0x190F2A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_60 Register DESC2_4_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_60 0x32A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_60 0x190F2A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_60 Register DESC3_4_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_60 0x32A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_60 0x190F2A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_60 Register DESC0_5_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_60 0x32A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_60 0x190F2A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_60 Register DESC1_5_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_60 0x32A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_60 0x190F2A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_60 Register DESC2_5_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_60 0x32A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_60 0x190F2A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_60 Register DESC3_5_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_60 0x32A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_60 0x190F2A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_60 Register DESC0_6_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_60 0x32A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_60 0x190F2A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_60 Register DESC1_6_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_60 0x32A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_60 0x190F2A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_60 Register DESC2_6_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_60 0x32A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_60 0x190F2A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_60 Register DESC3_6_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_60 0x32A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_60 0x190F2A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_60 Register DESC0_7_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_60 0x32A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_60 0x190F2A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_60 Register DESC1_7_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_60 0x32A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_60 0x190F2A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_60 Register DESC2_7_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_60 0x32A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_60 0x190F2A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_60_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_60 Register DESC3_7_PON_EGP_S_60 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_60 0x32A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_60 0x190F2A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_60_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_60_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_60_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_60_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_60_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_61 Register CFG_PON_EGP_61 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_61 0x32C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_61 0x190F2C00u //! Register Reset Value #define CFG_PON_EGP_61_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_61_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_61_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_61_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_61_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_61_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_61_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_61_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_61_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_61_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_61_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_61 Register IRNCR_PON_EGP_61 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_61 0x32C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_61 0x190F2C20u //! Register Reset Value #define IRNCR_PON_EGP_61_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_61_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_61_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_61_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_61_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_61 Register IRNICR_PON_EGP_61 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_61 0x32C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_61 0x190F2C24u //! Register Reset Value #define IRNICR_PON_EGP_61_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_61_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_61_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_61 Register IRNEN_PON_EGP_61 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_61 0x32C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_61 0x190F2C28u //! Register Reset Value #define IRNEN_PON_EGP_61_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_61_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_61_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_61_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_61_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_61 Register DPTR_PON_EGP_61 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_61 0x32C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_61 0x190F2C30u //! Register Reset Value #define DPTR_PON_EGP_61_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_61_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_61_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_61_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_61_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_61_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_61_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_61_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_61_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_61 Register DESC0_0_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_61 0x32D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_61 0x190F2D00u //! Register Reset Value #define DESC0_0_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_61 Register DESC1_0_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_61 0x32D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_61 0x190F2D04u //! Register Reset Value #define DESC1_0_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_61 Register DESC2_0_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_61 0x32D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_61 0x190F2D08u //! Register Reset Value #define DESC2_0_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_61 Register DESC3_0_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_61 0x32D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_61 0x190F2D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_61 Register DESC0_1_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_61 0x32D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_61 0x190F2D10u //! Register Reset Value #define DESC0_1_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_61 Register DESC1_1_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_61 0x32D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_61 0x190F2D14u //! Register Reset Value #define DESC1_1_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_61 Register DESC2_1_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_61 0x32D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_61 0x190F2D18u //! Register Reset Value #define DESC2_1_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_61 Register DESC3_1_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_61 0x32D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_61 0x190F2D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_61 Register DESC0_2_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_61 0x32D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_61 0x190F2D20u //! Register Reset Value #define DESC0_2_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_61 Register DESC1_2_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_61 0x32D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_61 0x190F2D24u //! Register Reset Value #define DESC1_2_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_61 Register DESC2_2_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_61 0x32D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_61 0x190F2D28u //! Register Reset Value #define DESC2_2_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_61 Register DESC3_2_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_61 0x32D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_61 0x190F2D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_61 Register DESC0_3_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_61 0x32D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_61 0x190F2D30u //! Register Reset Value #define DESC0_3_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_61 Register DESC1_3_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_61 0x32D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_61 0x190F2D34u //! Register Reset Value #define DESC1_3_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_61 Register DESC2_3_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_61 0x32D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_61 0x190F2D38u //! Register Reset Value #define DESC2_3_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_61 Register DESC3_3_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_61 0x32D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_61 0x190F2D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_61 Register DESC0_4_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_61 0x32D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_61 0x190F2D40u //! Register Reset Value #define DESC0_4_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_61 Register DESC1_4_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_61 0x32D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_61 0x190F2D44u //! Register Reset Value #define DESC1_4_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_61 Register DESC2_4_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_61 0x32D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_61 0x190F2D48u //! Register Reset Value #define DESC2_4_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_61 Register DESC3_4_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_61 0x32D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_61 0x190F2D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_61 Register DESC0_5_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_61 0x32D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_61 0x190F2D50u //! Register Reset Value #define DESC0_5_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_61 Register DESC1_5_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_61 0x32D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_61 0x190F2D54u //! Register Reset Value #define DESC1_5_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_61 Register DESC2_5_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_61 0x32D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_61 0x190F2D58u //! Register Reset Value #define DESC2_5_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_61 Register DESC3_5_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_61 0x32D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_61 0x190F2D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_61 Register DESC0_6_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_61 0x32D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_61 0x190F2D60u //! Register Reset Value #define DESC0_6_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_61 Register DESC1_6_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_61 0x32D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_61 0x190F2D64u //! Register Reset Value #define DESC1_6_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_61 Register DESC2_6_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_61 0x32D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_61 0x190F2D68u //! Register Reset Value #define DESC2_6_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_61 Register DESC3_6_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_61 0x32D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_61 0x190F2D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_61 Register DESC0_7_PON_EGP_61 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_61 0x32D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_61 0x190F2D70u //! Register Reset Value #define DESC0_7_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_61 Register DESC1_7_PON_EGP_61 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_61 0x32D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_61 0x190F2D74u //! Register Reset Value #define DESC1_7_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_61 Register DESC2_7_PON_EGP_61 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_61 0x32D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_61 0x190F2D78u //! Register Reset Value #define DESC2_7_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_61 Register DESC3_7_PON_EGP_61 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_61 0x32D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_61 0x190F2D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_61_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_61_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_61_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_61 Register DESC0_0_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_61 0x32E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_61 0x190F2E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_61 Register DESC1_0_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_61 0x32E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_61 0x190F2E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_61 Register DESC2_0_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_61 0x32E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_61 0x190F2E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_61 Register DESC3_0_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_61 0x32E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_61 0x190F2E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_61 Register DESC0_1_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_61 0x32E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_61 0x190F2E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_61 Register DESC1_1_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_61 0x32E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_61 0x190F2E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_61 Register DESC2_1_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_61 0x32E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_61 0x190F2E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_61 Register DESC3_1_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_61 0x32E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_61 0x190F2E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_61 Register DESC0_2_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_61 0x32E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_61 0x190F2E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_61 Register DESC1_2_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_61 0x32E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_61 0x190F2E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_61 Register DESC2_2_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_61 0x32E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_61 0x190F2E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_61 Register DESC3_2_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_61 0x32E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_61 0x190F2E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_61 Register DESC0_3_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_61 0x32E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_61 0x190F2E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_61 Register DESC1_3_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_61 0x32E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_61 0x190F2E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_61 Register DESC2_3_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_61 0x32E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_61 0x190F2E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_61 Register DESC3_3_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_61 0x32E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_61 0x190F2E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_61 Register DESC0_4_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_61 0x32E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_61 0x190F2E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_61 Register DESC1_4_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_61 0x32E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_61 0x190F2E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_61 Register DESC2_4_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_61 0x32E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_61 0x190F2E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_61 Register DESC3_4_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_61 0x32E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_61 0x190F2E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_61 Register DESC0_5_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_61 0x32E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_61 0x190F2E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_61 Register DESC1_5_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_61 0x32E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_61 0x190F2E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_61 Register DESC2_5_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_61 0x32E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_61 0x190F2E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_61 Register DESC3_5_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_61 0x32E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_61 0x190F2E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_61 Register DESC0_6_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_61 0x32E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_61 0x190F2E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_61 Register DESC1_6_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_61 0x32E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_61 0x190F2E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_61 Register DESC2_6_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_61 0x32E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_61 0x190F2E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_61 Register DESC3_6_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_61 0x32E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_61 0x190F2E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_61 Register DESC0_7_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_61 0x32E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_61 0x190F2E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_61 Register DESC1_7_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_61 0x32E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_61 0x190F2E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_61 Register DESC2_7_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_61 0x32E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_61 0x190F2E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_61_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_61 Register DESC3_7_PON_EGP_S_61 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_61 0x32E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_61 0x190F2E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_61_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_61_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_61_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_61_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_61_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_62 Register CFG_PON_EGP_62 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_62 0x33000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_62 0x190F3000u //! Register Reset Value #define CFG_PON_EGP_62_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_62_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_62_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_62_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_62_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_62_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_62_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_62_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_62_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_62_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_62_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_62 Register IRNCR_PON_EGP_62 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_62 0x33020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_62 0x190F3020u //! Register Reset Value #define IRNCR_PON_EGP_62_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_62_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_62_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_62_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_62_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_62 Register IRNICR_PON_EGP_62 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_62 0x33024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_62 0x190F3024u //! Register Reset Value #define IRNICR_PON_EGP_62_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_62_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_62_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_62 Register IRNEN_PON_EGP_62 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_62 0x33028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_62 0x190F3028u //! Register Reset Value #define IRNEN_PON_EGP_62_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_62_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_62_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_62_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_62_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_62 Register DPTR_PON_EGP_62 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_62 0x33030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_62 0x190F3030u //! Register Reset Value #define DPTR_PON_EGP_62_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_62_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_62_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_62_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_62_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_62_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_62_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_62_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_62_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_62 Register DESC0_0_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_62 0x33100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_62 0x190F3100u //! Register Reset Value #define DESC0_0_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_62 Register DESC1_0_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_62 0x33104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_62 0x190F3104u //! Register Reset Value #define DESC1_0_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_62 Register DESC2_0_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_62 0x33108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_62 0x190F3108u //! Register Reset Value #define DESC2_0_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_62 Register DESC3_0_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_62 0x3310C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_62 0x190F310Cu //! Register Reset Value #define DESC3_0_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_62 Register DESC0_1_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_62 0x33110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_62 0x190F3110u //! Register Reset Value #define DESC0_1_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_62 Register DESC1_1_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_62 0x33114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_62 0x190F3114u //! Register Reset Value #define DESC1_1_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_62 Register DESC2_1_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_62 0x33118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_62 0x190F3118u //! Register Reset Value #define DESC2_1_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_62 Register DESC3_1_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_62 0x3311C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_62 0x190F311Cu //! Register Reset Value #define DESC3_1_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_62 Register DESC0_2_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_62 0x33120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_62 0x190F3120u //! Register Reset Value #define DESC0_2_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_62 Register DESC1_2_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_62 0x33124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_62 0x190F3124u //! Register Reset Value #define DESC1_2_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_62 Register DESC2_2_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_62 0x33128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_62 0x190F3128u //! Register Reset Value #define DESC2_2_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_62 Register DESC3_2_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_62 0x3312C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_62 0x190F312Cu //! Register Reset Value #define DESC3_2_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_62 Register DESC0_3_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_62 0x33130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_62 0x190F3130u //! Register Reset Value #define DESC0_3_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_62 Register DESC1_3_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_62 0x33134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_62 0x190F3134u //! Register Reset Value #define DESC1_3_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_62 Register DESC2_3_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_62 0x33138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_62 0x190F3138u //! Register Reset Value #define DESC2_3_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_62 Register DESC3_3_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_62 0x3313C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_62 0x190F313Cu //! Register Reset Value #define DESC3_3_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_62 Register DESC0_4_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_62 0x33140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_62 0x190F3140u //! Register Reset Value #define DESC0_4_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_62 Register DESC1_4_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_62 0x33144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_62 0x190F3144u //! Register Reset Value #define DESC1_4_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_62 Register DESC2_4_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_62 0x33148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_62 0x190F3148u //! Register Reset Value #define DESC2_4_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_62 Register DESC3_4_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_62 0x3314C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_62 0x190F314Cu //! Register Reset Value #define DESC3_4_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_62 Register DESC0_5_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_62 0x33150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_62 0x190F3150u //! Register Reset Value #define DESC0_5_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_62 Register DESC1_5_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_62 0x33154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_62 0x190F3154u //! Register Reset Value #define DESC1_5_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_62 Register DESC2_5_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_62 0x33158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_62 0x190F3158u //! Register Reset Value #define DESC2_5_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_62 Register DESC3_5_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_62 0x3315C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_62 0x190F315Cu //! Register Reset Value #define DESC3_5_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_62 Register DESC0_6_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_62 0x33160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_62 0x190F3160u //! Register Reset Value #define DESC0_6_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_62 Register DESC1_6_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_62 0x33164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_62 0x190F3164u //! Register Reset Value #define DESC1_6_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_62 Register DESC2_6_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_62 0x33168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_62 0x190F3168u //! Register Reset Value #define DESC2_6_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_62 Register DESC3_6_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_62 0x3316C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_62 0x190F316Cu //! Register Reset Value #define DESC3_6_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_62 Register DESC0_7_PON_EGP_62 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_62 0x33170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_62 0x190F3170u //! Register Reset Value #define DESC0_7_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_62 Register DESC1_7_PON_EGP_62 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_62 0x33174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_62 0x190F3174u //! Register Reset Value #define DESC1_7_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_62 Register DESC2_7_PON_EGP_62 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_62 0x33178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_62 0x190F3178u //! Register Reset Value #define DESC2_7_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_62 Register DESC3_7_PON_EGP_62 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_62 0x3317C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_62 0x190F317Cu //! Register Reset Value #define DESC3_7_PON_EGP_62_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_62_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_62_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_62 Register DESC0_0_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_62 0x33200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_62 0x190F3200u //! Register Reset Value #define DESC0_0_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_62 Register DESC1_0_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_62 0x33204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_62 0x190F3204u //! Register Reset Value #define DESC1_0_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_62 Register DESC2_0_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_62 0x33208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_62 0x190F3208u //! Register Reset Value #define DESC2_0_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_62 Register DESC3_0_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_62 0x3320C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_62 0x190F320Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_62 Register DESC0_1_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_62 0x33210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_62 0x190F3210u //! Register Reset Value #define DESC0_1_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_62 Register DESC1_1_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_62 0x33214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_62 0x190F3214u //! Register Reset Value #define DESC1_1_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_62 Register DESC2_1_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_62 0x33218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_62 0x190F3218u //! Register Reset Value #define DESC2_1_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_62 Register DESC3_1_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_62 0x3321C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_62 0x190F321Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_62 Register DESC0_2_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_62 0x33220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_62 0x190F3220u //! Register Reset Value #define DESC0_2_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_62 Register DESC1_2_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_62 0x33224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_62 0x190F3224u //! Register Reset Value #define DESC1_2_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_62 Register DESC2_2_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_62 0x33228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_62 0x190F3228u //! Register Reset Value #define DESC2_2_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_62 Register DESC3_2_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_62 0x3322C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_62 0x190F322Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_62 Register DESC0_3_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_62 0x33230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_62 0x190F3230u //! Register Reset Value #define DESC0_3_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_62 Register DESC1_3_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_62 0x33234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_62 0x190F3234u //! Register Reset Value #define DESC1_3_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_62 Register DESC2_3_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_62 0x33238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_62 0x190F3238u //! Register Reset Value #define DESC2_3_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_62 Register DESC3_3_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_62 0x3323C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_62 0x190F323Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_62 Register DESC0_4_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_62 0x33240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_62 0x190F3240u //! Register Reset Value #define DESC0_4_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_62 Register DESC1_4_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_62 0x33244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_62 0x190F3244u //! Register Reset Value #define DESC1_4_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_62 Register DESC2_4_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_62 0x33248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_62 0x190F3248u //! Register Reset Value #define DESC2_4_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_62 Register DESC3_4_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_62 0x3324C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_62 0x190F324Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_62 Register DESC0_5_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_62 0x33250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_62 0x190F3250u //! Register Reset Value #define DESC0_5_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_62 Register DESC1_5_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_62 0x33254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_62 0x190F3254u //! Register Reset Value #define DESC1_5_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_62 Register DESC2_5_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_62 0x33258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_62 0x190F3258u //! Register Reset Value #define DESC2_5_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_62 Register DESC3_5_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_62 0x3325C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_62 0x190F325Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_62 Register DESC0_6_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_62 0x33260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_62 0x190F3260u //! Register Reset Value #define DESC0_6_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_62 Register DESC1_6_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_62 0x33264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_62 0x190F3264u //! Register Reset Value #define DESC1_6_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_62 Register DESC2_6_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_62 0x33268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_62 0x190F3268u //! Register Reset Value #define DESC2_6_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_62 Register DESC3_6_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_62 0x3326C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_62 0x190F326Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_62 Register DESC0_7_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_62 0x33270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_62 0x190F3270u //! Register Reset Value #define DESC0_7_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_62 Register DESC1_7_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_62 0x33274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_62 0x190F3274u //! Register Reset Value #define DESC1_7_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_62 Register DESC2_7_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_62 0x33278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_62 0x190F3278u //! Register Reset Value #define DESC2_7_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_62_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_62 Register DESC3_7_PON_EGP_S_62 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_62 0x3327C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_62 0x190F327Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_62_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_62_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_62_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_62_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_62_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_63 Register CFG_PON_EGP_63 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_63 0x33400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_63 0x190F3400u //! Register Reset Value #define CFG_PON_EGP_63_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_63_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_63_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_63_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_63_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_63_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_63_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_63_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_63_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_63_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_63_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_63 Register IRNCR_PON_EGP_63 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_63 0x33420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_63 0x190F3420u //! Register Reset Value #define IRNCR_PON_EGP_63_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_63_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_63_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_63_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_63_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_63 Register IRNICR_PON_EGP_63 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_63 0x33424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_63 0x190F3424u //! Register Reset Value #define IRNICR_PON_EGP_63_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_63_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_63_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_63 Register IRNEN_PON_EGP_63 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_63 0x33428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_63 0x190F3428u //! Register Reset Value #define IRNEN_PON_EGP_63_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_63_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_63_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_63_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_63_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_63 Register DPTR_PON_EGP_63 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_63 0x33430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_63 0x190F3430u //! Register Reset Value #define DPTR_PON_EGP_63_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_63_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_63_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_63_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_63_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_63_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_63_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_63_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_63_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_63 Register DESC0_0_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_63 0x33500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_63 0x190F3500u //! Register Reset Value #define DESC0_0_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_63 Register DESC1_0_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_63 0x33504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_63 0x190F3504u //! Register Reset Value #define DESC1_0_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_63 Register DESC2_0_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_63 0x33508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_63 0x190F3508u //! Register Reset Value #define DESC2_0_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_63 Register DESC3_0_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_63 0x3350C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_63 0x190F350Cu //! Register Reset Value #define DESC3_0_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_63 Register DESC0_1_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_63 0x33510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_63 0x190F3510u //! Register Reset Value #define DESC0_1_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_63 Register DESC1_1_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_63 0x33514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_63 0x190F3514u //! Register Reset Value #define DESC1_1_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_63 Register DESC2_1_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_63 0x33518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_63 0x190F3518u //! Register Reset Value #define DESC2_1_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_63 Register DESC3_1_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_63 0x3351C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_63 0x190F351Cu //! Register Reset Value #define DESC3_1_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_63 Register DESC0_2_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_63 0x33520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_63 0x190F3520u //! Register Reset Value #define DESC0_2_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_63 Register DESC1_2_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_63 0x33524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_63 0x190F3524u //! Register Reset Value #define DESC1_2_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_63 Register DESC2_2_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_63 0x33528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_63 0x190F3528u //! Register Reset Value #define DESC2_2_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_63 Register DESC3_2_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_63 0x3352C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_63 0x190F352Cu //! Register Reset Value #define DESC3_2_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_63 Register DESC0_3_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_63 0x33530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_63 0x190F3530u //! Register Reset Value #define DESC0_3_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_63 Register DESC1_3_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_63 0x33534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_63 0x190F3534u //! Register Reset Value #define DESC1_3_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_63 Register DESC2_3_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_63 0x33538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_63 0x190F3538u //! Register Reset Value #define DESC2_3_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_63 Register DESC3_3_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_63 0x3353C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_63 0x190F353Cu //! Register Reset Value #define DESC3_3_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_63 Register DESC0_4_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_63 0x33540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_63 0x190F3540u //! Register Reset Value #define DESC0_4_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_63 Register DESC1_4_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_63 0x33544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_63 0x190F3544u //! Register Reset Value #define DESC1_4_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_63 Register DESC2_4_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_63 0x33548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_63 0x190F3548u //! Register Reset Value #define DESC2_4_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_63 Register DESC3_4_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_63 0x3354C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_63 0x190F354Cu //! Register Reset Value #define DESC3_4_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_63 Register DESC0_5_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_63 0x33550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_63 0x190F3550u //! Register Reset Value #define DESC0_5_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_63 Register DESC1_5_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_63 0x33554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_63 0x190F3554u //! Register Reset Value #define DESC1_5_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_63 Register DESC2_5_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_63 0x33558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_63 0x190F3558u //! Register Reset Value #define DESC2_5_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_63 Register DESC3_5_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_63 0x3355C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_63 0x190F355Cu //! Register Reset Value #define DESC3_5_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_63 Register DESC0_6_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_63 0x33560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_63 0x190F3560u //! Register Reset Value #define DESC0_6_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_63 Register DESC1_6_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_63 0x33564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_63 0x190F3564u //! Register Reset Value #define DESC1_6_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_63 Register DESC2_6_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_63 0x33568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_63 0x190F3568u //! Register Reset Value #define DESC2_6_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_63 Register DESC3_6_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_63 0x3356C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_63 0x190F356Cu //! Register Reset Value #define DESC3_6_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_63 Register DESC0_7_PON_EGP_63 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_63 0x33570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_63 0x190F3570u //! Register Reset Value #define DESC0_7_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_63 Register DESC1_7_PON_EGP_63 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_63 0x33574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_63 0x190F3574u //! Register Reset Value #define DESC1_7_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_63 Register DESC2_7_PON_EGP_63 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_63 0x33578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_63 0x190F3578u //! Register Reset Value #define DESC2_7_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_63 Register DESC3_7_PON_EGP_63 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_63 0x3357C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_63 0x190F357Cu //! Register Reset Value #define DESC3_7_PON_EGP_63_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_63_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_63_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_63 Register DESC0_0_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_63 0x33600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_63 0x190F3600u //! Register Reset Value #define DESC0_0_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_63 Register DESC1_0_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_63 0x33604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_63 0x190F3604u //! Register Reset Value #define DESC1_0_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_63 Register DESC2_0_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_63 0x33608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_63 0x190F3608u //! Register Reset Value #define DESC2_0_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_63 Register DESC3_0_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_63 0x3360C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_63 0x190F360Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_63 Register DESC0_1_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_63 0x33610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_63 0x190F3610u //! Register Reset Value #define DESC0_1_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_63 Register DESC1_1_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_63 0x33614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_63 0x190F3614u //! Register Reset Value #define DESC1_1_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_63 Register DESC2_1_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_63 0x33618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_63 0x190F3618u //! Register Reset Value #define DESC2_1_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_63 Register DESC3_1_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_63 0x3361C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_63 0x190F361Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_63 Register DESC0_2_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_63 0x33620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_63 0x190F3620u //! Register Reset Value #define DESC0_2_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_63 Register DESC1_2_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_63 0x33624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_63 0x190F3624u //! Register Reset Value #define DESC1_2_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_63 Register DESC2_2_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_63 0x33628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_63 0x190F3628u //! Register Reset Value #define DESC2_2_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_63 Register DESC3_2_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_63 0x3362C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_63 0x190F362Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_63 Register DESC0_3_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_63 0x33630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_63 0x190F3630u //! Register Reset Value #define DESC0_3_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_63 Register DESC1_3_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_63 0x33634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_63 0x190F3634u //! Register Reset Value #define DESC1_3_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_63 Register DESC2_3_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_63 0x33638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_63 0x190F3638u //! Register Reset Value #define DESC2_3_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_63 Register DESC3_3_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_63 0x3363C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_63 0x190F363Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_63 Register DESC0_4_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_63 0x33640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_63 0x190F3640u //! Register Reset Value #define DESC0_4_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_63 Register DESC1_4_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_63 0x33644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_63 0x190F3644u //! Register Reset Value #define DESC1_4_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_63 Register DESC2_4_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_63 0x33648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_63 0x190F3648u //! Register Reset Value #define DESC2_4_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_63 Register DESC3_4_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_63 0x3364C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_63 0x190F364Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_63 Register DESC0_5_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_63 0x33650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_63 0x190F3650u //! Register Reset Value #define DESC0_5_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_63 Register DESC1_5_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_63 0x33654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_63 0x190F3654u //! Register Reset Value #define DESC1_5_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_63 Register DESC2_5_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_63 0x33658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_63 0x190F3658u //! Register Reset Value #define DESC2_5_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_63 Register DESC3_5_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_63 0x3365C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_63 0x190F365Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_63 Register DESC0_6_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_63 0x33660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_63 0x190F3660u //! Register Reset Value #define DESC0_6_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_63 Register DESC1_6_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_63 0x33664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_63 0x190F3664u //! Register Reset Value #define DESC1_6_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_63 Register DESC2_6_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_63 0x33668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_63 0x190F3668u //! Register Reset Value #define DESC2_6_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_63 Register DESC3_6_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_63 0x3366C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_63 0x190F366Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_63 Register DESC0_7_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_63 0x33670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_63 0x190F3670u //! Register Reset Value #define DESC0_7_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_63 Register DESC1_7_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_63 0x33674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_63 0x190F3674u //! Register Reset Value #define DESC1_7_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_63 Register DESC2_7_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_63 0x33678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_63 0x190F3678u //! Register Reset Value #define DESC2_7_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_63_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_63 Register DESC3_7_PON_EGP_S_63 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_63 0x3367C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_63 0x190F367Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_63_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_63_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_63_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_63_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_63_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_64 Register CFG_PON_EGP_64 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_64 0x33800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_64 0x190F3800u //! Register Reset Value #define CFG_PON_EGP_64_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_64_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_64_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_64_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_64_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_64_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_64_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_64_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_64_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_64_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_64_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_64 Register IRNCR_PON_EGP_64 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_64 0x33820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_64 0x190F3820u //! Register Reset Value #define IRNCR_PON_EGP_64_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_64_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_64_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_64_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_64_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_64 Register IRNICR_PON_EGP_64 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_64 0x33824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_64 0x190F3824u //! Register Reset Value #define IRNICR_PON_EGP_64_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_64_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_64_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_64 Register IRNEN_PON_EGP_64 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_64 0x33828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_64 0x190F3828u //! Register Reset Value #define IRNEN_PON_EGP_64_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_64_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_64_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_64_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_64_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_64 Register DPTR_PON_EGP_64 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_64 0x33830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_64 0x190F3830u //! Register Reset Value #define DPTR_PON_EGP_64_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_64_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_64_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_64_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_64_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_64_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_64_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_64_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_64_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_64 Register DESC0_0_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_64 0x33900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_64 0x190F3900u //! Register Reset Value #define DESC0_0_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_64 Register DESC1_0_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_64 0x33904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_64 0x190F3904u //! Register Reset Value #define DESC1_0_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_64 Register DESC2_0_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_64 0x33908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_64 0x190F3908u //! Register Reset Value #define DESC2_0_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_64 Register DESC3_0_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_64 0x3390C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_64 0x190F390Cu //! Register Reset Value #define DESC3_0_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_64 Register DESC0_1_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_64 0x33910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_64 0x190F3910u //! Register Reset Value #define DESC0_1_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_64 Register DESC1_1_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_64 0x33914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_64 0x190F3914u //! Register Reset Value #define DESC1_1_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_64 Register DESC2_1_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_64 0x33918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_64 0x190F3918u //! Register Reset Value #define DESC2_1_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_64 Register DESC3_1_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_64 0x3391C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_64 0x190F391Cu //! Register Reset Value #define DESC3_1_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_64 Register DESC0_2_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_64 0x33920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_64 0x190F3920u //! Register Reset Value #define DESC0_2_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_64 Register DESC1_2_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_64 0x33924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_64 0x190F3924u //! Register Reset Value #define DESC1_2_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_64 Register DESC2_2_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_64 0x33928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_64 0x190F3928u //! Register Reset Value #define DESC2_2_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_64 Register DESC3_2_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_64 0x3392C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_64 0x190F392Cu //! Register Reset Value #define DESC3_2_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_64 Register DESC0_3_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_64 0x33930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_64 0x190F3930u //! Register Reset Value #define DESC0_3_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_64 Register DESC1_3_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_64 0x33934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_64 0x190F3934u //! Register Reset Value #define DESC1_3_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_64 Register DESC2_3_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_64 0x33938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_64 0x190F3938u //! Register Reset Value #define DESC2_3_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_64 Register DESC3_3_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_64 0x3393C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_64 0x190F393Cu //! Register Reset Value #define DESC3_3_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_64 Register DESC0_4_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_64 0x33940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_64 0x190F3940u //! Register Reset Value #define DESC0_4_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_64 Register DESC1_4_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_64 0x33944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_64 0x190F3944u //! Register Reset Value #define DESC1_4_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_64 Register DESC2_4_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_64 0x33948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_64 0x190F3948u //! Register Reset Value #define DESC2_4_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_64 Register DESC3_4_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_64 0x3394C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_64 0x190F394Cu //! Register Reset Value #define DESC3_4_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_64 Register DESC0_5_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_64 0x33950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_64 0x190F3950u //! Register Reset Value #define DESC0_5_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_64 Register DESC1_5_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_64 0x33954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_64 0x190F3954u //! Register Reset Value #define DESC1_5_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_64 Register DESC2_5_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_64 0x33958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_64 0x190F3958u //! Register Reset Value #define DESC2_5_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_64 Register DESC3_5_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_64 0x3395C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_64 0x190F395Cu //! Register Reset Value #define DESC3_5_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_64 Register DESC0_6_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_64 0x33960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_64 0x190F3960u //! Register Reset Value #define DESC0_6_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_64 Register DESC1_6_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_64 0x33964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_64 0x190F3964u //! Register Reset Value #define DESC1_6_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_64 Register DESC2_6_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_64 0x33968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_64 0x190F3968u //! Register Reset Value #define DESC2_6_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_64 Register DESC3_6_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_64 0x3396C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_64 0x190F396Cu //! Register Reset Value #define DESC3_6_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_64 Register DESC0_7_PON_EGP_64 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_64 0x33970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_64 0x190F3970u //! Register Reset Value #define DESC0_7_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_64 Register DESC1_7_PON_EGP_64 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_64 0x33974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_64 0x190F3974u //! Register Reset Value #define DESC1_7_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_64 Register DESC2_7_PON_EGP_64 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_64 0x33978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_64 0x190F3978u //! Register Reset Value #define DESC2_7_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_64 Register DESC3_7_PON_EGP_64 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_64 0x3397C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_64 0x190F397Cu //! Register Reset Value #define DESC3_7_PON_EGP_64_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_64_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_64_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_64 Register DESC0_0_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_64 0x33A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_64 0x190F3A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_64 Register DESC1_0_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_64 0x33A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_64 0x190F3A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_64 Register DESC2_0_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_64 0x33A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_64 0x190F3A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_64 Register DESC3_0_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_64 0x33A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_64 0x190F3A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_64 Register DESC0_1_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_64 0x33A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_64 0x190F3A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_64 Register DESC1_1_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_64 0x33A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_64 0x190F3A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_64 Register DESC2_1_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_64 0x33A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_64 0x190F3A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_64 Register DESC3_1_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_64 0x33A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_64 0x190F3A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_64 Register DESC0_2_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_64 0x33A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_64 0x190F3A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_64 Register DESC1_2_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_64 0x33A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_64 0x190F3A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_64 Register DESC2_2_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_64 0x33A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_64 0x190F3A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_64 Register DESC3_2_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_64 0x33A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_64 0x190F3A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_64 Register DESC0_3_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_64 0x33A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_64 0x190F3A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_64 Register DESC1_3_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_64 0x33A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_64 0x190F3A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_64 Register DESC2_3_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_64 0x33A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_64 0x190F3A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_64 Register DESC3_3_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_64 0x33A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_64 0x190F3A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_64 Register DESC0_4_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_64 0x33A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_64 0x190F3A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_64 Register DESC1_4_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_64 0x33A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_64 0x190F3A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_64 Register DESC2_4_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_64 0x33A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_64 0x190F3A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_64 Register DESC3_4_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_64 0x33A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_64 0x190F3A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_64 Register DESC0_5_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_64 0x33A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_64 0x190F3A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_64 Register DESC1_5_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_64 0x33A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_64 0x190F3A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_64 Register DESC2_5_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_64 0x33A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_64 0x190F3A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_64 Register DESC3_5_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_64 0x33A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_64 0x190F3A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_64 Register DESC0_6_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_64 0x33A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_64 0x190F3A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_64 Register DESC1_6_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_64 0x33A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_64 0x190F3A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_64 Register DESC2_6_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_64 0x33A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_64 0x190F3A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_64 Register DESC3_6_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_64 0x33A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_64 0x190F3A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_64 Register DESC0_7_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_64 0x33A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_64 0x190F3A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_64 Register DESC1_7_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_64 0x33A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_64 0x190F3A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_64 Register DESC2_7_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_64 0x33A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_64 0x190F3A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_64_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_64 Register DESC3_7_PON_EGP_S_64 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_64 0x33A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_64 0x190F3A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_64_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_64_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_64_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_64_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_64_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_65 Register CFG_PON_EGP_65 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_65 0x33C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_65 0x190F3C00u //! Register Reset Value #define CFG_PON_EGP_65_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_65_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_65_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_65_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_65_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_65_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_65_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_65_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_65_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_65_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_65_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_65 Register IRNCR_PON_EGP_65 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_65 0x33C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_65 0x190F3C20u //! Register Reset Value #define IRNCR_PON_EGP_65_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_65_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_65_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_65_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_65_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_65 Register IRNICR_PON_EGP_65 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_65 0x33C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_65 0x190F3C24u //! Register Reset Value #define IRNICR_PON_EGP_65_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_65_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_65_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_65 Register IRNEN_PON_EGP_65 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_65 0x33C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_65 0x190F3C28u //! Register Reset Value #define IRNEN_PON_EGP_65_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_65_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_65_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_65_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_65_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_65 Register DPTR_PON_EGP_65 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_65 0x33C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_65 0x190F3C30u //! Register Reset Value #define DPTR_PON_EGP_65_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_65_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_65_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_65_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_65_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_65_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_65_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_65_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_65_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_65 Register DESC0_0_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_65 0x33D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_65 0x190F3D00u //! Register Reset Value #define DESC0_0_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_65 Register DESC1_0_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_65 0x33D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_65 0x190F3D04u //! Register Reset Value #define DESC1_0_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_65 Register DESC2_0_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_65 0x33D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_65 0x190F3D08u //! Register Reset Value #define DESC2_0_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_65 Register DESC3_0_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_65 0x33D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_65 0x190F3D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_65 Register DESC0_1_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_65 0x33D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_65 0x190F3D10u //! Register Reset Value #define DESC0_1_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_65 Register DESC1_1_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_65 0x33D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_65 0x190F3D14u //! Register Reset Value #define DESC1_1_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_65 Register DESC2_1_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_65 0x33D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_65 0x190F3D18u //! Register Reset Value #define DESC2_1_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_65 Register DESC3_1_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_65 0x33D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_65 0x190F3D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_65 Register DESC0_2_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_65 0x33D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_65 0x190F3D20u //! Register Reset Value #define DESC0_2_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_65 Register DESC1_2_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_65 0x33D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_65 0x190F3D24u //! Register Reset Value #define DESC1_2_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_65 Register DESC2_2_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_65 0x33D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_65 0x190F3D28u //! Register Reset Value #define DESC2_2_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_65 Register DESC3_2_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_65 0x33D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_65 0x190F3D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_65 Register DESC0_3_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_65 0x33D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_65 0x190F3D30u //! Register Reset Value #define DESC0_3_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_65 Register DESC1_3_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_65 0x33D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_65 0x190F3D34u //! Register Reset Value #define DESC1_3_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_65 Register DESC2_3_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_65 0x33D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_65 0x190F3D38u //! Register Reset Value #define DESC2_3_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_65 Register DESC3_3_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_65 0x33D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_65 0x190F3D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_65 Register DESC0_4_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_65 0x33D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_65 0x190F3D40u //! Register Reset Value #define DESC0_4_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_65 Register DESC1_4_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_65 0x33D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_65 0x190F3D44u //! Register Reset Value #define DESC1_4_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_65 Register DESC2_4_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_65 0x33D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_65 0x190F3D48u //! Register Reset Value #define DESC2_4_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_65 Register DESC3_4_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_65 0x33D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_65 0x190F3D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_65 Register DESC0_5_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_65 0x33D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_65 0x190F3D50u //! Register Reset Value #define DESC0_5_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_65 Register DESC1_5_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_65 0x33D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_65 0x190F3D54u //! Register Reset Value #define DESC1_5_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_65 Register DESC2_5_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_65 0x33D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_65 0x190F3D58u //! Register Reset Value #define DESC2_5_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_65 Register DESC3_5_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_65 0x33D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_65 0x190F3D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_65 Register DESC0_6_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_65 0x33D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_65 0x190F3D60u //! Register Reset Value #define DESC0_6_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_65 Register DESC1_6_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_65 0x33D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_65 0x190F3D64u //! Register Reset Value #define DESC1_6_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_65 Register DESC2_6_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_65 0x33D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_65 0x190F3D68u //! Register Reset Value #define DESC2_6_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_65 Register DESC3_6_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_65 0x33D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_65 0x190F3D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_65 Register DESC0_7_PON_EGP_65 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_65 0x33D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_65 0x190F3D70u //! Register Reset Value #define DESC0_7_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_65 Register DESC1_7_PON_EGP_65 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_65 0x33D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_65 0x190F3D74u //! Register Reset Value #define DESC1_7_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_65 Register DESC2_7_PON_EGP_65 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_65 0x33D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_65 0x190F3D78u //! Register Reset Value #define DESC2_7_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_65 Register DESC3_7_PON_EGP_65 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_65 0x33D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_65 0x190F3D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_65_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_65_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_65_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_65 Register DESC0_0_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_65 0x33E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_65 0x190F3E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_65 Register DESC1_0_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_65 0x33E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_65 0x190F3E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_65 Register DESC2_0_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_65 0x33E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_65 0x190F3E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_65 Register DESC3_0_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_65 0x33E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_65 0x190F3E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_65 Register DESC0_1_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_65 0x33E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_65 0x190F3E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_65 Register DESC1_1_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_65 0x33E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_65 0x190F3E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_65 Register DESC2_1_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_65 0x33E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_65 0x190F3E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_65 Register DESC3_1_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_65 0x33E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_65 0x190F3E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_65 Register DESC0_2_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_65 0x33E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_65 0x190F3E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_65 Register DESC1_2_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_65 0x33E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_65 0x190F3E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_65 Register DESC2_2_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_65 0x33E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_65 0x190F3E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_65 Register DESC3_2_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_65 0x33E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_65 0x190F3E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_65 Register DESC0_3_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_65 0x33E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_65 0x190F3E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_65 Register DESC1_3_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_65 0x33E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_65 0x190F3E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_65 Register DESC2_3_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_65 0x33E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_65 0x190F3E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_65 Register DESC3_3_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_65 0x33E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_65 0x190F3E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_65 Register DESC0_4_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_65 0x33E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_65 0x190F3E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_65 Register DESC1_4_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_65 0x33E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_65 0x190F3E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_65 Register DESC2_4_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_65 0x33E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_65 0x190F3E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_65 Register DESC3_4_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_65 0x33E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_65 0x190F3E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_65 Register DESC0_5_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_65 0x33E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_65 0x190F3E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_65 Register DESC1_5_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_65 0x33E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_65 0x190F3E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_65 Register DESC2_5_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_65 0x33E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_65 0x190F3E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_65 Register DESC3_5_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_65 0x33E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_65 0x190F3E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_65 Register DESC0_6_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_65 0x33E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_65 0x190F3E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_65 Register DESC1_6_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_65 0x33E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_65 0x190F3E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_65 Register DESC2_6_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_65 0x33E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_65 0x190F3E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_65 Register DESC3_6_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_65 0x33E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_65 0x190F3E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_65 Register DESC0_7_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_65 0x33E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_65 0x190F3E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_65 Register DESC1_7_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_65 0x33E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_65 0x190F3E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_65 Register DESC2_7_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_65 0x33E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_65 0x190F3E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_65_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_65 Register DESC3_7_PON_EGP_S_65 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_65 0x33E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_65 0x190F3E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_65_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_65_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_65_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_65_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_65_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_66 Register CFG_PON_EGP_66 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_66 0x34000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_66 0x190F4000u //! Register Reset Value #define CFG_PON_EGP_66_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_66_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_66_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_66_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_66_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_66_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_66_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_66_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_66_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_66_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_66_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_66 Register IRNCR_PON_EGP_66 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_66 0x34020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_66 0x190F4020u //! Register Reset Value #define IRNCR_PON_EGP_66_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_66_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_66_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_66_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_66_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_66 Register IRNICR_PON_EGP_66 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_66 0x34024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_66 0x190F4024u //! Register Reset Value #define IRNICR_PON_EGP_66_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_66_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_66_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_66 Register IRNEN_PON_EGP_66 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_66 0x34028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_66 0x190F4028u //! Register Reset Value #define IRNEN_PON_EGP_66_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_66_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_66_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_66_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_66_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_66 Register DPTR_PON_EGP_66 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_66 0x34030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_66 0x190F4030u //! Register Reset Value #define DPTR_PON_EGP_66_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_66_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_66_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_66_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_66_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_66_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_66_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_66_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_66_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_66 Register DESC0_0_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_66 0x34100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_66 0x190F4100u //! Register Reset Value #define DESC0_0_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_66 Register DESC1_0_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_66 0x34104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_66 0x190F4104u //! Register Reset Value #define DESC1_0_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_66 Register DESC2_0_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_66 0x34108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_66 0x190F4108u //! Register Reset Value #define DESC2_0_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_66 Register DESC3_0_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_66 0x3410C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_66 0x190F410Cu //! Register Reset Value #define DESC3_0_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_66 Register DESC0_1_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_66 0x34110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_66 0x190F4110u //! Register Reset Value #define DESC0_1_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_66 Register DESC1_1_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_66 0x34114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_66 0x190F4114u //! Register Reset Value #define DESC1_1_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_66 Register DESC2_1_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_66 0x34118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_66 0x190F4118u //! Register Reset Value #define DESC2_1_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_66 Register DESC3_1_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_66 0x3411C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_66 0x190F411Cu //! Register Reset Value #define DESC3_1_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_66 Register DESC0_2_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_66 0x34120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_66 0x190F4120u //! Register Reset Value #define DESC0_2_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_66 Register DESC1_2_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_66 0x34124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_66 0x190F4124u //! Register Reset Value #define DESC1_2_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_66 Register DESC2_2_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_66 0x34128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_66 0x190F4128u //! Register Reset Value #define DESC2_2_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_66 Register DESC3_2_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_66 0x3412C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_66 0x190F412Cu //! Register Reset Value #define DESC3_2_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_66 Register DESC0_3_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_66 0x34130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_66 0x190F4130u //! Register Reset Value #define DESC0_3_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_66 Register DESC1_3_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_66 0x34134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_66 0x190F4134u //! Register Reset Value #define DESC1_3_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_66 Register DESC2_3_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_66 0x34138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_66 0x190F4138u //! Register Reset Value #define DESC2_3_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_66 Register DESC3_3_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_66 0x3413C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_66 0x190F413Cu //! Register Reset Value #define DESC3_3_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_66 Register DESC0_4_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_66 0x34140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_66 0x190F4140u //! Register Reset Value #define DESC0_4_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_66 Register DESC1_4_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_66 0x34144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_66 0x190F4144u //! Register Reset Value #define DESC1_4_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_66 Register DESC2_4_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_66 0x34148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_66 0x190F4148u //! Register Reset Value #define DESC2_4_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_66 Register DESC3_4_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_66 0x3414C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_66 0x190F414Cu //! Register Reset Value #define DESC3_4_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_66 Register DESC0_5_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_66 0x34150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_66 0x190F4150u //! Register Reset Value #define DESC0_5_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_66 Register DESC1_5_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_66 0x34154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_66 0x190F4154u //! Register Reset Value #define DESC1_5_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_66 Register DESC2_5_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_66 0x34158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_66 0x190F4158u //! Register Reset Value #define DESC2_5_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_66 Register DESC3_5_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_66 0x3415C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_66 0x190F415Cu //! Register Reset Value #define DESC3_5_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_66 Register DESC0_6_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_66 0x34160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_66 0x190F4160u //! Register Reset Value #define DESC0_6_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_66 Register DESC1_6_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_66 0x34164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_66 0x190F4164u //! Register Reset Value #define DESC1_6_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_66 Register DESC2_6_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_66 0x34168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_66 0x190F4168u //! Register Reset Value #define DESC2_6_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_66 Register DESC3_6_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_66 0x3416C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_66 0x190F416Cu //! Register Reset Value #define DESC3_6_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_66 Register DESC0_7_PON_EGP_66 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_66 0x34170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_66 0x190F4170u //! Register Reset Value #define DESC0_7_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_66 Register DESC1_7_PON_EGP_66 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_66 0x34174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_66 0x190F4174u //! Register Reset Value #define DESC1_7_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_66 Register DESC2_7_PON_EGP_66 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_66 0x34178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_66 0x190F4178u //! Register Reset Value #define DESC2_7_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_66 Register DESC3_7_PON_EGP_66 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_66 0x3417C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_66 0x190F417Cu //! Register Reset Value #define DESC3_7_PON_EGP_66_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_66_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_66_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_66 Register DESC0_0_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_66 0x34200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_66 0x190F4200u //! Register Reset Value #define DESC0_0_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_66 Register DESC1_0_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_66 0x34204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_66 0x190F4204u //! Register Reset Value #define DESC1_0_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_66 Register DESC2_0_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_66 0x34208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_66 0x190F4208u //! Register Reset Value #define DESC2_0_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_66 Register DESC3_0_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_66 0x3420C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_66 0x190F420Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_66 Register DESC0_1_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_66 0x34210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_66 0x190F4210u //! Register Reset Value #define DESC0_1_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_66 Register DESC1_1_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_66 0x34214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_66 0x190F4214u //! Register Reset Value #define DESC1_1_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_66 Register DESC2_1_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_66 0x34218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_66 0x190F4218u //! Register Reset Value #define DESC2_1_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_66 Register DESC3_1_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_66 0x3421C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_66 0x190F421Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_66 Register DESC0_2_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_66 0x34220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_66 0x190F4220u //! Register Reset Value #define DESC0_2_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_66 Register DESC1_2_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_66 0x34224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_66 0x190F4224u //! Register Reset Value #define DESC1_2_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_66 Register DESC2_2_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_66 0x34228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_66 0x190F4228u //! Register Reset Value #define DESC2_2_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_66 Register DESC3_2_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_66 0x3422C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_66 0x190F422Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_66 Register DESC0_3_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_66 0x34230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_66 0x190F4230u //! Register Reset Value #define DESC0_3_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_66 Register DESC1_3_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_66 0x34234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_66 0x190F4234u //! Register Reset Value #define DESC1_3_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_66 Register DESC2_3_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_66 0x34238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_66 0x190F4238u //! Register Reset Value #define DESC2_3_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_66 Register DESC3_3_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_66 0x3423C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_66 0x190F423Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_66 Register DESC0_4_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_66 0x34240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_66 0x190F4240u //! Register Reset Value #define DESC0_4_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_66 Register DESC1_4_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_66 0x34244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_66 0x190F4244u //! Register Reset Value #define DESC1_4_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_66 Register DESC2_4_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_66 0x34248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_66 0x190F4248u //! Register Reset Value #define DESC2_4_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_66 Register DESC3_4_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_66 0x3424C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_66 0x190F424Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_66 Register DESC0_5_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_66 0x34250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_66 0x190F4250u //! Register Reset Value #define DESC0_5_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_66 Register DESC1_5_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_66 0x34254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_66 0x190F4254u //! Register Reset Value #define DESC1_5_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_66 Register DESC2_5_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_66 0x34258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_66 0x190F4258u //! Register Reset Value #define DESC2_5_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_66 Register DESC3_5_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_66 0x3425C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_66 0x190F425Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_66 Register DESC0_6_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_66 0x34260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_66 0x190F4260u //! Register Reset Value #define DESC0_6_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_66 Register DESC1_6_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_66 0x34264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_66 0x190F4264u //! Register Reset Value #define DESC1_6_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_66 Register DESC2_6_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_66 0x34268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_66 0x190F4268u //! Register Reset Value #define DESC2_6_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_66 Register DESC3_6_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_66 0x3426C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_66 0x190F426Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_66 Register DESC0_7_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_66 0x34270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_66 0x190F4270u //! Register Reset Value #define DESC0_7_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_66 Register DESC1_7_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_66 0x34274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_66 0x190F4274u //! Register Reset Value #define DESC1_7_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_66 Register DESC2_7_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_66 0x34278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_66 0x190F4278u //! Register Reset Value #define DESC2_7_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_66_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_66 Register DESC3_7_PON_EGP_S_66 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_66 0x3427C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_66 0x190F427Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_66_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_66_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_66_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_66_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_66_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_67 Register CFG_PON_EGP_67 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_67 0x34400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_67 0x190F4400u //! Register Reset Value #define CFG_PON_EGP_67_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_67_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_67_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_67_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_67_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_67_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_67_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_67_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_67_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_67_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_67_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_67 Register IRNCR_PON_EGP_67 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_67 0x34420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_67 0x190F4420u //! Register Reset Value #define IRNCR_PON_EGP_67_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_67_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_67_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_67_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_67_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_67 Register IRNICR_PON_EGP_67 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_67 0x34424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_67 0x190F4424u //! Register Reset Value #define IRNICR_PON_EGP_67_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_67_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_67_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_67 Register IRNEN_PON_EGP_67 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_67 0x34428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_67 0x190F4428u //! Register Reset Value #define IRNEN_PON_EGP_67_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_67_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_67_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_67_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_67_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_67 Register DPTR_PON_EGP_67 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_67 0x34430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_67 0x190F4430u //! Register Reset Value #define DPTR_PON_EGP_67_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_67_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_67_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_67_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_67_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_67_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_67_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_67_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_67_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_67 Register DESC0_0_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_67 0x34500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_67 0x190F4500u //! Register Reset Value #define DESC0_0_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_67 Register DESC1_0_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_67 0x34504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_67 0x190F4504u //! Register Reset Value #define DESC1_0_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_67 Register DESC2_0_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_67 0x34508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_67 0x190F4508u //! Register Reset Value #define DESC2_0_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_67 Register DESC3_0_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_67 0x3450C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_67 0x190F450Cu //! Register Reset Value #define DESC3_0_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_67 Register DESC0_1_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_67 0x34510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_67 0x190F4510u //! Register Reset Value #define DESC0_1_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_67 Register DESC1_1_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_67 0x34514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_67 0x190F4514u //! Register Reset Value #define DESC1_1_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_67 Register DESC2_1_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_67 0x34518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_67 0x190F4518u //! Register Reset Value #define DESC2_1_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_67 Register DESC3_1_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_67 0x3451C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_67 0x190F451Cu //! Register Reset Value #define DESC3_1_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_67 Register DESC0_2_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_67 0x34520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_67 0x190F4520u //! Register Reset Value #define DESC0_2_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_67 Register DESC1_2_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_67 0x34524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_67 0x190F4524u //! Register Reset Value #define DESC1_2_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_67 Register DESC2_2_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_67 0x34528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_67 0x190F4528u //! Register Reset Value #define DESC2_2_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_67 Register DESC3_2_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_67 0x3452C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_67 0x190F452Cu //! Register Reset Value #define DESC3_2_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_67 Register DESC0_3_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_67 0x34530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_67 0x190F4530u //! Register Reset Value #define DESC0_3_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_67 Register DESC1_3_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_67 0x34534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_67 0x190F4534u //! Register Reset Value #define DESC1_3_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_67 Register DESC2_3_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_67 0x34538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_67 0x190F4538u //! Register Reset Value #define DESC2_3_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_67 Register DESC3_3_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_67 0x3453C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_67 0x190F453Cu //! Register Reset Value #define DESC3_3_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_67 Register DESC0_4_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_67 0x34540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_67 0x190F4540u //! Register Reset Value #define DESC0_4_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_67 Register DESC1_4_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_67 0x34544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_67 0x190F4544u //! Register Reset Value #define DESC1_4_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_67 Register DESC2_4_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_67 0x34548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_67 0x190F4548u //! Register Reset Value #define DESC2_4_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_67 Register DESC3_4_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_67 0x3454C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_67 0x190F454Cu //! Register Reset Value #define DESC3_4_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_67 Register DESC0_5_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_67 0x34550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_67 0x190F4550u //! Register Reset Value #define DESC0_5_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_67 Register DESC1_5_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_67 0x34554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_67 0x190F4554u //! Register Reset Value #define DESC1_5_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_67 Register DESC2_5_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_67 0x34558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_67 0x190F4558u //! Register Reset Value #define DESC2_5_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_67 Register DESC3_5_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_67 0x3455C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_67 0x190F455Cu //! Register Reset Value #define DESC3_5_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_67 Register DESC0_6_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_67 0x34560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_67 0x190F4560u //! Register Reset Value #define DESC0_6_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_67 Register DESC1_6_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_67 0x34564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_67 0x190F4564u //! Register Reset Value #define DESC1_6_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_67 Register DESC2_6_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_67 0x34568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_67 0x190F4568u //! Register Reset Value #define DESC2_6_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_67 Register DESC3_6_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_67 0x3456C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_67 0x190F456Cu //! Register Reset Value #define DESC3_6_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_67 Register DESC0_7_PON_EGP_67 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_67 0x34570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_67 0x190F4570u //! Register Reset Value #define DESC0_7_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_67 Register DESC1_7_PON_EGP_67 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_67 0x34574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_67 0x190F4574u //! Register Reset Value #define DESC1_7_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_67 Register DESC2_7_PON_EGP_67 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_67 0x34578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_67 0x190F4578u //! Register Reset Value #define DESC2_7_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_67 Register DESC3_7_PON_EGP_67 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_67 0x3457C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_67 0x190F457Cu //! Register Reset Value #define DESC3_7_PON_EGP_67_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_67_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_67_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_67 Register DESC0_0_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_67 0x34600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_67 0x190F4600u //! Register Reset Value #define DESC0_0_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_67 Register DESC1_0_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_67 0x34604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_67 0x190F4604u //! Register Reset Value #define DESC1_0_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_67 Register DESC2_0_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_67 0x34608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_67 0x190F4608u //! Register Reset Value #define DESC2_0_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_67 Register DESC3_0_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_67 0x3460C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_67 0x190F460Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_67 Register DESC0_1_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_67 0x34610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_67 0x190F4610u //! Register Reset Value #define DESC0_1_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_67 Register DESC1_1_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_67 0x34614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_67 0x190F4614u //! Register Reset Value #define DESC1_1_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_67 Register DESC2_1_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_67 0x34618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_67 0x190F4618u //! Register Reset Value #define DESC2_1_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_67 Register DESC3_1_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_67 0x3461C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_67 0x190F461Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_67 Register DESC0_2_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_67 0x34620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_67 0x190F4620u //! Register Reset Value #define DESC0_2_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_67 Register DESC1_2_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_67 0x34624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_67 0x190F4624u //! Register Reset Value #define DESC1_2_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_67 Register DESC2_2_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_67 0x34628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_67 0x190F4628u //! Register Reset Value #define DESC2_2_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_67 Register DESC3_2_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_67 0x3462C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_67 0x190F462Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_67 Register DESC0_3_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_67 0x34630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_67 0x190F4630u //! Register Reset Value #define DESC0_3_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_67 Register DESC1_3_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_67 0x34634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_67 0x190F4634u //! Register Reset Value #define DESC1_3_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_67 Register DESC2_3_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_67 0x34638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_67 0x190F4638u //! Register Reset Value #define DESC2_3_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_67 Register DESC3_3_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_67 0x3463C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_67 0x190F463Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_67 Register DESC0_4_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_67 0x34640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_67 0x190F4640u //! Register Reset Value #define DESC0_4_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_67 Register DESC1_4_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_67 0x34644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_67 0x190F4644u //! Register Reset Value #define DESC1_4_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_67 Register DESC2_4_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_67 0x34648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_67 0x190F4648u //! Register Reset Value #define DESC2_4_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_67 Register DESC3_4_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_67 0x3464C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_67 0x190F464Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_67 Register DESC0_5_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_67 0x34650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_67 0x190F4650u //! Register Reset Value #define DESC0_5_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_67 Register DESC1_5_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_67 0x34654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_67 0x190F4654u //! Register Reset Value #define DESC1_5_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_67 Register DESC2_5_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_67 0x34658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_67 0x190F4658u //! Register Reset Value #define DESC2_5_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_67 Register DESC3_5_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_67 0x3465C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_67 0x190F465Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_67 Register DESC0_6_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_67 0x34660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_67 0x190F4660u //! Register Reset Value #define DESC0_6_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_67 Register DESC1_6_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_67 0x34664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_67 0x190F4664u //! Register Reset Value #define DESC1_6_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_67 Register DESC2_6_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_67 0x34668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_67 0x190F4668u //! Register Reset Value #define DESC2_6_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_67 Register DESC3_6_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_67 0x3466C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_67 0x190F466Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_67 Register DESC0_7_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_67 0x34670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_67 0x190F4670u //! Register Reset Value #define DESC0_7_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_67 Register DESC1_7_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_67 0x34674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_67 0x190F4674u //! Register Reset Value #define DESC1_7_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_67 Register DESC2_7_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_67 0x34678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_67 0x190F4678u //! Register Reset Value #define DESC2_7_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_67_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_67 Register DESC3_7_PON_EGP_S_67 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_67 0x3467C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_67 0x190F467Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_67_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_67_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_67_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_67_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_67_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_68 Register CFG_PON_EGP_68 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_68 0x34800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_68 0x190F4800u //! Register Reset Value #define CFG_PON_EGP_68_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_68_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_68_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_68_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_68_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_68_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_68_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_68_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_68_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_68_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_68_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_68 Register IRNCR_PON_EGP_68 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_68 0x34820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_68 0x190F4820u //! Register Reset Value #define IRNCR_PON_EGP_68_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_68_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_68_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_68_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_68_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_68 Register IRNICR_PON_EGP_68 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_68 0x34824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_68 0x190F4824u //! Register Reset Value #define IRNICR_PON_EGP_68_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_68_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_68_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_68 Register IRNEN_PON_EGP_68 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_68 0x34828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_68 0x190F4828u //! Register Reset Value #define IRNEN_PON_EGP_68_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_68_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_68_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_68_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_68_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_68 Register DPTR_PON_EGP_68 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_68 0x34830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_68 0x190F4830u //! Register Reset Value #define DPTR_PON_EGP_68_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_68_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_68_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_68_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_68_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_68_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_68_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_68_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_68_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_68 Register DESC0_0_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_68 0x34900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_68 0x190F4900u //! Register Reset Value #define DESC0_0_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_68 Register DESC1_0_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_68 0x34904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_68 0x190F4904u //! Register Reset Value #define DESC1_0_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_68 Register DESC2_0_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_68 0x34908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_68 0x190F4908u //! Register Reset Value #define DESC2_0_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_68 Register DESC3_0_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_68 0x3490C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_68 0x190F490Cu //! Register Reset Value #define DESC3_0_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_68 Register DESC0_1_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_68 0x34910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_68 0x190F4910u //! Register Reset Value #define DESC0_1_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_68 Register DESC1_1_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_68 0x34914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_68 0x190F4914u //! Register Reset Value #define DESC1_1_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_68 Register DESC2_1_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_68 0x34918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_68 0x190F4918u //! Register Reset Value #define DESC2_1_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_68 Register DESC3_1_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_68 0x3491C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_68 0x190F491Cu //! Register Reset Value #define DESC3_1_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_68 Register DESC0_2_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_68 0x34920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_68 0x190F4920u //! Register Reset Value #define DESC0_2_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_68 Register DESC1_2_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_68 0x34924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_68 0x190F4924u //! Register Reset Value #define DESC1_2_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_68 Register DESC2_2_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_68 0x34928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_68 0x190F4928u //! Register Reset Value #define DESC2_2_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_68 Register DESC3_2_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_68 0x3492C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_68 0x190F492Cu //! Register Reset Value #define DESC3_2_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_68 Register DESC0_3_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_68 0x34930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_68 0x190F4930u //! Register Reset Value #define DESC0_3_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_68 Register DESC1_3_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_68 0x34934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_68 0x190F4934u //! Register Reset Value #define DESC1_3_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_68 Register DESC2_3_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_68 0x34938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_68 0x190F4938u //! Register Reset Value #define DESC2_3_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_68 Register DESC3_3_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_68 0x3493C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_68 0x190F493Cu //! Register Reset Value #define DESC3_3_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_68 Register DESC0_4_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_68 0x34940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_68 0x190F4940u //! Register Reset Value #define DESC0_4_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_68 Register DESC1_4_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_68 0x34944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_68 0x190F4944u //! Register Reset Value #define DESC1_4_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_68 Register DESC2_4_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_68 0x34948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_68 0x190F4948u //! Register Reset Value #define DESC2_4_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_68 Register DESC3_4_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_68 0x3494C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_68 0x190F494Cu //! Register Reset Value #define DESC3_4_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_68 Register DESC0_5_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_68 0x34950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_68 0x190F4950u //! Register Reset Value #define DESC0_5_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_68 Register DESC1_5_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_68 0x34954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_68 0x190F4954u //! Register Reset Value #define DESC1_5_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_68 Register DESC2_5_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_68 0x34958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_68 0x190F4958u //! Register Reset Value #define DESC2_5_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_68 Register DESC3_5_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_68 0x3495C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_68 0x190F495Cu //! Register Reset Value #define DESC3_5_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_68 Register DESC0_6_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_68 0x34960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_68 0x190F4960u //! Register Reset Value #define DESC0_6_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_68 Register DESC1_6_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_68 0x34964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_68 0x190F4964u //! Register Reset Value #define DESC1_6_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_68 Register DESC2_6_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_68 0x34968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_68 0x190F4968u //! Register Reset Value #define DESC2_6_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_68 Register DESC3_6_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_68 0x3496C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_68 0x190F496Cu //! Register Reset Value #define DESC3_6_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_68 Register DESC0_7_PON_EGP_68 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_68 0x34970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_68 0x190F4970u //! Register Reset Value #define DESC0_7_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_68 Register DESC1_7_PON_EGP_68 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_68 0x34974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_68 0x190F4974u //! Register Reset Value #define DESC1_7_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_68 Register DESC2_7_PON_EGP_68 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_68 0x34978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_68 0x190F4978u //! Register Reset Value #define DESC2_7_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_68 Register DESC3_7_PON_EGP_68 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_68 0x3497C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_68 0x190F497Cu //! Register Reset Value #define DESC3_7_PON_EGP_68_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_68_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_68_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_68 Register DESC0_0_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_68 0x34A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_68 0x190F4A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_68 Register DESC1_0_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_68 0x34A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_68 0x190F4A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_68 Register DESC2_0_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_68 0x34A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_68 0x190F4A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_68 Register DESC3_0_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_68 0x34A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_68 0x190F4A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_68 Register DESC0_1_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_68 0x34A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_68 0x190F4A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_68 Register DESC1_1_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_68 0x34A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_68 0x190F4A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_68 Register DESC2_1_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_68 0x34A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_68 0x190F4A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_68 Register DESC3_1_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_68 0x34A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_68 0x190F4A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_68 Register DESC0_2_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_68 0x34A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_68 0x190F4A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_68 Register DESC1_2_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_68 0x34A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_68 0x190F4A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_68 Register DESC2_2_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_68 0x34A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_68 0x190F4A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_68 Register DESC3_2_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_68 0x34A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_68 0x190F4A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_68 Register DESC0_3_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_68 0x34A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_68 0x190F4A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_68 Register DESC1_3_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_68 0x34A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_68 0x190F4A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_68 Register DESC2_3_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_68 0x34A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_68 0x190F4A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_68 Register DESC3_3_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_68 0x34A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_68 0x190F4A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_68 Register DESC0_4_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_68 0x34A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_68 0x190F4A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_68 Register DESC1_4_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_68 0x34A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_68 0x190F4A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_68 Register DESC2_4_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_68 0x34A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_68 0x190F4A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_68 Register DESC3_4_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_68 0x34A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_68 0x190F4A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_68 Register DESC0_5_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_68 0x34A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_68 0x190F4A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_68 Register DESC1_5_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_68 0x34A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_68 0x190F4A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_68 Register DESC2_5_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_68 0x34A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_68 0x190F4A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_68 Register DESC3_5_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_68 0x34A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_68 0x190F4A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_68 Register DESC0_6_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_68 0x34A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_68 0x190F4A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_68 Register DESC1_6_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_68 0x34A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_68 0x190F4A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_68 Register DESC2_6_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_68 0x34A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_68 0x190F4A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_68 Register DESC3_6_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_68 0x34A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_68 0x190F4A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_68 Register DESC0_7_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_68 0x34A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_68 0x190F4A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_68 Register DESC1_7_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_68 0x34A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_68 0x190F4A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_68 Register DESC2_7_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_68 0x34A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_68 0x190F4A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_68_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_68 Register DESC3_7_PON_EGP_S_68 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_68 0x34A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_68 0x190F4A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_68_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_68_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_68_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_68_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_68_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_69 Register CFG_PON_EGP_69 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_69 0x34C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_69 0x190F4C00u //! Register Reset Value #define CFG_PON_EGP_69_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_69_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_69_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_69_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_69_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_69_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_69_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_69_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_69_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_69_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_69_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_69 Register IRNCR_PON_EGP_69 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_69 0x34C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_69 0x190F4C20u //! Register Reset Value #define IRNCR_PON_EGP_69_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_69_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_69_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_69_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_69_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_69 Register IRNICR_PON_EGP_69 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_69 0x34C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_69 0x190F4C24u //! Register Reset Value #define IRNICR_PON_EGP_69_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_69_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_69_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_69 Register IRNEN_PON_EGP_69 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_69 0x34C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_69 0x190F4C28u //! Register Reset Value #define IRNEN_PON_EGP_69_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_69_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_69_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_69_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_69_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_69 Register DPTR_PON_EGP_69 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_69 0x34C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_69 0x190F4C30u //! Register Reset Value #define DPTR_PON_EGP_69_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_69_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_69_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_69_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_69_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_69_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_69_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_69_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_69_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_69 Register DESC0_0_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_69 0x34D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_69 0x190F4D00u //! Register Reset Value #define DESC0_0_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_69 Register DESC1_0_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_69 0x34D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_69 0x190F4D04u //! Register Reset Value #define DESC1_0_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_69 Register DESC2_0_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_69 0x34D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_69 0x190F4D08u //! Register Reset Value #define DESC2_0_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_69 Register DESC3_0_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_69 0x34D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_69 0x190F4D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_69 Register DESC0_1_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_69 0x34D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_69 0x190F4D10u //! Register Reset Value #define DESC0_1_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_69 Register DESC1_1_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_69 0x34D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_69 0x190F4D14u //! Register Reset Value #define DESC1_1_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_69 Register DESC2_1_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_69 0x34D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_69 0x190F4D18u //! Register Reset Value #define DESC2_1_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_69 Register DESC3_1_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_69 0x34D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_69 0x190F4D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_69 Register DESC0_2_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_69 0x34D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_69 0x190F4D20u //! Register Reset Value #define DESC0_2_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_69 Register DESC1_2_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_69 0x34D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_69 0x190F4D24u //! Register Reset Value #define DESC1_2_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_69 Register DESC2_2_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_69 0x34D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_69 0x190F4D28u //! Register Reset Value #define DESC2_2_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_69 Register DESC3_2_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_69 0x34D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_69 0x190F4D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_69 Register DESC0_3_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_69 0x34D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_69 0x190F4D30u //! Register Reset Value #define DESC0_3_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_69 Register DESC1_3_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_69 0x34D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_69 0x190F4D34u //! Register Reset Value #define DESC1_3_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_69 Register DESC2_3_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_69 0x34D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_69 0x190F4D38u //! Register Reset Value #define DESC2_3_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_69 Register DESC3_3_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_69 0x34D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_69 0x190F4D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_69 Register DESC0_4_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_69 0x34D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_69 0x190F4D40u //! Register Reset Value #define DESC0_4_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_69 Register DESC1_4_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_69 0x34D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_69 0x190F4D44u //! Register Reset Value #define DESC1_4_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_69 Register DESC2_4_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_69 0x34D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_69 0x190F4D48u //! Register Reset Value #define DESC2_4_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_69 Register DESC3_4_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_69 0x34D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_69 0x190F4D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_69 Register DESC0_5_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_69 0x34D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_69 0x190F4D50u //! Register Reset Value #define DESC0_5_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_69 Register DESC1_5_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_69 0x34D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_69 0x190F4D54u //! Register Reset Value #define DESC1_5_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_69 Register DESC2_5_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_69 0x34D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_69 0x190F4D58u //! Register Reset Value #define DESC2_5_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_69 Register DESC3_5_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_69 0x34D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_69 0x190F4D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_69 Register DESC0_6_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_69 0x34D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_69 0x190F4D60u //! Register Reset Value #define DESC0_6_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_69 Register DESC1_6_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_69 0x34D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_69 0x190F4D64u //! Register Reset Value #define DESC1_6_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_69 Register DESC2_6_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_69 0x34D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_69 0x190F4D68u //! Register Reset Value #define DESC2_6_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_69 Register DESC3_6_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_69 0x34D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_69 0x190F4D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_69 Register DESC0_7_PON_EGP_69 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_69 0x34D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_69 0x190F4D70u //! Register Reset Value #define DESC0_7_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_69 Register DESC1_7_PON_EGP_69 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_69 0x34D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_69 0x190F4D74u //! Register Reset Value #define DESC1_7_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_69 Register DESC2_7_PON_EGP_69 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_69 0x34D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_69 0x190F4D78u //! Register Reset Value #define DESC2_7_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_69 Register DESC3_7_PON_EGP_69 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_69 0x34D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_69 0x190F4D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_69_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_69_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_69_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_69 Register DESC0_0_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_69 0x34E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_69 0x190F4E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_69 Register DESC1_0_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_69 0x34E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_69 0x190F4E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_69 Register DESC2_0_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_69 0x34E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_69 0x190F4E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_69 Register DESC3_0_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_69 0x34E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_69 0x190F4E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_69 Register DESC0_1_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_69 0x34E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_69 0x190F4E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_69 Register DESC1_1_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_69 0x34E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_69 0x190F4E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_69 Register DESC2_1_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_69 0x34E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_69 0x190F4E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_69 Register DESC3_1_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_69 0x34E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_69 0x190F4E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_69 Register DESC0_2_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_69 0x34E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_69 0x190F4E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_69 Register DESC1_2_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_69 0x34E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_69 0x190F4E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_69 Register DESC2_2_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_69 0x34E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_69 0x190F4E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_69 Register DESC3_2_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_69 0x34E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_69 0x190F4E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_69 Register DESC0_3_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_69 0x34E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_69 0x190F4E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_69 Register DESC1_3_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_69 0x34E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_69 0x190F4E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_69 Register DESC2_3_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_69 0x34E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_69 0x190F4E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_69 Register DESC3_3_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_69 0x34E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_69 0x190F4E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_69 Register DESC0_4_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_69 0x34E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_69 0x190F4E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_69 Register DESC1_4_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_69 0x34E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_69 0x190F4E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_69 Register DESC2_4_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_69 0x34E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_69 0x190F4E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_69 Register DESC3_4_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_69 0x34E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_69 0x190F4E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_69 Register DESC0_5_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_69 0x34E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_69 0x190F4E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_69 Register DESC1_5_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_69 0x34E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_69 0x190F4E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_69 Register DESC2_5_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_69 0x34E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_69 0x190F4E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_69 Register DESC3_5_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_69 0x34E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_69 0x190F4E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_69 Register DESC0_6_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_69 0x34E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_69 0x190F4E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_69 Register DESC1_6_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_69 0x34E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_69 0x190F4E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_69 Register DESC2_6_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_69 0x34E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_69 0x190F4E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_69 Register DESC3_6_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_69 0x34E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_69 0x190F4E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_69 Register DESC0_7_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_69 0x34E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_69 0x190F4E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_69 Register DESC1_7_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_69 0x34E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_69 0x190F4E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_69 Register DESC2_7_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_69 0x34E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_69 0x190F4E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_69_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_69 Register DESC3_7_PON_EGP_S_69 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_69 0x34E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_69 0x190F4E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_69_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_69_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_69_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_69_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_69_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_70 Register CFG_PON_EGP_70 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_70 0x35000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_70 0x190F5000u //! Register Reset Value #define CFG_PON_EGP_70_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_70_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_70_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_70_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_70_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_70_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_70_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_70_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_70_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_70_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_70_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_70 Register IRNCR_PON_EGP_70 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_70 0x35020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_70 0x190F5020u //! Register Reset Value #define IRNCR_PON_EGP_70_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_70_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_70_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_70_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_70_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_70 Register IRNICR_PON_EGP_70 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_70 0x35024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_70 0x190F5024u //! Register Reset Value #define IRNICR_PON_EGP_70_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_70_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_70_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_70 Register IRNEN_PON_EGP_70 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_70 0x35028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_70 0x190F5028u //! Register Reset Value #define IRNEN_PON_EGP_70_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_70_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_70_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_70_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_70_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_70 Register DPTR_PON_EGP_70 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_70 0x35030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_70 0x190F5030u //! Register Reset Value #define DPTR_PON_EGP_70_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_70_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_70_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_70_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_70_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_70_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_70_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_70_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_70_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_70 Register DESC0_0_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_70 0x35100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_70 0x190F5100u //! Register Reset Value #define DESC0_0_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_70 Register DESC1_0_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_70 0x35104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_70 0x190F5104u //! Register Reset Value #define DESC1_0_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_70 Register DESC2_0_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_70 0x35108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_70 0x190F5108u //! Register Reset Value #define DESC2_0_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_70 Register DESC3_0_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_70 0x3510C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_70 0x190F510Cu //! Register Reset Value #define DESC3_0_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_70 Register DESC0_1_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_70 0x35110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_70 0x190F5110u //! Register Reset Value #define DESC0_1_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_70 Register DESC1_1_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_70 0x35114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_70 0x190F5114u //! Register Reset Value #define DESC1_1_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_70 Register DESC2_1_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_70 0x35118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_70 0x190F5118u //! Register Reset Value #define DESC2_1_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_70 Register DESC3_1_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_70 0x3511C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_70 0x190F511Cu //! Register Reset Value #define DESC3_1_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_70 Register DESC0_2_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_70 0x35120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_70 0x190F5120u //! Register Reset Value #define DESC0_2_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_70 Register DESC1_2_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_70 0x35124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_70 0x190F5124u //! Register Reset Value #define DESC1_2_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_70 Register DESC2_2_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_70 0x35128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_70 0x190F5128u //! Register Reset Value #define DESC2_2_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_70 Register DESC3_2_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_70 0x3512C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_70 0x190F512Cu //! Register Reset Value #define DESC3_2_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_70 Register DESC0_3_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_70 0x35130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_70 0x190F5130u //! Register Reset Value #define DESC0_3_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_70 Register DESC1_3_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_70 0x35134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_70 0x190F5134u //! Register Reset Value #define DESC1_3_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_70 Register DESC2_3_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_70 0x35138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_70 0x190F5138u //! Register Reset Value #define DESC2_3_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_70 Register DESC3_3_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_70 0x3513C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_70 0x190F513Cu //! Register Reset Value #define DESC3_3_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_70 Register DESC0_4_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_70 0x35140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_70 0x190F5140u //! Register Reset Value #define DESC0_4_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_70 Register DESC1_4_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_70 0x35144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_70 0x190F5144u //! Register Reset Value #define DESC1_4_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_70 Register DESC2_4_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_70 0x35148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_70 0x190F5148u //! Register Reset Value #define DESC2_4_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_70 Register DESC3_4_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_70 0x3514C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_70 0x190F514Cu //! Register Reset Value #define DESC3_4_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_70 Register DESC0_5_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_70 0x35150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_70 0x190F5150u //! Register Reset Value #define DESC0_5_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_70 Register DESC1_5_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_70 0x35154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_70 0x190F5154u //! Register Reset Value #define DESC1_5_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_70 Register DESC2_5_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_70 0x35158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_70 0x190F5158u //! Register Reset Value #define DESC2_5_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_70 Register DESC3_5_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_70 0x3515C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_70 0x190F515Cu //! Register Reset Value #define DESC3_5_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_70 Register DESC0_6_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_70 0x35160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_70 0x190F5160u //! Register Reset Value #define DESC0_6_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_70 Register DESC1_6_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_70 0x35164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_70 0x190F5164u //! Register Reset Value #define DESC1_6_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_70 Register DESC2_6_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_70 0x35168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_70 0x190F5168u //! Register Reset Value #define DESC2_6_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_70 Register DESC3_6_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_70 0x3516C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_70 0x190F516Cu //! Register Reset Value #define DESC3_6_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_70 Register DESC0_7_PON_EGP_70 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_70 0x35170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_70 0x190F5170u //! Register Reset Value #define DESC0_7_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_70 Register DESC1_7_PON_EGP_70 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_70 0x35174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_70 0x190F5174u //! Register Reset Value #define DESC1_7_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_70 Register DESC2_7_PON_EGP_70 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_70 0x35178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_70 0x190F5178u //! Register Reset Value #define DESC2_7_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_70 Register DESC3_7_PON_EGP_70 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_70 0x3517C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_70 0x190F517Cu //! Register Reset Value #define DESC3_7_PON_EGP_70_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_70_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_70_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_70 Register DESC0_0_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_70 0x35200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_70 0x190F5200u //! Register Reset Value #define DESC0_0_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_70 Register DESC1_0_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_70 0x35204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_70 0x190F5204u //! Register Reset Value #define DESC1_0_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_70 Register DESC2_0_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_70 0x35208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_70 0x190F5208u //! Register Reset Value #define DESC2_0_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_70 Register DESC3_0_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_70 0x3520C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_70 0x190F520Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_70 Register DESC0_1_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_70 0x35210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_70 0x190F5210u //! Register Reset Value #define DESC0_1_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_70 Register DESC1_1_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_70 0x35214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_70 0x190F5214u //! Register Reset Value #define DESC1_1_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_70 Register DESC2_1_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_70 0x35218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_70 0x190F5218u //! Register Reset Value #define DESC2_1_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_70 Register DESC3_1_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_70 0x3521C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_70 0x190F521Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_70 Register DESC0_2_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_70 0x35220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_70 0x190F5220u //! Register Reset Value #define DESC0_2_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_70 Register DESC1_2_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_70 0x35224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_70 0x190F5224u //! Register Reset Value #define DESC1_2_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_70 Register DESC2_2_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_70 0x35228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_70 0x190F5228u //! Register Reset Value #define DESC2_2_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_70 Register DESC3_2_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_70 0x3522C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_70 0x190F522Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_70 Register DESC0_3_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_70 0x35230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_70 0x190F5230u //! Register Reset Value #define DESC0_3_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_70 Register DESC1_3_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_70 0x35234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_70 0x190F5234u //! Register Reset Value #define DESC1_3_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_70 Register DESC2_3_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_70 0x35238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_70 0x190F5238u //! Register Reset Value #define DESC2_3_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_70 Register DESC3_3_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_70 0x3523C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_70 0x190F523Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_70 Register DESC0_4_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_70 0x35240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_70 0x190F5240u //! Register Reset Value #define DESC0_4_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_70 Register DESC1_4_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_70 0x35244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_70 0x190F5244u //! Register Reset Value #define DESC1_4_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_70 Register DESC2_4_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_70 0x35248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_70 0x190F5248u //! Register Reset Value #define DESC2_4_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_70 Register DESC3_4_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_70 0x3524C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_70 0x190F524Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_70 Register DESC0_5_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_70 0x35250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_70 0x190F5250u //! Register Reset Value #define DESC0_5_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_70 Register DESC1_5_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_70 0x35254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_70 0x190F5254u //! Register Reset Value #define DESC1_5_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_70 Register DESC2_5_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_70 0x35258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_70 0x190F5258u //! Register Reset Value #define DESC2_5_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_70 Register DESC3_5_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_70 0x3525C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_70 0x190F525Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_70 Register DESC0_6_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_70 0x35260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_70 0x190F5260u //! Register Reset Value #define DESC0_6_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_70 Register DESC1_6_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_70 0x35264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_70 0x190F5264u //! Register Reset Value #define DESC1_6_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_70 Register DESC2_6_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_70 0x35268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_70 0x190F5268u //! Register Reset Value #define DESC2_6_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_70 Register DESC3_6_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_70 0x3526C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_70 0x190F526Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_70 Register DESC0_7_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_70 0x35270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_70 0x190F5270u //! Register Reset Value #define DESC0_7_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_70 Register DESC1_7_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_70 0x35274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_70 0x190F5274u //! Register Reset Value #define DESC1_7_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_70 Register DESC2_7_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_70 0x35278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_70 0x190F5278u //! Register Reset Value #define DESC2_7_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_70_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_70 Register DESC3_7_PON_EGP_S_70 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_70 0x3527C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_70 0x190F527Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_70_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_70_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_70_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_70_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_70_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_71 Register CFG_PON_EGP_71 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_71 0x35400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_71 0x190F5400u //! Register Reset Value #define CFG_PON_EGP_71_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_71_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_71_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_71_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_71_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_71_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_71_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_71_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_71_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_71_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_71_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_71 Register IRNCR_PON_EGP_71 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_71 0x35420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_71 0x190F5420u //! Register Reset Value #define IRNCR_PON_EGP_71_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_71_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_71_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_71_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_71_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_71 Register IRNICR_PON_EGP_71 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_71 0x35424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_71 0x190F5424u //! Register Reset Value #define IRNICR_PON_EGP_71_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_71_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_71_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_71 Register IRNEN_PON_EGP_71 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_71 0x35428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_71 0x190F5428u //! Register Reset Value #define IRNEN_PON_EGP_71_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_71_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_71_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_71_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_71_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_71 Register DPTR_PON_EGP_71 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_71 0x35430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_71 0x190F5430u //! Register Reset Value #define DPTR_PON_EGP_71_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_71_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_71_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_71_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_71_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_71_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_71_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_71_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_71_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_71 Register DESC0_0_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_71 0x35500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_71 0x190F5500u //! Register Reset Value #define DESC0_0_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_71 Register DESC1_0_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_71 0x35504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_71 0x190F5504u //! Register Reset Value #define DESC1_0_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_71 Register DESC2_0_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_71 0x35508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_71 0x190F5508u //! Register Reset Value #define DESC2_0_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_71 Register DESC3_0_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_71 0x3550C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_71 0x190F550Cu //! Register Reset Value #define DESC3_0_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_71 Register DESC0_1_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_71 0x35510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_71 0x190F5510u //! Register Reset Value #define DESC0_1_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_71 Register DESC1_1_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_71 0x35514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_71 0x190F5514u //! Register Reset Value #define DESC1_1_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_71 Register DESC2_1_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_71 0x35518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_71 0x190F5518u //! Register Reset Value #define DESC2_1_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_71 Register DESC3_1_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_71 0x3551C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_71 0x190F551Cu //! Register Reset Value #define DESC3_1_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_71 Register DESC0_2_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_71 0x35520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_71 0x190F5520u //! Register Reset Value #define DESC0_2_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_71 Register DESC1_2_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_71 0x35524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_71 0x190F5524u //! Register Reset Value #define DESC1_2_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_71 Register DESC2_2_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_71 0x35528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_71 0x190F5528u //! Register Reset Value #define DESC2_2_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_71 Register DESC3_2_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_71 0x3552C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_71 0x190F552Cu //! Register Reset Value #define DESC3_2_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_71 Register DESC0_3_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_71 0x35530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_71 0x190F5530u //! Register Reset Value #define DESC0_3_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_71 Register DESC1_3_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_71 0x35534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_71 0x190F5534u //! Register Reset Value #define DESC1_3_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_71 Register DESC2_3_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_71 0x35538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_71 0x190F5538u //! Register Reset Value #define DESC2_3_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_71 Register DESC3_3_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_71 0x3553C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_71 0x190F553Cu //! Register Reset Value #define DESC3_3_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_71 Register DESC0_4_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_71 0x35540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_71 0x190F5540u //! Register Reset Value #define DESC0_4_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_71 Register DESC1_4_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_71 0x35544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_71 0x190F5544u //! Register Reset Value #define DESC1_4_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_71 Register DESC2_4_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_71 0x35548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_71 0x190F5548u //! Register Reset Value #define DESC2_4_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_71 Register DESC3_4_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_71 0x3554C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_71 0x190F554Cu //! Register Reset Value #define DESC3_4_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_71 Register DESC0_5_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_71 0x35550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_71 0x190F5550u //! Register Reset Value #define DESC0_5_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_71 Register DESC1_5_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_71 0x35554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_71 0x190F5554u //! Register Reset Value #define DESC1_5_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_71 Register DESC2_5_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_71 0x35558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_71 0x190F5558u //! Register Reset Value #define DESC2_5_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_71 Register DESC3_5_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_71 0x3555C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_71 0x190F555Cu //! Register Reset Value #define DESC3_5_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_71 Register DESC0_6_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_71 0x35560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_71 0x190F5560u //! Register Reset Value #define DESC0_6_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_71 Register DESC1_6_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_71 0x35564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_71 0x190F5564u //! Register Reset Value #define DESC1_6_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_71 Register DESC2_6_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_71 0x35568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_71 0x190F5568u //! Register Reset Value #define DESC2_6_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_71 Register DESC3_6_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_71 0x3556C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_71 0x190F556Cu //! Register Reset Value #define DESC3_6_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_71 Register DESC0_7_PON_EGP_71 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_71 0x35570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_71 0x190F5570u //! Register Reset Value #define DESC0_7_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_71 Register DESC1_7_PON_EGP_71 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_71 0x35574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_71 0x190F5574u //! Register Reset Value #define DESC1_7_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_71 Register DESC2_7_PON_EGP_71 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_71 0x35578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_71 0x190F5578u //! Register Reset Value #define DESC2_7_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_71 Register DESC3_7_PON_EGP_71 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_71 0x3557C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_71 0x190F557Cu //! Register Reset Value #define DESC3_7_PON_EGP_71_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_71_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_71_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_71 Register DESC0_0_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_71 0x35600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_71 0x190F5600u //! Register Reset Value #define DESC0_0_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_71 Register DESC1_0_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_71 0x35604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_71 0x190F5604u //! Register Reset Value #define DESC1_0_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_71 Register DESC2_0_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_71 0x35608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_71 0x190F5608u //! Register Reset Value #define DESC2_0_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_71 Register DESC3_0_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_71 0x3560C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_71 0x190F560Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_71 Register DESC0_1_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_71 0x35610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_71 0x190F5610u //! Register Reset Value #define DESC0_1_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_71 Register DESC1_1_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_71 0x35614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_71 0x190F5614u //! Register Reset Value #define DESC1_1_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_71 Register DESC2_1_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_71 0x35618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_71 0x190F5618u //! Register Reset Value #define DESC2_1_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_71 Register DESC3_1_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_71 0x3561C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_71 0x190F561Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_71 Register DESC0_2_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_71 0x35620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_71 0x190F5620u //! Register Reset Value #define DESC0_2_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_71 Register DESC1_2_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_71 0x35624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_71 0x190F5624u //! Register Reset Value #define DESC1_2_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_71 Register DESC2_2_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_71 0x35628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_71 0x190F5628u //! Register Reset Value #define DESC2_2_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_71 Register DESC3_2_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_71 0x3562C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_71 0x190F562Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_71 Register DESC0_3_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_71 0x35630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_71 0x190F5630u //! Register Reset Value #define DESC0_3_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_71 Register DESC1_3_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_71 0x35634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_71 0x190F5634u //! Register Reset Value #define DESC1_3_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_71 Register DESC2_3_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_71 0x35638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_71 0x190F5638u //! Register Reset Value #define DESC2_3_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_71 Register DESC3_3_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_71 0x3563C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_71 0x190F563Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_71 Register DESC0_4_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_71 0x35640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_71 0x190F5640u //! Register Reset Value #define DESC0_4_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_71 Register DESC1_4_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_71 0x35644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_71 0x190F5644u //! Register Reset Value #define DESC1_4_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_71 Register DESC2_4_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_71 0x35648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_71 0x190F5648u //! Register Reset Value #define DESC2_4_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_71 Register DESC3_4_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_71 0x3564C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_71 0x190F564Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_71 Register DESC0_5_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_71 0x35650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_71 0x190F5650u //! Register Reset Value #define DESC0_5_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_71 Register DESC1_5_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_71 0x35654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_71 0x190F5654u //! Register Reset Value #define DESC1_5_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_71 Register DESC2_5_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_71 0x35658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_71 0x190F5658u //! Register Reset Value #define DESC2_5_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_71 Register DESC3_5_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_71 0x3565C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_71 0x190F565Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_71 Register DESC0_6_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_71 0x35660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_71 0x190F5660u //! Register Reset Value #define DESC0_6_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_71 Register DESC1_6_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_71 0x35664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_71 0x190F5664u //! Register Reset Value #define DESC1_6_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_71 Register DESC2_6_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_71 0x35668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_71 0x190F5668u //! Register Reset Value #define DESC2_6_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_71 Register DESC3_6_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_71 0x3566C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_71 0x190F566Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_71 Register DESC0_7_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_71 0x35670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_71 0x190F5670u //! Register Reset Value #define DESC0_7_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_71 Register DESC1_7_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_71 0x35674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_71 0x190F5674u //! Register Reset Value #define DESC1_7_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_71 Register DESC2_7_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_71 0x35678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_71 0x190F5678u //! Register Reset Value #define DESC2_7_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_71_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_71 Register DESC3_7_PON_EGP_S_71 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_71 0x3567C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_71 0x190F567Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_71_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_71_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_71_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_71_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_71_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_72 Register CFG_PON_EGP_72 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_72 0x35800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_72 0x190F5800u //! Register Reset Value #define CFG_PON_EGP_72_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_72_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_72_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_72_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_72_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_72_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_72_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_72_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_72_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_72_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_72_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_72 Register IRNCR_PON_EGP_72 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_72 0x35820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_72 0x190F5820u //! Register Reset Value #define IRNCR_PON_EGP_72_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_72_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_72_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_72_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_72_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_72 Register IRNICR_PON_EGP_72 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_72 0x35824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_72 0x190F5824u //! Register Reset Value #define IRNICR_PON_EGP_72_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_72_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_72_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_72 Register IRNEN_PON_EGP_72 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_72 0x35828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_72 0x190F5828u //! Register Reset Value #define IRNEN_PON_EGP_72_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_72_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_72_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_72_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_72_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_72 Register DPTR_PON_EGP_72 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_72 0x35830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_72 0x190F5830u //! Register Reset Value #define DPTR_PON_EGP_72_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_72_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_72_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_72_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_72_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_72_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_72_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_72_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_72_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_72 Register DESC0_0_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_72 0x35900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_72 0x190F5900u //! Register Reset Value #define DESC0_0_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_72 Register DESC1_0_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_72 0x35904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_72 0x190F5904u //! Register Reset Value #define DESC1_0_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_72 Register DESC2_0_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_72 0x35908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_72 0x190F5908u //! Register Reset Value #define DESC2_0_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_72 Register DESC3_0_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_72 0x3590C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_72 0x190F590Cu //! Register Reset Value #define DESC3_0_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_72 Register DESC0_1_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_72 0x35910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_72 0x190F5910u //! Register Reset Value #define DESC0_1_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_72 Register DESC1_1_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_72 0x35914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_72 0x190F5914u //! Register Reset Value #define DESC1_1_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_72 Register DESC2_1_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_72 0x35918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_72 0x190F5918u //! Register Reset Value #define DESC2_1_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_72 Register DESC3_1_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_72 0x3591C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_72 0x190F591Cu //! Register Reset Value #define DESC3_1_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_72 Register DESC0_2_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_72 0x35920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_72 0x190F5920u //! Register Reset Value #define DESC0_2_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_72 Register DESC1_2_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_72 0x35924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_72 0x190F5924u //! Register Reset Value #define DESC1_2_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_72 Register DESC2_2_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_72 0x35928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_72 0x190F5928u //! Register Reset Value #define DESC2_2_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_72 Register DESC3_2_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_72 0x3592C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_72 0x190F592Cu //! Register Reset Value #define DESC3_2_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_72 Register DESC0_3_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_72 0x35930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_72 0x190F5930u //! Register Reset Value #define DESC0_3_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_72 Register DESC1_3_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_72 0x35934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_72 0x190F5934u //! Register Reset Value #define DESC1_3_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_72 Register DESC2_3_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_72 0x35938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_72 0x190F5938u //! Register Reset Value #define DESC2_3_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_72 Register DESC3_3_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_72 0x3593C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_72 0x190F593Cu //! Register Reset Value #define DESC3_3_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_72 Register DESC0_4_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_72 0x35940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_72 0x190F5940u //! Register Reset Value #define DESC0_4_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_72 Register DESC1_4_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_72 0x35944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_72 0x190F5944u //! Register Reset Value #define DESC1_4_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_72 Register DESC2_4_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_72 0x35948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_72 0x190F5948u //! Register Reset Value #define DESC2_4_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_72 Register DESC3_4_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_72 0x3594C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_72 0x190F594Cu //! Register Reset Value #define DESC3_4_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_72 Register DESC0_5_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_72 0x35950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_72 0x190F5950u //! Register Reset Value #define DESC0_5_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_72 Register DESC1_5_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_72 0x35954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_72 0x190F5954u //! Register Reset Value #define DESC1_5_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_72 Register DESC2_5_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_72 0x35958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_72 0x190F5958u //! Register Reset Value #define DESC2_5_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_72 Register DESC3_5_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_72 0x3595C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_72 0x190F595Cu //! Register Reset Value #define DESC3_5_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_72 Register DESC0_6_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_72 0x35960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_72 0x190F5960u //! Register Reset Value #define DESC0_6_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_72 Register DESC1_6_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_72 0x35964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_72 0x190F5964u //! Register Reset Value #define DESC1_6_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_72 Register DESC2_6_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_72 0x35968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_72 0x190F5968u //! Register Reset Value #define DESC2_6_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_72 Register DESC3_6_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_72 0x3596C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_72 0x190F596Cu //! Register Reset Value #define DESC3_6_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_72 Register DESC0_7_PON_EGP_72 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_72 0x35970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_72 0x190F5970u //! Register Reset Value #define DESC0_7_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_72 Register DESC1_7_PON_EGP_72 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_72 0x35974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_72 0x190F5974u //! Register Reset Value #define DESC1_7_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_72 Register DESC2_7_PON_EGP_72 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_72 0x35978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_72 0x190F5978u //! Register Reset Value #define DESC2_7_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_72 Register DESC3_7_PON_EGP_72 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_72 0x3597C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_72 0x190F597Cu //! Register Reset Value #define DESC3_7_PON_EGP_72_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_72_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_72_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_72 Register DESC0_0_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_72 0x35A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_72 0x190F5A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_72 Register DESC1_0_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_72 0x35A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_72 0x190F5A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_72 Register DESC2_0_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_72 0x35A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_72 0x190F5A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_72 Register DESC3_0_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_72 0x35A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_72 0x190F5A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_72 Register DESC0_1_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_72 0x35A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_72 0x190F5A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_72 Register DESC1_1_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_72 0x35A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_72 0x190F5A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_72 Register DESC2_1_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_72 0x35A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_72 0x190F5A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_72 Register DESC3_1_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_72 0x35A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_72 0x190F5A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_72 Register DESC0_2_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_72 0x35A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_72 0x190F5A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_72 Register DESC1_2_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_72 0x35A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_72 0x190F5A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_72 Register DESC2_2_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_72 0x35A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_72 0x190F5A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_72 Register DESC3_2_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_72 0x35A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_72 0x190F5A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_72 Register DESC0_3_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_72 0x35A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_72 0x190F5A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_72 Register DESC1_3_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_72 0x35A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_72 0x190F5A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_72 Register DESC2_3_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_72 0x35A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_72 0x190F5A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_72 Register DESC3_3_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_72 0x35A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_72 0x190F5A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_72 Register DESC0_4_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_72 0x35A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_72 0x190F5A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_72 Register DESC1_4_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_72 0x35A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_72 0x190F5A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_72 Register DESC2_4_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_72 0x35A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_72 0x190F5A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_72 Register DESC3_4_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_72 0x35A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_72 0x190F5A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_72 Register DESC0_5_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_72 0x35A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_72 0x190F5A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_72 Register DESC1_5_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_72 0x35A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_72 0x190F5A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_72 Register DESC2_5_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_72 0x35A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_72 0x190F5A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_72 Register DESC3_5_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_72 0x35A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_72 0x190F5A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_72 Register DESC0_6_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_72 0x35A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_72 0x190F5A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_72 Register DESC1_6_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_72 0x35A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_72 0x190F5A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_72 Register DESC2_6_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_72 0x35A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_72 0x190F5A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_72 Register DESC3_6_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_72 0x35A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_72 0x190F5A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_72 Register DESC0_7_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_72 0x35A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_72 0x190F5A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_72 Register DESC1_7_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_72 0x35A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_72 0x190F5A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_72 Register DESC2_7_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_72 0x35A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_72 0x190F5A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_72_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_72 Register DESC3_7_PON_EGP_S_72 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_72 0x35A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_72 0x190F5A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_72_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_72_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_72_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_72_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_72_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_73 Register CFG_PON_EGP_73 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_73 0x35C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_73 0x190F5C00u //! Register Reset Value #define CFG_PON_EGP_73_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_73_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_73_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_73_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_73_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_73_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_73_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_73_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_73_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_73_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_73_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_73 Register IRNCR_PON_EGP_73 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_73 0x35C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_73 0x190F5C20u //! Register Reset Value #define IRNCR_PON_EGP_73_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_73_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_73_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_73_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_73_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_73 Register IRNICR_PON_EGP_73 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_73 0x35C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_73 0x190F5C24u //! Register Reset Value #define IRNICR_PON_EGP_73_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_73_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_73_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_73 Register IRNEN_PON_EGP_73 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_73 0x35C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_73 0x190F5C28u //! Register Reset Value #define IRNEN_PON_EGP_73_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_73_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_73_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_73_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_73_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_73 Register DPTR_PON_EGP_73 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_73 0x35C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_73 0x190F5C30u //! Register Reset Value #define DPTR_PON_EGP_73_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_73_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_73_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_73_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_73_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_73_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_73_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_73_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_73_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_73 Register DESC0_0_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_73 0x35D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_73 0x190F5D00u //! Register Reset Value #define DESC0_0_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_73 Register DESC1_0_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_73 0x35D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_73 0x190F5D04u //! Register Reset Value #define DESC1_0_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_73 Register DESC2_0_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_73 0x35D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_73 0x190F5D08u //! Register Reset Value #define DESC2_0_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_73 Register DESC3_0_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_73 0x35D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_73 0x190F5D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_73 Register DESC0_1_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_73 0x35D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_73 0x190F5D10u //! Register Reset Value #define DESC0_1_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_73 Register DESC1_1_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_73 0x35D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_73 0x190F5D14u //! Register Reset Value #define DESC1_1_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_73 Register DESC2_1_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_73 0x35D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_73 0x190F5D18u //! Register Reset Value #define DESC2_1_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_73 Register DESC3_1_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_73 0x35D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_73 0x190F5D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_73 Register DESC0_2_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_73 0x35D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_73 0x190F5D20u //! Register Reset Value #define DESC0_2_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_73 Register DESC1_2_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_73 0x35D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_73 0x190F5D24u //! Register Reset Value #define DESC1_2_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_73 Register DESC2_2_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_73 0x35D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_73 0x190F5D28u //! Register Reset Value #define DESC2_2_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_73 Register DESC3_2_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_73 0x35D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_73 0x190F5D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_73 Register DESC0_3_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_73 0x35D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_73 0x190F5D30u //! Register Reset Value #define DESC0_3_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_73 Register DESC1_3_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_73 0x35D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_73 0x190F5D34u //! Register Reset Value #define DESC1_3_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_73 Register DESC2_3_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_73 0x35D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_73 0x190F5D38u //! Register Reset Value #define DESC2_3_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_73 Register DESC3_3_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_73 0x35D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_73 0x190F5D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_73 Register DESC0_4_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_73 0x35D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_73 0x190F5D40u //! Register Reset Value #define DESC0_4_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_73 Register DESC1_4_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_73 0x35D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_73 0x190F5D44u //! Register Reset Value #define DESC1_4_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_73 Register DESC2_4_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_73 0x35D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_73 0x190F5D48u //! Register Reset Value #define DESC2_4_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_73 Register DESC3_4_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_73 0x35D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_73 0x190F5D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_73 Register DESC0_5_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_73 0x35D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_73 0x190F5D50u //! Register Reset Value #define DESC0_5_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_73 Register DESC1_5_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_73 0x35D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_73 0x190F5D54u //! Register Reset Value #define DESC1_5_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_73 Register DESC2_5_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_73 0x35D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_73 0x190F5D58u //! Register Reset Value #define DESC2_5_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_73 Register DESC3_5_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_73 0x35D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_73 0x190F5D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_73 Register DESC0_6_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_73 0x35D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_73 0x190F5D60u //! Register Reset Value #define DESC0_6_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_73 Register DESC1_6_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_73 0x35D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_73 0x190F5D64u //! Register Reset Value #define DESC1_6_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_73 Register DESC2_6_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_73 0x35D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_73 0x190F5D68u //! Register Reset Value #define DESC2_6_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_73 Register DESC3_6_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_73 0x35D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_73 0x190F5D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_73 Register DESC0_7_PON_EGP_73 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_73 0x35D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_73 0x190F5D70u //! Register Reset Value #define DESC0_7_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_73 Register DESC1_7_PON_EGP_73 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_73 0x35D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_73 0x190F5D74u //! Register Reset Value #define DESC1_7_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_73 Register DESC2_7_PON_EGP_73 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_73 0x35D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_73 0x190F5D78u //! Register Reset Value #define DESC2_7_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_73 Register DESC3_7_PON_EGP_73 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_73 0x35D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_73 0x190F5D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_73_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_73_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_73_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_73 Register DESC0_0_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_73 0x35E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_73 0x190F5E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_73 Register DESC1_0_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_73 0x35E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_73 0x190F5E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_73 Register DESC2_0_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_73 0x35E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_73 0x190F5E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_73 Register DESC3_0_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_73 0x35E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_73 0x190F5E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_73 Register DESC0_1_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_73 0x35E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_73 0x190F5E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_73 Register DESC1_1_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_73 0x35E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_73 0x190F5E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_73 Register DESC2_1_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_73 0x35E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_73 0x190F5E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_73 Register DESC3_1_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_73 0x35E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_73 0x190F5E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_73 Register DESC0_2_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_73 0x35E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_73 0x190F5E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_73 Register DESC1_2_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_73 0x35E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_73 0x190F5E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_73 Register DESC2_2_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_73 0x35E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_73 0x190F5E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_73 Register DESC3_2_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_73 0x35E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_73 0x190F5E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_73 Register DESC0_3_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_73 0x35E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_73 0x190F5E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_73 Register DESC1_3_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_73 0x35E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_73 0x190F5E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_73 Register DESC2_3_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_73 0x35E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_73 0x190F5E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_73 Register DESC3_3_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_73 0x35E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_73 0x190F5E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_73 Register DESC0_4_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_73 0x35E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_73 0x190F5E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_73 Register DESC1_4_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_73 0x35E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_73 0x190F5E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_73 Register DESC2_4_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_73 0x35E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_73 0x190F5E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_73 Register DESC3_4_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_73 0x35E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_73 0x190F5E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_73 Register DESC0_5_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_73 0x35E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_73 0x190F5E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_73 Register DESC1_5_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_73 0x35E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_73 0x190F5E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_73 Register DESC2_5_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_73 0x35E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_73 0x190F5E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_73 Register DESC3_5_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_73 0x35E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_73 0x190F5E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_73 Register DESC0_6_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_73 0x35E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_73 0x190F5E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_73 Register DESC1_6_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_73 0x35E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_73 0x190F5E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_73 Register DESC2_6_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_73 0x35E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_73 0x190F5E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_73 Register DESC3_6_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_73 0x35E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_73 0x190F5E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_73 Register DESC0_7_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_73 0x35E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_73 0x190F5E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_73 Register DESC1_7_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_73 0x35E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_73 0x190F5E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_73 Register DESC2_7_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_73 0x35E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_73 0x190F5E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_73_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_73 Register DESC3_7_PON_EGP_S_73 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_73 0x35E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_73 0x190F5E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_73_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_73_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_73_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_73_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_73_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_74 Register CFG_PON_EGP_74 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_74 0x36000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_74 0x190F6000u //! Register Reset Value #define CFG_PON_EGP_74_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_74_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_74_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_74_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_74_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_74_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_74_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_74_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_74_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_74_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_74_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_74 Register IRNCR_PON_EGP_74 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_74 0x36020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_74 0x190F6020u //! Register Reset Value #define IRNCR_PON_EGP_74_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_74_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_74_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_74_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_74_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_74 Register IRNICR_PON_EGP_74 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_74 0x36024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_74 0x190F6024u //! Register Reset Value #define IRNICR_PON_EGP_74_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_74_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_74_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_74 Register IRNEN_PON_EGP_74 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_74 0x36028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_74 0x190F6028u //! Register Reset Value #define IRNEN_PON_EGP_74_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_74_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_74_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_74_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_74_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_74 Register DPTR_PON_EGP_74 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_74 0x36030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_74 0x190F6030u //! Register Reset Value #define DPTR_PON_EGP_74_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_74_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_74_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_74_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_74_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_74_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_74_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_74_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_74_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_74 Register DESC0_0_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_74 0x36100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_74 0x190F6100u //! Register Reset Value #define DESC0_0_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_74 Register DESC1_0_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_74 0x36104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_74 0x190F6104u //! Register Reset Value #define DESC1_0_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_74 Register DESC2_0_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_74 0x36108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_74 0x190F6108u //! Register Reset Value #define DESC2_0_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_74 Register DESC3_0_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_74 0x3610C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_74 0x190F610Cu //! Register Reset Value #define DESC3_0_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_74 Register DESC0_1_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_74 0x36110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_74 0x190F6110u //! Register Reset Value #define DESC0_1_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_74 Register DESC1_1_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_74 0x36114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_74 0x190F6114u //! Register Reset Value #define DESC1_1_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_74 Register DESC2_1_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_74 0x36118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_74 0x190F6118u //! Register Reset Value #define DESC2_1_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_74 Register DESC3_1_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_74 0x3611C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_74 0x190F611Cu //! Register Reset Value #define DESC3_1_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_74 Register DESC0_2_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_74 0x36120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_74 0x190F6120u //! Register Reset Value #define DESC0_2_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_74 Register DESC1_2_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_74 0x36124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_74 0x190F6124u //! Register Reset Value #define DESC1_2_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_74 Register DESC2_2_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_74 0x36128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_74 0x190F6128u //! Register Reset Value #define DESC2_2_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_74 Register DESC3_2_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_74 0x3612C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_74 0x190F612Cu //! Register Reset Value #define DESC3_2_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_74 Register DESC0_3_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_74 0x36130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_74 0x190F6130u //! Register Reset Value #define DESC0_3_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_74 Register DESC1_3_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_74 0x36134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_74 0x190F6134u //! Register Reset Value #define DESC1_3_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_74 Register DESC2_3_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_74 0x36138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_74 0x190F6138u //! Register Reset Value #define DESC2_3_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_74 Register DESC3_3_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_74 0x3613C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_74 0x190F613Cu //! Register Reset Value #define DESC3_3_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_74 Register DESC0_4_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_74 0x36140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_74 0x190F6140u //! Register Reset Value #define DESC0_4_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_74 Register DESC1_4_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_74 0x36144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_74 0x190F6144u //! Register Reset Value #define DESC1_4_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_74 Register DESC2_4_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_74 0x36148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_74 0x190F6148u //! Register Reset Value #define DESC2_4_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_74 Register DESC3_4_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_74 0x3614C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_74 0x190F614Cu //! Register Reset Value #define DESC3_4_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_74 Register DESC0_5_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_74 0x36150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_74 0x190F6150u //! Register Reset Value #define DESC0_5_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_74 Register DESC1_5_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_74 0x36154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_74 0x190F6154u //! Register Reset Value #define DESC1_5_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_74 Register DESC2_5_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_74 0x36158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_74 0x190F6158u //! Register Reset Value #define DESC2_5_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_74 Register DESC3_5_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_74 0x3615C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_74 0x190F615Cu //! Register Reset Value #define DESC3_5_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_74 Register DESC0_6_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_74 0x36160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_74 0x190F6160u //! Register Reset Value #define DESC0_6_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_74 Register DESC1_6_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_74 0x36164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_74 0x190F6164u //! Register Reset Value #define DESC1_6_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_74 Register DESC2_6_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_74 0x36168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_74 0x190F6168u //! Register Reset Value #define DESC2_6_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_74 Register DESC3_6_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_74 0x3616C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_74 0x190F616Cu //! Register Reset Value #define DESC3_6_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_74 Register DESC0_7_PON_EGP_74 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_74 0x36170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_74 0x190F6170u //! Register Reset Value #define DESC0_7_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_74 Register DESC1_7_PON_EGP_74 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_74 0x36174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_74 0x190F6174u //! Register Reset Value #define DESC1_7_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_74 Register DESC2_7_PON_EGP_74 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_74 0x36178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_74 0x190F6178u //! Register Reset Value #define DESC2_7_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_74 Register DESC3_7_PON_EGP_74 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_74 0x3617C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_74 0x190F617Cu //! Register Reset Value #define DESC3_7_PON_EGP_74_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_74_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_74_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_74 Register DESC0_0_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_74 0x36200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_74 0x190F6200u //! Register Reset Value #define DESC0_0_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_74 Register DESC1_0_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_74 0x36204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_74 0x190F6204u //! Register Reset Value #define DESC1_0_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_74 Register DESC2_0_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_74 0x36208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_74 0x190F6208u //! Register Reset Value #define DESC2_0_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_74 Register DESC3_0_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_74 0x3620C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_74 0x190F620Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_74 Register DESC0_1_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_74 0x36210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_74 0x190F6210u //! Register Reset Value #define DESC0_1_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_74 Register DESC1_1_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_74 0x36214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_74 0x190F6214u //! Register Reset Value #define DESC1_1_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_74 Register DESC2_1_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_74 0x36218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_74 0x190F6218u //! Register Reset Value #define DESC2_1_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_74 Register DESC3_1_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_74 0x3621C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_74 0x190F621Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_74 Register DESC0_2_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_74 0x36220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_74 0x190F6220u //! Register Reset Value #define DESC0_2_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_74 Register DESC1_2_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_74 0x36224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_74 0x190F6224u //! Register Reset Value #define DESC1_2_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_74 Register DESC2_2_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_74 0x36228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_74 0x190F6228u //! Register Reset Value #define DESC2_2_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_74 Register DESC3_2_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_74 0x3622C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_74 0x190F622Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_74 Register DESC0_3_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_74 0x36230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_74 0x190F6230u //! Register Reset Value #define DESC0_3_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_74 Register DESC1_3_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_74 0x36234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_74 0x190F6234u //! Register Reset Value #define DESC1_3_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_74 Register DESC2_3_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_74 0x36238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_74 0x190F6238u //! Register Reset Value #define DESC2_3_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_74 Register DESC3_3_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_74 0x3623C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_74 0x190F623Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_74 Register DESC0_4_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_74 0x36240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_74 0x190F6240u //! Register Reset Value #define DESC0_4_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_74 Register DESC1_4_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_74 0x36244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_74 0x190F6244u //! Register Reset Value #define DESC1_4_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_74 Register DESC2_4_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_74 0x36248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_74 0x190F6248u //! Register Reset Value #define DESC2_4_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_74 Register DESC3_4_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_74 0x3624C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_74 0x190F624Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_74 Register DESC0_5_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_74 0x36250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_74 0x190F6250u //! Register Reset Value #define DESC0_5_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_74 Register DESC1_5_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_74 0x36254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_74 0x190F6254u //! Register Reset Value #define DESC1_5_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_74 Register DESC2_5_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_74 0x36258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_74 0x190F6258u //! Register Reset Value #define DESC2_5_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_74 Register DESC3_5_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_74 0x3625C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_74 0x190F625Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_74 Register DESC0_6_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_74 0x36260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_74 0x190F6260u //! Register Reset Value #define DESC0_6_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_74 Register DESC1_6_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_74 0x36264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_74 0x190F6264u //! Register Reset Value #define DESC1_6_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_74 Register DESC2_6_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_74 0x36268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_74 0x190F6268u //! Register Reset Value #define DESC2_6_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_74 Register DESC3_6_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_74 0x3626C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_74 0x190F626Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_74 Register DESC0_7_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_74 0x36270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_74 0x190F6270u //! Register Reset Value #define DESC0_7_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_74 Register DESC1_7_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_74 0x36274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_74 0x190F6274u //! Register Reset Value #define DESC1_7_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_74 Register DESC2_7_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_74 0x36278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_74 0x190F6278u //! Register Reset Value #define DESC2_7_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_74_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_74 Register DESC3_7_PON_EGP_S_74 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_74 0x3627C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_74 0x190F627Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_74_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_74_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_74_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_74_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_74_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_75 Register CFG_PON_EGP_75 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_75 0x36400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_75 0x190F6400u //! Register Reset Value #define CFG_PON_EGP_75_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_75_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_75_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_75_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_75_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_75_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_75_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_75_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_75_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_75_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_75_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_75 Register IRNCR_PON_EGP_75 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_75 0x36420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_75 0x190F6420u //! Register Reset Value #define IRNCR_PON_EGP_75_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_75_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_75_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_75_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_75_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_75 Register IRNICR_PON_EGP_75 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_75 0x36424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_75 0x190F6424u //! Register Reset Value #define IRNICR_PON_EGP_75_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_75_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_75_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_75 Register IRNEN_PON_EGP_75 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_75 0x36428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_75 0x190F6428u //! Register Reset Value #define IRNEN_PON_EGP_75_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_75_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_75_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_75_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_75_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_75 Register DPTR_PON_EGP_75 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_75 0x36430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_75 0x190F6430u //! Register Reset Value #define DPTR_PON_EGP_75_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_75_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_75_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_75_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_75_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_75_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_75_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_75_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_75_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_75 Register DESC0_0_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_75 0x36500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_75 0x190F6500u //! Register Reset Value #define DESC0_0_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_75 Register DESC1_0_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_75 0x36504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_75 0x190F6504u //! Register Reset Value #define DESC1_0_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_75 Register DESC2_0_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_75 0x36508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_75 0x190F6508u //! Register Reset Value #define DESC2_0_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_75 Register DESC3_0_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_75 0x3650C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_75 0x190F650Cu //! Register Reset Value #define DESC3_0_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_75 Register DESC0_1_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_75 0x36510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_75 0x190F6510u //! Register Reset Value #define DESC0_1_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_75 Register DESC1_1_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_75 0x36514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_75 0x190F6514u //! Register Reset Value #define DESC1_1_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_75 Register DESC2_1_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_75 0x36518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_75 0x190F6518u //! Register Reset Value #define DESC2_1_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_75 Register DESC3_1_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_75 0x3651C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_75 0x190F651Cu //! Register Reset Value #define DESC3_1_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_75 Register DESC0_2_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_75 0x36520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_75 0x190F6520u //! Register Reset Value #define DESC0_2_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_75 Register DESC1_2_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_75 0x36524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_75 0x190F6524u //! Register Reset Value #define DESC1_2_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_75 Register DESC2_2_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_75 0x36528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_75 0x190F6528u //! Register Reset Value #define DESC2_2_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_75 Register DESC3_2_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_75 0x3652C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_75 0x190F652Cu //! Register Reset Value #define DESC3_2_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_75 Register DESC0_3_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_75 0x36530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_75 0x190F6530u //! Register Reset Value #define DESC0_3_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_75 Register DESC1_3_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_75 0x36534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_75 0x190F6534u //! Register Reset Value #define DESC1_3_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_75 Register DESC2_3_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_75 0x36538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_75 0x190F6538u //! Register Reset Value #define DESC2_3_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_75 Register DESC3_3_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_75 0x3653C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_75 0x190F653Cu //! Register Reset Value #define DESC3_3_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_75 Register DESC0_4_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_75 0x36540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_75 0x190F6540u //! Register Reset Value #define DESC0_4_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_75 Register DESC1_4_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_75 0x36544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_75 0x190F6544u //! Register Reset Value #define DESC1_4_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_75 Register DESC2_4_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_75 0x36548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_75 0x190F6548u //! Register Reset Value #define DESC2_4_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_75 Register DESC3_4_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_75 0x3654C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_75 0x190F654Cu //! Register Reset Value #define DESC3_4_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_75 Register DESC0_5_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_75 0x36550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_75 0x190F6550u //! Register Reset Value #define DESC0_5_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_75 Register DESC1_5_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_75 0x36554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_75 0x190F6554u //! Register Reset Value #define DESC1_5_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_75 Register DESC2_5_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_75 0x36558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_75 0x190F6558u //! Register Reset Value #define DESC2_5_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_75 Register DESC3_5_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_75 0x3655C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_75 0x190F655Cu //! Register Reset Value #define DESC3_5_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_75 Register DESC0_6_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_75 0x36560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_75 0x190F6560u //! Register Reset Value #define DESC0_6_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_75 Register DESC1_6_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_75 0x36564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_75 0x190F6564u //! Register Reset Value #define DESC1_6_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_75 Register DESC2_6_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_75 0x36568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_75 0x190F6568u //! Register Reset Value #define DESC2_6_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_75 Register DESC3_6_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_75 0x3656C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_75 0x190F656Cu //! Register Reset Value #define DESC3_6_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_75 Register DESC0_7_PON_EGP_75 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_75 0x36570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_75 0x190F6570u //! Register Reset Value #define DESC0_7_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_75 Register DESC1_7_PON_EGP_75 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_75 0x36574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_75 0x190F6574u //! Register Reset Value #define DESC1_7_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_75 Register DESC2_7_PON_EGP_75 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_75 0x36578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_75 0x190F6578u //! Register Reset Value #define DESC2_7_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_75 Register DESC3_7_PON_EGP_75 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_75 0x3657C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_75 0x190F657Cu //! Register Reset Value #define DESC3_7_PON_EGP_75_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_75_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_75_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_75 Register DESC0_0_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_75 0x36600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_75 0x190F6600u //! Register Reset Value #define DESC0_0_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_75 Register DESC1_0_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_75 0x36604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_75 0x190F6604u //! Register Reset Value #define DESC1_0_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_75 Register DESC2_0_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_75 0x36608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_75 0x190F6608u //! Register Reset Value #define DESC2_0_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_75 Register DESC3_0_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_75 0x3660C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_75 0x190F660Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_75 Register DESC0_1_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_75 0x36610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_75 0x190F6610u //! Register Reset Value #define DESC0_1_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_75 Register DESC1_1_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_75 0x36614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_75 0x190F6614u //! Register Reset Value #define DESC1_1_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_75 Register DESC2_1_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_75 0x36618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_75 0x190F6618u //! Register Reset Value #define DESC2_1_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_75 Register DESC3_1_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_75 0x3661C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_75 0x190F661Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_75 Register DESC0_2_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_75 0x36620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_75 0x190F6620u //! Register Reset Value #define DESC0_2_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_75 Register DESC1_2_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_75 0x36624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_75 0x190F6624u //! Register Reset Value #define DESC1_2_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_75 Register DESC2_2_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_75 0x36628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_75 0x190F6628u //! Register Reset Value #define DESC2_2_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_75 Register DESC3_2_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_75 0x3662C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_75 0x190F662Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_75 Register DESC0_3_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_75 0x36630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_75 0x190F6630u //! Register Reset Value #define DESC0_3_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_75 Register DESC1_3_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_75 0x36634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_75 0x190F6634u //! Register Reset Value #define DESC1_3_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_75 Register DESC2_3_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_75 0x36638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_75 0x190F6638u //! Register Reset Value #define DESC2_3_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_75 Register DESC3_3_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_75 0x3663C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_75 0x190F663Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_75 Register DESC0_4_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_75 0x36640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_75 0x190F6640u //! Register Reset Value #define DESC0_4_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_75 Register DESC1_4_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_75 0x36644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_75 0x190F6644u //! Register Reset Value #define DESC1_4_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_75 Register DESC2_4_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_75 0x36648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_75 0x190F6648u //! Register Reset Value #define DESC2_4_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_75 Register DESC3_4_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_75 0x3664C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_75 0x190F664Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_75 Register DESC0_5_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_75 0x36650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_75 0x190F6650u //! Register Reset Value #define DESC0_5_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_75 Register DESC1_5_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_75 0x36654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_75 0x190F6654u //! Register Reset Value #define DESC1_5_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_75 Register DESC2_5_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_75 0x36658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_75 0x190F6658u //! Register Reset Value #define DESC2_5_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_75 Register DESC3_5_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_75 0x3665C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_75 0x190F665Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_75 Register DESC0_6_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_75 0x36660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_75 0x190F6660u //! Register Reset Value #define DESC0_6_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_75 Register DESC1_6_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_75 0x36664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_75 0x190F6664u //! Register Reset Value #define DESC1_6_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_75 Register DESC2_6_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_75 0x36668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_75 0x190F6668u //! Register Reset Value #define DESC2_6_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_75 Register DESC3_6_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_75 0x3666C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_75 0x190F666Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_75 Register DESC0_7_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_75 0x36670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_75 0x190F6670u //! Register Reset Value #define DESC0_7_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_75 Register DESC1_7_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_75 0x36674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_75 0x190F6674u //! Register Reset Value #define DESC1_7_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_75 Register DESC2_7_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_75 0x36678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_75 0x190F6678u //! Register Reset Value #define DESC2_7_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_75_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_75 Register DESC3_7_PON_EGP_S_75 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_75 0x3667C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_75 0x190F667Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_75_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_75_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_75_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_75_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_75_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_76 Register CFG_PON_EGP_76 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_76 0x36800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_76 0x190F6800u //! Register Reset Value #define CFG_PON_EGP_76_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_76_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_76_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_76_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_76_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_76_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_76_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_76_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_76_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_76_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_76_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_76 Register IRNCR_PON_EGP_76 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_76 0x36820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_76 0x190F6820u //! Register Reset Value #define IRNCR_PON_EGP_76_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_76_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_76_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_76_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_76_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_76 Register IRNICR_PON_EGP_76 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_76 0x36824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_76 0x190F6824u //! Register Reset Value #define IRNICR_PON_EGP_76_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_76_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_76_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_76 Register IRNEN_PON_EGP_76 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_76 0x36828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_76 0x190F6828u //! Register Reset Value #define IRNEN_PON_EGP_76_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_76_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_76_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_76_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_76_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_76 Register DPTR_PON_EGP_76 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_76 0x36830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_76 0x190F6830u //! Register Reset Value #define DPTR_PON_EGP_76_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_76_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_76_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_76_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_76_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_76_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_76_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_76_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_76_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_76 Register DESC0_0_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_76 0x36900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_76 0x190F6900u //! Register Reset Value #define DESC0_0_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_76 Register DESC1_0_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_76 0x36904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_76 0x190F6904u //! Register Reset Value #define DESC1_0_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_76 Register DESC2_0_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_76 0x36908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_76 0x190F6908u //! Register Reset Value #define DESC2_0_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_76 Register DESC3_0_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_76 0x3690C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_76 0x190F690Cu //! Register Reset Value #define DESC3_0_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_76 Register DESC0_1_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_76 0x36910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_76 0x190F6910u //! Register Reset Value #define DESC0_1_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_76 Register DESC1_1_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_76 0x36914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_76 0x190F6914u //! Register Reset Value #define DESC1_1_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_76 Register DESC2_1_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_76 0x36918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_76 0x190F6918u //! Register Reset Value #define DESC2_1_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_76 Register DESC3_1_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_76 0x3691C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_76 0x190F691Cu //! Register Reset Value #define DESC3_1_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_76 Register DESC0_2_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_76 0x36920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_76 0x190F6920u //! Register Reset Value #define DESC0_2_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_76 Register DESC1_2_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_76 0x36924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_76 0x190F6924u //! Register Reset Value #define DESC1_2_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_76 Register DESC2_2_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_76 0x36928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_76 0x190F6928u //! Register Reset Value #define DESC2_2_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_76 Register DESC3_2_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_76 0x3692C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_76 0x190F692Cu //! Register Reset Value #define DESC3_2_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_76 Register DESC0_3_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_76 0x36930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_76 0x190F6930u //! Register Reset Value #define DESC0_3_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_76 Register DESC1_3_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_76 0x36934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_76 0x190F6934u //! Register Reset Value #define DESC1_3_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_76 Register DESC2_3_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_76 0x36938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_76 0x190F6938u //! Register Reset Value #define DESC2_3_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_76 Register DESC3_3_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_76 0x3693C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_76 0x190F693Cu //! Register Reset Value #define DESC3_3_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_76 Register DESC0_4_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_76 0x36940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_76 0x190F6940u //! Register Reset Value #define DESC0_4_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_76 Register DESC1_4_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_76 0x36944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_76 0x190F6944u //! Register Reset Value #define DESC1_4_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_76 Register DESC2_4_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_76 0x36948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_76 0x190F6948u //! Register Reset Value #define DESC2_4_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_76 Register DESC3_4_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_76 0x3694C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_76 0x190F694Cu //! Register Reset Value #define DESC3_4_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_76 Register DESC0_5_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_76 0x36950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_76 0x190F6950u //! Register Reset Value #define DESC0_5_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_76 Register DESC1_5_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_76 0x36954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_76 0x190F6954u //! Register Reset Value #define DESC1_5_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_76 Register DESC2_5_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_76 0x36958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_76 0x190F6958u //! Register Reset Value #define DESC2_5_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_76 Register DESC3_5_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_76 0x3695C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_76 0x190F695Cu //! Register Reset Value #define DESC3_5_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_76 Register DESC0_6_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_76 0x36960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_76 0x190F6960u //! Register Reset Value #define DESC0_6_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_76 Register DESC1_6_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_76 0x36964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_76 0x190F6964u //! Register Reset Value #define DESC1_6_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_76 Register DESC2_6_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_76 0x36968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_76 0x190F6968u //! Register Reset Value #define DESC2_6_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_76 Register DESC3_6_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_76 0x3696C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_76 0x190F696Cu //! Register Reset Value #define DESC3_6_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_76 Register DESC0_7_PON_EGP_76 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_76 0x36970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_76 0x190F6970u //! Register Reset Value #define DESC0_7_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_76 Register DESC1_7_PON_EGP_76 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_76 0x36974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_76 0x190F6974u //! Register Reset Value #define DESC1_7_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_76 Register DESC2_7_PON_EGP_76 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_76 0x36978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_76 0x190F6978u //! Register Reset Value #define DESC2_7_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_76 Register DESC3_7_PON_EGP_76 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_76 0x3697C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_76 0x190F697Cu //! Register Reset Value #define DESC3_7_PON_EGP_76_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_76_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_76_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_76 Register DESC0_0_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_76 0x36A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_76 0x190F6A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_76 Register DESC1_0_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_76 0x36A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_76 0x190F6A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_76 Register DESC2_0_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_76 0x36A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_76 0x190F6A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_76 Register DESC3_0_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_76 0x36A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_76 0x190F6A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_76 Register DESC0_1_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_76 0x36A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_76 0x190F6A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_76 Register DESC1_1_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_76 0x36A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_76 0x190F6A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_76 Register DESC2_1_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_76 0x36A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_76 0x190F6A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_76 Register DESC3_1_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_76 0x36A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_76 0x190F6A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_76 Register DESC0_2_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_76 0x36A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_76 0x190F6A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_76 Register DESC1_2_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_76 0x36A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_76 0x190F6A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_76 Register DESC2_2_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_76 0x36A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_76 0x190F6A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_76 Register DESC3_2_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_76 0x36A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_76 0x190F6A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_76 Register DESC0_3_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_76 0x36A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_76 0x190F6A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_76 Register DESC1_3_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_76 0x36A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_76 0x190F6A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_76 Register DESC2_3_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_76 0x36A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_76 0x190F6A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_76 Register DESC3_3_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_76 0x36A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_76 0x190F6A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_76 Register DESC0_4_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_76 0x36A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_76 0x190F6A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_76 Register DESC1_4_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_76 0x36A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_76 0x190F6A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_76 Register DESC2_4_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_76 0x36A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_76 0x190F6A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_76 Register DESC3_4_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_76 0x36A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_76 0x190F6A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_76 Register DESC0_5_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_76 0x36A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_76 0x190F6A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_76 Register DESC1_5_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_76 0x36A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_76 0x190F6A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_76 Register DESC2_5_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_76 0x36A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_76 0x190F6A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_76 Register DESC3_5_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_76 0x36A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_76 0x190F6A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_76 Register DESC0_6_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_76 0x36A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_76 0x190F6A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_76 Register DESC1_6_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_76 0x36A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_76 0x190F6A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_76 Register DESC2_6_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_76 0x36A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_76 0x190F6A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_76 Register DESC3_6_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_76 0x36A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_76 0x190F6A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_76 Register DESC0_7_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_76 0x36A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_76 0x190F6A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_76 Register DESC1_7_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_76 0x36A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_76 0x190F6A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_76 Register DESC2_7_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_76 0x36A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_76 0x190F6A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_76_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_76 Register DESC3_7_PON_EGP_S_76 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_76 0x36A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_76 0x190F6A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_76_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_76_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_76_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_76_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_76_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_77 Register CFG_PON_EGP_77 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_77 0x36C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_77 0x190F6C00u //! Register Reset Value #define CFG_PON_EGP_77_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_77_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_77_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_77_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_77_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_77_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_77_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_77_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_77_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_77_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_77_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_77 Register IRNCR_PON_EGP_77 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_77 0x36C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_77 0x190F6C20u //! Register Reset Value #define IRNCR_PON_EGP_77_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_77_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_77_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_77_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_77_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_77 Register IRNICR_PON_EGP_77 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_77 0x36C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_77 0x190F6C24u //! Register Reset Value #define IRNICR_PON_EGP_77_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_77_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_77_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_77 Register IRNEN_PON_EGP_77 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_77 0x36C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_77 0x190F6C28u //! Register Reset Value #define IRNEN_PON_EGP_77_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_77_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_77_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_77_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_77_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_77 Register DPTR_PON_EGP_77 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_77 0x36C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_77 0x190F6C30u //! Register Reset Value #define DPTR_PON_EGP_77_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_77_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_77_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_77_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_77_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_77_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_77_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_77_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_77_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_77 Register DESC0_0_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_77 0x36D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_77 0x190F6D00u //! Register Reset Value #define DESC0_0_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_77 Register DESC1_0_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_77 0x36D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_77 0x190F6D04u //! Register Reset Value #define DESC1_0_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_77 Register DESC2_0_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_77 0x36D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_77 0x190F6D08u //! Register Reset Value #define DESC2_0_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_77 Register DESC3_0_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_77 0x36D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_77 0x190F6D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_77 Register DESC0_1_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_77 0x36D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_77 0x190F6D10u //! Register Reset Value #define DESC0_1_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_77 Register DESC1_1_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_77 0x36D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_77 0x190F6D14u //! Register Reset Value #define DESC1_1_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_77 Register DESC2_1_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_77 0x36D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_77 0x190F6D18u //! Register Reset Value #define DESC2_1_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_77 Register DESC3_1_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_77 0x36D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_77 0x190F6D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_77 Register DESC0_2_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_77 0x36D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_77 0x190F6D20u //! Register Reset Value #define DESC0_2_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_77 Register DESC1_2_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_77 0x36D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_77 0x190F6D24u //! Register Reset Value #define DESC1_2_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_77 Register DESC2_2_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_77 0x36D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_77 0x190F6D28u //! Register Reset Value #define DESC2_2_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_77 Register DESC3_2_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_77 0x36D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_77 0x190F6D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_77 Register DESC0_3_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_77 0x36D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_77 0x190F6D30u //! Register Reset Value #define DESC0_3_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_77 Register DESC1_3_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_77 0x36D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_77 0x190F6D34u //! Register Reset Value #define DESC1_3_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_77 Register DESC2_3_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_77 0x36D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_77 0x190F6D38u //! Register Reset Value #define DESC2_3_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_77 Register DESC3_3_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_77 0x36D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_77 0x190F6D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_77 Register DESC0_4_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_77 0x36D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_77 0x190F6D40u //! Register Reset Value #define DESC0_4_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_77 Register DESC1_4_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_77 0x36D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_77 0x190F6D44u //! Register Reset Value #define DESC1_4_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_77 Register DESC2_4_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_77 0x36D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_77 0x190F6D48u //! Register Reset Value #define DESC2_4_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_77 Register DESC3_4_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_77 0x36D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_77 0x190F6D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_77 Register DESC0_5_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_77 0x36D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_77 0x190F6D50u //! Register Reset Value #define DESC0_5_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_77 Register DESC1_5_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_77 0x36D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_77 0x190F6D54u //! Register Reset Value #define DESC1_5_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_77 Register DESC2_5_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_77 0x36D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_77 0x190F6D58u //! Register Reset Value #define DESC2_5_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_77 Register DESC3_5_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_77 0x36D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_77 0x190F6D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_77 Register DESC0_6_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_77 0x36D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_77 0x190F6D60u //! Register Reset Value #define DESC0_6_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_77 Register DESC1_6_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_77 0x36D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_77 0x190F6D64u //! Register Reset Value #define DESC1_6_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_77 Register DESC2_6_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_77 0x36D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_77 0x190F6D68u //! Register Reset Value #define DESC2_6_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_77 Register DESC3_6_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_77 0x36D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_77 0x190F6D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_77 Register DESC0_7_PON_EGP_77 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_77 0x36D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_77 0x190F6D70u //! Register Reset Value #define DESC0_7_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_77 Register DESC1_7_PON_EGP_77 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_77 0x36D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_77 0x190F6D74u //! Register Reset Value #define DESC1_7_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_77 Register DESC2_7_PON_EGP_77 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_77 0x36D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_77 0x190F6D78u //! Register Reset Value #define DESC2_7_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_77 Register DESC3_7_PON_EGP_77 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_77 0x36D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_77 0x190F6D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_77_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_77_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_77_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_77 Register DESC0_0_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_77 0x36E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_77 0x190F6E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_77 Register DESC1_0_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_77 0x36E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_77 0x190F6E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_77 Register DESC2_0_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_77 0x36E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_77 0x190F6E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_77 Register DESC3_0_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_77 0x36E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_77 0x190F6E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_77 Register DESC0_1_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_77 0x36E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_77 0x190F6E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_77 Register DESC1_1_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_77 0x36E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_77 0x190F6E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_77 Register DESC2_1_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_77 0x36E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_77 0x190F6E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_77 Register DESC3_1_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_77 0x36E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_77 0x190F6E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_77 Register DESC0_2_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_77 0x36E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_77 0x190F6E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_77 Register DESC1_2_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_77 0x36E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_77 0x190F6E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_77 Register DESC2_2_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_77 0x36E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_77 0x190F6E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_77 Register DESC3_2_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_77 0x36E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_77 0x190F6E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_77 Register DESC0_3_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_77 0x36E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_77 0x190F6E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_77 Register DESC1_3_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_77 0x36E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_77 0x190F6E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_77 Register DESC2_3_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_77 0x36E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_77 0x190F6E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_77 Register DESC3_3_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_77 0x36E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_77 0x190F6E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_77 Register DESC0_4_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_77 0x36E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_77 0x190F6E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_77 Register DESC1_4_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_77 0x36E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_77 0x190F6E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_77 Register DESC2_4_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_77 0x36E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_77 0x190F6E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_77 Register DESC3_4_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_77 0x36E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_77 0x190F6E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_77 Register DESC0_5_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_77 0x36E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_77 0x190F6E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_77 Register DESC1_5_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_77 0x36E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_77 0x190F6E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_77 Register DESC2_5_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_77 0x36E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_77 0x190F6E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_77 Register DESC3_5_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_77 0x36E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_77 0x190F6E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_77 Register DESC0_6_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_77 0x36E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_77 0x190F6E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_77 Register DESC1_6_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_77 0x36E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_77 0x190F6E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_77 Register DESC2_6_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_77 0x36E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_77 0x190F6E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_77 Register DESC3_6_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_77 0x36E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_77 0x190F6E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_77 Register DESC0_7_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_77 0x36E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_77 0x190F6E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_77 Register DESC1_7_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_77 0x36E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_77 0x190F6E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_77 Register DESC2_7_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_77 0x36E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_77 0x190F6E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_77_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_77 Register DESC3_7_PON_EGP_S_77 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_77 0x36E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_77 0x190F6E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_77_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_77_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_77_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_77_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_77_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_78 Register CFG_PON_EGP_78 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_78 0x37000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_78 0x190F7000u //! Register Reset Value #define CFG_PON_EGP_78_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_78_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_78_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_78_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_78_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_78_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_78_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_78_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_78_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_78_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_78_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_78 Register IRNCR_PON_EGP_78 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_78 0x37020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_78 0x190F7020u //! Register Reset Value #define IRNCR_PON_EGP_78_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_78_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_78_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_78_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_78_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_78 Register IRNICR_PON_EGP_78 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_78 0x37024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_78 0x190F7024u //! Register Reset Value #define IRNICR_PON_EGP_78_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_78_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_78_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_78 Register IRNEN_PON_EGP_78 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_78 0x37028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_78 0x190F7028u //! Register Reset Value #define IRNEN_PON_EGP_78_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_78_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_78_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_78_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_78_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_78 Register DPTR_PON_EGP_78 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_78 0x37030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_78 0x190F7030u //! Register Reset Value #define DPTR_PON_EGP_78_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_78_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_78_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_78_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_78_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_78_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_78_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_78_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_78_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_78 Register DESC0_0_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_78 0x37100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_78 0x190F7100u //! Register Reset Value #define DESC0_0_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_78 Register DESC1_0_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_78 0x37104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_78 0x190F7104u //! Register Reset Value #define DESC1_0_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_78 Register DESC2_0_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_78 0x37108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_78 0x190F7108u //! Register Reset Value #define DESC2_0_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_78 Register DESC3_0_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_78 0x3710C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_78 0x190F710Cu //! Register Reset Value #define DESC3_0_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_78 Register DESC0_1_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_78 0x37110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_78 0x190F7110u //! Register Reset Value #define DESC0_1_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_78 Register DESC1_1_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_78 0x37114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_78 0x190F7114u //! Register Reset Value #define DESC1_1_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_78 Register DESC2_1_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_78 0x37118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_78 0x190F7118u //! Register Reset Value #define DESC2_1_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_78 Register DESC3_1_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_78 0x3711C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_78 0x190F711Cu //! Register Reset Value #define DESC3_1_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_78 Register DESC0_2_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_78 0x37120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_78 0x190F7120u //! Register Reset Value #define DESC0_2_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_78 Register DESC1_2_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_78 0x37124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_78 0x190F7124u //! Register Reset Value #define DESC1_2_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_78 Register DESC2_2_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_78 0x37128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_78 0x190F7128u //! Register Reset Value #define DESC2_2_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_78 Register DESC3_2_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_78 0x3712C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_78 0x190F712Cu //! Register Reset Value #define DESC3_2_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_78 Register DESC0_3_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_78 0x37130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_78 0x190F7130u //! Register Reset Value #define DESC0_3_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_78 Register DESC1_3_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_78 0x37134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_78 0x190F7134u //! Register Reset Value #define DESC1_3_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_78 Register DESC2_3_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_78 0x37138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_78 0x190F7138u //! Register Reset Value #define DESC2_3_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_78 Register DESC3_3_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_78 0x3713C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_78 0x190F713Cu //! Register Reset Value #define DESC3_3_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_78 Register DESC0_4_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_78 0x37140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_78 0x190F7140u //! Register Reset Value #define DESC0_4_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_78 Register DESC1_4_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_78 0x37144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_78 0x190F7144u //! Register Reset Value #define DESC1_4_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_78 Register DESC2_4_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_78 0x37148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_78 0x190F7148u //! Register Reset Value #define DESC2_4_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_78 Register DESC3_4_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_78 0x3714C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_78 0x190F714Cu //! Register Reset Value #define DESC3_4_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_78 Register DESC0_5_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_78 0x37150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_78 0x190F7150u //! Register Reset Value #define DESC0_5_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_78 Register DESC1_5_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_78 0x37154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_78 0x190F7154u //! Register Reset Value #define DESC1_5_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_78 Register DESC2_5_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_78 0x37158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_78 0x190F7158u //! Register Reset Value #define DESC2_5_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_78 Register DESC3_5_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_78 0x3715C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_78 0x190F715Cu //! Register Reset Value #define DESC3_5_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_78 Register DESC0_6_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_78 0x37160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_78 0x190F7160u //! Register Reset Value #define DESC0_6_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_78 Register DESC1_6_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_78 0x37164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_78 0x190F7164u //! Register Reset Value #define DESC1_6_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_78 Register DESC2_6_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_78 0x37168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_78 0x190F7168u //! Register Reset Value #define DESC2_6_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_78 Register DESC3_6_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_78 0x3716C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_78 0x190F716Cu //! Register Reset Value #define DESC3_6_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_78 Register DESC0_7_PON_EGP_78 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_78 0x37170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_78 0x190F7170u //! Register Reset Value #define DESC0_7_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_78 Register DESC1_7_PON_EGP_78 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_78 0x37174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_78 0x190F7174u //! Register Reset Value #define DESC1_7_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_78 Register DESC2_7_PON_EGP_78 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_78 0x37178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_78 0x190F7178u //! Register Reset Value #define DESC2_7_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_78 Register DESC3_7_PON_EGP_78 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_78 0x3717C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_78 0x190F717Cu //! Register Reset Value #define DESC3_7_PON_EGP_78_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_78_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_78_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_78 Register DESC0_0_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_78 0x37200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_78 0x190F7200u //! Register Reset Value #define DESC0_0_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_78 Register DESC1_0_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_78 0x37204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_78 0x190F7204u //! Register Reset Value #define DESC1_0_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_78 Register DESC2_0_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_78 0x37208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_78 0x190F7208u //! Register Reset Value #define DESC2_0_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_78 Register DESC3_0_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_78 0x3720C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_78 0x190F720Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_78 Register DESC0_1_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_78 0x37210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_78 0x190F7210u //! Register Reset Value #define DESC0_1_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_78 Register DESC1_1_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_78 0x37214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_78 0x190F7214u //! Register Reset Value #define DESC1_1_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_78 Register DESC2_1_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_78 0x37218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_78 0x190F7218u //! Register Reset Value #define DESC2_1_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_78 Register DESC3_1_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_78 0x3721C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_78 0x190F721Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_78 Register DESC0_2_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_78 0x37220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_78 0x190F7220u //! Register Reset Value #define DESC0_2_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_78 Register DESC1_2_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_78 0x37224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_78 0x190F7224u //! Register Reset Value #define DESC1_2_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_78 Register DESC2_2_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_78 0x37228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_78 0x190F7228u //! Register Reset Value #define DESC2_2_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_78 Register DESC3_2_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_78 0x3722C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_78 0x190F722Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_78 Register DESC0_3_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_78 0x37230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_78 0x190F7230u //! Register Reset Value #define DESC0_3_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_78 Register DESC1_3_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_78 0x37234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_78 0x190F7234u //! Register Reset Value #define DESC1_3_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_78 Register DESC2_3_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_78 0x37238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_78 0x190F7238u //! Register Reset Value #define DESC2_3_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_78 Register DESC3_3_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_78 0x3723C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_78 0x190F723Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_78 Register DESC0_4_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_78 0x37240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_78 0x190F7240u //! Register Reset Value #define DESC0_4_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_78 Register DESC1_4_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_78 0x37244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_78 0x190F7244u //! Register Reset Value #define DESC1_4_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_78 Register DESC2_4_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_78 0x37248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_78 0x190F7248u //! Register Reset Value #define DESC2_4_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_78 Register DESC3_4_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_78 0x3724C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_78 0x190F724Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_78 Register DESC0_5_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_78 0x37250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_78 0x190F7250u //! Register Reset Value #define DESC0_5_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_78 Register DESC1_5_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_78 0x37254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_78 0x190F7254u //! Register Reset Value #define DESC1_5_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_78 Register DESC2_5_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_78 0x37258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_78 0x190F7258u //! Register Reset Value #define DESC2_5_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_78 Register DESC3_5_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_78 0x3725C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_78 0x190F725Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_78 Register DESC0_6_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_78 0x37260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_78 0x190F7260u //! Register Reset Value #define DESC0_6_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_78 Register DESC1_6_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_78 0x37264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_78 0x190F7264u //! Register Reset Value #define DESC1_6_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_78 Register DESC2_6_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_78 0x37268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_78 0x190F7268u //! Register Reset Value #define DESC2_6_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_78 Register DESC3_6_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_78 0x3726C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_78 0x190F726Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_78 Register DESC0_7_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_78 0x37270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_78 0x190F7270u //! Register Reset Value #define DESC0_7_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_78 Register DESC1_7_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_78 0x37274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_78 0x190F7274u //! Register Reset Value #define DESC1_7_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_78 Register DESC2_7_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_78 0x37278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_78 0x190F7278u //! Register Reset Value #define DESC2_7_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_78_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_78 Register DESC3_7_PON_EGP_S_78 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_78 0x3727C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_78 0x190F727Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_78_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_78_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_78_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_78_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_78_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_79 Register CFG_PON_EGP_79 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_79 0x37400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_79 0x190F7400u //! Register Reset Value #define CFG_PON_EGP_79_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_79_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_79_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_79_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_79_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_79_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_79_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_79_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_79_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_79_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_79_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_79 Register IRNCR_PON_EGP_79 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_79 0x37420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_79 0x190F7420u //! Register Reset Value #define IRNCR_PON_EGP_79_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_79_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_79_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_79_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_79_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_79 Register IRNICR_PON_EGP_79 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_79 0x37424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_79 0x190F7424u //! Register Reset Value #define IRNICR_PON_EGP_79_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_79_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_79_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_79 Register IRNEN_PON_EGP_79 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_79 0x37428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_79 0x190F7428u //! Register Reset Value #define IRNEN_PON_EGP_79_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_79_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_79_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_79_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_79_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_79 Register DPTR_PON_EGP_79 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_79 0x37430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_79 0x190F7430u //! Register Reset Value #define DPTR_PON_EGP_79_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_79_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_79_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_79_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_79_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_79_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_79_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_79_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_79_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_79 Register DESC0_0_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_79 0x37500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_79 0x190F7500u //! Register Reset Value #define DESC0_0_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_79 Register DESC1_0_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_79 0x37504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_79 0x190F7504u //! Register Reset Value #define DESC1_0_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_79 Register DESC2_0_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_79 0x37508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_79 0x190F7508u //! Register Reset Value #define DESC2_0_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_79 Register DESC3_0_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_79 0x3750C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_79 0x190F750Cu //! Register Reset Value #define DESC3_0_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_79 Register DESC0_1_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_79 0x37510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_79 0x190F7510u //! Register Reset Value #define DESC0_1_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_79 Register DESC1_1_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_79 0x37514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_79 0x190F7514u //! Register Reset Value #define DESC1_1_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_79 Register DESC2_1_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_79 0x37518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_79 0x190F7518u //! Register Reset Value #define DESC2_1_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_79 Register DESC3_1_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_79 0x3751C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_79 0x190F751Cu //! Register Reset Value #define DESC3_1_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_79 Register DESC0_2_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_79 0x37520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_79 0x190F7520u //! Register Reset Value #define DESC0_2_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_79 Register DESC1_2_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_79 0x37524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_79 0x190F7524u //! Register Reset Value #define DESC1_2_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_79 Register DESC2_2_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_79 0x37528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_79 0x190F7528u //! Register Reset Value #define DESC2_2_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_79 Register DESC3_2_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_79 0x3752C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_79 0x190F752Cu //! Register Reset Value #define DESC3_2_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_79 Register DESC0_3_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_79 0x37530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_79 0x190F7530u //! Register Reset Value #define DESC0_3_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_79 Register DESC1_3_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_79 0x37534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_79 0x190F7534u //! Register Reset Value #define DESC1_3_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_79 Register DESC2_3_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_79 0x37538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_79 0x190F7538u //! Register Reset Value #define DESC2_3_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_79 Register DESC3_3_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_79 0x3753C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_79 0x190F753Cu //! Register Reset Value #define DESC3_3_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_79 Register DESC0_4_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_79 0x37540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_79 0x190F7540u //! Register Reset Value #define DESC0_4_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_79 Register DESC1_4_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_79 0x37544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_79 0x190F7544u //! Register Reset Value #define DESC1_4_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_79 Register DESC2_4_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_79 0x37548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_79 0x190F7548u //! Register Reset Value #define DESC2_4_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_79 Register DESC3_4_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_79 0x3754C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_79 0x190F754Cu //! Register Reset Value #define DESC3_4_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_79 Register DESC0_5_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_79 0x37550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_79 0x190F7550u //! Register Reset Value #define DESC0_5_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_79 Register DESC1_5_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_79 0x37554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_79 0x190F7554u //! Register Reset Value #define DESC1_5_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_79 Register DESC2_5_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_79 0x37558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_79 0x190F7558u //! Register Reset Value #define DESC2_5_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_79 Register DESC3_5_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_79 0x3755C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_79 0x190F755Cu //! Register Reset Value #define DESC3_5_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_79 Register DESC0_6_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_79 0x37560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_79 0x190F7560u //! Register Reset Value #define DESC0_6_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_79 Register DESC1_6_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_79 0x37564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_79 0x190F7564u //! Register Reset Value #define DESC1_6_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_79 Register DESC2_6_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_79 0x37568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_79 0x190F7568u //! Register Reset Value #define DESC2_6_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_79 Register DESC3_6_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_79 0x3756C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_79 0x190F756Cu //! Register Reset Value #define DESC3_6_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_79 Register DESC0_7_PON_EGP_79 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_79 0x37570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_79 0x190F7570u //! Register Reset Value #define DESC0_7_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_79 Register DESC1_7_PON_EGP_79 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_79 0x37574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_79 0x190F7574u //! Register Reset Value #define DESC1_7_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_79 Register DESC2_7_PON_EGP_79 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_79 0x37578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_79 0x190F7578u //! Register Reset Value #define DESC2_7_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_79 Register DESC3_7_PON_EGP_79 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_79 0x3757C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_79 0x190F757Cu //! Register Reset Value #define DESC3_7_PON_EGP_79_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_79_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_79_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_79 Register DESC0_0_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_79 0x37600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_79 0x190F7600u //! Register Reset Value #define DESC0_0_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_79 Register DESC1_0_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_79 0x37604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_79 0x190F7604u //! Register Reset Value #define DESC1_0_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_79 Register DESC2_0_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_79 0x37608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_79 0x190F7608u //! Register Reset Value #define DESC2_0_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_79 Register DESC3_0_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_79 0x3760C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_79 0x190F760Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_79 Register DESC0_1_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_79 0x37610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_79 0x190F7610u //! Register Reset Value #define DESC0_1_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_79 Register DESC1_1_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_79 0x37614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_79 0x190F7614u //! Register Reset Value #define DESC1_1_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_79 Register DESC2_1_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_79 0x37618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_79 0x190F7618u //! Register Reset Value #define DESC2_1_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_79 Register DESC3_1_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_79 0x3761C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_79 0x190F761Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_79 Register DESC0_2_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_79 0x37620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_79 0x190F7620u //! Register Reset Value #define DESC0_2_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_79 Register DESC1_2_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_79 0x37624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_79 0x190F7624u //! Register Reset Value #define DESC1_2_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_79 Register DESC2_2_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_79 0x37628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_79 0x190F7628u //! Register Reset Value #define DESC2_2_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_79 Register DESC3_2_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_79 0x3762C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_79 0x190F762Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_79 Register DESC0_3_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_79 0x37630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_79 0x190F7630u //! Register Reset Value #define DESC0_3_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_79 Register DESC1_3_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_79 0x37634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_79 0x190F7634u //! Register Reset Value #define DESC1_3_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_79 Register DESC2_3_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_79 0x37638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_79 0x190F7638u //! Register Reset Value #define DESC2_3_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_79 Register DESC3_3_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_79 0x3763C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_79 0x190F763Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_79 Register DESC0_4_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_79 0x37640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_79 0x190F7640u //! Register Reset Value #define DESC0_4_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_79 Register DESC1_4_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_79 0x37644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_79 0x190F7644u //! Register Reset Value #define DESC1_4_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_79 Register DESC2_4_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_79 0x37648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_79 0x190F7648u //! Register Reset Value #define DESC2_4_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_79 Register DESC3_4_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_79 0x3764C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_79 0x190F764Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_79 Register DESC0_5_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_79 0x37650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_79 0x190F7650u //! Register Reset Value #define DESC0_5_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_79 Register DESC1_5_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_79 0x37654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_79 0x190F7654u //! Register Reset Value #define DESC1_5_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_79 Register DESC2_5_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_79 0x37658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_79 0x190F7658u //! Register Reset Value #define DESC2_5_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_79 Register DESC3_5_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_79 0x3765C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_79 0x190F765Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_79 Register DESC0_6_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_79 0x37660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_79 0x190F7660u //! Register Reset Value #define DESC0_6_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_79 Register DESC1_6_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_79 0x37664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_79 0x190F7664u //! Register Reset Value #define DESC1_6_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_79 Register DESC2_6_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_79 0x37668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_79 0x190F7668u //! Register Reset Value #define DESC2_6_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_79 Register DESC3_6_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_79 0x3766C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_79 0x190F766Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_79 Register DESC0_7_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_79 0x37670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_79 0x190F7670u //! Register Reset Value #define DESC0_7_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_79 Register DESC1_7_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_79 0x37674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_79 0x190F7674u //! Register Reset Value #define DESC1_7_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_79 Register DESC2_7_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_79 0x37678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_79 0x190F7678u //! Register Reset Value #define DESC2_7_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_79_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_79 Register DESC3_7_PON_EGP_S_79 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_79 0x3767C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_79 0x190F767Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_79_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_79_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_79_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_79_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_79_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_80 Register CFG_PON_EGP_80 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_80 0x37800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_80 0x190F7800u //! Register Reset Value #define CFG_PON_EGP_80_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_80_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_80_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_80_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_80_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_80_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_80_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_80_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_80_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_80_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_80_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_80 Register IRNCR_PON_EGP_80 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_80 0x37820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_80 0x190F7820u //! Register Reset Value #define IRNCR_PON_EGP_80_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_80_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_80_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_80_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_80_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_80 Register IRNICR_PON_EGP_80 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_80 0x37824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_80 0x190F7824u //! Register Reset Value #define IRNICR_PON_EGP_80_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_80_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_80_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_80 Register IRNEN_PON_EGP_80 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_80 0x37828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_80 0x190F7828u //! Register Reset Value #define IRNEN_PON_EGP_80_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_80_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_80_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_80_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_80_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_80 Register DPTR_PON_EGP_80 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_80 0x37830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_80 0x190F7830u //! Register Reset Value #define DPTR_PON_EGP_80_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_80_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_80_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_80_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_80_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_80_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_80_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_80_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_80_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_80 Register DESC0_0_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_80 0x37900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_80 0x190F7900u //! Register Reset Value #define DESC0_0_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_80 Register DESC1_0_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_80 0x37904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_80 0x190F7904u //! Register Reset Value #define DESC1_0_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_80 Register DESC2_0_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_80 0x37908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_80 0x190F7908u //! Register Reset Value #define DESC2_0_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_80 Register DESC3_0_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_80 0x3790C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_80 0x190F790Cu //! Register Reset Value #define DESC3_0_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_80 Register DESC0_1_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_80 0x37910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_80 0x190F7910u //! Register Reset Value #define DESC0_1_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_80 Register DESC1_1_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_80 0x37914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_80 0x190F7914u //! Register Reset Value #define DESC1_1_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_80 Register DESC2_1_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_80 0x37918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_80 0x190F7918u //! Register Reset Value #define DESC2_1_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_80 Register DESC3_1_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_80 0x3791C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_80 0x190F791Cu //! Register Reset Value #define DESC3_1_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_80 Register DESC0_2_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_80 0x37920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_80 0x190F7920u //! Register Reset Value #define DESC0_2_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_80 Register DESC1_2_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_80 0x37924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_80 0x190F7924u //! Register Reset Value #define DESC1_2_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_80 Register DESC2_2_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_80 0x37928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_80 0x190F7928u //! Register Reset Value #define DESC2_2_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_80 Register DESC3_2_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_80 0x3792C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_80 0x190F792Cu //! Register Reset Value #define DESC3_2_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_80 Register DESC0_3_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_80 0x37930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_80 0x190F7930u //! Register Reset Value #define DESC0_3_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_80 Register DESC1_3_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_80 0x37934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_80 0x190F7934u //! Register Reset Value #define DESC1_3_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_80 Register DESC2_3_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_80 0x37938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_80 0x190F7938u //! Register Reset Value #define DESC2_3_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_80 Register DESC3_3_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_80 0x3793C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_80 0x190F793Cu //! Register Reset Value #define DESC3_3_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_80 Register DESC0_4_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_80 0x37940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_80 0x190F7940u //! Register Reset Value #define DESC0_4_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_80 Register DESC1_4_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_80 0x37944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_80 0x190F7944u //! Register Reset Value #define DESC1_4_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_80 Register DESC2_4_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_80 0x37948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_80 0x190F7948u //! Register Reset Value #define DESC2_4_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_80 Register DESC3_4_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_80 0x3794C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_80 0x190F794Cu //! Register Reset Value #define DESC3_4_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_80 Register DESC0_5_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_80 0x37950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_80 0x190F7950u //! Register Reset Value #define DESC0_5_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_80 Register DESC1_5_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_80 0x37954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_80 0x190F7954u //! Register Reset Value #define DESC1_5_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_80 Register DESC2_5_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_80 0x37958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_80 0x190F7958u //! Register Reset Value #define DESC2_5_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_80 Register DESC3_5_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_80 0x3795C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_80 0x190F795Cu //! Register Reset Value #define DESC3_5_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_80 Register DESC0_6_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_80 0x37960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_80 0x190F7960u //! Register Reset Value #define DESC0_6_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_80 Register DESC1_6_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_80 0x37964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_80 0x190F7964u //! Register Reset Value #define DESC1_6_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_80 Register DESC2_6_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_80 0x37968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_80 0x190F7968u //! Register Reset Value #define DESC2_6_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_80 Register DESC3_6_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_80 0x3796C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_80 0x190F796Cu //! Register Reset Value #define DESC3_6_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_80 Register DESC0_7_PON_EGP_80 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_80 0x37970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_80 0x190F7970u //! Register Reset Value #define DESC0_7_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_80 Register DESC1_7_PON_EGP_80 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_80 0x37974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_80 0x190F7974u //! Register Reset Value #define DESC1_7_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_80 Register DESC2_7_PON_EGP_80 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_80 0x37978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_80 0x190F7978u //! Register Reset Value #define DESC2_7_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_80 Register DESC3_7_PON_EGP_80 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_80 0x3797C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_80 0x190F797Cu //! Register Reset Value #define DESC3_7_PON_EGP_80_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_80_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_80_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_80 Register DESC0_0_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_80 0x37A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_80 0x190F7A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_80 Register DESC1_0_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_80 0x37A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_80 0x190F7A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_80 Register DESC2_0_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_80 0x37A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_80 0x190F7A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_80 Register DESC3_0_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_80 0x37A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_80 0x190F7A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_80 Register DESC0_1_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_80 0x37A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_80 0x190F7A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_80 Register DESC1_1_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_80 0x37A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_80 0x190F7A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_80 Register DESC2_1_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_80 0x37A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_80 0x190F7A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_80 Register DESC3_1_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_80 0x37A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_80 0x190F7A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_80 Register DESC0_2_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_80 0x37A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_80 0x190F7A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_80 Register DESC1_2_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_80 0x37A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_80 0x190F7A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_80 Register DESC2_2_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_80 0x37A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_80 0x190F7A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_80 Register DESC3_2_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_80 0x37A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_80 0x190F7A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_80 Register DESC0_3_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_80 0x37A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_80 0x190F7A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_80 Register DESC1_3_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_80 0x37A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_80 0x190F7A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_80 Register DESC2_3_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_80 0x37A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_80 0x190F7A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_80 Register DESC3_3_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_80 0x37A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_80 0x190F7A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_80 Register DESC0_4_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_80 0x37A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_80 0x190F7A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_80 Register DESC1_4_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_80 0x37A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_80 0x190F7A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_80 Register DESC2_4_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_80 0x37A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_80 0x190F7A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_80 Register DESC3_4_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_80 0x37A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_80 0x190F7A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_80 Register DESC0_5_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_80 0x37A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_80 0x190F7A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_80 Register DESC1_5_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_80 0x37A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_80 0x190F7A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_80 Register DESC2_5_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_80 0x37A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_80 0x190F7A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_80 Register DESC3_5_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_80 0x37A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_80 0x190F7A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_80 Register DESC0_6_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_80 0x37A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_80 0x190F7A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_80 Register DESC1_6_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_80 0x37A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_80 0x190F7A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_80 Register DESC2_6_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_80 0x37A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_80 0x190F7A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_80 Register DESC3_6_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_80 0x37A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_80 0x190F7A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_80 Register DESC0_7_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_80 0x37A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_80 0x190F7A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_80 Register DESC1_7_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_80 0x37A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_80 0x190F7A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_80 Register DESC2_7_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_80 0x37A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_80 0x190F7A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_80_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_80 Register DESC3_7_PON_EGP_S_80 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_80 0x37A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_80 0x190F7A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_80_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_80_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_80_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_80_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_80_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_81 Register CFG_PON_EGP_81 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_81 0x37C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_81 0x190F7C00u //! Register Reset Value #define CFG_PON_EGP_81_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_81_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_81_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_81_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_81_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_81_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_81_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_81_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_81_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_81_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_81_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_81 Register IRNCR_PON_EGP_81 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_81 0x37C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_81 0x190F7C20u //! Register Reset Value #define IRNCR_PON_EGP_81_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_81_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_81_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_81_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_81_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_81 Register IRNICR_PON_EGP_81 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_81 0x37C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_81 0x190F7C24u //! Register Reset Value #define IRNICR_PON_EGP_81_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_81_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_81_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_81 Register IRNEN_PON_EGP_81 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_81 0x37C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_81 0x190F7C28u //! Register Reset Value #define IRNEN_PON_EGP_81_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_81_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_81_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_81_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_81_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_81 Register DPTR_PON_EGP_81 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_81 0x37C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_81 0x190F7C30u //! Register Reset Value #define DPTR_PON_EGP_81_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_81_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_81_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_81_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_81_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_81_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_81_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_81_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_81_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_81 Register DESC0_0_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_81 0x37D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_81 0x190F7D00u //! Register Reset Value #define DESC0_0_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_81 Register DESC1_0_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_81 0x37D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_81 0x190F7D04u //! Register Reset Value #define DESC1_0_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_81 Register DESC2_0_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_81 0x37D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_81 0x190F7D08u //! Register Reset Value #define DESC2_0_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_81 Register DESC3_0_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_81 0x37D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_81 0x190F7D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_81 Register DESC0_1_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_81 0x37D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_81 0x190F7D10u //! Register Reset Value #define DESC0_1_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_81 Register DESC1_1_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_81 0x37D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_81 0x190F7D14u //! Register Reset Value #define DESC1_1_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_81 Register DESC2_1_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_81 0x37D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_81 0x190F7D18u //! Register Reset Value #define DESC2_1_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_81 Register DESC3_1_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_81 0x37D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_81 0x190F7D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_81 Register DESC0_2_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_81 0x37D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_81 0x190F7D20u //! Register Reset Value #define DESC0_2_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_81 Register DESC1_2_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_81 0x37D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_81 0x190F7D24u //! Register Reset Value #define DESC1_2_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_81 Register DESC2_2_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_81 0x37D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_81 0x190F7D28u //! Register Reset Value #define DESC2_2_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_81 Register DESC3_2_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_81 0x37D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_81 0x190F7D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_81 Register DESC0_3_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_81 0x37D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_81 0x190F7D30u //! Register Reset Value #define DESC0_3_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_81 Register DESC1_3_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_81 0x37D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_81 0x190F7D34u //! Register Reset Value #define DESC1_3_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_81 Register DESC2_3_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_81 0x37D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_81 0x190F7D38u //! Register Reset Value #define DESC2_3_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_81 Register DESC3_3_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_81 0x37D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_81 0x190F7D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_81 Register DESC0_4_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_81 0x37D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_81 0x190F7D40u //! Register Reset Value #define DESC0_4_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_81 Register DESC1_4_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_81 0x37D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_81 0x190F7D44u //! Register Reset Value #define DESC1_4_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_81 Register DESC2_4_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_81 0x37D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_81 0x190F7D48u //! Register Reset Value #define DESC2_4_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_81 Register DESC3_4_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_81 0x37D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_81 0x190F7D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_81 Register DESC0_5_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_81 0x37D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_81 0x190F7D50u //! Register Reset Value #define DESC0_5_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_81 Register DESC1_5_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_81 0x37D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_81 0x190F7D54u //! Register Reset Value #define DESC1_5_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_81 Register DESC2_5_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_81 0x37D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_81 0x190F7D58u //! Register Reset Value #define DESC2_5_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_81 Register DESC3_5_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_81 0x37D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_81 0x190F7D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_81 Register DESC0_6_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_81 0x37D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_81 0x190F7D60u //! Register Reset Value #define DESC0_6_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_81 Register DESC1_6_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_81 0x37D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_81 0x190F7D64u //! Register Reset Value #define DESC1_6_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_81 Register DESC2_6_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_81 0x37D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_81 0x190F7D68u //! Register Reset Value #define DESC2_6_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_81 Register DESC3_6_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_81 0x37D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_81 0x190F7D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_81 Register DESC0_7_PON_EGP_81 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_81 0x37D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_81 0x190F7D70u //! Register Reset Value #define DESC0_7_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_81 Register DESC1_7_PON_EGP_81 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_81 0x37D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_81 0x190F7D74u //! Register Reset Value #define DESC1_7_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_81 Register DESC2_7_PON_EGP_81 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_81 0x37D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_81 0x190F7D78u //! Register Reset Value #define DESC2_7_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_81 Register DESC3_7_PON_EGP_81 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_81 0x37D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_81 0x190F7D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_81_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_81_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_81_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_81 Register DESC0_0_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_81 0x37E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_81 0x190F7E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_81 Register DESC1_0_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_81 0x37E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_81 0x190F7E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_81 Register DESC2_0_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_81 0x37E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_81 0x190F7E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_81 Register DESC3_0_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_81 0x37E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_81 0x190F7E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_81 Register DESC0_1_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_81 0x37E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_81 0x190F7E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_81 Register DESC1_1_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_81 0x37E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_81 0x190F7E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_81 Register DESC2_1_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_81 0x37E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_81 0x190F7E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_81 Register DESC3_1_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_81 0x37E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_81 0x190F7E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_81 Register DESC0_2_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_81 0x37E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_81 0x190F7E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_81 Register DESC1_2_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_81 0x37E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_81 0x190F7E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_81 Register DESC2_2_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_81 0x37E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_81 0x190F7E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_81 Register DESC3_2_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_81 0x37E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_81 0x190F7E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_81 Register DESC0_3_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_81 0x37E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_81 0x190F7E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_81 Register DESC1_3_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_81 0x37E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_81 0x190F7E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_81 Register DESC2_3_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_81 0x37E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_81 0x190F7E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_81 Register DESC3_3_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_81 0x37E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_81 0x190F7E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_81 Register DESC0_4_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_81 0x37E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_81 0x190F7E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_81 Register DESC1_4_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_81 0x37E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_81 0x190F7E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_81 Register DESC2_4_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_81 0x37E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_81 0x190F7E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_81 Register DESC3_4_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_81 0x37E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_81 0x190F7E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_81 Register DESC0_5_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_81 0x37E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_81 0x190F7E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_81 Register DESC1_5_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_81 0x37E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_81 0x190F7E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_81 Register DESC2_5_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_81 0x37E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_81 0x190F7E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_81 Register DESC3_5_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_81 0x37E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_81 0x190F7E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_81 Register DESC0_6_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_81 0x37E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_81 0x190F7E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_81 Register DESC1_6_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_81 0x37E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_81 0x190F7E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_81 Register DESC2_6_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_81 0x37E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_81 0x190F7E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_81 Register DESC3_6_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_81 0x37E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_81 0x190F7E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_81 Register DESC0_7_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_81 0x37E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_81 0x190F7E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_81 Register DESC1_7_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_81 0x37E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_81 0x190F7E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_81 Register DESC2_7_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_81 0x37E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_81 0x190F7E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_81_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_81 Register DESC3_7_PON_EGP_S_81 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_81 0x37E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_81 0x190F7E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_81_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_81_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_81_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_81_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_81_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_82 Register CFG_PON_EGP_82 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_82 0x38000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_82 0x190F8000u //! Register Reset Value #define CFG_PON_EGP_82_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_82_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_82_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_82_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_82_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_82_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_82_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_82_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_82_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_82_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_82_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_82 Register IRNCR_PON_EGP_82 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_82 0x38020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_82 0x190F8020u //! Register Reset Value #define IRNCR_PON_EGP_82_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_82_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_82_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_82_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_82_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_82 Register IRNICR_PON_EGP_82 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_82 0x38024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_82 0x190F8024u //! Register Reset Value #define IRNICR_PON_EGP_82_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_82_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_82_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_82 Register IRNEN_PON_EGP_82 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_82 0x38028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_82 0x190F8028u //! Register Reset Value #define IRNEN_PON_EGP_82_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_82_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_82_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_82_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_82_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_82 Register DPTR_PON_EGP_82 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_82 0x38030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_82 0x190F8030u //! Register Reset Value #define DPTR_PON_EGP_82_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_82_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_82_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_82_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_82_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_82_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_82_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_82_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_82_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_82 Register DESC0_0_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_82 0x38100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_82 0x190F8100u //! Register Reset Value #define DESC0_0_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_82 Register DESC1_0_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_82 0x38104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_82 0x190F8104u //! Register Reset Value #define DESC1_0_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_82 Register DESC2_0_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_82 0x38108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_82 0x190F8108u //! Register Reset Value #define DESC2_0_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_82 Register DESC3_0_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_82 0x3810C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_82 0x190F810Cu //! Register Reset Value #define DESC3_0_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_82 Register DESC0_1_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_82 0x38110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_82 0x190F8110u //! Register Reset Value #define DESC0_1_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_82 Register DESC1_1_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_82 0x38114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_82 0x190F8114u //! Register Reset Value #define DESC1_1_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_82 Register DESC2_1_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_82 0x38118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_82 0x190F8118u //! Register Reset Value #define DESC2_1_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_82 Register DESC3_1_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_82 0x3811C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_82 0x190F811Cu //! Register Reset Value #define DESC3_1_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_82 Register DESC0_2_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_82 0x38120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_82 0x190F8120u //! Register Reset Value #define DESC0_2_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_82 Register DESC1_2_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_82 0x38124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_82 0x190F8124u //! Register Reset Value #define DESC1_2_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_82 Register DESC2_2_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_82 0x38128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_82 0x190F8128u //! Register Reset Value #define DESC2_2_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_82 Register DESC3_2_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_82 0x3812C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_82 0x190F812Cu //! Register Reset Value #define DESC3_2_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_82 Register DESC0_3_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_82 0x38130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_82 0x190F8130u //! Register Reset Value #define DESC0_3_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_82 Register DESC1_3_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_82 0x38134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_82 0x190F8134u //! Register Reset Value #define DESC1_3_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_82 Register DESC2_3_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_82 0x38138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_82 0x190F8138u //! Register Reset Value #define DESC2_3_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_82 Register DESC3_3_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_82 0x3813C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_82 0x190F813Cu //! Register Reset Value #define DESC3_3_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_82 Register DESC0_4_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_82 0x38140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_82 0x190F8140u //! Register Reset Value #define DESC0_4_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_82 Register DESC1_4_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_82 0x38144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_82 0x190F8144u //! Register Reset Value #define DESC1_4_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_82 Register DESC2_4_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_82 0x38148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_82 0x190F8148u //! Register Reset Value #define DESC2_4_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_82 Register DESC3_4_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_82 0x3814C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_82 0x190F814Cu //! Register Reset Value #define DESC3_4_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_82 Register DESC0_5_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_82 0x38150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_82 0x190F8150u //! Register Reset Value #define DESC0_5_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_82 Register DESC1_5_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_82 0x38154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_82 0x190F8154u //! Register Reset Value #define DESC1_5_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_82 Register DESC2_5_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_82 0x38158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_82 0x190F8158u //! Register Reset Value #define DESC2_5_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_82 Register DESC3_5_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_82 0x3815C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_82 0x190F815Cu //! Register Reset Value #define DESC3_5_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_82 Register DESC0_6_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_82 0x38160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_82 0x190F8160u //! Register Reset Value #define DESC0_6_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_82 Register DESC1_6_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_82 0x38164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_82 0x190F8164u //! Register Reset Value #define DESC1_6_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_82 Register DESC2_6_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_82 0x38168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_82 0x190F8168u //! Register Reset Value #define DESC2_6_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_82 Register DESC3_6_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_82 0x3816C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_82 0x190F816Cu //! Register Reset Value #define DESC3_6_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_82 Register DESC0_7_PON_EGP_82 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_82 0x38170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_82 0x190F8170u //! Register Reset Value #define DESC0_7_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_82 Register DESC1_7_PON_EGP_82 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_82 0x38174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_82 0x190F8174u //! Register Reset Value #define DESC1_7_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_82 Register DESC2_7_PON_EGP_82 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_82 0x38178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_82 0x190F8178u //! Register Reset Value #define DESC2_7_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_82 Register DESC3_7_PON_EGP_82 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_82 0x3817C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_82 0x190F817Cu //! Register Reset Value #define DESC3_7_PON_EGP_82_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_82_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_82_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_82 Register DESC0_0_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_82 0x38200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_82 0x190F8200u //! Register Reset Value #define DESC0_0_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_82 Register DESC1_0_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_82 0x38204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_82 0x190F8204u //! Register Reset Value #define DESC1_0_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_82 Register DESC2_0_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_82 0x38208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_82 0x190F8208u //! Register Reset Value #define DESC2_0_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_82 Register DESC3_0_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_82 0x3820C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_82 0x190F820Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_82 Register DESC0_1_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_82 0x38210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_82 0x190F8210u //! Register Reset Value #define DESC0_1_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_82 Register DESC1_1_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_82 0x38214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_82 0x190F8214u //! Register Reset Value #define DESC1_1_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_82 Register DESC2_1_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_82 0x38218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_82 0x190F8218u //! Register Reset Value #define DESC2_1_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_82 Register DESC3_1_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_82 0x3821C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_82 0x190F821Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_82 Register DESC0_2_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_82 0x38220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_82 0x190F8220u //! Register Reset Value #define DESC0_2_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_82 Register DESC1_2_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_82 0x38224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_82 0x190F8224u //! Register Reset Value #define DESC1_2_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_82 Register DESC2_2_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_82 0x38228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_82 0x190F8228u //! Register Reset Value #define DESC2_2_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_82 Register DESC3_2_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_82 0x3822C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_82 0x190F822Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_82 Register DESC0_3_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_82 0x38230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_82 0x190F8230u //! Register Reset Value #define DESC0_3_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_82 Register DESC1_3_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_82 0x38234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_82 0x190F8234u //! Register Reset Value #define DESC1_3_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_82 Register DESC2_3_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_82 0x38238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_82 0x190F8238u //! Register Reset Value #define DESC2_3_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_82 Register DESC3_3_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_82 0x3823C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_82 0x190F823Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_82 Register DESC0_4_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_82 0x38240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_82 0x190F8240u //! Register Reset Value #define DESC0_4_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_82 Register DESC1_4_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_82 0x38244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_82 0x190F8244u //! Register Reset Value #define DESC1_4_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_82 Register DESC2_4_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_82 0x38248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_82 0x190F8248u //! Register Reset Value #define DESC2_4_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_82 Register DESC3_4_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_82 0x3824C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_82 0x190F824Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_82 Register DESC0_5_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_82 0x38250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_82 0x190F8250u //! Register Reset Value #define DESC0_5_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_82 Register DESC1_5_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_82 0x38254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_82 0x190F8254u //! Register Reset Value #define DESC1_5_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_82 Register DESC2_5_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_82 0x38258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_82 0x190F8258u //! Register Reset Value #define DESC2_5_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_82 Register DESC3_5_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_82 0x3825C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_82 0x190F825Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_82 Register DESC0_6_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_82 0x38260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_82 0x190F8260u //! Register Reset Value #define DESC0_6_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_82 Register DESC1_6_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_82 0x38264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_82 0x190F8264u //! Register Reset Value #define DESC1_6_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_82 Register DESC2_6_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_82 0x38268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_82 0x190F8268u //! Register Reset Value #define DESC2_6_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_82 Register DESC3_6_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_82 0x3826C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_82 0x190F826Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_82 Register DESC0_7_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_82 0x38270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_82 0x190F8270u //! Register Reset Value #define DESC0_7_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_82 Register DESC1_7_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_82 0x38274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_82 0x190F8274u //! Register Reset Value #define DESC1_7_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_82 Register DESC2_7_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_82 0x38278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_82 0x190F8278u //! Register Reset Value #define DESC2_7_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_82_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_82 Register DESC3_7_PON_EGP_S_82 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_82 0x3827C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_82 0x190F827Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_82_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_82_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_82_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_82_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_82_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_83 Register CFG_PON_EGP_83 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_83 0x38400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_83 0x190F8400u //! Register Reset Value #define CFG_PON_EGP_83_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_83_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_83_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_83_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_83_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_83_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_83_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_83_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_83_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_83_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_83_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_83 Register IRNCR_PON_EGP_83 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_83 0x38420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_83 0x190F8420u //! Register Reset Value #define IRNCR_PON_EGP_83_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_83_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_83_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_83_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_83_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_83 Register IRNICR_PON_EGP_83 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_83 0x38424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_83 0x190F8424u //! Register Reset Value #define IRNICR_PON_EGP_83_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_83_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_83_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_83 Register IRNEN_PON_EGP_83 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_83 0x38428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_83 0x190F8428u //! Register Reset Value #define IRNEN_PON_EGP_83_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_83_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_83_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_83_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_83_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_83 Register DPTR_PON_EGP_83 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_83 0x38430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_83 0x190F8430u //! Register Reset Value #define DPTR_PON_EGP_83_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_83_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_83_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_83_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_83_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_83_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_83_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_83_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_83_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_83 Register DESC0_0_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_83 0x38500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_83 0x190F8500u //! Register Reset Value #define DESC0_0_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_83 Register DESC1_0_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_83 0x38504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_83 0x190F8504u //! Register Reset Value #define DESC1_0_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_83 Register DESC2_0_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_83 0x38508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_83 0x190F8508u //! Register Reset Value #define DESC2_0_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_83 Register DESC3_0_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_83 0x3850C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_83 0x190F850Cu //! Register Reset Value #define DESC3_0_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_83 Register DESC0_1_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_83 0x38510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_83 0x190F8510u //! Register Reset Value #define DESC0_1_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_83 Register DESC1_1_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_83 0x38514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_83 0x190F8514u //! Register Reset Value #define DESC1_1_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_83 Register DESC2_1_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_83 0x38518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_83 0x190F8518u //! Register Reset Value #define DESC2_1_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_83 Register DESC3_1_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_83 0x3851C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_83 0x190F851Cu //! Register Reset Value #define DESC3_1_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_83 Register DESC0_2_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_83 0x38520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_83 0x190F8520u //! Register Reset Value #define DESC0_2_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_83 Register DESC1_2_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_83 0x38524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_83 0x190F8524u //! Register Reset Value #define DESC1_2_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_83 Register DESC2_2_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_83 0x38528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_83 0x190F8528u //! Register Reset Value #define DESC2_2_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_83 Register DESC3_2_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_83 0x3852C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_83 0x190F852Cu //! Register Reset Value #define DESC3_2_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_83 Register DESC0_3_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_83 0x38530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_83 0x190F8530u //! Register Reset Value #define DESC0_3_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_83 Register DESC1_3_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_83 0x38534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_83 0x190F8534u //! Register Reset Value #define DESC1_3_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_83 Register DESC2_3_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_83 0x38538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_83 0x190F8538u //! Register Reset Value #define DESC2_3_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_83 Register DESC3_3_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_83 0x3853C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_83 0x190F853Cu //! Register Reset Value #define DESC3_3_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_83 Register DESC0_4_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_83 0x38540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_83 0x190F8540u //! Register Reset Value #define DESC0_4_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_83 Register DESC1_4_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_83 0x38544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_83 0x190F8544u //! Register Reset Value #define DESC1_4_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_83 Register DESC2_4_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_83 0x38548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_83 0x190F8548u //! Register Reset Value #define DESC2_4_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_83 Register DESC3_4_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_83 0x3854C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_83 0x190F854Cu //! Register Reset Value #define DESC3_4_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_83 Register DESC0_5_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_83 0x38550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_83 0x190F8550u //! Register Reset Value #define DESC0_5_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_83 Register DESC1_5_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_83 0x38554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_83 0x190F8554u //! Register Reset Value #define DESC1_5_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_83 Register DESC2_5_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_83 0x38558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_83 0x190F8558u //! Register Reset Value #define DESC2_5_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_83 Register DESC3_5_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_83 0x3855C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_83 0x190F855Cu //! Register Reset Value #define DESC3_5_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_83 Register DESC0_6_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_83 0x38560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_83 0x190F8560u //! Register Reset Value #define DESC0_6_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_83 Register DESC1_6_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_83 0x38564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_83 0x190F8564u //! Register Reset Value #define DESC1_6_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_83 Register DESC2_6_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_83 0x38568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_83 0x190F8568u //! Register Reset Value #define DESC2_6_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_83 Register DESC3_6_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_83 0x3856C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_83 0x190F856Cu //! Register Reset Value #define DESC3_6_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_83 Register DESC0_7_PON_EGP_83 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_83 0x38570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_83 0x190F8570u //! Register Reset Value #define DESC0_7_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_83 Register DESC1_7_PON_EGP_83 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_83 0x38574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_83 0x190F8574u //! Register Reset Value #define DESC1_7_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_83 Register DESC2_7_PON_EGP_83 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_83 0x38578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_83 0x190F8578u //! Register Reset Value #define DESC2_7_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_83 Register DESC3_7_PON_EGP_83 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_83 0x3857C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_83 0x190F857Cu //! Register Reset Value #define DESC3_7_PON_EGP_83_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_83_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_83_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_83 Register DESC0_0_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_83 0x38600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_83 0x190F8600u //! Register Reset Value #define DESC0_0_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_83 Register DESC1_0_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_83 0x38604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_83 0x190F8604u //! Register Reset Value #define DESC1_0_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_83 Register DESC2_0_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_83 0x38608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_83 0x190F8608u //! Register Reset Value #define DESC2_0_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_83 Register DESC3_0_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_83 0x3860C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_83 0x190F860Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_83 Register DESC0_1_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_83 0x38610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_83 0x190F8610u //! Register Reset Value #define DESC0_1_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_83 Register DESC1_1_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_83 0x38614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_83 0x190F8614u //! Register Reset Value #define DESC1_1_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_83 Register DESC2_1_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_83 0x38618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_83 0x190F8618u //! Register Reset Value #define DESC2_1_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_83 Register DESC3_1_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_83 0x3861C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_83 0x190F861Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_83 Register DESC0_2_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_83 0x38620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_83 0x190F8620u //! Register Reset Value #define DESC0_2_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_83 Register DESC1_2_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_83 0x38624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_83 0x190F8624u //! Register Reset Value #define DESC1_2_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_83 Register DESC2_2_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_83 0x38628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_83 0x190F8628u //! Register Reset Value #define DESC2_2_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_83 Register DESC3_2_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_83 0x3862C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_83 0x190F862Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_83 Register DESC0_3_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_83 0x38630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_83 0x190F8630u //! Register Reset Value #define DESC0_3_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_83 Register DESC1_3_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_83 0x38634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_83 0x190F8634u //! Register Reset Value #define DESC1_3_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_83 Register DESC2_3_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_83 0x38638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_83 0x190F8638u //! Register Reset Value #define DESC2_3_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_83 Register DESC3_3_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_83 0x3863C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_83 0x190F863Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_83 Register DESC0_4_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_83 0x38640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_83 0x190F8640u //! Register Reset Value #define DESC0_4_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_83 Register DESC1_4_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_83 0x38644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_83 0x190F8644u //! Register Reset Value #define DESC1_4_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_83 Register DESC2_4_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_83 0x38648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_83 0x190F8648u //! Register Reset Value #define DESC2_4_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_83 Register DESC3_4_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_83 0x3864C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_83 0x190F864Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_83 Register DESC0_5_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_83 0x38650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_83 0x190F8650u //! Register Reset Value #define DESC0_5_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_83 Register DESC1_5_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_83 0x38654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_83 0x190F8654u //! Register Reset Value #define DESC1_5_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_83 Register DESC2_5_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_83 0x38658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_83 0x190F8658u //! Register Reset Value #define DESC2_5_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_83 Register DESC3_5_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_83 0x3865C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_83 0x190F865Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_83 Register DESC0_6_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_83 0x38660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_83 0x190F8660u //! Register Reset Value #define DESC0_6_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_83 Register DESC1_6_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_83 0x38664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_83 0x190F8664u //! Register Reset Value #define DESC1_6_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_83 Register DESC2_6_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_83 0x38668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_83 0x190F8668u //! Register Reset Value #define DESC2_6_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_83 Register DESC3_6_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_83 0x3866C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_83 0x190F866Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_83 Register DESC0_7_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_83 0x38670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_83 0x190F8670u //! Register Reset Value #define DESC0_7_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_83 Register DESC1_7_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_83 0x38674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_83 0x190F8674u //! Register Reset Value #define DESC1_7_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_83 Register DESC2_7_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_83 0x38678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_83 0x190F8678u //! Register Reset Value #define DESC2_7_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_83_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_83 Register DESC3_7_PON_EGP_S_83 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_83 0x3867C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_83 0x190F867Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_83_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_83_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_83_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_83_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_83_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_84 Register CFG_PON_EGP_84 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_84 0x38800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_84 0x190F8800u //! Register Reset Value #define CFG_PON_EGP_84_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_84_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_84_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_84_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_84_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_84_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_84_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_84_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_84_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_84_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_84_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_84 Register IRNCR_PON_EGP_84 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_84 0x38820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_84 0x190F8820u //! Register Reset Value #define IRNCR_PON_EGP_84_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_84_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_84_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_84_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_84_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_84 Register IRNICR_PON_EGP_84 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_84 0x38824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_84 0x190F8824u //! Register Reset Value #define IRNICR_PON_EGP_84_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_84_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_84_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_84 Register IRNEN_PON_EGP_84 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_84 0x38828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_84 0x190F8828u //! Register Reset Value #define IRNEN_PON_EGP_84_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_84_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_84_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_84_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_84_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_84 Register DPTR_PON_EGP_84 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_84 0x38830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_84 0x190F8830u //! Register Reset Value #define DPTR_PON_EGP_84_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_84_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_84_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_84_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_84_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_84_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_84_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_84_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_84_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_84 Register DESC0_0_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_84 0x38900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_84 0x190F8900u //! Register Reset Value #define DESC0_0_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_84 Register DESC1_0_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_84 0x38904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_84 0x190F8904u //! Register Reset Value #define DESC1_0_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_84 Register DESC2_0_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_84 0x38908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_84 0x190F8908u //! Register Reset Value #define DESC2_0_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_84 Register DESC3_0_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_84 0x3890C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_84 0x190F890Cu //! Register Reset Value #define DESC3_0_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_84 Register DESC0_1_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_84 0x38910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_84 0x190F8910u //! Register Reset Value #define DESC0_1_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_84 Register DESC1_1_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_84 0x38914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_84 0x190F8914u //! Register Reset Value #define DESC1_1_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_84 Register DESC2_1_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_84 0x38918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_84 0x190F8918u //! Register Reset Value #define DESC2_1_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_84 Register DESC3_1_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_84 0x3891C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_84 0x190F891Cu //! Register Reset Value #define DESC3_1_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_84 Register DESC0_2_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_84 0x38920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_84 0x190F8920u //! Register Reset Value #define DESC0_2_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_84 Register DESC1_2_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_84 0x38924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_84 0x190F8924u //! Register Reset Value #define DESC1_2_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_84 Register DESC2_2_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_84 0x38928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_84 0x190F8928u //! Register Reset Value #define DESC2_2_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_84 Register DESC3_2_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_84 0x3892C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_84 0x190F892Cu //! Register Reset Value #define DESC3_2_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_84 Register DESC0_3_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_84 0x38930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_84 0x190F8930u //! Register Reset Value #define DESC0_3_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_84 Register DESC1_3_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_84 0x38934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_84 0x190F8934u //! Register Reset Value #define DESC1_3_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_84 Register DESC2_3_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_84 0x38938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_84 0x190F8938u //! Register Reset Value #define DESC2_3_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_84 Register DESC3_3_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_84 0x3893C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_84 0x190F893Cu //! Register Reset Value #define DESC3_3_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_84 Register DESC0_4_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_84 0x38940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_84 0x190F8940u //! Register Reset Value #define DESC0_4_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_84 Register DESC1_4_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_84 0x38944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_84 0x190F8944u //! Register Reset Value #define DESC1_4_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_84 Register DESC2_4_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_84 0x38948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_84 0x190F8948u //! Register Reset Value #define DESC2_4_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_84 Register DESC3_4_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_84 0x3894C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_84 0x190F894Cu //! Register Reset Value #define DESC3_4_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_84 Register DESC0_5_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_84 0x38950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_84 0x190F8950u //! Register Reset Value #define DESC0_5_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_84 Register DESC1_5_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_84 0x38954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_84 0x190F8954u //! Register Reset Value #define DESC1_5_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_84 Register DESC2_5_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_84 0x38958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_84 0x190F8958u //! Register Reset Value #define DESC2_5_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_84 Register DESC3_5_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_84 0x3895C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_84 0x190F895Cu //! Register Reset Value #define DESC3_5_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_84 Register DESC0_6_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_84 0x38960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_84 0x190F8960u //! Register Reset Value #define DESC0_6_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_84 Register DESC1_6_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_84 0x38964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_84 0x190F8964u //! Register Reset Value #define DESC1_6_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_84 Register DESC2_6_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_84 0x38968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_84 0x190F8968u //! Register Reset Value #define DESC2_6_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_84 Register DESC3_6_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_84 0x3896C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_84 0x190F896Cu //! Register Reset Value #define DESC3_6_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_84 Register DESC0_7_PON_EGP_84 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_84 0x38970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_84 0x190F8970u //! Register Reset Value #define DESC0_7_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_84 Register DESC1_7_PON_EGP_84 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_84 0x38974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_84 0x190F8974u //! Register Reset Value #define DESC1_7_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_84 Register DESC2_7_PON_EGP_84 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_84 0x38978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_84 0x190F8978u //! Register Reset Value #define DESC2_7_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_84 Register DESC3_7_PON_EGP_84 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_84 0x3897C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_84 0x190F897Cu //! Register Reset Value #define DESC3_7_PON_EGP_84_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_84_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_84_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_84 Register DESC0_0_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_84 0x38A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_84 0x190F8A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_84 Register DESC1_0_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_84 0x38A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_84 0x190F8A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_84 Register DESC2_0_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_84 0x38A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_84 0x190F8A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_84 Register DESC3_0_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_84 0x38A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_84 0x190F8A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_84 Register DESC0_1_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_84 0x38A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_84 0x190F8A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_84 Register DESC1_1_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_84 0x38A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_84 0x190F8A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_84 Register DESC2_1_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_84 0x38A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_84 0x190F8A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_84 Register DESC3_1_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_84 0x38A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_84 0x190F8A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_84 Register DESC0_2_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_84 0x38A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_84 0x190F8A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_84 Register DESC1_2_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_84 0x38A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_84 0x190F8A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_84 Register DESC2_2_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_84 0x38A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_84 0x190F8A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_84 Register DESC3_2_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_84 0x38A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_84 0x190F8A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_84 Register DESC0_3_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_84 0x38A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_84 0x190F8A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_84 Register DESC1_3_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_84 0x38A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_84 0x190F8A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_84 Register DESC2_3_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_84 0x38A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_84 0x190F8A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_84 Register DESC3_3_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_84 0x38A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_84 0x190F8A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_84 Register DESC0_4_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_84 0x38A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_84 0x190F8A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_84 Register DESC1_4_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_84 0x38A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_84 0x190F8A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_84 Register DESC2_4_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_84 0x38A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_84 0x190F8A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_84 Register DESC3_4_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_84 0x38A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_84 0x190F8A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_84 Register DESC0_5_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_84 0x38A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_84 0x190F8A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_84 Register DESC1_5_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_84 0x38A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_84 0x190F8A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_84 Register DESC2_5_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_84 0x38A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_84 0x190F8A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_84 Register DESC3_5_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_84 0x38A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_84 0x190F8A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_84 Register DESC0_6_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_84 0x38A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_84 0x190F8A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_84 Register DESC1_6_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_84 0x38A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_84 0x190F8A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_84 Register DESC2_6_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_84 0x38A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_84 0x190F8A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_84 Register DESC3_6_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_84 0x38A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_84 0x190F8A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_84 Register DESC0_7_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_84 0x38A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_84 0x190F8A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_84 Register DESC1_7_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_84 0x38A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_84 0x190F8A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_84 Register DESC2_7_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_84 0x38A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_84 0x190F8A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_84_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_84 Register DESC3_7_PON_EGP_S_84 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_84 0x38A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_84 0x190F8A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_84_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_84_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_84_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_84_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_84_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_85 Register CFG_PON_EGP_85 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_85 0x38C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_85 0x190F8C00u //! Register Reset Value #define CFG_PON_EGP_85_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_85_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_85_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_85_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_85_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_85_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_85_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_85_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_85_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_85_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_85_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_85 Register IRNCR_PON_EGP_85 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_85 0x38C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_85 0x190F8C20u //! Register Reset Value #define IRNCR_PON_EGP_85_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_85_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_85_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_85_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_85_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_85 Register IRNICR_PON_EGP_85 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_85 0x38C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_85 0x190F8C24u //! Register Reset Value #define IRNICR_PON_EGP_85_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_85_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_85_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_85 Register IRNEN_PON_EGP_85 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_85 0x38C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_85 0x190F8C28u //! Register Reset Value #define IRNEN_PON_EGP_85_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_85_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_85_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_85_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_85_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_85 Register DPTR_PON_EGP_85 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_85 0x38C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_85 0x190F8C30u //! Register Reset Value #define DPTR_PON_EGP_85_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_85_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_85_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_85_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_85_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_85_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_85_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_85_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_85_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_85 Register DESC0_0_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_85 0x38D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_85 0x190F8D00u //! Register Reset Value #define DESC0_0_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_85 Register DESC1_0_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_85 0x38D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_85 0x190F8D04u //! Register Reset Value #define DESC1_0_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_85 Register DESC2_0_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_85 0x38D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_85 0x190F8D08u //! Register Reset Value #define DESC2_0_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_85 Register DESC3_0_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_85 0x38D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_85 0x190F8D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_85 Register DESC0_1_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_85 0x38D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_85 0x190F8D10u //! Register Reset Value #define DESC0_1_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_85 Register DESC1_1_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_85 0x38D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_85 0x190F8D14u //! Register Reset Value #define DESC1_1_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_85 Register DESC2_1_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_85 0x38D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_85 0x190F8D18u //! Register Reset Value #define DESC2_1_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_85 Register DESC3_1_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_85 0x38D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_85 0x190F8D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_85 Register DESC0_2_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_85 0x38D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_85 0x190F8D20u //! Register Reset Value #define DESC0_2_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_85 Register DESC1_2_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_85 0x38D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_85 0x190F8D24u //! Register Reset Value #define DESC1_2_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_85 Register DESC2_2_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_85 0x38D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_85 0x190F8D28u //! Register Reset Value #define DESC2_2_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_85 Register DESC3_2_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_85 0x38D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_85 0x190F8D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_85 Register DESC0_3_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_85 0x38D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_85 0x190F8D30u //! Register Reset Value #define DESC0_3_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_85 Register DESC1_3_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_85 0x38D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_85 0x190F8D34u //! Register Reset Value #define DESC1_3_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_85 Register DESC2_3_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_85 0x38D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_85 0x190F8D38u //! Register Reset Value #define DESC2_3_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_85 Register DESC3_3_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_85 0x38D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_85 0x190F8D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_85 Register DESC0_4_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_85 0x38D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_85 0x190F8D40u //! Register Reset Value #define DESC0_4_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_85 Register DESC1_4_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_85 0x38D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_85 0x190F8D44u //! Register Reset Value #define DESC1_4_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_85 Register DESC2_4_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_85 0x38D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_85 0x190F8D48u //! Register Reset Value #define DESC2_4_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_85 Register DESC3_4_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_85 0x38D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_85 0x190F8D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_85 Register DESC0_5_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_85 0x38D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_85 0x190F8D50u //! Register Reset Value #define DESC0_5_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_85 Register DESC1_5_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_85 0x38D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_85 0x190F8D54u //! Register Reset Value #define DESC1_5_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_85 Register DESC2_5_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_85 0x38D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_85 0x190F8D58u //! Register Reset Value #define DESC2_5_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_85 Register DESC3_5_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_85 0x38D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_85 0x190F8D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_85 Register DESC0_6_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_85 0x38D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_85 0x190F8D60u //! Register Reset Value #define DESC0_6_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_85 Register DESC1_6_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_85 0x38D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_85 0x190F8D64u //! Register Reset Value #define DESC1_6_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_85 Register DESC2_6_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_85 0x38D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_85 0x190F8D68u //! Register Reset Value #define DESC2_6_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_85 Register DESC3_6_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_85 0x38D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_85 0x190F8D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_85 Register DESC0_7_PON_EGP_85 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_85 0x38D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_85 0x190F8D70u //! Register Reset Value #define DESC0_7_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_85 Register DESC1_7_PON_EGP_85 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_85 0x38D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_85 0x190F8D74u //! Register Reset Value #define DESC1_7_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_85 Register DESC2_7_PON_EGP_85 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_85 0x38D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_85 0x190F8D78u //! Register Reset Value #define DESC2_7_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_85 Register DESC3_7_PON_EGP_85 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_85 0x38D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_85 0x190F8D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_85_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_85_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_85_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_85 Register DESC0_0_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_85 0x38E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_85 0x190F8E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_85 Register DESC1_0_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_85 0x38E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_85 0x190F8E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_85 Register DESC2_0_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_85 0x38E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_85 0x190F8E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_85 Register DESC3_0_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_85 0x38E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_85 0x190F8E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_85 Register DESC0_1_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_85 0x38E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_85 0x190F8E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_85 Register DESC1_1_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_85 0x38E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_85 0x190F8E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_85 Register DESC2_1_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_85 0x38E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_85 0x190F8E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_85 Register DESC3_1_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_85 0x38E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_85 0x190F8E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_85 Register DESC0_2_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_85 0x38E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_85 0x190F8E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_85 Register DESC1_2_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_85 0x38E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_85 0x190F8E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_85 Register DESC2_2_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_85 0x38E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_85 0x190F8E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_85 Register DESC3_2_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_85 0x38E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_85 0x190F8E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_85 Register DESC0_3_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_85 0x38E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_85 0x190F8E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_85 Register DESC1_3_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_85 0x38E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_85 0x190F8E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_85 Register DESC2_3_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_85 0x38E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_85 0x190F8E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_85 Register DESC3_3_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_85 0x38E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_85 0x190F8E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_85 Register DESC0_4_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_85 0x38E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_85 0x190F8E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_85 Register DESC1_4_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_85 0x38E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_85 0x190F8E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_85 Register DESC2_4_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_85 0x38E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_85 0x190F8E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_85 Register DESC3_4_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_85 0x38E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_85 0x190F8E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_85 Register DESC0_5_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_85 0x38E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_85 0x190F8E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_85 Register DESC1_5_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_85 0x38E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_85 0x190F8E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_85 Register DESC2_5_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_85 0x38E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_85 0x190F8E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_85 Register DESC3_5_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_85 0x38E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_85 0x190F8E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_85 Register DESC0_6_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_85 0x38E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_85 0x190F8E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_85 Register DESC1_6_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_85 0x38E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_85 0x190F8E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_85 Register DESC2_6_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_85 0x38E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_85 0x190F8E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_85 Register DESC3_6_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_85 0x38E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_85 0x190F8E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_85 Register DESC0_7_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_85 0x38E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_85 0x190F8E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_85 Register DESC1_7_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_85 0x38E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_85 0x190F8E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_85 Register DESC2_7_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_85 0x38E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_85 0x190F8E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_85_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_85 Register DESC3_7_PON_EGP_S_85 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_85 0x38E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_85 0x190F8E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_85_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_85_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_85_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_85_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_85_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_86 Register CFG_PON_EGP_86 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_86 0x39000 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_86 0x190F9000u //! Register Reset Value #define CFG_PON_EGP_86_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_86_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_86_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_86_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_86_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_86_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_86_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_86_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_86_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_86_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_86_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_86 Register IRNCR_PON_EGP_86 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_86 0x39020 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_86 0x190F9020u //! Register Reset Value #define IRNCR_PON_EGP_86_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_86_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_86_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_86_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_86_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_86 Register IRNICR_PON_EGP_86 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_86 0x39024 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_86 0x190F9024u //! Register Reset Value #define IRNICR_PON_EGP_86_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_86_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_86_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_86 Register IRNEN_PON_EGP_86 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_86 0x39028 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_86 0x190F9028u //! Register Reset Value #define IRNEN_PON_EGP_86_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_86_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_86_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_86_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_86_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_86 Register DPTR_PON_EGP_86 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_86 0x39030 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_86 0x190F9030u //! Register Reset Value #define DPTR_PON_EGP_86_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_86_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_86_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_86_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_86_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_86_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_86_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_86_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_86_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_86 Register DESC0_0_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_86 0x39100 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_86 0x190F9100u //! Register Reset Value #define DESC0_0_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_86 Register DESC1_0_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_86 0x39104 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_86 0x190F9104u //! Register Reset Value #define DESC1_0_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_86 Register DESC2_0_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_86 0x39108 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_86 0x190F9108u //! Register Reset Value #define DESC2_0_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_86 Register DESC3_0_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_86 0x3910C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_86 0x190F910Cu //! Register Reset Value #define DESC3_0_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_86 Register DESC0_1_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_86 0x39110 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_86 0x190F9110u //! Register Reset Value #define DESC0_1_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_86 Register DESC1_1_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_86 0x39114 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_86 0x190F9114u //! Register Reset Value #define DESC1_1_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_86 Register DESC2_1_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_86 0x39118 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_86 0x190F9118u //! Register Reset Value #define DESC2_1_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_86 Register DESC3_1_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_86 0x3911C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_86 0x190F911Cu //! Register Reset Value #define DESC3_1_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_86 Register DESC0_2_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_86 0x39120 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_86 0x190F9120u //! Register Reset Value #define DESC0_2_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_86 Register DESC1_2_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_86 0x39124 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_86 0x190F9124u //! Register Reset Value #define DESC1_2_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_86 Register DESC2_2_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_86 0x39128 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_86 0x190F9128u //! Register Reset Value #define DESC2_2_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_86 Register DESC3_2_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_86 0x3912C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_86 0x190F912Cu //! Register Reset Value #define DESC3_2_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_86 Register DESC0_3_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_86 0x39130 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_86 0x190F9130u //! Register Reset Value #define DESC0_3_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_86 Register DESC1_3_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_86 0x39134 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_86 0x190F9134u //! Register Reset Value #define DESC1_3_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_86 Register DESC2_3_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_86 0x39138 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_86 0x190F9138u //! Register Reset Value #define DESC2_3_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_86 Register DESC3_3_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_86 0x3913C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_86 0x190F913Cu //! Register Reset Value #define DESC3_3_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_86 Register DESC0_4_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_86 0x39140 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_86 0x190F9140u //! Register Reset Value #define DESC0_4_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_86 Register DESC1_4_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_86 0x39144 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_86 0x190F9144u //! Register Reset Value #define DESC1_4_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_86 Register DESC2_4_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_86 0x39148 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_86 0x190F9148u //! Register Reset Value #define DESC2_4_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_86 Register DESC3_4_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_86 0x3914C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_86 0x190F914Cu //! Register Reset Value #define DESC3_4_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_86 Register DESC0_5_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_86 0x39150 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_86 0x190F9150u //! Register Reset Value #define DESC0_5_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_86 Register DESC1_5_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_86 0x39154 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_86 0x190F9154u //! Register Reset Value #define DESC1_5_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_86 Register DESC2_5_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_86 0x39158 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_86 0x190F9158u //! Register Reset Value #define DESC2_5_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_86 Register DESC3_5_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_86 0x3915C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_86 0x190F915Cu //! Register Reset Value #define DESC3_5_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_86 Register DESC0_6_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_86 0x39160 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_86 0x190F9160u //! Register Reset Value #define DESC0_6_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_86 Register DESC1_6_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_86 0x39164 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_86 0x190F9164u //! Register Reset Value #define DESC1_6_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_86 Register DESC2_6_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_86 0x39168 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_86 0x190F9168u //! Register Reset Value #define DESC2_6_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_86 Register DESC3_6_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_86 0x3916C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_86 0x190F916Cu //! Register Reset Value #define DESC3_6_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_86 Register DESC0_7_PON_EGP_86 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_86 0x39170 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_86 0x190F9170u //! Register Reset Value #define DESC0_7_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_86 Register DESC1_7_PON_EGP_86 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_86 0x39174 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_86 0x190F9174u //! Register Reset Value #define DESC1_7_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_86 Register DESC2_7_PON_EGP_86 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_86 0x39178 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_86 0x190F9178u //! Register Reset Value #define DESC2_7_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_86 Register DESC3_7_PON_EGP_86 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_86 0x3917C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_86 0x190F917Cu //! Register Reset Value #define DESC3_7_PON_EGP_86_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_86_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_86_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_86 Register DESC0_0_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_86 0x39200 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_86 0x190F9200u //! Register Reset Value #define DESC0_0_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_86 Register DESC1_0_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_86 0x39204 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_86 0x190F9204u //! Register Reset Value #define DESC1_0_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_86 Register DESC2_0_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_86 0x39208 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_86 0x190F9208u //! Register Reset Value #define DESC2_0_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_86 Register DESC3_0_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_86 0x3920C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_86 0x190F920Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_86 Register DESC0_1_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_86 0x39210 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_86 0x190F9210u //! Register Reset Value #define DESC0_1_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_86 Register DESC1_1_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_86 0x39214 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_86 0x190F9214u //! Register Reset Value #define DESC1_1_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_86 Register DESC2_1_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_86 0x39218 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_86 0x190F9218u //! Register Reset Value #define DESC2_1_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_86 Register DESC3_1_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_86 0x3921C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_86 0x190F921Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_86 Register DESC0_2_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_86 0x39220 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_86 0x190F9220u //! Register Reset Value #define DESC0_2_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_86 Register DESC1_2_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_86 0x39224 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_86 0x190F9224u //! Register Reset Value #define DESC1_2_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_86 Register DESC2_2_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_86 0x39228 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_86 0x190F9228u //! Register Reset Value #define DESC2_2_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_86 Register DESC3_2_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_86 0x3922C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_86 0x190F922Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_86 Register DESC0_3_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_86 0x39230 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_86 0x190F9230u //! Register Reset Value #define DESC0_3_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_86 Register DESC1_3_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_86 0x39234 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_86 0x190F9234u //! Register Reset Value #define DESC1_3_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_86 Register DESC2_3_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_86 0x39238 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_86 0x190F9238u //! Register Reset Value #define DESC2_3_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_86 Register DESC3_3_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_86 0x3923C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_86 0x190F923Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_86 Register DESC0_4_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_86 0x39240 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_86 0x190F9240u //! Register Reset Value #define DESC0_4_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_86 Register DESC1_4_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_86 0x39244 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_86 0x190F9244u //! Register Reset Value #define DESC1_4_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_86 Register DESC2_4_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_86 0x39248 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_86 0x190F9248u //! Register Reset Value #define DESC2_4_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_86 Register DESC3_4_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_86 0x3924C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_86 0x190F924Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_86 Register DESC0_5_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_86 0x39250 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_86 0x190F9250u //! Register Reset Value #define DESC0_5_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_86 Register DESC1_5_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_86 0x39254 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_86 0x190F9254u //! Register Reset Value #define DESC1_5_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_86 Register DESC2_5_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_86 0x39258 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_86 0x190F9258u //! Register Reset Value #define DESC2_5_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_86 Register DESC3_5_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_86 0x3925C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_86 0x190F925Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_86 Register DESC0_6_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_86 0x39260 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_86 0x190F9260u //! Register Reset Value #define DESC0_6_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_86 Register DESC1_6_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_86 0x39264 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_86 0x190F9264u //! Register Reset Value #define DESC1_6_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_86 Register DESC2_6_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_86 0x39268 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_86 0x190F9268u //! Register Reset Value #define DESC2_6_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_86 Register DESC3_6_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_86 0x3926C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_86 0x190F926Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_86 Register DESC0_7_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_86 0x39270 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_86 0x190F9270u //! Register Reset Value #define DESC0_7_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_86 Register DESC1_7_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_86 0x39274 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_86 0x190F9274u //! Register Reset Value #define DESC1_7_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_86 Register DESC2_7_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_86 0x39278 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_86 0x190F9278u //! Register Reset Value #define DESC2_7_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_86_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_86 Register DESC3_7_PON_EGP_S_86 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_86 0x3927C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_86 0x190F927Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_86_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_86_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_86_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_86_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_86_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_87 Register CFG_PON_EGP_87 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_87 0x39400 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_87 0x190F9400u //! Register Reset Value #define CFG_PON_EGP_87_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_87_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_87_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_87_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_87_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_87_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_87_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_87_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_87_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_87_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_87_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_87 Register IRNCR_PON_EGP_87 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_87 0x39420 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_87 0x190F9420u //! Register Reset Value #define IRNCR_PON_EGP_87_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_87_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_87_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_87_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_87_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_87 Register IRNICR_PON_EGP_87 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_87 0x39424 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_87 0x190F9424u //! Register Reset Value #define IRNICR_PON_EGP_87_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_87_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_87_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_87 Register IRNEN_PON_EGP_87 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_87 0x39428 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_87 0x190F9428u //! Register Reset Value #define IRNEN_PON_EGP_87_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_87_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_87_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_87_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_87_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_87 Register DPTR_PON_EGP_87 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_87 0x39430 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_87 0x190F9430u //! Register Reset Value #define DPTR_PON_EGP_87_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_87_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_87_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_87_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_87_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_87_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_87_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_87_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_87_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_87 Register DESC0_0_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_87 0x39500 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_87 0x190F9500u //! Register Reset Value #define DESC0_0_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_87 Register DESC1_0_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_87 0x39504 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_87 0x190F9504u //! Register Reset Value #define DESC1_0_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_87 Register DESC2_0_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_87 0x39508 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_87 0x190F9508u //! Register Reset Value #define DESC2_0_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_87 Register DESC3_0_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_87 0x3950C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_87 0x190F950Cu //! Register Reset Value #define DESC3_0_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_87 Register DESC0_1_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_87 0x39510 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_87 0x190F9510u //! Register Reset Value #define DESC0_1_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_87 Register DESC1_1_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_87 0x39514 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_87 0x190F9514u //! Register Reset Value #define DESC1_1_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_87 Register DESC2_1_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_87 0x39518 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_87 0x190F9518u //! Register Reset Value #define DESC2_1_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_87 Register DESC3_1_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_87 0x3951C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_87 0x190F951Cu //! Register Reset Value #define DESC3_1_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_87 Register DESC0_2_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_87 0x39520 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_87 0x190F9520u //! Register Reset Value #define DESC0_2_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_87 Register DESC1_2_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_87 0x39524 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_87 0x190F9524u //! Register Reset Value #define DESC1_2_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_87 Register DESC2_2_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_87 0x39528 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_87 0x190F9528u //! Register Reset Value #define DESC2_2_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_87 Register DESC3_2_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_87 0x3952C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_87 0x190F952Cu //! Register Reset Value #define DESC3_2_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_87 Register DESC0_3_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_87 0x39530 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_87 0x190F9530u //! Register Reset Value #define DESC0_3_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_87 Register DESC1_3_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_87 0x39534 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_87 0x190F9534u //! Register Reset Value #define DESC1_3_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_87 Register DESC2_3_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_87 0x39538 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_87 0x190F9538u //! Register Reset Value #define DESC2_3_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_87 Register DESC3_3_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_87 0x3953C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_87 0x190F953Cu //! Register Reset Value #define DESC3_3_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_87 Register DESC0_4_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_87 0x39540 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_87 0x190F9540u //! Register Reset Value #define DESC0_4_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_87 Register DESC1_4_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_87 0x39544 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_87 0x190F9544u //! Register Reset Value #define DESC1_4_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_87 Register DESC2_4_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_87 0x39548 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_87 0x190F9548u //! Register Reset Value #define DESC2_4_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_87 Register DESC3_4_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_87 0x3954C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_87 0x190F954Cu //! Register Reset Value #define DESC3_4_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_87 Register DESC0_5_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_87 0x39550 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_87 0x190F9550u //! Register Reset Value #define DESC0_5_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_87 Register DESC1_5_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_87 0x39554 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_87 0x190F9554u //! Register Reset Value #define DESC1_5_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_87 Register DESC2_5_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_87 0x39558 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_87 0x190F9558u //! Register Reset Value #define DESC2_5_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_87 Register DESC3_5_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_87 0x3955C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_87 0x190F955Cu //! Register Reset Value #define DESC3_5_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_87 Register DESC0_6_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_87 0x39560 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_87 0x190F9560u //! Register Reset Value #define DESC0_6_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_87 Register DESC1_6_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_87 0x39564 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_87 0x190F9564u //! Register Reset Value #define DESC1_6_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_87 Register DESC2_6_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_87 0x39568 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_87 0x190F9568u //! Register Reset Value #define DESC2_6_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_87 Register DESC3_6_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_87 0x3956C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_87 0x190F956Cu //! Register Reset Value #define DESC3_6_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_87 Register DESC0_7_PON_EGP_87 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_87 0x39570 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_87 0x190F9570u //! Register Reset Value #define DESC0_7_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_87 Register DESC1_7_PON_EGP_87 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_87 0x39574 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_87 0x190F9574u //! Register Reset Value #define DESC1_7_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_87 Register DESC2_7_PON_EGP_87 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_87 0x39578 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_87 0x190F9578u //! Register Reset Value #define DESC2_7_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_87 Register DESC3_7_PON_EGP_87 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_87 0x3957C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_87 0x190F957Cu //! Register Reset Value #define DESC3_7_PON_EGP_87_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_87_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_87_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_87 Register DESC0_0_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_87 0x39600 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_87 0x190F9600u //! Register Reset Value #define DESC0_0_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_87 Register DESC1_0_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_87 0x39604 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_87 0x190F9604u //! Register Reset Value #define DESC1_0_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_87 Register DESC2_0_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_87 0x39608 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_87 0x190F9608u //! Register Reset Value #define DESC2_0_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_87 Register DESC3_0_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_87 0x3960C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_87 0x190F960Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_87 Register DESC0_1_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_87 0x39610 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_87 0x190F9610u //! Register Reset Value #define DESC0_1_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_87 Register DESC1_1_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_87 0x39614 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_87 0x190F9614u //! Register Reset Value #define DESC1_1_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_87 Register DESC2_1_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_87 0x39618 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_87 0x190F9618u //! Register Reset Value #define DESC2_1_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_87 Register DESC3_1_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_87 0x3961C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_87 0x190F961Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_87 Register DESC0_2_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_87 0x39620 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_87 0x190F9620u //! Register Reset Value #define DESC0_2_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_87 Register DESC1_2_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_87 0x39624 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_87 0x190F9624u //! Register Reset Value #define DESC1_2_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_87 Register DESC2_2_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_87 0x39628 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_87 0x190F9628u //! Register Reset Value #define DESC2_2_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_87 Register DESC3_2_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_87 0x3962C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_87 0x190F962Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_87 Register DESC0_3_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_87 0x39630 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_87 0x190F9630u //! Register Reset Value #define DESC0_3_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_87 Register DESC1_3_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_87 0x39634 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_87 0x190F9634u //! Register Reset Value #define DESC1_3_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_87 Register DESC2_3_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_87 0x39638 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_87 0x190F9638u //! Register Reset Value #define DESC2_3_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_87 Register DESC3_3_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_87 0x3963C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_87 0x190F963Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_87 Register DESC0_4_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_87 0x39640 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_87 0x190F9640u //! Register Reset Value #define DESC0_4_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_87 Register DESC1_4_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_87 0x39644 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_87 0x190F9644u //! Register Reset Value #define DESC1_4_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_87 Register DESC2_4_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_87 0x39648 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_87 0x190F9648u //! Register Reset Value #define DESC2_4_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_87 Register DESC3_4_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_87 0x3964C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_87 0x190F964Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_87 Register DESC0_5_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_87 0x39650 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_87 0x190F9650u //! Register Reset Value #define DESC0_5_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_87 Register DESC1_5_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_87 0x39654 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_87 0x190F9654u //! Register Reset Value #define DESC1_5_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_87 Register DESC2_5_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_87 0x39658 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_87 0x190F9658u //! Register Reset Value #define DESC2_5_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_87 Register DESC3_5_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_87 0x3965C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_87 0x190F965Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_87 Register DESC0_6_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_87 0x39660 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_87 0x190F9660u //! Register Reset Value #define DESC0_6_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_87 Register DESC1_6_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_87 0x39664 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_87 0x190F9664u //! Register Reset Value #define DESC1_6_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_87 Register DESC2_6_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_87 0x39668 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_87 0x190F9668u //! Register Reset Value #define DESC2_6_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_87 Register DESC3_6_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_87 0x3966C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_87 0x190F966Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_87 Register DESC0_7_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_87 0x39670 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_87 0x190F9670u //! Register Reset Value #define DESC0_7_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_87 Register DESC1_7_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_87 0x39674 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_87 0x190F9674u //! Register Reset Value #define DESC1_7_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_87 Register DESC2_7_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_87 0x39678 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_87 0x190F9678u //! Register Reset Value #define DESC2_7_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_87_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_87 Register DESC3_7_PON_EGP_S_87 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_87 0x3967C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_87 0x190F967Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_87_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_87_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_87_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_87_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_87_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_88 Register CFG_PON_EGP_88 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_88 0x39800 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_88 0x190F9800u //! Register Reset Value #define CFG_PON_EGP_88_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_88_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_88_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_88_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_88_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_88_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_88_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_88_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_88_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_88_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_88_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_88 Register IRNCR_PON_EGP_88 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_88 0x39820 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_88 0x190F9820u //! Register Reset Value #define IRNCR_PON_EGP_88_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_88_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_88_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_88_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_88_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_88 Register IRNICR_PON_EGP_88 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_88 0x39824 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_88 0x190F9824u //! Register Reset Value #define IRNICR_PON_EGP_88_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_88_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_88_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_88 Register IRNEN_PON_EGP_88 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_88 0x39828 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_88 0x190F9828u //! Register Reset Value #define IRNEN_PON_EGP_88_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_88_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_88_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_88_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_88_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_88 Register DPTR_PON_EGP_88 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_88 0x39830 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_88 0x190F9830u //! Register Reset Value #define DPTR_PON_EGP_88_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_88_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_88_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_88_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_88_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_88_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_88_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_88_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_88_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_88 Register DESC0_0_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_88 0x39900 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_88 0x190F9900u //! Register Reset Value #define DESC0_0_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_88 Register DESC1_0_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_88 0x39904 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_88 0x190F9904u //! Register Reset Value #define DESC1_0_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_88 Register DESC2_0_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_88 0x39908 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_88 0x190F9908u //! Register Reset Value #define DESC2_0_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_88 Register DESC3_0_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_88 0x3990C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_88 0x190F990Cu //! Register Reset Value #define DESC3_0_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_88 Register DESC0_1_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_88 0x39910 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_88 0x190F9910u //! Register Reset Value #define DESC0_1_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_88 Register DESC1_1_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_88 0x39914 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_88 0x190F9914u //! Register Reset Value #define DESC1_1_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_88 Register DESC2_1_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_88 0x39918 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_88 0x190F9918u //! Register Reset Value #define DESC2_1_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_88 Register DESC3_1_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_88 0x3991C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_88 0x190F991Cu //! Register Reset Value #define DESC3_1_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_88 Register DESC0_2_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_88 0x39920 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_88 0x190F9920u //! Register Reset Value #define DESC0_2_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_88 Register DESC1_2_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_88 0x39924 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_88 0x190F9924u //! Register Reset Value #define DESC1_2_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_88 Register DESC2_2_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_88 0x39928 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_88 0x190F9928u //! Register Reset Value #define DESC2_2_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_88 Register DESC3_2_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_88 0x3992C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_88 0x190F992Cu //! Register Reset Value #define DESC3_2_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_88 Register DESC0_3_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_88 0x39930 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_88 0x190F9930u //! Register Reset Value #define DESC0_3_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_88 Register DESC1_3_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_88 0x39934 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_88 0x190F9934u //! Register Reset Value #define DESC1_3_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_88 Register DESC2_3_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_88 0x39938 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_88 0x190F9938u //! Register Reset Value #define DESC2_3_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_88 Register DESC3_3_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_88 0x3993C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_88 0x190F993Cu //! Register Reset Value #define DESC3_3_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_88 Register DESC0_4_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_88 0x39940 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_88 0x190F9940u //! Register Reset Value #define DESC0_4_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_88 Register DESC1_4_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_88 0x39944 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_88 0x190F9944u //! Register Reset Value #define DESC1_4_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_88 Register DESC2_4_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_88 0x39948 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_88 0x190F9948u //! Register Reset Value #define DESC2_4_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_88 Register DESC3_4_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_88 0x3994C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_88 0x190F994Cu //! Register Reset Value #define DESC3_4_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_88 Register DESC0_5_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_88 0x39950 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_88 0x190F9950u //! Register Reset Value #define DESC0_5_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_88 Register DESC1_5_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_88 0x39954 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_88 0x190F9954u //! Register Reset Value #define DESC1_5_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_88 Register DESC2_5_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_88 0x39958 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_88 0x190F9958u //! Register Reset Value #define DESC2_5_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_88 Register DESC3_5_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_88 0x3995C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_88 0x190F995Cu //! Register Reset Value #define DESC3_5_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_88 Register DESC0_6_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_88 0x39960 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_88 0x190F9960u //! Register Reset Value #define DESC0_6_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_88 Register DESC1_6_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_88 0x39964 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_88 0x190F9964u //! Register Reset Value #define DESC1_6_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_88 Register DESC2_6_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_88 0x39968 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_88 0x190F9968u //! Register Reset Value #define DESC2_6_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_88 Register DESC3_6_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_88 0x3996C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_88 0x190F996Cu //! Register Reset Value #define DESC3_6_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_88 Register DESC0_7_PON_EGP_88 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_88 0x39970 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_88 0x190F9970u //! Register Reset Value #define DESC0_7_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_88 Register DESC1_7_PON_EGP_88 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_88 0x39974 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_88 0x190F9974u //! Register Reset Value #define DESC1_7_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_88 Register DESC2_7_PON_EGP_88 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_88 0x39978 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_88 0x190F9978u //! Register Reset Value #define DESC2_7_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_88 Register DESC3_7_PON_EGP_88 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_88 0x3997C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_88 0x190F997Cu //! Register Reset Value #define DESC3_7_PON_EGP_88_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_88_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_88_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_88 Register DESC0_0_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_88 0x39A00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_88 0x190F9A00u //! Register Reset Value #define DESC0_0_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_88 Register DESC1_0_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_88 0x39A04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_88 0x190F9A04u //! Register Reset Value #define DESC1_0_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_88 Register DESC2_0_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_88 0x39A08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_88 0x190F9A08u //! Register Reset Value #define DESC2_0_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_88 Register DESC3_0_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_88 0x39A0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_88 0x190F9A0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_88 Register DESC0_1_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_88 0x39A10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_88 0x190F9A10u //! Register Reset Value #define DESC0_1_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_88 Register DESC1_1_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_88 0x39A14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_88 0x190F9A14u //! Register Reset Value #define DESC1_1_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_88 Register DESC2_1_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_88 0x39A18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_88 0x190F9A18u //! Register Reset Value #define DESC2_1_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_88 Register DESC3_1_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_88 0x39A1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_88 0x190F9A1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_88 Register DESC0_2_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_88 0x39A20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_88 0x190F9A20u //! Register Reset Value #define DESC0_2_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_88 Register DESC1_2_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_88 0x39A24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_88 0x190F9A24u //! Register Reset Value #define DESC1_2_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_88 Register DESC2_2_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_88 0x39A28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_88 0x190F9A28u //! Register Reset Value #define DESC2_2_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_88 Register DESC3_2_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_88 0x39A2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_88 0x190F9A2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_88 Register DESC0_3_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_88 0x39A30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_88 0x190F9A30u //! Register Reset Value #define DESC0_3_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_88 Register DESC1_3_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_88 0x39A34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_88 0x190F9A34u //! Register Reset Value #define DESC1_3_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_88 Register DESC2_3_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_88 0x39A38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_88 0x190F9A38u //! Register Reset Value #define DESC2_3_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_88 Register DESC3_3_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_88 0x39A3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_88 0x190F9A3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_88 Register DESC0_4_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_88 0x39A40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_88 0x190F9A40u //! Register Reset Value #define DESC0_4_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_88 Register DESC1_4_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_88 0x39A44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_88 0x190F9A44u //! Register Reset Value #define DESC1_4_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_88 Register DESC2_4_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_88 0x39A48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_88 0x190F9A48u //! Register Reset Value #define DESC2_4_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_88 Register DESC3_4_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_88 0x39A4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_88 0x190F9A4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_88 Register DESC0_5_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_88 0x39A50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_88 0x190F9A50u //! Register Reset Value #define DESC0_5_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_88 Register DESC1_5_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_88 0x39A54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_88 0x190F9A54u //! Register Reset Value #define DESC1_5_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_88 Register DESC2_5_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_88 0x39A58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_88 0x190F9A58u //! Register Reset Value #define DESC2_5_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_88 Register DESC3_5_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_88 0x39A5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_88 0x190F9A5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_88 Register DESC0_6_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_88 0x39A60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_88 0x190F9A60u //! Register Reset Value #define DESC0_6_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_88 Register DESC1_6_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_88 0x39A64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_88 0x190F9A64u //! Register Reset Value #define DESC1_6_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_88 Register DESC2_6_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_88 0x39A68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_88 0x190F9A68u //! Register Reset Value #define DESC2_6_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_88 Register DESC3_6_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_88 0x39A6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_88 0x190F9A6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_88 Register DESC0_7_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_88 0x39A70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_88 0x190F9A70u //! Register Reset Value #define DESC0_7_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_88 Register DESC1_7_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_88 0x39A74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_88 0x190F9A74u //! Register Reset Value #define DESC1_7_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_88 Register DESC2_7_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_88 0x39A78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_88 0x190F9A78u //! Register Reset Value #define DESC2_7_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_88_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_88 Register DESC3_7_PON_EGP_S_88 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_88 0x39A7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_88 0x190F9A7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_88_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_88_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_88_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_88_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_88_OWN_MASK 0x80000000u //! @} //! \defgroup CFG_PON_EGP_89 Register CFG_PON_EGP_89 - PON Egress Port Configuration //! @{ //! Register Offset (relative) #define CFG_PON_EGP_89 0x39C00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_CFG_PON_EGP_89 0x190F9C00u //! Register Reset Value #define CFG_PON_EGP_89_RST 0x00000000u //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_89_DQREQ_POS 0 //! Field DQREQ - Enable PON Dequeue Request #define CFG_PON_EGP_89_DQREQ_MASK 0x1u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_89_DQREQ_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_89_DQREQ_EN 0x1 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_89_DQPCEN_POS 8 //! Field DQPCEN - Dequeue Counter Enable #define CFG_PON_EGP_89_DQPCEN_MASK 0x100u //! Constant DIS - DIS #define CONST_CFG_PON_EGP_89_DQPCEN_DIS 0x0 //! Constant EN - EN #define CONST_CFG_PON_EGP_89_DQPCEN_EN 0x1 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_89_EPMAP_POS 16 //! Field EPMAP - Egress port mapping #define CFG_PON_EGP_89_EPMAP_MASK 0x7F0000u //! @} //! \defgroup IRNCR_PON_EGP_89 Register IRNCR_PON_EGP_89 - PON Egress Port IRN Capture Register //! @{ //! Register Offset (relative) #define IRNCR_PON_EGP_89 0x39C20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNCR_PON_EGP_89 0x190F9C20u //! Register Reset Value #define IRNCR_PON_EGP_89_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_89_DR_POS 1 //! Field DR - Descriptor Ready #define IRNCR_PON_EGP_89_DR_MASK 0x2u //! Constant NUL - NULL #define CONST_IRNCR_PON_EGP_89_DR_NUL 0x0 //! Constant INTOCC - INTOCC #define CONST_IRNCR_PON_EGP_89_DR_INTOCC 0x1 //! @} //! \defgroup IRNICR_PON_EGP_89 Register IRNICR_PON_EGP_89 - PON Egress Port IRN Interrupt Control Register //! @{ //! Register Offset (relative) #define IRNICR_PON_EGP_89 0x39C24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNICR_PON_EGP_89 0x190F9C24u //! Register Reset Value #define IRNICR_PON_EGP_89_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_89_DR_POS 1 //! Field DR - Descriptor Ready #define IRNICR_PON_EGP_89_DR_MASK 0x2u //! @} //! \defgroup IRNEN_PON_EGP_89 Register IRNEN_PON_EGP_89 - PON Egress Port IRN Interrupt Enable Register //! @{ //! Register Offset (relative) #define IRNEN_PON_EGP_89 0x39C28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_IRNEN_PON_EGP_89 0x190F9C28u //! Register Reset Value #define IRNEN_PON_EGP_89_RST 0x00000000u //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_89_DR_POS 1 //! Field DR - Descriptor Ready #define IRNEN_PON_EGP_89_DR_MASK 0x2u //! Constant DIS - DIS #define CONST_IRNEN_PON_EGP_89_DR_DIS 0x0 //! Constant EN - EN #define CONST_IRNEN_PON_EGP_89_DR_EN 0x1 //! @} //! \defgroup DPTR_PON_EGP_89 Register DPTR_PON_EGP_89 - PON Egress Port Descriptor Pointer //! @{ //! Register Offset (relative) #define DPTR_PON_EGP_89 0x39C30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DPTR_PON_EGP_89 0x190F9C30u //! Register Reset Value #define DPTR_PON_EGP_89_RST 0x00000707u //! Field ND - Number of Descriptors #define DPTR_PON_EGP_89_ND_POS 0 //! Field ND - Number of Descriptors #define DPTR_PON_EGP_89_ND_MASK 0x7u //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_89_NSD_POS 8 //! Field NSD - Number of Segmented Descriptors #define DPTR_PON_EGP_89_NSD_MASK 0x700u //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_89_DPTR_POS 16 //! Field DPTR - Descriptor Pointer #define DPTR_PON_EGP_89_DPTR_MASK 0x70000u //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_89_SDPTR_POS 24 //! Field SDPTR - Descriptor Pointer #define DPTR_PON_EGP_89_SDPTR_MASK 0x7000000u //! @} //! \defgroup DESC0_0_PON_EGP_89 Register DESC0_0_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_89 0x39D00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_89 0x190F9D00u //! Register Reset Value #define DESC0_0_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_0_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_89 Register DESC1_0_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_89 0x39D04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_89 0x190F9D04u //! Register Reset Value #define DESC1_0_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_0_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_89 Register DESC2_0_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_89 0x39D08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_89 0x190F9D08u //! Register Reset Value #define DESC2_0_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_0_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_89 Register DESC3_0_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_89 0x39D0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_89 0x190F9D0Cu //! Register Reset Value #define DESC3_0_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_0_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_0_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_89 Register DESC0_1_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_89 0x39D10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_89 0x190F9D10u //! Register Reset Value #define DESC0_1_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_1_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_89 Register DESC1_1_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_89 0x39D14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_89 0x190F9D14u //! Register Reset Value #define DESC1_1_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_1_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_89 Register DESC2_1_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_89 0x39D18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_89 0x190F9D18u //! Register Reset Value #define DESC2_1_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_1_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_89 Register DESC3_1_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_89 0x39D1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_89 0x190F9D1Cu //! Register Reset Value #define DESC3_1_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_1_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_1_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_89 Register DESC0_2_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_89 0x39D20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_89 0x190F9D20u //! Register Reset Value #define DESC0_2_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_2_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_89 Register DESC1_2_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_89 0x39D24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_89 0x190F9D24u //! Register Reset Value #define DESC1_2_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_2_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_89 Register DESC2_2_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_89 0x39D28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_89 0x190F9D28u //! Register Reset Value #define DESC2_2_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_2_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_89 Register DESC3_2_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_89 0x39D2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_89 0x190F9D2Cu //! Register Reset Value #define DESC3_2_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_2_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_2_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_89 Register DESC0_3_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_89 0x39D30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_89 0x190F9D30u //! Register Reset Value #define DESC0_3_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_3_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_89 Register DESC1_3_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_89 0x39D34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_89 0x190F9D34u //! Register Reset Value #define DESC1_3_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_3_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_89 Register DESC2_3_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_89 0x39D38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_89 0x190F9D38u //! Register Reset Value #define DESC2_3_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_3_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_89 Register DESC3_3_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_89 0x39D3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_89 0x190F9D3Cu //! Register Reset Value #define DESC3_3_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_3_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_3_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_89 Register DESC0_4_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_89 0x39D40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_89 0x190F9D40u //! Register Reset Value #define DESC0_4_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_4_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_89 Register DESC1_4_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_89 0x39D44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_89 0x190F9D44u //! Register Reset Value #define DESC1_4_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_4_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_89 Register DESC2_4_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_89 0x39D48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_89 0x190F9D48u //! Register Reset Value #define DESC2_4_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_4_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_89 Register DESC3_4_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_89 0x39D4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_89 0x190F9D4Cu //! Register Reset Value #define DESC3_4_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_4_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_4_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_89 Register DESC0_5_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_89 0x39D50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_89 0x190F9D50u //! Register Reset Value #define DESC0_5_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_5_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_89 Register DESC1_5_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_89 0x39D54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_89 0x190F9D54u //! Register Reset Value #define DESC1_5_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_5_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_89 Register DESC2_5_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_89 0x39D58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_89 0x190F9D58u //! Register Reset Value #define DESC2_5_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_5_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_89 Register DESC3_5_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_89 0x39D5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_89 0x190F9D5Cu //! Register Reset Value #define DESC3_5_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_5_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_5_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_89 Register DESC0_6_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_89 0x39D60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_89 0x190F9D60u //! Register Reset Value #define DESC0_6_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_6_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_89 Register DESC1_6_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_89 0x39D64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_89 0x190F9D64u //! Register Reset Value #define DESC1_6_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_6_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_89 Register DESC2_6_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_89 0x39D68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_89 0x190F9D68u //! Register Reset Value #define DESC2_6_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_6_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_89 Register DESC3_6_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_89 0x39D6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_89 0x190F9D6Cu //! Register Reset Value #define DESC3_6_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_6_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_6_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_89 Register DESC0_7_PON_EGP_89 - PON Egress Port Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_89 0x39D70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_89 0x190F9D70u //! Register Reset Value #define DESC0_7_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 0 #define DESC0_7_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_89 Register DESC1_7_PON_EGP_89 - PON Egress Port Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_89 0x39D74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_89 0x190F9D74u //! Register Reset Value #define DESC1_7_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 1 #define DESC1_7_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_89 Register DESC2_7_PON_EGP_89 - PON Egress Port Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_89 0x39D78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_89 0x190F9D78u //! Register Reset Value #define DESC2_7_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 2 #define DESC2_7_PON_EGP_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_89 Register DESC3_7_PON_EGP_89 - PON Egress Port Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_89 0x39D7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_89 0x190F9D7Cu //! Register Reset Value #define DESC3_7_PON_EGP_89_RST 0x00000000u //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_89_DESC_POS 0 //! Field DESC - Descriptor Double Word 3 #define DESC3_7_PON_EGP_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_89_OWN_POS 31 //! Field OWN - Descriptor OWN bit #define DESC3_7_PON_EGP_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_0_PON_EGP_S_89 Register DESC0_0_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_0_PON_EGP_S_89 0x39E00 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_0_PON_EGP_S_89 0x190F9E00u //! Register Reset Value #define DESC0_0_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_0_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_0_PON_EGP_S_89 Register DESC1_0_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_0_PON_EGP_S_89 0x39E04 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_0_PON_EGP_S_89 0x190F9E04u //! Register Reset Value #define DESC1_0_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_0_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_0_PON_EGP_S_89 Register DESC2_0_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_0_PON_EGP_S_89 0x39E08 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_0_PON_EGP_S_89 0x190F9E08u //! Register Reset Value #define DESC2_0_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_0_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_0_PON_EGP_S_89 Register DESC3_0_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_0_PON_EGP_S_89 0x39E0C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_0_PON_EGP_S_89 0x190F9E0Cu //! Register Reset Value #define DESC3_0_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_0_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_0_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_1_PON_EGP_S_89 Register DESC0_1_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_1_PON_EGP_S_89 0x39E10 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_1_PON_EGP_S_89 0x190F9E10u //! Register Reset Value #define DESC0_1_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_1_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_1_PON_EGP_S_89 Register DESC1_1_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_1_PON_EGP_S_89 0x39E14 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_1_PON_EGP_S_89 0x190F9E14u //! Register Reset Value #define DESC1_1_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_1_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_1_PON_EGP_S_89 Register DESC2_1_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_1_PON_EGP_S_89 0x39E18 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_1_PON_EGP_S_89 0x190F9E18u //! Register Reset Value #define DESC2_1_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_1_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_1_PON_EGP_S_89 Register DESC3_1_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_1_PON_EGP_S_89 0x39E1C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_1_PON_EGP_S_89 0x190F9E1Cu //! Register Reset Value #define DESC3_1_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_1_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_1_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_2_PON_EGP_S_89 Register DESC0_2_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_2_PON_EGP_S_89 0x39E20 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_2_PON_EGP_S_89 0x190F9E20u //! Register Reset Value #define DESC0_2_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_2_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_2_PON_EGP_S_89 Register DESC1_2_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_2_PON_EGP_S_89 0x39E24 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_2_PON_EGP_S_89 0x190F9E24u //! Register Reset Value #define DESC1_2_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_2_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_2_PON_EGP_S_89 Register DESC2_2_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_2_PON_EGP_S_89 0x39E28 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_2_PON_EGP_S_89 0x190F9E28u //! Register Reset Value #define DESC2_2_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_2_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_2_PON_EGP_S_89 Register DESC3_2_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_2_PON_EGP_S_89 0x39E2C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_2_PON_EGP_S_89 0x190F9E2Cu //! Register Reset Value #define DESC3_2_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_2_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_2_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_3_PON_EGP_S_89 Register DESC0_3_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_3_PON_EGP_S_89 0x39E30 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_3_PON_EGP_S_89 0x190F9E30u //! Register Reset Value #define DESC0_3_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_3_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_3_PON_EGP_S_89 Register DESC1_3_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_3_PON_EGP_S_89 0x39E34 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_3_PON_EGP_S_89 0x190F9E34u //! Register Reset Value #define DESC1_3_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_3_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_3_PON_EGP_S_89 Register DESC2_3_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_3_PON_EGP_S_89 0x39E38 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_3_PON_EGP_S_89 0x190F9E38u //! Register Reset Value #define DESC2_3_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_3_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_3_PON_EGP_S_89 Register DESC3_3_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_3_PON_EGP_S_89 0x39E3C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_3_PON_EGP_S_89 0x190F9E3Cu //! Register Reset Value #define DESC3_3_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_3_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_3_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_4_PON_EGP_S_89 Register DESC0_4_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_4_PON_EGP_S_89 0x39E40 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_4_PON_EGP_S_89 0x190F9E40u //! Register Reset Value #define DESC0_4_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_4_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_4_PON_EGP_S_89 Register DESC1_4_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_4_PON_EGP_S_89 0x39E44 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_4_PON_EGP_S_89 0x190F9E44u //! Register Reset Value #define DESC1_4_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_4_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_4_PON_EGP_S_89 Register DESC2_4_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_4_PON_EGP_S_89 0x39E48 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_4_PON_EGP_S_89 0x190F9E48u //! Register Reset Value #define DESC2_4_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_4_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_4_PON_EGP_S_89 Register DESC3_4_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_4_PON_EGP_S_89 0x39E4C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_4_PON_EGP_S_89 0x190F9E4Cu //! Register Reset Value #define DESC3_4_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_4_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_4_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_5_PON_EGP_S_89 Register DESC0_5_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_5_PON_EGP_S_89 0x39E50 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_5_PON_EGP_S_89 0x190F9E50u //! Register Reset Value #define DESC0_5_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_5_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_5_PON_EGP_S_89 Register DESC1_5_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_5_PON_EGP_S_89 0x39E54 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_5_PON_EGP_S_89 0x190F9E54u //! Register Reset Value #define DESC1_5_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_5_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_5_PON_EGP_S_89 Register DESC2_5_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_5_PON_EGP_S_89 0x39E58 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_5_PON_EGP_S_89 0x190F9E58u //! Register Reset Value #define DESC2_5_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_5_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_5_PON_EGP_S_89 Register DESC3_5_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_5_PON_EGP_S_89 0x39E5C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_5_PON_EGP_S_89 0x190F9E5Cu //! Register Reset Value #define DESC3_5_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_5_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_5_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_6_PON_EGP_S_89 Register DESC0_6_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_6_PON_EGP_S_89 0x39E60 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_6_PON_EGP_S_89 0x190F9E60u //! Register Reset Value #define DESC0_6_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_6_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_6_PON_EGP_S_89 Register DESC1_6_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_6_PON_EGP_S_89 0x39E64 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_6_PON_EGP_S_89 0x190F9E64u //! Register Reset Value #define DESC1_6_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_6_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_6_PON_EGP_S_89 Register DESC2_6_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_6_PON_EGP_S_89 0x39E68 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_6_PON_EGP_S_89 0x190F9E68u //! Register Reset Value #define DESC2_6_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_6_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_6_PON_EGP_S_89 Register DESC3_6_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_6_PON_EGP_S_89 0x39E6C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_6_PON_EGP_S_89 0x190F9E6Cu //! Register Reset Value #define DESC3_6_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_6_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_6_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! \defgroup DESC0_7_PON_EGP_S_89 Register DESC0_7_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW0 //! @{ //! Register Offset (relative) #define DESC0_7_PON_EGP_S_89 0x39E70 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC0_7_PON_EGP_S_89 0x190F9E70u //! Register Reset Value #define DESC0_7_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 0 #define DESC0_7_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC1_7_PON_EGP_S_89 Register DESC1_7_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW1 //! @{ //! Register Offset (relative) #define DESC1_7_PON_EGP_S_89 0x39E74 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC1_7_PON_EGP_S_89 0x190F9E74u //! Register Reset Value #define DESC1_7_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 1 #define DESC1_7_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC2_7_PON_EGP_S_89 Register DESC2_7_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW2 //! @{ //! Register Offset (relative) #define DESC2_7_PON_EGP_S_89 0x39E78 //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC2_7_PON_EGP_S_89 0x190F9E78u //! Register Reset Value #define DESC2_7_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 2 #define DESC2_7_PON_EGP_S_89_DESC_MASK 0xFFFFFFFFu //! @} //! \defgroup DESC3_7_PON_EGP_S_89 Register DESC3_7_PON_EGP_S_89 - PON Egress Port Segmented Descriptor DW3 //! @{ //! Register Offset (relative) #define DESC3_7_PON_EGP_S_89 0x39E7C //! Register Offset (absolute) for 1st Instance CQEM_DEQ #define CQEM_DEQ_DESC3_7_PON_EGP_S_89 0x190F9E7Cu //! Register Reset Value #define DESC3_7_PON_EGP_S_89_RST 0x00000000u //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_89_DESC_POS 0 //! Field DESC - Segmented Descriptor Double Word 3 #define DESC3_7_PON_EGP_S_89_DESC_MASK 0x7FFFFFFFu //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_89_OWN_POS 31 //! Field OWN - OWN Bit for the Segmented Descriptor #define DESC3_7_PON_EGP_S_89_OWN_MASK 0x80000000u //! @} //! @} #endif