//----------------------------------------------------------------------------- // LSD Generator //----------------------------------------------------------------------------- // Perl Package : LSD::generator::targetC (v1.1) // LSD Source : C:/Users/huchunfe/Perforce/huchunfe_huchunfe-MOBL1_dev.FalcONT/ipg_lsd/lsd_sys/source/xml/reg_files/CBM_Desc64b.xml // Register File Name : CQEM_DESC64B // Register File Title : Central QoS Manager 64-Bit Descriptor Register Description // Register Width : 64 // Note : Doxygen compliant comments //----------------------------------------------------------------------------- #ifndef _CQEM_DESC64B_H #define _CQEM_DESC64B_H //! \defgroup CQEM_DESC64B Register File CQEM_DESC64B - Central QoS Manager 64-Bit Descriptor Register Description //! @{ //! Base Address of CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_MODULE_BASE 0x18F00000u //! \defgroup DESC0_0_IGP_4 Register DESC0_0_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_4 0x0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_4 0x18F00000u //! Register Reset Value #define DESC0_0_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_4 Register DESC1_0_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_4 0x8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_4 0x18F00008u //! Register Reset Value #define DESC1_0_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_4 Register DESC0_1_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_4 0x10 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_4 0x18F00010u //! Register Reset Value #define DESC0_1_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_4 Register DESC1_1_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_4 0x18 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_4 0x18F00018u //! Register Reset Value #define DESC1_1_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_4 Register DESC0_2_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_4 0x20 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_4 0x18F00020u //! Register Reset Value #define DESC0_2_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_4 Register DESC1_2_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_4 0x28 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_4 0x18F00028u //! Register Reset Value #define DESC1_2_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_4 Register DESC0_3_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_4 0x30 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_4 0x18F00030u //! Register Reset Value #define DESC0_3_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_4 Register DESC1_3_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_4 0x38 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_4 0x18F00038u //! Register Reset Value #define DESC1_3_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_4 Register DESC0_4_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_4 0x40 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_4 0x18F00040u //! Register Reset Value #define DESC0_4_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_4 Register DESC1_4_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_4 0x48 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_4 0x18F00048u //! Register Reset Value #define DESC1_4_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_4 Register DESC0_5_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_4 0x50 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_4 0x18F00050u //! Register Reset Value #define DESC0_5_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_4 Register DESC1_5_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_4 0x58 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_4 0x18F00058u //! Register Reset Value #define DESC1_5_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_4 Register DESC0_6_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_4 0x60 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_4 0x18F00060u //! Register Reset Value #define DESC0_6_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_4 Register DESC1_6_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_4 0x68 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_4 0x18F00068u //! Register Reset Value #define DESC1_6_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_4 Register DESC0_7_IGP_4 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_4 0x70 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_4 0x18F00070u //! Register Reset Value #define DESC0_7_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_4 Register DESC1_7_IGP_4 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_4 0x78 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_4 0x18F00078u //! Register Reset Value #define DESC1_7_IGP_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_5 Register DESC0_0_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_5 0x1000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_5 0x18F01000u //! Register Reset Value #define DESC0_0_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_5 Register DESC1_0_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_5 0x1008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_5 0x18F01008u //! Register Reset Value #define DESC1_0_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_5 Register DESC0_1_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_5 0x1010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_5 0x18F01010u //! Register Reset Value #define DESC0_1_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_5 Register DESC1_1_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_5 0x1018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_5 0x18F01018u //! Register Reset Value #define DESC1_1_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_5 Register DESC0_2_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_5 0x1020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_5 0x18F01020u //! Register Reset Value #define DESC0_2_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_5 Register DESC1_2_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_5 0x1028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_5 0x18F01028u //! Register Reset Value #define DESC1_2_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_5 Register DESC0_3_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_5 0x1030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_5 0x18F01030u //! Register Reset Value #define DESC0_3_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_5 Register DESC1_3_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_5 0x1038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_5 0x18F01038u //! Register Reset Value #define DESC1_3_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_5 Register DESC0_4_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_5 0x1040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_5 0x18F01040u //! Register Reset Value #define DESC0_4_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_5 Register DESC1_4_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_5 0x1048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_5 0x18F01048u //! Register Reset Value #define DESC1_4_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_5 Register DESC0_5_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_5 0x1050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_5 0x18F01050u //! Register Reset Value #define DESC0_5_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_5 Register DESC1_5_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_5 0x1058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_5 0x18F01058u //! Register Reset Value #define DESC1_5_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_5 Register DESC0_6_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_5 0x1060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_5 0x18F01060u //! Register Reset Value #define DESC0_6_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_5 Register DESC1_6_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_5 0x1068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_5 0x18F01068u //! Register Reset Value #define DESC1_6_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_5 Register DESC0_7_IGP_5 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_5 0x1070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_5 0x18F01070u //! Register Reset Value #define DESC0_7_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_5 Register DESC1_7_IGP_5 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_5 0x1078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_5 0x18F01078u //! Register Reset Value #define DESC1_7_IGP_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_6 Register DESC0_0_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_6 0x2000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_6 0x18F02000u //! Register Reset Value #define DESC0_0_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_6 Register DESC1_0_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_6 0x2008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_6 0x18F02008u //! Register Reset Value #define DESC1_0_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_6 Register DESC0_1_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_6 0x2010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_6 0x18F02010u //! Register Reset Value #define DESC0_1_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_6 Register DESC1_1_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_6 0x2018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_6 0x18F02018u //! Register Reset Value #define DESC1_1_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_6 Register DESC0_2_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_6 0x2020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_6 0x18F02020u //! Register Reset Value #define DESC0_2_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_6 Register DESC1_2_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_6 0x2028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_6 0x18F02028u //! Register Reset Value #define DESC1_2_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_6 Register DESC0_3_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_6 0x2030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_6 0x18F02030u //! Register Reset Value #define DESC0_3_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_6 Register DESC1_3_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_6 0x2038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_6 0x18F02038u //! Register Reset Value #define DESC1_3_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_6 Register DESC0_4_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_6 0x2040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_6 0x18F02040u //! Register Reset Value #define DESC0_4_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_6 Register DESC1_4_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_6 0x2048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_6 0x18F02048u //! Register Reset Value #define DESC1_4_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_6 Register DESC0_5_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_6 0x2050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_6 0x18F02050u //! Register Reset Value #define DESC0_5_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_6 Register DESC1_5_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_6 0x2058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_6 0x18F02058u //! Register Reset Value #define DESC1_5_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_6 Register DESC0_6_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_6 0x2060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_6 0x18F02060u //! Register Reset Value #define DESC0_6_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_6 Register DESC1_6_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_6 0x2068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_6 0x18F02068u //! Register Reset Value #define DESC1_6_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_6 Register DESC0_7_IGP_6 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_6 0x2070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_6 0x18F02070u //! Register Reset Value #define DESC0_7_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_6 Register DESC1_7_IGP_6 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_6 0x2078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_6 0x18F02078u //! Register Reset Value #define DESC1_7_IGP_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_7 Register DESC0_0_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_7 0x3000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_7 0x18F03000u //! Register Reset Value #define DESC0_0_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_7 Register DESC1_0_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_7 0x3008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_7 0x18F03008u //! Register Reset Value #define DESC1_0_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_7 Register DESC0_1_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_7 0x3010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_7 0x18F03010u //! Register Reset Value #define DESC0_1_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_7 Register DESC1_1_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_7 0x3018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_7 0x18F03018u //! Register Reset Value #define DESC1_1_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_7 Register DESC0_2_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_7 0x3020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_7 0x18F03020u //! Register Reset Value #define DESC0_2_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_7 Register DESC1_2_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_7 0x3028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_7 0x18F03028u //! Register Reset Value #define DESC1_2_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_7 Register DESC0_3_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_7 0x3030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_7 0x18F03030u //! Register Reset Value #define DESC0_3_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_7 Register DESC1_3_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_7 0x3038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_7 0x18F03038u //! Register Reset Value #define DESC1_3_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_7 Register DESC0_4_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_7 0x3040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_7 0x18F03040u //! Register Reset Value #define DESC0_4_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_7 Register DESC1_4_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_7 0x3048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_7 0x18F03048u //! Register Reset Value #define DESC1_4_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_7 Register DESC0_5_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_7 0x3050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_7 0x18F03050u //! Register Reset Value #define DESC0_5_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_7 Register DESC1_5_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_7 0x3058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_7 0x18F03058u //! Register Reset Value #define DESC1_5_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_7 Register DESC0_6_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_7 0x3060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_7 0x18F03060u //! Register Reset Value #define DESC0_6_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_7 Register DESC1_6_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_7 0x3068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_7 0x18F03068u //! Register Reset Value #define DESC1_6_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_7 Register DESC0_7_IGP_7 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_7 0x3070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_7 0x18F03070u //! Register Reset Value #define DESC0_7_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_7 Register DESC1_7_IGP_7 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_7 0x3078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_7 0x18F03078u //! Register Reset Value #define DESC1_7_IGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_8 Register DESC0_0_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_8 0x4000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_8 0x18F04000u //! Register Reset Value #define DESC0_0_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_8 Register DESC1_0_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_8 0x4008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_8 0x18F04008u //! Register Reset Value #define DESC1_0_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_8 Register DESC0_1_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_8 0x4010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_8 0x18F04010u //! Register Reset Value #define DESC0_1_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_8 Register DESC1_1_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_8 0x4018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_8 0x18F04018u //! Register Reset Value #define DESC1_1_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_8 Register DESC0_2_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_8 0x4020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_8 0x18F04020u //! Register Reset Value #define DESC0_2_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_8 Register DESC1_2_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_8 0x4028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_8 0x18F04028u //! Register Reset Value #define DESC1_2_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_8 Register DESC0_3_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_8 0x4030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_8 0x18F04030u //! Register Reset Value #define DESC0_3_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_8 Register DESC1_3_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_8 0x4038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_8 0x18F04038u //! Register Reset Value #define DESC1_3_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_8 Register DESC0_4_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_8 0x4040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_8 0x18F04040u //! Register Reset Value #define DESC0_4_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_8 Register DESC1_4_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_8 0x4048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_8 0x18F04048u //! Register Reset Value #define DESC1_4_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_8 Register DESC0_5_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_8 0x4050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_8 0x18F04050u //! Register Reset Value #define DESC0_5_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_8 Register DESC1_5_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_8 0x4058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_8 0x18F04058u //! Register Reset Value #define DESC1_5_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_8 Register DESC0_6_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_8 0x4060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_8 0x18F04060u //! Register Reset Value #define DESC0_6_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_8 Register DESC1_6_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_8 0x4068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_8 0x18F04068u //! Register Reset Value #define DESC1_6_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_8 Register DESC0_7_IGP_8 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_8 0x4070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_8 0x18F04070u //! Register Reset Value #define DESC0_7_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_8 Register DESC1_7_IGP_8 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_8 0x4078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_8 0x18F04078u //! Register Reset Value #define DESC1_7_IGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_9 Register DESC0_0_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_9 0x5000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_9 0x18F05000u //! Register Reset Value #define DESC0_0_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_9 Register DESC1_0_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_9 0x5008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_9 0x18F05008u //! Register Reset Value #define DESC1_0_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_9 Register DESC0_1_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_9 0x5010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_9 0x18F05010u //! Register Reset Value #define DESC0_1_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_9 Register DESC1_1_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_9 0x5018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_9 0x18F05018u //! Register Reset Value #define DESC1_1_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_9 Register DESC0_2_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_9 0x5020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_9 0x18F05020u //! Register Reset Value #define DESC0_2_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_9 Register DESC1_2_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_9 0x5028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_9 0x18F05028u //! Register Reset Value #define DESC1_2_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_9 Register DESC0_3_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_9 0x5030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_9 0x18F05030u //! Register Reset Value #define DESC0_3_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_9 Register DESC1_3_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_9 0x5038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_9 0x18F05038u //! Register Reset Value #define DESC1_3_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_9 Register DESC0_4_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_9 0x5040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_9 0x18F05040u //! Register Reset Value #define DESC0_4_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_9 Register DESC1_4_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_9 0x5048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_9 0x18F05048u //! Register Reset Value #define DESC1_4_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_9 Register DESC0_5_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_9 0x5050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_9 0x18F05050u //! Register Reset Value #define DESC0_5_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_9 Register DESC1_5_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_9 0x5058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_9 0x18F05058u //! Register Reset Value #define DESC1_5_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_9 Register DESC0_6_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_9 0x5060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_9 0x18F05060u //! Register Reset Value #define DESC0_6_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_9 Register DESC1_6_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_9 0x5068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_9 0x18F05068u //! Register Reset Value #define DESC1_6_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_9 Register DESC0_7_IGP_9 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_9 0x5070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_9 0x18F05070u //! Register Reset Value #define DESC0_7_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_9 Register DESC1_7_IGP_9 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_9 0x5078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_9 0x18F05078u //! Register Reset Value #define DESC1_7_IGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_10 Register DESC0_0_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_10 0x6000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_10 0x18F06000u //! Register Reset Value #define DESC0_0_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_10 Register DESC1_0_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_10 0x6008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_10 0x18F06008u //! Register Reset Value #define DESC1_0_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_10 Register DESC0_1_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_10 0x6010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_10 0x18F06010u //! Register Reset Value #define DESC0_1_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_10 Register DESC1_1_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_10 0x6018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_10 0x18F06018u //! Register Reset Value #define DESC1_1_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_10 Register DESC0_2_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_10 0x6020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_10 0x18F06020u //! Register Reset Value #define DESC0_2_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_10 Register DESC1_2_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_10 0x6028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_10 0x18F06028u //! Register Reset Value #define DESC1_2_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_10 Register DESC0_3_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_10 0x6030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_10 0x18F06030u //! Register Reset Value #define DESC0_3_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_10 Register DESC1_3_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_10 0x6038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_10 0x18F06038u //! Register Reset Value #define DESC1_3_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_10 Register DESC0_4_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_10 0x6040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_10 0x18F06040u //! Register Reset Value #define DESC0_4_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_10 Register DESC1_4_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_10 0x6048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_10 0x18F06048u //! Register Reset Value #define DESC1_4_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_10 Register DESC0_5_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_10 0x6050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_10 0x18F06050u //! Register Reset Value #define DESC0_5_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_10 Register DESC1_5_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_10 0x6058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_10 0x18F06058u //! Register Reset Value #define DESC1_5_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_10 Register DESC0_6_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_10 0x6060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_10 0x18F06060u //! Register Reset Value #define DESC0_6_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_10 Register DESC1_6_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_10 0x6068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_10 0x18F06068u //! Register Reset Value #define DESC1_6_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_10 Register DESC0_7_IGP_10 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_10 0x6070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_10 0x18F06070u //! Register Reset Value #define DESC0_7_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_10 Register DESC1_7_IGP_10 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_10 0x6078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_10 0x18F06078u //! Register Reset Value #define DESC1_7_IGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_11 Register DESC0_0_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_11 0x7000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_11 0x18F07000u //! Register Reset Value #define DESC0_0_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_11 Register DESC1_0_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_11 0x7008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_11 0x18F07008u //! Register Reset Value #define DESC1_0_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_11 Register DESC0_1_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_11 0x7010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_11 0x18F07010u //! Register Reset Value #define DESC0_1_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_11 Register DESC1_1_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_11 0x7018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_11 0x18F07018u //! Register Reset Value #define DESC1_1_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_11 Register DESC0_2_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_11 0x7020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_11 0x18F07020u //! Register Reset Value #define DESC0_2_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_11 Register DESC1_2_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_11 0x7028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_11 0x18F07028u //! Register Reset Value #define DESC1_2_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_11 Register DESC0_3_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_11 0x7030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_11 0x18F07030u //! Register Reset Value #define DESC0_3_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_11 Register DESC1_3_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_11 0x7038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_11 0x18F07038u //! Register Reset Value #define DESC1_3_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_11 Register DESC0_4_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_11 0x7040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_11 0x18F07040u //! Register Reset Value #define DESC0_4_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_11 Register DESC1_4_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_11 0x7048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_11 0x18F07048u //! Register Reset Value #define DESC1_4_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_11 Register DESC0_5_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_11 0x7050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_11 0x18F07050u //! Register Reset Value #define DESC0_5_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_11 Register DESC1_5_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_11 0x7058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_11 0x18F07058u //! Register Reset Value #define DESC1_5_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_11 Register DESC0_6_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_11 0x7060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_11 0x18F07060u //! Register Reset Value #define DESC0_6_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_11 Register DESC1_6_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_11 0x7068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_11 0x18F07068u //! Register Reset Value #define DESC1_6_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_11 Register DESC0_7_IGP_11 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_11 0x7070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_11 0x18F07070u //! Register Reset Value #define DESC0_7_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_11 Register DESC1_7_IGP_11 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_11 0x7078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_11 0x18F07078u //! Register Reset Value #define DESC1_7_IGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_12 Register DESC0_0_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_12 0x8000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_12 0x18F08000u //! Register Reset Value #define DESC0_0_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_12 Register DESC1_0_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_12 0x8008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_12 0x18F08008u //! Register Reset Value #define DESC1_0_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_12 Register DESC0_1_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_12 0x8010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_12 0x18F08010u //! Register Reset Value #define DESC0_1_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_12 Register DESC1_1_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_12 0x8018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_12 0x18F08018u //! Register Reset Value #define DESC1_1_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_12 Register DESC0_2_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_12 0x8020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_12 0x18F08020u //! Register Reset Value #define DESC0_2_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_12 Register DESC1_2_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_12 0x8028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_12 0x18F08028u //! Register Reset Value #define DESC1_2_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_12 Register DESC0_3_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_12 0x8030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_12 0x18F08030u //! Register Reset Value #define DESC0_3_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_12 Register DESC1_3_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_12 0x8038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_12 0x18F08038u //! Register Reset Value #define DESC1_3_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_12 Register DESC0_4_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_12 0x8040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_12 0x18F08040u //! Register Reset Value #define DESC0_4_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_12 Register DESC1_4_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_12 0x8048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_12 0x18F08048u //! Register Reset Value #define DESC1_4_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_12 Register DESC0_5_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_12 0x8050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_12 0x18F08050u //! Register Reset Value #define DESC0_5_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_12 Register DESC1_5_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_12 0x8058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_12 0x18F08058u //! Register Reset Value #define DESC1_5_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_12 Register DESC0_6_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_12 0x8060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_12 0x18F08060u //! Register Reset Value #define DESC0_6_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_12 Register DESC1_6_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_12 0x8068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_12 0x18F08068u //! Register Reset Value #define DESC1_6_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_12 Register DESC0_7_IGP_12 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_12 0x8070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_12 0x18F08070u //! Register Reset Value #define DESC0_7_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_12 Register DESC1_7_IGP_12 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_12 0x8078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_12 0x18F08078u //! Register Reset Value #define DESC1_7_IGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_13 Register DESC0_0_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_13 0x9000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_13 0x18F09000u //! Register Reset Value #define DESC0_0_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_13 Register DESC1_0_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_13 0x9008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_13 0x18F09008u //! Register Reset Value #define DESC1_0_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_13 Register DESC0_1_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_13 0x9010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_13 0x18F09010u //! Register Reset Value #define DESC0_1_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_13 Register DESC1_1_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_13 0x9018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_13 0x18F09018u //! Register Reset Value #define DESC1_1_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_13 Register DESC0_2_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_13 0x9020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_13 0x18F09020u //! Register Reset Value #define DESC0_2_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_13 Register DESC1_2_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_13 0x9028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_13 0x18F09028u //! Register Reset Value #define DESC1_2_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_13 Register DESC0_3_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_13 0x9030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_13 0x18F09030u //! Register Reset Value #define DESC0_3_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_13 Register DESC1_3_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_13 0x9038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_13 0x18F09038u //! Register Reset Value #define DESC1_3_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_13 Register DESC0_4_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_13 0x9040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_13 0x18F09040u //! Register Reset Value #define DESC0_4_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_13 Register DESC1_4_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_13 0x9048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_13 0x18F09048u //! Register Reset Value #define DESC1_4_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_13 Register DESC0_5_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_13 0x9050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_13 0x18F09050u //! Register Reset Value #define DESC0_5_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_13 Register DESC1_5_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_13 0x9058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_13 0x18F09058u //! Register Reset Value #define DESC1_5_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_13 Register DESC0_6_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_13 0x9060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_13 0x18F09060u //! Register Reset Value #define DESC0_6_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_13 Register DESC1_6_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_13 0x9068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_13 0x18F09068u //! Register Reset Value #define DESC1_6_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_13 Register DESC0_7_IGP_13 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_13 0x9070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_13 0x18F09070u //! Register Reset Value #define DESC0_7_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_13 Register DESC1_7_IGP_13 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_13 0x9078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_13 0x18F09078u //! Register Reset Value #define DESC1_7_IGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_14 Register DESC0_0_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_14 0xA000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_14 0x18F0A000u //! Register Reset Value #define DESC0_0_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_14 Register DESC1_0_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_14 0xA008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_14 0x18F0A008u //! Register Reset Value #define DESC1_0_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_14 Register DESC0_1_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_14 0xA010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_14 0x18F0A010u //! Register Reset Value #define DESC0_1_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_14 Register DESC1_1_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_14 0xA018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_14 0x18F0A018u //! Register Reset Value #define DESC1_1_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_14 Register DESC0_2_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_14 0xA020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_14 0x18F0A020u //! Register Reset Value #define DESC0_2_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_14 Register DESC1_2_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_14 0xA028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_14 0x18F0A028u //! Register Reset Value #define DESC1_2_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_14 Register DESC0_3_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_14 0xA030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_14 0x18F0A030u //! Register Reset Value #define DESC0_3_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_14 Register DESC1_3_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_14 0xA038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_14 0x18F0A038u //! Register Reset Value #define DESC1_3_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_14 Register DESC0_4_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_14 0xA040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_14 0x18F0A040u //! Register Reset Value #define DESC0_4_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_14 Register DESC1_4_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_14 0xA048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_14 0x18F0A048u //! Register Reset Value #define DESC1_4_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_14 Register DESC0_5_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_14 0xA050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_14 0x18F0A050u //! Register Reset Value #define DESC0_5_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_14 Register DESC1_5_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_14 0xA058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_14 0x18F0A058u //! Register Reset Value #define DESC1_5_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_14 Register DESC0_6_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_14 0xA060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_14 0x18F0A060u //! Register Reset Value #define DESC0_6_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_14 Register DESC1_6_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_14 0xA068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_14 0x18F0A068u //! Register Reset Value #define DESC1_6_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_14 Register DESC0_7_IGP_14 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_14 0xA070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_14 0x18F0A070u //! Register Reset Value #define DESC0_7_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_14 Register DESC1_7_IGP_14 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_14 0xA078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_14 0x18F0A078u //! Register Reset Value #define DESC1_7_IGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_IGP_15 Register DESC0_0_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_IGP_15 0xB000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_IGP_15 0x18F0B000u //! Register Reset Value #define DESC0_0_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_IGP_15 Register DESC1_0_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_IGP_15 0xB008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_IGP_15 0x18F0B008u //! Register Reset Value #define DESC1_0_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_IGP_15 Register DESC0_1_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_IGP_15 0xB010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_IGP_15 0x18F0B010u //! Register Reset Value #define DESC0_1_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_IGP_15 Register DESC1_1_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_IGP_15 0xB018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_IGP_15 0x18F0B018u //! Register Reset Value #define DESC1_1_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_IGP_15 Register DESC0_2_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_IGP_15 0xB020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_IGP_15 0x18F0B020u //! Register Reset Value #define DESC0_2_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_IGP_15 Register DESC1_2_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_IGP_15 0xB028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_IGP_15 0x18F0B028u //! Register Reset Value #define DESC1_2_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_IGP_15 Register DESC0_3_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_IGP_15 0xB030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_IGP_15 0x18F0B030u //! Register Reset Value #define DESC0_3_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_IGP_15 Register DESC1_3_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_IGP_15 0xB038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_IGP_15 0x18F0B038u //! Register Reset Value #define DESC1_3_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_IGP_15 Register DESC0_4_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_IGP_15 0xB040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_IGP_15 0x18F0B040u //! Register Reset Value #define DESC0_4_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_IGP_15 Register DESC1_4_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_IGP_15 0xB048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_IGP_15 0x18F0B048u //! Register Reset Value #define DESC1_4_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_IGP_15 Register DESC0_5_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_IGP_15 0xB050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_IGP_15 0x18F0B050u //! Register Reset Value #define DESC0_5_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_IGP_15 Register DESC1_5_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_IGP_15 0xB058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_IGP_15 0x18F0B058u //! Register Reset Value #define DESC1_5_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_IGP_15 Register DESC0_6_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_IGP_15 0xB060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_IGP_15 0x18F0B060u //! Register Reset Value #define DESC0_6_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_IGP_15 Register DESC1_6_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_IGP_15 0xB068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_IGP_15 0x18F0B068u //! Register Reset Value #define DESC1_6_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_IGP_15 Register DESC0_7_IGP_15 - Ingress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_IGP_15 0xB070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_IGP_15 0x18F0B070u //! Register Reset Value #define DESC0_7_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_IGP_15 Register DESC1_7_IGP_15 - Ingress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_IGP_15 0xB078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_IGP_15 0x18F0B078u //! Register Reset Value #define DESC1_7_IGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_IGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_7 Register DESC0_0_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_7 0x40000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_7 0x18F40000u //! Register Reset Value #define DESC0_0_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_7 Register DESC1_0_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_7 0x40008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_7 0x18F40008u //! Register Reset Value #define DESC1_0_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_7 Register DESC0_1_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_7 0x40010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_7 0x18F40010u //! Register Reset Value #define DESC0_1_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_7 Register DESC1_1_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_7 0x40018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_7 0x18F40018u //! Register Reset Value #define DESC1_1_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_7 Register DESC0_2_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_7 0x40020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_7 0x18F40020u //! Register Reset Value #define DESC0_2_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_7 Register DESC1_2_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_7 0x40028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_7 0x18F40028u //! Register Reset Value #define DESC1_2_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_7 Register DESC0_3_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_7 0x40030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_7 0x18F40030u //! Register Reset Value #define DESC0_3_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_7 Register DESC1_3_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_7 0x40038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_7 0x18F40038u //! Register Reset Value #define DESC1_3_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_7 Register DESC0_4_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_7 0x40040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_7 0x18F40040u //! Register Reset Value #define DESC0_4_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_7 Register DESC1_4_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_7 0x40048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_7 0x18F40048u //! Register Reset Value #define DESC1_4_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_7 Register DESC0_5_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_7 0x40050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_7 0x18F40050u //! Register Reset Value #define DESC0_5_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_7 Register DESC1_5_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_7 0x40058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_7 0x18F40058u //! Register Reset Value #define DESC1_5_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_7 Register DESC0_6_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_7 0x40060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_7 0x18F40060u //! Register Reset Value #define DESC0_6_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_7 Register DESC1_6_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_7 0x40068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_7 0x18F40068u //! Register Reset Value #define DESC1_6_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_7 Register DESC0_7_EGP_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_7 0x40070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_7 0x18F40070u //! Register Reset Value #define DESC0_7_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_7 Register DESC1_7_EGP_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_7 0x40078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_7 0x18F40078u //! Register Reset Value #define DESC1_7_EGP_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_8 Register DESC0_0_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_8 0x41000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_8 0x18F41000u //! Register Reset Value #define DESC0_0_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_8 Register DESC1_0_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_8 0x41008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_8 0x18F41008u //! Register Reset Value #define DESC1_0_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_8 Register DESC0_1_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_8 0x41010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_8 0x18F41010u //! Register Reset Value #define DESC0_1_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_8 Register DESC1_1_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_8 0x41018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_8 0x18F41018u //! Register Reset Value #define DESC1_1_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_8 Register DESC0_2_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_8 0x41020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_8 0x18F41020u //! Register Reset Value #define DESC0_2_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_8 Register DESC1_2_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_8 0x41028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_8 0x18F41028u //! Register Reset Value #define DESC1_2_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_8 Register DESC0_3_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_8 0x41030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_8 0x18F41030u //! Register Reset Value #define DESC0_3_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_8 Register DESC1_3_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_8 0x41038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_8 0x18F41038u //! Register Reset Value #define DESC1_3_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_8 Register DESC0_4_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_8 0x41040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_8 0x18F41040u //! Register Reset Value #define DESC0_4_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_8 Register DESC1_4_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_8 0x41048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_8 0x18F41048u //! Register Reset Value #define DESC1_4_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_8 Register DESC0_5_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_8 0x41050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_8 0x18F41050u //! Register Reset Value #define DESC0_5_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_8 Register DESC1_5_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_8 0x41058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_8 0x18F41058u //! Register Reset Value #define DESC1_5_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_8 Register DESC0_6_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_8 0x41060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_8 0x18F41060u //! Register Reset Value #define DESC0_6_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_8 Register DESC1_6_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_8 0x41068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_8 0x18F41068u //! Register Reset Value #define DESC1_6_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_8 Register DESC0_7_EGP_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_8 0x41070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_8 0x18F41070u //! Register Reset Value #define DESC0_7_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_8 Register DESC1_7_EGP_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_8 0x41078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_8 0x18F41078u //! Register Reset Value #define DESC1_7_EGP_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_9 Register DESC0_0_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_9 0x42000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_9 0x18F42000u //! Register Reset Value #define DESC0_0_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_9 Register DESC1_0_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_9 0x42008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_9 0x18F42008u //! Register Reset Value #define DESC1_0_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_9 Register DESC0_1_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_9 0x42010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_9 0x18F42010u //! Register Reset Value #define DESC0_1_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_9 Register DESC1_1_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_9 0x42018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_9 0x18F42018u //! Register Reset Value #define DESC1_1_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_9 Register DESC0_2_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_9 0x42020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_9 0x18F42020u //! Register Reset Value #define DESC0_2_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_9 Register DESC1_2_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_9 0x42028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_9 0x18F42028u //! Register Reset Value #define DESC1_2_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_9 Register DESC0_3_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_9 0x42030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_9 0x18F42030u //! Register Reset Value #define DESC0_3_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_9 Register DESC1_3_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_9 0x42038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_9 0x18F42038u //! Register Reset Value #define DESC1_3_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_9 Register DESC0_4_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_9 0x42040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_9 0x18F42040u //! Register Reset Value #define DESC0_4_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_9 Register DESC1_4_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_9 0x42048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_9 0x18F42048u //! Register Reset Value #define DESC1_4_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_9 Register DESC0_5_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_9 0x42050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_9 0x18F42050u //! Register Reset Value #define DESC0_5_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_9 Register DESC1_5_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_9 0x42058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_9 0x18F42058u //! Register Reset Value #define DESC1_5_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_9 Register DESC0_6_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_9 0x42060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_9 0x18F42060u //! Register Reset Value #define DESC0_6_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_9 Register DESC1_6_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_9 0x42068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_9 0x18F42068u //! Register Reset Value #define DESC1_6_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_9 Register DESC0_7_EGP_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_9 0x42070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_9 0x18F42070u //! Register Reset Value #define DESC0_7_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_9 Register DESC1_7_EGP_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_9 0x42078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_9 0x18F42078u //! Register Reset Value #define DESC1_7_EGP_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_10 Register DESC0_0_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_10 0x43000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_10 0x18F43000u //! Register Reset Value #define DESC0_0_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_10 Register DESC1_0_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_10 0x43008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_10 0x18F43008u //! Register Reset Value #define DESC1_0_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_10 Register DESC0_1_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_10 0x43010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_10 0x18F43010u //! Register Reset Value #define DESC0_1_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_10 Register DESC1_1_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_10 0x43018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_10 0x18F43018u //! Register Reset Value #define DESC1_1_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_10 Register DESC0_2_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_10 0x43020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_10 0x18F43020u //! Register Reset Value #define DESC0_2_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_10 Register DESC1_2_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_10 0x43028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_10 0x18F43028u //! Register Reset Value #define DESC1_2_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_10 Register DESC0_3_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_10 0x43030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_10 0x18F43030u //! Register Reset Value #define DESC0_3_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_10 Register DESC1_3_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_10 0x43038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_10 0x18F43038u //! Register Reset Value #define DESC1_3_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_10 Register DESC0_4_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_10 0x43040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_10 0x18F43040u //! Register Reset Value #define DESC0_4_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_10 Register DESC1_4_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_10 0x43048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_10 0x18F43048u //! Register Reset Value #define DESC1_4_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_10 Register DESC0_5_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_10 0x43050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_10 0x18F43050u //! Register Reset Value #define DESC0_5_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_10 Register DESC1_5_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_10 0x43058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_10 0x18F43058u //! Register Reset Value #define DESC1_5_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_10 Register DESC0_6_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_10 0x43060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_10 0x18F43060u //! Register Reset Value #define DESC0_6_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_10 Register DESC1_6_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_10 0x43068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_10 0x18F43068u //! Register Reset Value #define DESC1_6_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_10 Register DESC0_7_EGP_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_10 0x43070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_10 0x18F43070u //! Register Reset Value #define DESC0_7_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_10 Register DESC1_7_EGP_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_10 0x43078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_10 0x18F43078u //! Register Reset Value #define DESC1_7_EGP_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_11 Register DESC0_0_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_11 0x44000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_11 0x18F44000u //! Register Reset Value #define DESC0_0_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_11 Register DESC1_0_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_11 0x44008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_11 0x18F44008u //! Register Reset Value #define DESC1_0_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_11 Register DESC0_1_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_11 0x44010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_11 0x18F44010u //! Register Reset Value #define DESC0_1_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_11 Register DESC1_1_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_11 0x44018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_11 0x18F44018u //! Register Reset Value #define DESC1_1_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_11 Register DESC0_2_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_11 0x44020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_11 0x18F44020u //! Register Reset Value #define DESC0_2_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_11 Register DESC1_2_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_11 0x44028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_11 0x18F44028u //! Register Reset Value #define DESC1_2_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_11 Register DESC0_3_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_11 0x44030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_11 0x18F44030u //! Register Reset Value #define DESC0_3_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_11 Register DESC1_3_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_11 0x44038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_11 0x18F44038u //! Register Reset Value #define DESC1_3_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_11 Register DESC0_4_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_11 0x44040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_11 0x18F44040u //! Register Reset Value #define DESC0_4_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_11 Register DESC1_4_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_11 0x44048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_11 0x18F44048u //! Register Reset Value #define DESC1_4_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_11 Register DESC0_5_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_11 0x44050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_11 0x18F44050u //! Register Reset Value #define DESC0_5_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_11 Register DESC1_5_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_11 0x44058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_11 0x18F44058u //! Register Reset Value #define DESC1_5_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_11 Register DESC0_6_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_11 0x44060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_11 0x18F44060u //! Register Reset Value #define DESC0_6_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_11 Register DESC1_6_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_11 0x44068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_11 0x18F44068u //! Register Reset Value #define DESC1_6_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_11 Register DESC0_7_EGP_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_11 0x44070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_11 0x18F44070u //! Register Reset Value #define DESC0_7_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_11 Register DESC1_7_EGP_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_11 0x44078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_11 0x18F44078u //! Register Reset Value #define DESC1_7_EGP_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_12 Register DESC0_0_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_12 0x45000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_12 0x18F45000u //! Register Reset Value #define DESC0_0_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_12 Register DESC1_0_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_12 0x45008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_12 0x18F45008u //! Register Reset Value #define DESC1_0_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_12 Register DESC0_1_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_12 0x45010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_12 0x18F45010u //! Register Reset Value #define DESC0_1_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_12 Register DESC1_1_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_12 0x45018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_12 0x18F45018u //! Register Reset Value #define DESC1_1_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_12 Register DESC0_2_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_12 0x45020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_12 0x18F45020u //! Register Reset Value #define DESC0_2_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_12 Register DESC1_2_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_12 0x45028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_12 0x18F45028u //! Register Reset Value #define DESC1_2_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_12 Register DESC0_3_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_12 0x45030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_12 0x18F45030u //! Register Reset Value #define DESC0_3_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_12 Register DESC1_3_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_12 0x45038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_12 0x18F45038u //! Register Reset Value #define DESC1_3_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_12 Register DESC0_4_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_12 0x45040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_12 0x18F45040u //! Register Reset Value #define DESC0_4_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_12 Register DESC1_4_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_12 0x45048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_12 0x18F45048u //! Register Reset Value #define DESC1_4_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_12 Register DESC0_5_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_12 0x45050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_12 0x18F45050u //! Register Reset Value #define DESC0_5_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_12 Register DESC1_5_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_12 0x45058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_12 0x18F45058u //! Register Reset Value #define DESC1_5_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_12 Register DESC0_6_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_12 0x45060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_12 0x18F45060u //! Register Reset Value #define DESC0_6_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_12 Register DESC1_6_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_12 0x45068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_12 0x18F45068u //! Register Reset Value #define DESC1_6_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_12 Register DESC0_7_EGP_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_12 0x45070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_12 0x18F45070u //! Register Reset Value #define DESC0_7_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_12 Register DESC1_7_EGP_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_12 0x45078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_12 0x18F45078u //! Register Reset Value #define DESC1_7_EGP_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_13 Register DESC0_0_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_13 0x46000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_13 0x18F46000u //! Register Reset Value #define DESC0_0_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_13 Register DESC1_0_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_13 0x46008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_13 0x18F46008u //! Register Reset Value #define DESC1_0_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_13 Register DESC0_1_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_13 0x46010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_13 0x18F46010u //! Register Reset Value #define DESC0_1_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_13 Register DESC1_1_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_13 0x46018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_13 0x18F46018u //! Register Reset Value #define DESC1_1_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_13 Register DESC0_2_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_13 0x46020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_13 0x18F46020u //! Register Reset Value #define DESC0_2_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_13 Register DESC1_2_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_13 0x46028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_13 0x18F46028u //! Register Reset Value #define DESC1_2_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_13 Register DESC0_3_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_13 0x46030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_13 0x18F46030u //! Register Reset Value #define DESC0_3_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_13 Register DESC1_3_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_13 0x46038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_13 0x18F46038u //! Register Reset Value #define DESC1_3_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_13 Register DESC0_4_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_13 0x46040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_13 0x18F46040u //! Register Reset Value #define DESC0_4_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_13 Register DESC1_4_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_13 0x46048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_13 0x18F46048u //! Register Reset Value #define DESC1_4_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_13 Register DESC0_5_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_13 0x46050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_13 0x18F46050u //! Register Reset Value #define DESC0_5_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_13 Register DESC1_5_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_13 0x46058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_13 0x18F46058u //! Register Reset Value #define DESC1_5_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_13 Register DESC0_6_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_13 0x46060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_13 0x18F46060u //! Register Reset Value #define DESC0_6_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_13 Register DESC1_6_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_13 0x46068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_13 0x18F46068u //! Register Reset Value #define DESC1_6_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_13 Register DESC0_7_EGP_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_13 0x46070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_13 0x18F46070u //! Register Reset Value #define DESC0_7_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_13 Register DESC1_7_EGP_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_13 0x46078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_13 0x18F46078u //! Register Reset Value #define DESC1_7_EGP_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_14 Register DESC0_0_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_14 0x47000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_14 0x18F47000u //! Register Reset Value #define DESC0_0_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_14 Register DESC1_0_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_14 0x47008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_14 0x18F47008u //! Register Reset Value #define DESC1_0_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_14 Register DESC0_1_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_14 0x47010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_14 0x18F47010u //! Register Reset Value #define DESC0_1_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_14 Register DESC1_1_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_14 0x47018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_14 0x18F47018u //! Register Reset Value #define DESC1_1_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_14 Register DESC0_2_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_14 0x47020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_14 0x18F47020u //! Register Reset Value #define DESC0_2_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_14 Register DESC1_2_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_14 0x47028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_14 0x18F47028u //! Register Reset Value #define DESC1_2_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_14 Register DESC0_3_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_14 0x47030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_14 0x18F47030u //! Register Reset Value #define DESC0_3_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_14 Register DESC1_3_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_14 0x47038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_14 0x18F47038u //! Register Reset Value #define DESC1_3_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_14 Register DESC0_4_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_14 0x47040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_14 0x18F47040u //! Register Reset Value #define DESC0_4_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_14 Register DESC1_4_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_14 0x47048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_14 0x18F47048u //! Register Reset Value #define DESC1_4_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_14 Register DESC0_5_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_14 0x47050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_14 0x18F47050u //! Register Reset Value #define DESC0_5_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_14 Register DESC1_5_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_14 0x47058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_14 0x18F47058u //! Register Reset Value #define DESC1_5_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_14 Register DESC0_6_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_14 0x47060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_14 0x18F47060u //! Register Reset Value #define DESC0_6_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_14 Register DESC1_6_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_14 0x47068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_14 0x18F47068u //! Register Reset Value #define DESC1_6_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_14 Register DESC0_7_EGP_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_14 0x47070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_14 0x18F47070u //! Register Reset Value #define DESC0_7_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_14 Register DESC1_7_EGP_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_14 0x47078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_14 0x18F47078u //! Register Reset Value #define DESC1_7_EGP_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_15 Register DESC0_0_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_15 0x48000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_15 0x18F48000u //! Register Reset Value #define DESC0_0_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_15 Register DESC1_0_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_15 0x48008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_15 0x18F48008u //! Register Reset Value #define DESC1_0_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_15 Register DESC0_1_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_15 0x48010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_15 0x18F48010u //! Register Reset Value #define DESC0_1_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_15 Register DESC1_1_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_15 0x48018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_15 0x18F48018u //! Register Reset Value #define DESC1_1_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_15 Register DESC0_2_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_15 0x48020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_15 0x18F48020u //! Register Reset Value #define DESC0_2_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_15 Register DESC1_2_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_15 0x48028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_15 0x18F48028u //! Register Reset Value #define DESC1_2_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_15 Register DESC0_3_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_15 0x48030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_15 0x18F48030u //! Register Reset Value #define DESC0_3_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_15 Register DESC1_3_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_15 0x48038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_15 0x18F48038u //! Register Reset Value #define DESC1_3_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_15 Register DESC0_4_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_15 0x48040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_15 0x18F48040u //! Register Reset Value #define DESC0_4_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_15 Register DESC1_4_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_15 0x48048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_15 0x18F48048u //! Register Reset Value #define DESC1_4_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_15 Register DESC0_5_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_15 0x48050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_15 0x18F48050u //! Register Reset Value #define DESC0_5_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_15 Register DESC1_5_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_15 0x48058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_15 0x18F48058u //! Register Reset Value #define DESC1_5_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_15 Register DESC0_6_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_15 0x48060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_15 0x18F48060u //! Register Reset Value #define DESC0_6_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_15 Register DESC1_6_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_15 0x48068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_15 0x18F48068u //! Register Reset Value #define DESC1_6_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_15 Register DESC0_7_EGP_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_15 0x48070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_15 0x18F48070u //! Register Reset Value #define DESC0_7_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_15 Register DESC1_7_EGP_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_15 0x48078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_15 0x18F48078u //! Register Reset Value #define DESC1_7_EGP_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_16 Register DESC0_0_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_16 0x49000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_16 0x18F49000u //! Register Reset Value #define DESC0_0_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_16 Register DESC1_0_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_16 0x49008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_16 0x18F49008u //! Register Reset Value #define DESC1_0_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_16 Register DESC0_1_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_16 0x49010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_16 0x18F49010u //! Register Reset Value #define DESC0_1_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_16 Register DESC1_1_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_16 0x49018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_16 0x18F49018u //! Register Reset Value #define DESC1_1_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_16 Register DESC0_2_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_16 0x49020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_16 0x18F49020u //! Register Reset Value #define DESC0_2_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_16 Register DESC1_2_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_16 0x49028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_16 0x18F49028u //! Register Reset Value #define DESC1_2_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_16 Register DESC0_3_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_16 0x49030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_16 0x18F49030u //! Register Reset Value #define DESC0_3_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_16 Register DESC1_3_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_16 0x49038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_16 0x18F49038u //! Register Reset Value #define DESC1_3_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_16 Register DESC0_4_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_16 0x49040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_16 0x18F49040u //! Register Reset Value #define DESC0_4_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_16 Register DESC1_4_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_16 0x49048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_16 0x18F49048u //! Register Reset Value #define DESC1_4_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_16 Register DESC0_5_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_16 0x49050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_16 0x18F49050u //! Register Reset Value #define DESC0_5_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_16 Register DESC1_5_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_16 0x49058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_16 0x18F49058u //! Register Reset Value #define DESC1_5_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_16 Register DESC0_6_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_16 0x49060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_16 0x18F49060u //! Register Reset Value #define DESC0_6_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_16 Register DESC1_6_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_16 0x49068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_16 0x18F49068u //! Register Reset Value #define DESC1_6_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_16 Register DESC0_7_EGP_16 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_16 0x49070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_16 0x18F49070u //! Register Reset Value #define DESC0_7_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_16 Register DESC1_7_EGP_16 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_16 0x49078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_16 0x18F49078u //! Register Reset Value #define DESC1_7_EGP_16_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_16_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_16_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_17 Register DESC0_0_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_17 0x4A000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_17 0x18F4A000u //! Register Reset Value #define DESC0_0_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_17 Register DESC1_0_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_17 0x4A008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_17 0x18F4A008u //! Register Reset Value #define DESC1_0_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_17 Register DESC0_1_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_17 0x4A010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_17 0x18F4A010u //! Register Reset Value #define DESC0_1_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_17 Register DESC1_1_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_17 0x4A018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_17 0x18F4A018u //! Register Reset Value #define DESC1_1_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_17 Register DESC0_2_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_17 0x4A020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_17 0x18F4A020u //! Register Reset Value #define DESC0_2_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_17 Register DESC1_2_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_17 0x4A028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_17 0x18F4A028u //! Register Reset Value #define DESC1_2_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_17 Register DESC0_3_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_17 0x4A030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_17 0x18F4A030u //! Register Reset Value #define DESC0_3_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_17 Register DESC1_3_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_17 0x4A038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_17 0x18F4A038u //! Register Reset Value #define DESC1_3_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_17 Register DESC0_4_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_17 0x4A040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_17 0x18F4A040u //! Register Reset Value #define DESC0_4_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_17 Register DESC1_4_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_17 0x4A048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_17 0x18F4A048u //! Register Reset Value #define DESC1_4_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_17 Register DESC0_5_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_17 0x4A050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_17 0x18F4A050u //! Register Reset Value #define DESC0_5_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_17 Register DESC1_5_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_17 0x4A058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_17 0x18F4A058u //! Register Reset Value #define DESC1_5_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_17 Register DESC0_6_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_17 0x4A060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_17 0x18F4A060u //! Register Reset Value #define DESC0_6_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_17 Register DESC1_6_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_17 0x4A068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_17 0x18F4A068u //! Register Reset Value #define DESC1_6_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_17 Register DESC0_7_EGP_17 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_17 0x4A070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_17 0x18F4A070u //! Register Reset Value #define DESC0_7_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_17 Register DESC1_7_EGP_17 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_17 0x4A078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_17 0x18F4A078u //! Register Reset Value #define DESC1_7_EGP_17_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_17_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_17_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_18 Register DESC0_0_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_18 0x4B000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_18 0x18F4B000u //! Register Reset Value #define DESC0_0_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_18 Register DESC1_0_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_18 0x4B008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_18 0x18F4B008u //! Register Reset Value #define DESC1_0_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_18 Register DESC0_1_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_18 0x4B010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_18 0x18F4B010u //! Register Reset Value #define DESC0_1_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_18 Register DESC1_1_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_18 0x4B018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_18 0x18F4B018u //! Register Reset Value #define DESC1_1_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_18 Register DESC0_2_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_18 0x4B020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_18 0x18F4B020u //! Register Reset Value #define DESC0_2_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_18 Register DESC1_2_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_18 0x4B028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_18 0x18F4B028u //! Register Reset Value #define DESC1_2_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_18 Register DESC0_3_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_18 0x4B030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_18 0x18F4B030u //! Register Reset Value #define DESC0_3_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_18 Register DESC1_3_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_18 0x4B038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_18 0x18F4B038u //! Register Reset Value #define DESC1_3_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_18 Register DESC0_4_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_18 0x4B040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_18 0x18F4B040u //! Register Reset Value #define DESC0_4_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_18 Register DESC1_4_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_18 0x4B048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_18 0x18F4B048u //! Register Reset Value #define DESC1_4_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_18 Register DESC0_5_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_18 0x4B050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_18 0x18F4B050u //! Register Reset Value #define DESC0_5_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_18 Register DESC1_5_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_18 0x4B058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_18 0x18F4B058u //! Register Reset Value #define DESC1_5_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_18 Register DESC0_6_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_18 0x4B060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_18 0x18F4B060u //! Register Reset Value #define DESC0_6_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_18 Register DESC1_6_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_18 0x4B068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_18 0x18F4B068u //! Register Reset Value #define DESC1_6_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_18 Register DESC0_7_EGP_18 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_18 0x4B070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_18 0x18F4B070u //! Register Reset Value #define DESC0_7_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_18 Register DESC1_7_EGP_18 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_18 0x4B078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_18 0x18F4B078u //! Register Reset Value #define DESC1_7_EGP_18_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_18_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_18_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_19 Register DESC0_0_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_19 0x4C000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_19 0x18F4C000u //! Register Reset Value #define DESC0_0_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_19 Register DESC1_0_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_19 0x4C008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_19 0x18F4C008u //! Register Reset Value #define DESC1_0_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_19 Register DESC0_1_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_19 0x4C010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_19 0x18F4C010u //! Register Reset Value #define DESC0_1_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_19 Register DESC1_1_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_19 0x4C018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_19 0x18F4C018u //! Register Reset Value #define DESC1_1_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_19 Register DESC0_2_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_19 0x4C020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_19 0x18F4C020u //! Register Reset Value #define DESC0_2_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_19 Register DESC1_2_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_19 0x4C028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_19 0x18F4C028u //! Register Reset Value #define DESC1_2_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_19 Register DESC0_3_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_19 0x4C030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_19 0x18F4C030u //! Register Reset Value #define DESC0_3_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_19 Register DESC1_3_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_19 0x4C038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_19 0x18F4C038u //! Register Reset Value #define DESC1_3_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_19 Register DESC0_4_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_19 0x4C040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_19 0x18F4C040u //! Register Reset Value #define DESC0_4_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_19 Register DESC1_4_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_19 0x4C048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_19 0x18F4C048u //! Register Reset Value #define DESC1_4_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_19 Register DESC0_5_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_19 0x4C050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_19 0x18F4C050u //! Register Reset Value #define DESC0_5_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_19 Register DESC1_5_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_19 0x4C058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_19 0x18F4C058u //! Register Reset Value #define DESC1_5_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_19 Register DESC0_6_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_19 0x4C060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_19 0x18F4C060u //! Register Reset Value #define DESC0_6_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_19 Register DESC1_6_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_19 0x4C068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_19 0x18F4C068u //! Register Reset Value #define DESC1_6_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_19 Register DESC0_7_EGP_19 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_19 0x4C070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_19 0x18F4C070u //! Register Reset Value #define DESC0_7_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_19 Register DESC1_7_EGP_19 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_19 0x4C078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_19 0x18F4C078u //! Register Reset Value #define DESC1_7_EGP_19_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_19_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_19_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_20 Register DESC0_0_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_20 0x4D000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_20 0x18F4D000u //! Register Reset Value #define DESC0_0_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_20 Register DESC1_0_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_20 0x4D008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_20 0x18F4D008u //! Register Reset Value #define DESC1_0_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_20 Register DESC0_1_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_20 0x4D010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_20 0x18F4D010u //! Register Reset Value #define DESC0_1_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_20 Register DESC1_1_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_20 0x4D018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_20 0x18F4D018u //! Register Reset Value #define DESC1_1_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_20 Register DESC0_2_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_20 0x4D020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_20 0x18F4D020u //! Register Reset Value #define DESC0_2_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_20 Register DESC1_2_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_20 0x4D028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_20 0x18F4D028u //! Register Reset Value #define DESC1_2_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_20 Register DESC0_3_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_20 0x4D030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_20 0x18F4D030u //! Register Reset Value #define DESC0_3_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_20 Register DESC1_3_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_20 0x4D038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_20 0x18F4D038u //! Register Reset Value #define DESC1_3_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_20 Register DESC0_4_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_20 0x4D040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_20 0x18F4D040u //! Register Reset Value #define DESC0_4_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_20 Register DESC1_4_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_20 0x4D048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_20 0x18F4D048u //! Register Reset Value #define DESC1_4_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_20 Register DESC0_5_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_20 0x4D050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_20 0x18F4D050u //! Register Reset Value #define DESC0_5_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_20 Register DESC1_5_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_20 0x4D058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_20 0x18F4D058u //! Register Reset Value #define DESC1_5_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_20 Register DESC0_6_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_20 0x4D060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_20 0x18F4D060u //! Register Reset Value #define DESC0_6_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_20 Register DESC1_6_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_20 0x4D068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_20 0x18F4D068u //! Register Reset Value #define DESC1_6_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_20 Register DESC0_7_EGP_20 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_20 0x4D070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_20 0x18F4D070u //! Register Reset Value #define DESC0_7_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_20 Register DESC1_7_EGP_20 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_20 0x4D078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_20 0x18F4D078u //! Register Reset Value #define DESC1_7_EGP_20_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_20_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_20_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_21 Register DESC0_0_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_21 0x4E000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_21 0x18F4E000u //! Register Reset Value #define DESC0_0_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_21 Register DESC1_0_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_21 0x4E008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_21 0x18F4E008u //! Register Reset Value #define DESC1_0_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_21 Register DESC0_1_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_21 0x4E010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_21 0x18F4E010u //! Register Reset Value #define DESC0_1_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_21 Register DESC1_1_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_21 0x4E018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_21 0x18F4E018u //! Register Reset Value #define DESC1_1_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_21 Register DESC0_2_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_21 0x4E020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_21 0x18F4E020u //! Register Reset Value #define DESC0_2_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_21 Register DESC1_2_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_21 0x4E028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_21 0x18F4E028u //! Register Reset Value #define DESC1_2_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_21 Register DESC0_3_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_21 0x4E030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_21 0x18F4E030u //! Register Reset Value #define DESC0_3_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_21 Register DESC1_3_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_21 0x4E038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_21 0x18F4E038u //! Register Reset Value #define DESC1_3_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_21 Register DESC0_4_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_21 0x4E040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_21 0x18F4E040u //! Register Reset Value #define DESC0_4_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_21 Register DESC1_4_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_21 0x4E048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_21 0x18F4E048u //! Register Reset Value #define DESC1_4_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_21 Register DESC0_5_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_21 0x4E050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_21 0x18F4E050u //! Register Reset Value #define DESC0_5_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_21 Register DESC1_5_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_21 0x4E058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_21 0x18F4E058u //! Register Reset Value #define DESC1_5_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_21 Register DESC0_6_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_21 0x4E060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_21 0x18F4E060u //! Register Reset Value #define DESC0_6_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_21 Register DESC1_6_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_21 0x4E068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_21 0x18F4E068u //! Register Reset Value #define DESC1_6_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_21 Register DESC0_7_EGP_21 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_21 0x4E070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_21 0x18F4E070u //! Register Reset Value #define DESC0_7_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_21 Register DESC1_7_EGP_21 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_21 0x4E078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_21 0x18F4E078u //! Register Reset Value #define DESC1_7_EGP_21_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_21_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_21_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_22 Register DESC0_0_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_22 0x4F000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_22 0x18F4F000u //! Register Reset Value #define DESC0_0_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_22 Register DESC1_0_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_22 0x4F008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_22 0x18F4F008u //! Register Reset Value #define DESC1_0_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_22 Register DESC0_1_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_22 0x4F010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_22 0x18F4F010u //! Register Reset Value #define DESC0_1_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_22 Register DESC1_1_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_22 0x4F018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_22 0x18F4F018u //! Register Reset Value #define DESC1_1_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_22 Register DESC0_2_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_22 0x4F020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_22 0x18F4F020u //! Register Reset Value #define DESC0_2_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_22 Register DESC1_2_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_22 0x4F028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_22 0x18F4F028u //! Register Reset Value #define DESC1_2_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_22 Register DESC0_3_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_22 0x4F030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_22 0x18F4F030u //! Register Reset Value #define DESC0_3_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_22 Register DESC1_3_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_22 0x4F038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_22 0x18F4F038u //! Register Reset Value #define DESC1_3_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_22 Register DESC0_4_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_22 0x4F040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_22 0x18F4F040u //! Register Reset Value #define DESC0_4_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_22 Register DESC1_4_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_22 0x4F048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_22 0x18F4F048u //! Register Reset Value #define DESC1_4_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_22 Register DESC0_5_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_22 0x4F050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_22 0x18F4F050u //! Register Reset Value #define DESC0_5_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_22 Register DESC1_5_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_22 0x4F058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_22 0x18F4F058u //! Register Reset Value #define DESC1_5_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_22 Register DESC0_6_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_22 0x4F060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_22 0x18F4F060u //! Register Reset Value #define DESC0_6_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_22 Register DESC1_6_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_22 0x4F068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_22 0x18F4F068u //! Register Reset Value #define DESC1_6_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_22 Register DESC0_7_EGP_22 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_22 0x4F070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_22 0x18F4F070u //! Register Reset Value #define DESC0_7_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_22 Register DESC1_7_EGP_22 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_22 0x4F078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_22 0x18F4F078u //! Register Reset Value #define DESC1_7_EGP_22_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_22_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_22_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_23 Register DESC0_0_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_23 0x50000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_23 0x18F50000u //! Register Reset Value #define DESC0_0_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_23 Register DESC1_0_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_23 0x50008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_23 0x18F50008u //! Register Reset Value #define DESC1_0_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_23 Register DESC0_1_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_23 0x50010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_23 0x18F50010u //! Register Reset Value #define DESC0_1_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_23 Register DESC1_1_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_23 0x50018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_23 0x18F50018u //! Register Reset Value #define DESC1_1_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_23 Register DESC0_2_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_23 0x50020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_23 0x18F50020u //! Register Reset Value #define DESC0_2_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_23 Register DESC1_2_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_23 0x50028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_23 0x18F50028u //! Register Reset Value #define DESC1_2_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_23 Register DESC0_3_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_23 0x50030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_23 0x18F50030u //! Register Reset Value #define DESC0_3_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_23 Register DESC1_3_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_23 0x50038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_23 0x18F50038u //! Register Reset Value #define DESC1_3_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_23 Register DESC0_4_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_23 0x50040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_23 0x18F50040u //! Register Reset Value #define DESC0_4_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_23 Register DESC1_4_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_23 0x50048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_23 0x18F50048u //! Register Reset Value #define DESC1_4_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_23 Register DESC0_5_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_23 0x50050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_23 0x18F50050u //! Register Reset Value #define DESC0_5_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_23 Register DESC1_5_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_23 0x50058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_23 0x18F50058u //! Register Reset Value #define DESC1_5_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_23 Register DESC0_6_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_23 0x50060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_23 0x18F50060u //! Register Reset Value #define DESC0_6_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_23 Register DESC1_6_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_23 0x50068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_23 0x18F50068u //! Register Reset Value #define DESC1_6_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_23 Register DESC0_7_EGP_23 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_23 0x50070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_23 0x18F50070u //! Register Reset Value #define DESC0_7_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_23 Register DESC1_7_EGP_23 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_23 0x50078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_23 0x18F50078u //! Register Reset Value #define DESC1_7_EGP_23_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_23_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_23_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_24 Register DESC0_0_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_24 0x51000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_24 0x18F51000u //! Register Reset Value #define DESC0_0_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_24 Register DESC1_0_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_24 0x51008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_24 0x18F51008u //! Register Reset Value #define DESC1_0_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_24 Register DESC0_1_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_24 0x51010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_24 0x18F51010u //! Register Reset Value #define DESC0_1_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_24 Register DESC1_1_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_24 0x51018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_24 0x18F51018u //! Register Reset Value #define DESC1_1_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_24 Register DESC0_2_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_24 0x51020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_24 0x18F51020u //! Register Reset Value #define DESC0_2_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_24 Register DESC1_2_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_24 0x51028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_24 0x18F51028u //! Register Reset Value #define DESC1_2_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_24 Register DESC0_3_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_24 0x51030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_24 0x18F51030u //! Register Reset Value #define DESC0_3_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_24 Register DESC1_3_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_24 0x51038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_24 0x18F51038u //! Register Reset Value #define DESC1_3_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_24 Register DESC0_4_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_24 0x51040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_24 0x18F51040u //! Register Reset Value #define DESC0_4_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_24 Register DESC1_4_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_24 0x51048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_24 0x18F51048u //! Register Reset Value #define DESC1_4_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_24 Register DESC0_5_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_24 0x51050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_24 0x18F51050u //! Register Reset Value #define DESC0_5_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_24 Register DESC1_5_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_24 0x51058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_24 0x18F51058u //! Register Reset Value #define DESC1_5_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_24 Register DESC0_6_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_24 0x51060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_24 0x18F51060u //! Register Reset Value #define DESC0_6_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_24 Register DESC1_6_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_24 0x51068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_24 0x18F51068u //! Register Reset Value #define DESC1_6_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_24 Register DESC0_7_EGP_24 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_24 0x51070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_24 0x18F51070u //! Register Reset Value #define DESC0_7_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_24 Register DESC1_7_EGP_24 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_24 0x51078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_24 0x18F51078u //! Register Reset Value #define DESC1_7_EGP_24_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_24_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_24_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_0_EGP_25 Register DESC0_0_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_0_EGP_25 0x52000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_0_EGP_25 0x18F52000u //! Register Reset Value #define DESC0_0_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_0_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_0_EGP_25 Register DESC1_0_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_0_EGP_25 0x52008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_0_EGP_25 0x18F52008u //! Register Reset Value #define DESC1_0_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_0_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_1_EGP_25 Register DESC0_1_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_1_EGP_25 0x52010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_1_EGP_25 0x18F52010u //! Register Reset Value #define DESC0_1_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_1_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_1_EGP_25 Register DESC1_1_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_1_EGP_25 0x52018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_1_EGP_25 0x18F52018u //! Register Reset Value #define DESC1_1_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_1_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_2_EGP_25 Register DESC0_2_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_2_EGP_25 0x52020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_2_EGP_25 0x18F52020u //! Register Reset Value #define DESC0_2_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_2_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_2_EGP_25 Register DESC1_2_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_2_EGP_25 0x52028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_2_EGP_25 0x18F52028u //! Register Reset Value #define DESC1_2_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_2_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_3_EGP_25 Register DESC0_3_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_3_EGP_25 0x52030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_3_EGP_25 0x18F52030u //! Register Reset Value #define DESC0_3_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_3_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_3_EGP_25 Register DESC1_3_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_3_EGP_25 0x52038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_3_EGP_25 0x18F52038u //! Register Reset Value #define DESC1_3_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_3_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_4_EGP_25 Register DESC0_4_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_4_EGP_25 0x52040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_4_EGP_25 0x18F52040u //! Register Reset Value #define DESC0_4_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_4_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_4_EGP_25 Register DESC1_4_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_4_EGP_25 0x52048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_4_EGP_25 0x18F52048u //! Register Reset Value #define DESC1_4_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_4_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_5_EGP_25 Register DESC0_5_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_5_EGP_25 0x52050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_5_EGP_25 0x18F52050u //! Register Reset Value #define DESC0_5_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_5_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_5_EGP_25 Register DESC1_5_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_5_EGP_25 0x52058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_5_EGP_25 0x18F52058u //! Register Reset Value #define DESC1_5_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_5_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_6_EGP_25 Register DESC0_6_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_6_EGP_25 0x52060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_6_EGP_25 0x18F52060u //! Register Reset Value #define DESC0_6_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_6_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_6_EGP_25 Register DESC1_6_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_6_EGP_25 0x52068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_6_EGP_25 0x18F52068u //! Register Reset Value #define DESC1_6_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_6_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_7_EGP_25 Register DESC0_7_EGP_25 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_7_EGP_25 0x52070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_7_EGP_25 0x18F52070u //! Register Reset Value #define DESC0_7_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_7_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_7_EGP_25 Register DESC1_7_EGP_25 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_7_EGP_25 0x52078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_7_EGP_25 0x18F52078u //! Register Reset Value #define DESC1_7_EGP_25_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_25_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_7_EGP_25_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_0 Register DESC0_EGP_PON_0 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_0 0x60000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_0 0x18F60000u //! Register Reset Value #define DESC0_EGP_PON_0_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_0_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_0_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_0 Register DESC1_EGP_PON_0 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_0 0x60008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_0 0x18F60008u //! Register Reset Value #define DESC1_EGP_PON_0_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_0_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_0_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_1 Register DESC0_EGP_PON_1 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_1 0x60010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_1 0x18F60010u //! Register Reset Value #define DESC0_EGP_PON_1_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_1_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_1_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_1 Register DESC1_EGP_PON_1 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_1 0x60018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_1 0x18F60018u //! Register Reset Value #define DESC1_EGP_PON_1_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_1_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_1_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_2 Register DESC0_EGP_PON_2 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_2 0x60020 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_2 0x18F60020u //! Register Reset Value #define DESC0_EGP_PON_2_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_2_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_2_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_2 Register DESC1_EGP_PON_2 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_2 0x60028 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_2 0x18F60028u //! Register Reset Value #define DESC1_EGP_PON_2_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_2_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_2_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_3 Register DESC0_EGP_PON_3 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_3 0x60030 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_3 0x18F60030u //! Register Reset Value #define DESC0_EGP_PON_3_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_3_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_3_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_3 Register DESC1_EGP_PON_3 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_3 0x60038 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_3 0x18F60038u //! Register Reset Value #define DESC1_EGP_PON_3_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_3_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_3_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_4 Register DESC0_EGP_PON_4 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_4 0x60040 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_4 0x18F60040u //! Register Reset Value #define DESC0_EGP_PON_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_4 Register DESC1_EGP_PON_4 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_4 0x60048 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_4 0x18F60048u //! Register Reset Value #define DESC1_EGP_PON_4_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_4_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_4_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_5 Register DESC0_EGP_PON_5 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_5 0x60050 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_5 0x18F60050u //! Register Reset Value #define DESC0_EGP_PON_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_5 Register DESC1_EGP_PON_5 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_5 0x60058 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_5 0x18F60058u //! Register Reset Value #define DESC1_EGP_PON_5_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_5_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_5_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_6 Register DESC0_EGP_PON_6 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_6 0x60060 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_6 0x18F60060u //! Register Reset Value #define DESC0_EGP_PON_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_6 Register DESC1_EGP_PON_6 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_6 0x60068 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_6 0x18F60068u //! Register Reset Value #define DESC1_EGP_PON_6_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_6_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_6_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_7 Register DESC0_EGP_PON_7 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_7 0x60070 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_7 0x18F60070u //! Register Reset Value #define DESC0_EGP_PON_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_7 Register DESC1_EGP_PON_7 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_7 0x60078 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_7 0x18F60078u //! Register Reset Value #define DESC1_EGP_PON_7_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_7_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_7_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_8 Register DESC0_EGP_PON_8 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_8 0x60080 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_8 0x18F60080u //! Register Reset Value #define DESC0_EGP_PON_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_8 Register DESC1_EGP_PON_8 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_8 0x60088 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_8 0x18F60088u //! Register Reset Value #define DESC1_EGP_PON_8_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_8_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_8_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_9 Register DESC0_EGP_PON_9 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_9 0x60090 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_9 0x18F60090u //! Register Reset Value #define DESC0_EGP_PON_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_9 Register DESC1_EGP_PON_9 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_9 0x60098 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_9 0x18F60098u //! Register Reset Value #define DESC1_EGP_PON_9_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_9_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_9_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_10 Register DESC0_EGP_PON_10 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_10 0x600A0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_10 0x18F600A0u //! Register Reset Value #define DESC0_EGP_PON_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_10 Register DESC1_EGP_PON_10 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_10 0x600A8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_10 0x18F600A8u //! Register Reset Value #define DESC1_EGP_PON_10_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_10_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_10_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_11 Register DESC0_EGP_PON_11 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_11 0x600B0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_11 0x18F600B0u //! Register Reset Value #define DESC0_EGP_PON_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_11 Register DESC1_EGP_PON_11 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_11 0x600B8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_11 0x18F600B8u //! Register Reset Value #define DESC1_EGP_PON_11_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_11_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_11_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_12 Register DESC0_EGP_PON_12 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_12 0x600C0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_12 0x18F600C0u //! Register Reset Value #define DESC0_EGP_PON_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_12 Register DESC1_EGP_PON_12 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_12 0x600C8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_12 0x18F600C8u //! Register Reset Value #define DESC1_EGP_PON_12_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_12_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_12_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_13 Register DESC0_EGP_PON_13 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_13 0x600D0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_13 0x18F600D0u //! Register Reset Value #define DESC0_EGP_PON_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_13 Register DESC1_EGP_PON_13 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_13 0x600D8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_13 0x18F600D8u //! Register Reset Value #define DESC1_EGP_PON_13_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_13_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_13_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_14 Register DESC0_EGP_PON_14 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_14 0x600E0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_14 0x18F600E0u //! Register Reset Value #define DESC0_EGP_PON_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_14 Register DESC1_EGP_PON_14 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_14 0x600E8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_14 0x18F600E8u //! Register Reset Value #define DESC1_EGP_PON_14_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_14_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_14_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC0_EGP_PON_15 Register DESC0_EGP_PON_15 - Egress Port 64 Bit Descriptor DDW0 //! @{ //! Register Offset (relative) #define DESC0_EGP_PON_15 0x600F0 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC0_EGP_PON_15 0x18F600F0u //! Register Reset Value #define DESC0_EGP_PON_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 0 #define DESC0_EGP_PON_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DESC1_EGP_PON_15 Register DESC1_EGP_PON_15 - Egress Port 64 Bit Descriptor DDW1 //! @{ //! Register Offset (relative) #define DESC1_EGP_PON_15 0x600F8 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DESC1_EGP_PON_15 0x18F600F8u //! Register Reset Value #define DESC1_EGP_PON_15_RST 0x0000000000000000u //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_15_DESC_POS 0 //! Field DESC - Descriptor Double Double Word 1 #define DESC1_EGP_PON_15_DESC_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DBG_DESC64_0 Register DBG_DESC64_0 - Hardware Debug Register //! @{ //! Register Offset (relative) #define DBG_DESC64_0 0x80000 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DBG_DESC64_0 0x18F80000u //! Register Reset Value #define DBG_DESC64_0_RST 0x0000000000000000u //! Field DBG - Debug #define DBG_DESC64_0_DBG_POS 0 //! Field DBG - Debug #define DBG_DESC64_0_DBG_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup DBG_DESC64_1 Register DBG_DESC64_1 - Hardware Debug Register //! @{ //! Register Offset (relative) #define DBG_DESC64_1 0x80008 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_DBG_DESC64_1 0x18F80008u //! Register Reset Value #define DBG_DESC64_1_RST 0x0000000000000000u //! Field DBG - Debug #define DBG_DESC64_1_DBG_POS 0 //! Field DBG - Debug #define DBG_DESC64_1_DBG_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEST_DESC64_0 Register TEST_DESC64_0 - Hardware Test Register //! @{ //! Register Offset (relative) #define TEST_DESC64_0 0x80010 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_TEST_DESC64_0 0x18F80010u //! Register Reset Value #define TEST_DESC64_0_RST 0x0000000000000000u //! Field TEST - Test #define TEST_DESC64_0_TEST_POS 0 //! Field TEST - Test #define TEST_DESC64_0_TEST_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! \defgroup TEST_DESC64_1 Register TEST_DESC64_1 - Hardware Test Register //! @{ //! Register Offset (relative) #define TEST_DESC64_1 0x80018 //! Register Offset (absolute) for 1st Instance CQEM_DMA_DESC_PORT #define CQEM_DMA_DESC_PORT_TEST_DESC64_1 0x18F80018u //! Register Reset Value #define TEST_DESC64_1_RST 0x0000000000000000u //! Field TEST - Test #define TEST_DESC64_1_TEST_POS 0 //! Field TEST - Test #define TEST_DESC64_1_TEST_MASK 0xFFFFFFFFFFFFFFFFu //! @} //! @} #endif