//----------------------------------------------------------------------------- // LSD Generator //----------------------------------------------------------------------------- // Perl Package : LSD::generator::targetC (v1.1) // LSD Source : C:/Users/huchunfe/Perforce/huchunfe_huchunfe-MOBL1_dev.FalcONT/ipg_lsd/lsd_sys/source/xml/reg_files/txmngr.xml // Register File Name : TX_MANAGER // Register File Title : Tx Manager Registers // Register Width : 32 // Note : Doxygen compliant comments //----------------------------------------------------------------------------- #ifndef _TX_MANAGER_H #define _TX_MANAGER_H //! \defgroup TX_MANAGER Register File TX_MANAGER - Tx Manager Registers //! @{ //! Base Address of TX_MANAGER #define TX_MANAGER_MODULE_BASE 0x18810000u //! \defgroup TXMNGR_TXMNGR_TXPORT_EN_0_31 Register TXMNGR_TXMNGR_TXPORT_EN_0_31 - txmngr_txport_en_0_31 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_EN_0_31 0x0 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_EN_0_31 0x18810000u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_EN_0_31_RST 0x00000000u //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_0_31_TXPORT_EN_POS 0 //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_0_31_TXPORT_EN_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_EN_32_63 Register TXMNGR_TXMNGR_TXPORT_EN_32_63 - txmngr_txport_en_32_63 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_EN_32_63 0x4 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_EN_32_63 0x18810004u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_EN_32_63_RST 0x00000000u //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_32_63_TXPORT_EN_POS 0 //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_32_63_TXPORT_EN_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_EN_64_95 Register TXMNGR_TXMNGR_TXPORT_EN_64_95 - txmngr_txport_en_64_95 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_EN_64_95 0x8 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_EN_64_95 0x18810008u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_EN_64_95_RST 0x00000000u //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_64_95_TXPORT_EN_POS 0 //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_64_95_TXPORT_EN_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_EN_96_127 Register TXMNGR_TXMNGR_TXPORT_EN_96_127 - txmngr_txport_en_96_127 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_EN_96_127 0xC //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_EN_96_127 0x1881000Cu //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_EN_96_127_RST 0x00000000u //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_96_127_TXPORT_EN_POS 0 //! Field TXPORT_EN - txport_en #define TXMNGR_TXMNGR_TXPORT_EN_96_127_TXPORT_EN_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_RST_0_31 Register TXMNGR_TXMNGR_TXPORT_RST_0_31 - txmngr_txport_rst_0_31 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_RST_0_31 0x10 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_RST_0_31 0x18810010u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_RST_0_31_RST 0x00000000u //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_0_31_TXPORT_RST_POS 0 //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_0_31_TXPORT_RST_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_RST_32_63 Register TXMNGR_TXMNGR_TXPORT_RST_32_63 - txmngr_txport_rst_32_63 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_RST_32_63 0x14 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_RST_32_63 0x18810014u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_RST_32_63_RST 0x00000000u //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_32_63_TXPORT_RST_POS 0 //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_32_63_TXPORT_RST_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_RST_64_95 Register TXMNGR_TXMNGR_TXPORT_RST_64_95 - txmngr_txport_rst_64_95 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_RST_64_95 0x18 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_RST_64_95 0x18810018u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_RST_64_95_RST 0x00000000u //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_64_95_TXPORT_RST_POS 0 //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_64_95_TXPORT_RST_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_RST_96_127 Register TXMNGR_TXMNGR_TXPORT_RST_96_127 - txmngr_txport_rst_96_127 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_RST_96_127 0x1C //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_RST_96_127 0x1881001Cu //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_RST_96_127_RST 0x00000000u //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_96_127_TXPORT_RST_POS 0 //! Field TXPORT_RST - txport_rst #define TXMNGR_TXMNGR_TXPORT_RST_96_127_TXPORT_RST_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31 Register TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31 - txmngr_txport_byte_crdt_dis_0_31 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31 0x20 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31 0x18810020u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31_RST 0x00000000u //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31_TXPORT_BCRDT_DIS_POS 0 //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_0_31_TXPORT_BCRDT_DIS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63 Register TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63 - txmngr_txport_byte_crdt_dis_32_63 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63 0x24 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63 0x18810024u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63_RST 0x00000000u //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63_TXPORT_BCRDT_DIS_POS 0 //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_32_63_TXPORT_BCRDT_DIS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95 Register TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95 - txmngr_txport_byte_crdt_dis_64_95 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95 0x28 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95 0x18810028u //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95_RST 0x00000000u //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95_TXPORT_BCRDT_DIS_POS 0 //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_64_95_TXPORT_BCRDT_DIS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127 Register TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127 - txmngr_txport_byte_crdt_dis_96_127 //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127 0x2C //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127 0x1881002Cu //! Register Reset Value #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127_RST 0x00000000u //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127_TXPORT_BCRDT_DIS_POS 0 //! Field TXPORT_BCRDT_DIS - txport_bcrdt_dis #define TXMNGR_TXMNGR_TXPORT_BYTE_CRDT_DIS_96_127_TXPORT_BCRDT_DIS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_SCHD_ADDRH_REG Register TXMNGR_TXMNGR_SCHD_ADDRH_REG - txmngr_schd_addrh_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_SCHD_ADDRH_REG 0x30 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_SCHD_ADDRH_REG 0x18810030u //! Register Reset Value #define TXMNGR_TXMNGR_SCHD_ADDRH_REG_RST 0x00000000u //! Field SCHD_ADDRH - schd_addrh #define TXMNGR_TXMNGR_SCHD_ADDRH_REG_SCHD_ADDRH_POS 0 //! Field SCHD_ADDRH - schd_addrh #define TXMNGR_TXMNGR_SCHD_ADDRH_REG_SCHD_ADDRH_MASK 0xFFu //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_SCHD_ADDRH_REG_RSV1_POS 8 //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_SCHD_ADDRH_REG_RSV1_MASK 0xFFFFFF00u //! @} //! \defgroup TXMNGR_TXMNGR_SCHD_ADDRL_REG Register TXMNGR_TXMNGR_SCHD_ADDRL_REG - txmngr_schd_addrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_SCHD_ADDRL_REG 0x34 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_SCHD_ADDRL_REG 0x18810034u //! Register Reset Value #define TXMNGR_TXMNGR_SCHD_ADDRL_REG_RST 0x00000000u //! Field SCHD_ADDRL - schd_addrl #define TXMNGR_TXMNGR_SCHD_ADDRL_REG_SCHD_ADDRL_POS 0 //! Field SCHD_ADDRL - schd_addrl #define TXMNGR_TXMNGR_SCHD_ADDRL_REG_SCHD_ADDRL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_MCTRL_ADDRH_REG Register TXMNGR_TXMNGR_MCTRL_ADDRH_REG - txmngr_mctrl_addrh_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG 0x38 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_MCTRL_ADDRH_REG 0x18810038u //! Register Reset Value #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG_RST 0x00000000u //! Field MCTRL_ADDRH - mctrl_addrh #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG_MCTRL_ADDRH_POS 0 //! Field MCTRL_ADDRH - mctrl_addrh #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG_MCTRL_ADDRH_MASK 0xFFu //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG_RSV1_POS 8 //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_MCTRL_ADDRH_REG_RSV1_MASK 0xFFFFFF00u //! @} //! \defgroup TXMNGR_TXMNGR_MCTRL_ADDRL_REG Register TXMNGR_TXMNGR_MCTRL_ADDRL_REG - txmngr_mctrl_addrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_MCTRL_ADDRL_REG 0x3C //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_MCTRL_ADDRL_REG 0x1881003Cu //! Register Reset Value #define TXMNGR_TXMNGR_MCTRL_ADDRL_REG_RST 0x00000000u //! Field MCTRL_ADDRL - mctrl_addrl #define TXMNGR_TXMNGR_MCTRL_ADDRL_REG_MCTRL_ADDRL_POS 0 //! Field MCTRL_ADDRL - mctrl_addrl #define TXMNGR_TXMNGR_MCTRL_ADDRL_REG_MCTRL_ADDRL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_SCHD_CMDRXH_REG Register TXMNGR_DBG_SCHD_CMDRXH_REG - dbg_schd_cmdrxh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_SCHD_CMDRXH_REG 0x440 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_SCHD_CMDRXH_REG 0x18810440u //! Register Reset Value #define TXMNGR_DBG_SCHD_CMDRXH_REG_RST 0x00000000u //! Field DBG_SCHD_CMDRXH - dbg_schd_cmdrxh #define TXMNGR_DBG_SCHD_CMDRXH_REG_DBG_SCHD_CMDRXH_POS 0 //! Field DBG_SCHD_CMDRXH - dbg_schd_cmdrxh #define TXMNGR_DBG_SCHD_CMDRXH_REG_DBG_SCHD_CMDRXH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_SCHD_CMDRXL_REG Register TXMNGR_DBG_SCHD_CMDRXL_REG - dbg_schd_cmdrxl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_SCHD_CMDRXL_REG 0x444 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_SCHD_CMDRXL_REG 0x18810444u //! Register Reset Value #define TXMNGR_DBG_SCHD_CMDRXL_REG_RST 0x00000000u //! Field DBG_SCHD_CMDRXL - dbg_schd_cmdrxl #define TXMNGR_DBG_SCHD_CMDRXL_REG_DBG_SCHD_CMDRXL_POS 0 //! Field DBG_SCHD_CMDRXL - dbg_schd_cmdrxl #define TXMNGR_DBG_SCHD_CMDRXL_REG_DBG_SCHD_CMDRXL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_SCHD_CMDDNH_REG Register TXMNGR_DBG_SCHD_CMDDNH_REG - dbg_schd_cmddnh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_SCHD_CMDDNH_REG 0x448 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_SCHD_CMDDNH_REG 0x18810448u //! Register Reset Value #define TXMNGR_DBG_SCHD_CMDDNH_REG_RST 0x00000000u //! Field DBG_SCHD_CMDDNH - dbg_schd_cmddnh #define TXMNGR_DBG_SCHD_CMDDNH_REG_DBG_SCHD_CMDDNH_POS 0 //! Field DBG_SCHD_CMDDNH - dbg_schd_cmddnh #define TXMNGR_DBG_SCHD_CMDDNH_REG_DBG_SCHD_CMDDNH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_SCHD_CMDDNL_REG Register TXMNGR_DBG_SCHD_CMDDNL_REG - dbg_schd_cmddnl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_SCHD_CMDDNL_REG 0x44C //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_SCHD_CMDDNL_REG 0x1881044Cu //! Register Reset Value #define TXMNGR_DBG_SCHD_CMDDNL_REG_RST 0x00000000u //! Field DBG_SCHD_CMDDNL - dbg_schd_cmddnl #define TXMNGR_DBG_SCHD_CMDDNL_REG_DBG_SCHD_CMDDNL_POS 0 //! Field DBG_SCHD_CMDDNL - dbg_schd_cmddnl #define TXMNGR_DBG_SCHD_CMDDNL_REG_DBG_SCHD_CMDDNL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_QM_POPDH_REG Register TXMNGR_DBG_QM_POPDH_REG - dbg_qm_popdh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_QM_POPDH_REG 0x450 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_QM_POPDH_REG 0x18810450u //! Register Reset Value #define TXMNGR_DBG_QM_POPDH_REG_RST 0x00000000u //! Field DBG_QM_POPDH - dbg_qm_popdh #define TXMNGR_DBG_QM_POPDH_REG_DBG_QM_POPDH_POS 0 //! Field DBG_QM_POPDH - dbg_qm_popdh #define TXMNGR_DBG_QM_POPDH_REG_DBG_QM_POPDH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_QM_POPDL_REG Register TXMNGR_DBG_QM_POPDL_REG - dbg_qm_popdl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_QM_POPDL_REG 0x454 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_QM_POPDL_REG 0x18810454u //! Register Reset Value #define TXMNGR_DBG_QM_POPDL_REG_RST 0x00000000u //! Field DBG_QM_POPDL - dbg_qm_popdl #define TXMNGR_DBG_QM_POPDL_REG_DBG_QM_POPDL_POS 0 //! Field DBG_QM_POPDL - dbg_qm_popdl #define TXMNGR_DBG_QM_POPDL_REG_DBG_QM_POPDL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_ERROR_REG Register TXMNGR_TXMNGR_ERROR_REG - txmngr_error_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_ERROR_REG 0x458 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_ERROR_REG 0x18810458u //! Register Reset Value #define TXMNGR_TXMNGR_ERROR_REG_RST 0x00000000u //! Field TXMNGR_ERR_PORT - txmngr_err_port #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_PORT_POS 0 //! Field TXMNGR_ERR_PORT - txmngr_err_port #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_PORT_MASK 0xFFu //! Field TXMNGR_ERR_WR_DIS - txmngr_err_wr_dis #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_WR_DIS_POS 8 //! Field TXMNGR_ERR_WR_DIS - txmngr_err_wr_dis #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_WR_DIS_MASK 0x100u //! Field TXMNGR_ERR_WR_FULL - txmngr_err_wr_full #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_WR_FULL_POS 9 //! Field TXMNGR_ERR_WR_FULL - txmngr_err_wr_full #define TXMNGR_TXMNGR_ERROR_REG_TXMNGR_ERR_WR_FULL_MASK 0x200u //! Field RSV - RSV #define TXMNGR_TXMNGR_ERROR_REG_RSV_POS 10 //! Field RSV - RSV #define TXMNGR_TXMNGR_ERROR_REG_RSV_MASK 0xFFFFFC00u //! @} //! \defgroup TXMNGR_TXMNGR_CTRL_REG Register TXMNGR_TXMNGR_CTRL_REG - txmngr_ctrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_CTRL_REG 0x45C //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_CTRL_REG 0x1881045Cu //! Register Reset Value #define TXMNGR_TXMNGR_CTRL_REG_RST 0x00000000u //! Field TXMNGR_CMDFIFO_THRESHOLD - txmngr_cmdfifo_threshold #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_CMDFIFO_THRESHOLD_POS 0 //! Field TXMNGR_CMDFIFO_THRESHOLD - txmngr_cmdfifo_threshold #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_CMDFIFO_THRESHOLD_MASK 0xFu //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_CTRL_REG_RSV1_POS 4 //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_CTRL_REG_RSV1_MASK 0xF0u //! Field TXMNGR_BCKPRS_STALL - txmngr_bckprs_stall #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_BCKPRS_STALL_POS 8 //! Field TXMNGR_BCKPRS_STALL - txmngr_bckprs_stall #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_BCKPRS_STALL_MASK 0x100u //! Field TXMNGR_QALIAS_DIS - txmngr_qalias_dis #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_QALIAS_DIS_POS 9 //! Field TXMNGR_QALIAS_DIS - txmngr_qalias_dis #define TXMNGR_TXMNGR_CTRL_REG_TXMNGR_QALIAS_DIS_MASK 0x200u //! Field RSV2 - RSV2 #define TXMNGR_TXMNGR_CTRL_REG_RSV2_POS 10 //! Field RSV2 - RSV2 #define TXMNGR_TXMNGR_CTRL_REG_RSV2_MASK 0xFFFFFC00u //! @} //! \defgroup TXMNGR_DBG_BCKPRS_STATUS_0_31 Register TXMNGR_DBG_BCKPRS_STATUS_0_31 - dbg_bckprs_status_0_31 //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BCKPRS_STATUS_0_31 0x4E0 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BCKPRS_STATUS_0_31 0x188104E0u //! Register Reset Value #define TXMNGR_DBG_BCKPRS_STATUS_0_31_RST 0x00000000u //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_0_31_DBG_BCKPRS_STS_POS 0 //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_0_31_DBG_BCKPRS_STS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_BCKPRS_STATUS_32_63 Register TXMNGR_DBG_BCKPRS_STATUS_32_63 - dbg_bckprs_status_32_63 //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BCKPRS_STATUS_32_63 0x4E4 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BCKPRS_STATUS_32_63 0x188104E4u //! Register Reset Value #define TXMNGR_DBG_BCKPRS_STATUS_32_63_RST 0x00000000u //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_32_63_DBG_BCKPRS_STS_POS 0 //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_32_63_DBG_BCKPRS_STS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_BCKPRS_STATUS_64_95 Register TXMNGR_DBG_BCKPRS_STATUS_64_95 - dbg_bckprs_status_64_95 //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BCKPRS_STATUS_64_95 0x4E8 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BCKPRS_STATUS_64_95 0x188104E8u //! Register Reset Value #define TXMNGR_DBG_BCKPRS_STATUS_64_95_RST 0x00000000u //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_64_95_DBG_BCKPRS_STS_POS 0 //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_64_95_DBG_BCKPRS_STS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_BCKPRS_STATUS_96_127 Register TXMNGR_DBG_BCKPRS_STATUS_96_127 - dbg_bckprs_status_96_127 //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BCKPRS_STATUS_96_127 0x4EC //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BCKPRS_STATUS_96_127 0x188104ECu //! Register Reset Value #define TXMNGR_DBG_BCKPRS_STATUS_96_127_RST 0x00000000u //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_96_127_DBG_BCKPRS_STS_POS 0 //! Field DBG_BCKPRS_STS - dbg_bckprs_sts #define TXMNGR_DBG_BCKPRS_STATUS_96_127_DBG_BCKPRS_STS_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG Register TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG - dbg_txport_bckprs_ctrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG 0x4F0 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG 0x188104F0u //! Register Reset Value #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_RST 0x00000000u //! Field DBG_BCKPRSH_PORT1 - dbg_bckprsh_port1 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT1_POS 0 //! Field DBG_BCKPRSH_PORT1 - dbg_bckprsh_port1 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT1_MASK 0xFFu //! Field DBG_BCKPRSH_PORT2 - dbg_bckprsh_port2 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT2_POS 8 //! Field DBG_BCKPRSH_PORT2 - dbg_bckprsh_port2 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT2_MASK 0xFF00u //! Field DBG_BCKPRSH_PORT3 - dbg_bckprsh_port3 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT3_POS 16 //! Field DBG_BCKPRSH_PORT3 - dbg_bckprsh_port3 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT3_MASK 0xFF0000u //! Field DBG_BCKPRSH_PORT4 - dbg_bckprsh_port4 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT4_POS 24 //! Field DBG_BCKPRSH_PORT4 - dbg_bckprsh_port4 #define TXMNGR_DBG_TXPORT_BCKPRS_CTRL_REG_DBG_BCKPRSH_PORT4_MASK 0xFF000000u //! @} //! \defgroup TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG Register TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG - txmngr_sccmd_ind_unlock_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG 0x4F4 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG 0x188104F4u //! Register Reset Value #define TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG_RST 0x00000000u //! Field TXMNGR_SCCMD_IND_UNLOCK - txmngr_sccmd_ind_unlock #define TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG_TXMNGR_SCCMD_IND_UNLOCK_POS 0 //! Field TXMNGR_SCCMD_IND_UNLOCK - txmngr_sccmd_ind_unlock #define TXMNGR_TXMNGR_SCCMD_IND_UNLOCK_REG_TXMNGR_SCCMD_IND_UNLOCK_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXMNGR_SCCMD_INDADD_REG Register TXMNGR_TXMNGR_SCCMD_INDADD_REG - txmngr_sccmd_indadd_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_SCCMD_INDADD_REG 0x4F8 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_SCCMD_INDADD_REG 0x188104F8u //! Register Reset Value #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_RST 0x00000000u //! Field TXMNGR_SCCMD_INDADD - txmngr_sccmd_indadd #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDADD_POS 0 //! Field TXMNGR_SCCMD_INDADD - txmngr_sccmd_indadd #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDADD_MASK 0x7FFu //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_RSV1_POS 11 //! Field RSV1 - RSV1 #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_RSV1_MASK 0x3FFFF800u //! Field TXMNGR_SCCMD_INDRWB - txmngr_sccmd_indrwb #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDRWB_POS 30 //! Field TXMNGR_SCCMD_INDRWB - txmngr_sccmd_indrwb #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDRWB_MASK 0x40000000u //! Field TXMNGR_SCCMD_INDEN - txmngr_sccmd_inden #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDEN_POS 31 //! Field TXMNGR_SCCMD_INDEN - txmngr_sccmd_inden #define TXMNGR_TXMNGR_SCCMD_INDADD_REG_TXMNGR_SCCMD_INDEN_MASK 0x80000000u //! @} //! \defgroup TXMNGR_TXMNGR_SCCMD_INDDAT_REG Register TXMNGR_TXMNGR_SCCMD_INDDAT_REG - txmngr_sccmd_inddat_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXMNGR_SCCMD_INDDAT_REG 0x4FC //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXMNGR_SCCMD_INDDAT_REG 0x188104FCu //! Register Reset Value #define TXMNGR_TXMNGR_SCCMD_INDDAT_REG_RST 0x00000000u //! Field TXMNGR_SCCMD_INDDAT - txmngr_sccmd_inddat #define TXMNGR_TXMNGR_SCCMD_INDDAT_REG_TXMNGR_SCCMD_INDDAT_POS 0 //! Field TXMNGR_SCCMD_INDDAT - txmngr_sccmd_inddat #define TXMNGR_TXMNGR_SCCMD_INDDAT_REG_TXMNGR_SCCMD_INDDAT_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_TXPORT_RSZ_ADDRH_REG Register TXMNGR_TXPORT_RSZ_ADDRH_REG - txport_rsz_addrh_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXPORT_RSZ_ADDRH_REG 0x500 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXPORT_RSZ_ADDRH_REG 0x18810500u //! Register Reset Value #define TXMNGR_TXPORT_RSZ_ADDRH_REG_RST 0x00000000u //! Field TXPORT_ADDRH - txport_addrh #define TXMNGR_TXPORT_RSZ_ADDRH_REG_TXPORT_ADDRH_POS 0 //! Field TXPORT_ADDRH - txport_addrh #define TXMNGR_TXPORT_RSZ_ADDRH_REG_TXPORT_ADDRH_MASK 0xFFu //! Field TXPORT_RSZ - txport_rsz #define TXMNGR_TXPORT_RSZ_ADDRH_REG_TXPORT_RSZ_POS 8 //! Field TXPORT_RSZ - txport_rsz #define TXMNGR_TXPORT_RSZ_ADDRH_REG_TXPORT_RSZ_MASK 0xFFFFFF00u //! @} //! \defgroup TXMNGR_TXPORT_ADDRL_REG Register TXMNGR_TXPORT_ADDRL_REG - txport_addrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_TXPORT_ADDRL_REG 0x700 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_TXPORT_ADDRL_REG 0x18810700u //! Register Reset Value #define TXMNGR_TXPORT_ADDRL_REG_RST 0x00000000u //! Field TXPORT_ADDRL - txport_addrl #define TXMNGR_TXPORT_ADDRL_REG_TXPORT_ADDRL_POS 0 //! Field TXPORT_ADDRL - txport_addrl #define TXMNGR_TXPORT_ADDRL_REG_TXPORT_ADDRL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_BYTE_CTR_CTRL_REG Register TXMNGR_DBG_BYTE_CTR_CTRL_REG - dbg_byte_ctr_ctrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BYTE_CTR_CTRL_REG 0x900 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BYTE_CTR_CTRL_REG 0x18810900u //! Register Reset Value #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_RST 0x00000000u //! Field DBG_TXMCHN - dbg_txmchn #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXMCHN_POS 0 //! Field DBG_TXMCHN - dbg_txmchn #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXMCHN_MASK 0x7Fu //! Field DBG_TXMCHN_ALL - dbg_txmchn_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXMCHN_ALL_POS 7 //! Field DBG_TXMCHN_ALL - dbg_txmchn_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXMCHN_ALL_MASK 0x80u //! Field DBG_TXPORT - dbg_txport #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXPORT_POS 8 //! Field DBG_TXPORT - dbg_txport #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXPORT_MASK 0x7F00u //! Field DBG_TXPORT_ALL - dbg_txport_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXPORT_ALL_POS 15 //! Field DBG_TXPORT_ALL - dbg_txport_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_TXPORT_ALL_MASK 0x8000u //! Field DBG_QMQUEUE - dbg_qmqueue #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_QMQUEUE_POS 16 //! Field DBG_QMQUEUE - dbg_qmqueue #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_QMQUEUE_MASK 0x3FF0000u //! Field DBG_QMQUEUE_ALL - dbg_qmqueue_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_QMQUEUE_ALL_POS 26 //! Field DBG_QMQUEUE_ALL - dbg_qmqueue_all #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_DBG_QMQUEUE_ALL_MASK 0x4000000u //! Field RSV2 - RSV2 #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_RSV2_POS 27 //! Field RSV2 - RSV2 #define TXMNGR_DBG_BYTE_CTR_CTRL_REG_RSV2_MASK 0xF8000000u //! @} //! \defgroup TXMNGR_DBG_BYTE_CTRH_REG Register TXMNGR_DBG_BYTE_CTRH_REG - dbg_byte_ctrh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BYTE_CTRH_REG 0x910 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BYTE_CTRH_REG 0x18810910u //! Register Reset Value #define TXMNGR_DBG_BYTE_CTRH_REG_RST 0x00000000u //! Field DBG_BYTE_CTRH - dbg_byte_ctrh #define TXMNGR_DBG_BYTE_CTRH_REG_DBG_BYTE_CTRH_POS 0 //! Field DBG_BYTE_CTRH - dbg_byte_ctrh #define TXMNGR_DBG_BYTE_CTRH_REG_DBG_BYTE_CTRH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_BYTE_CTRL_REG Register TXMNGR_DBG_BYTE_CTRL_REG - dbg_byte_ctrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_BYTE_CTRL_REG 0x920 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_BYTE_CTRL_REG 0x18810920u //! Register Reset Value #define TXMNGR_DBG_BYTE_CTRL_REG_RST 0x00000000u //! Field DBG_BYTE_CTRL - dbg_byte_ctrl #define TXMNGR_DBG_BYTE_CTRL_REG_DBG_BYTE_CTRL_POS 0 //! Field DBG_BYTE_CTRL - dbg_byte_ctrl #define TXMNGR_DBG_BYTE_CTRL_REG_DBG_BYTE_CTRL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_QM_POP_DLY_CTRL_REG Register TXMNGR_DBG_QM_POP_DLY_CTRL_REG - dbg_qm_pop_dly_ctrl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG 0x930 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_QM_POP_DLY_CTRL_REG 0x18810930u //! Register Reset Value #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_RST 0x00000000u //! Field DBG_TRESHOLD - dbg_treshold #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TRESHOLD_POS 0 //! Field DBG_TRESHOLD - dbg_treshold #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TRESHOLD_MASK 0xFFu //! Field DBG_TXPORT - dbg_txport #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TXPORT_POS 8 //! Field DBG_TXPORT - dbg_txport #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TXPORT_MASK 0x7F00u //! Field DBG_TXPORT_ALL - dbg_txport_all #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TXPORT_ALL_POS 15 //! Field DBG_TXPORT_ALL - dbg_txport_all #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_TXPORT_ALL_MASK 0x8000u //! Field DBG_QMQUEUE - dbg_qmqueue #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_QMQUEUE_POS 16 //! Field DBG_QMQUEUE - dbg_qmqueue #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_QMQUEUE_MASK 0x3FF0000u //! Field DBG_QMQUEUE_ALL - dbg_qmqueue_all #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_QMQUEUE_ALL_POS 26 //! Field DBG_QMQUEUE_ALL - dbg_qmqueue_all #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_DBG_QMQUEUE_ALL_MASK 0x4000000u //! Field RSV2 - RSV2 #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_RSV2_POS 27 //! Field RSV2 - RSV2 #define TXMNGR_DBG_QM_POP_DLY_CTRL_REG_RSV2_MASK 0xF8000000u //! @} //! \defgroup TXMNGR_DBG_QM_POPDLYH_REG Register TXMNGR_DBG_QM_POPDLYH_REG - dbg_qm_popdlyh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_QM_POPDLYH_REG 0x940 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_QM_POPDLYH_REG 0x18810940u //! Register Reset Value #define TXMNGR_DBG_QM_POPDLYH_REG_RST 0x00000000u //! Field DBG_QM_POPDLYH - dbg_qm_popdlyh #define TXMNGR_DBG_QM_POPDLYH_REG_DBG_QM_POPDLYH_POS 0 //! Field DBG_QM_POPDLYH - dbg_qm_popdlyh #define TXMNGR_DBG_QM_POPDLYH_REG_DBG_QM_POPDLYH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_QM_POPDLYL_REG Register TXMNGR_DBG_QM_POPDLYL_REG - dbg_qm_popdlyl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_QM_POPDLYL_REG 0x950 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_QM_POPDLYL_REG 0x18810950u //! Register Reset Value #define TXMNGR_DBG_QM_POPDLYL_REG_RST 0x00000000u //! Field DBG_QM_POPDLYL - dbg_qm_popdlyl #define TXMNGR_DBG_QM_POPDLYL_REG_DBG_QM_POPDLYL_POS 0 //! Field DBG_QM_POPDLYL - dbg_qm_popdlyl #define TXMNGR_DBG_QM_POPDLYL_REG_DBG_QM_POPDLYL_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG Register TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG - dbg_txport_act_pkt_crdt_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG 0x960 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG 0x18810960u //! Register Reset Value #define TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG_RST 0x00000000u //! Field DBG_TXPORT_PKT_CRDT - dbg_txport_pkt_crdt #define TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG_DBG_TXPORT_PKT_CRDT_POS 0 //! Field DBG_TXPORT_PKT_CRDT - dbg_txport_pkt_crdt #define TXMNGR_DBG_TXPORT_ACT_PKT_CRDT_REG_DBG_TXPORT_PKT_CRDT_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG Register TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG - dbg_txport_act_byte_crdt_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG 0xB60 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG 0x18810B60u //! Register Reset Value #define TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG_RST 0x00000000u //! Field DBG_TXPORT_BYTE_CRDT - dbg_txport_byte_crdt #define TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG_DBG_TXPORT_BYTE_CRDT_POS 0 //! Field DBG_TXPORT_BYTE_CRDT - dbg_txport_byte_crdt #define TXMNGR_DBG_TXPORT_ACT_BYTE_CRDT_REG_DBG_TXPORT_BYTE_CRDT_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_TXPORT_BCKPRSH_REG Register TXMNGR_DBG_TXPORT_BCKPRSH_REG - dbg_txport_bckprsh_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_TXPORT_BCKPRSH_REG 0xD60 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_TXPORT_BCKPRSH_REG 0x18810D60u //! Register Reset Value #define TXMNGR_DBG_TXPORT_BCKPRSH_REG_RST 0x00000000u //! Field DBG_TXPORT_BCKPRSH - dbg_txport_bckprsh #define TXMNGR_DBG_TXPORT_BCKPRSH_REG_DBG_TXPORT_BCKPRSH_POS 0 //! Field DBG_TXPORT_BCKPRSH - dbg_txport_bckprsh #define TXMNGR_DBG_TXPORT_BCKPRSH_REG_DBG_TXPORT_BCKPRSH_MASK 0xFFFFFFFFu //! @} //! \defgroup TXMNGR_DBG_TXPORT_BCKPRSL_REG Register TXMNGR_DBG_TXPORT_BCKPRSL_REG - dbg_txport_bckprsl_reg //! @{ //! Register Offset (relative) #define TXMNGR_DBG_TXPORT_BCKPRSL_REG 0xD70 //! Register Offset (absolute) for 1st Instance TX_MANAGER #define TX_MANAGER_TXMNGR_DBG_TXPORT_BCKPRSL_REG 0x18810D70u //! Register Reset Value #define TXMNGR_DBG_TXPORT_BCKPRSL_REG_RST 0x00000000u //! Field DBG_TXPORT_BCKPRSL - dbg_txport_bckprsl #define TXMNGR_DBG_TXPORT_BCKPRSL_REG_DBG_TXPORT_BCKPRSL_POS 0 //! Field DBG_TXPORT_BCKPRSL - dbg_txport_bckprsl #define TXMNGR_DBG_TXPORT_BCKPRSL_REG_DBG_TXPORT_BCKPRSL_MASK 0xFFFFFFFFu //! @} //! @} #endif