--- zzzz-none-000/linux-4.9.276/arch/mips/Kconfig 2021-07-20 14:21:16.000000000 +0000 +++ falcon-5530-750/linux-4.9.276/arch/mips/Kconfig 2023-04-05 08:19:00.000000000 +0000 @@ -1,6 +1,7 @@ config MIPS bool default y + select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_SUPPORTS_UPROBES select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO @@ -56,6 +57,7 @@ select CLONE_BACKWARDS select HAVE_DEBUG_STACKOVERFLOW select HAVE_CC_STACKPROTECTOR + select LD_DEAD_CODE_DATA_ELIMINATION select CPU_PM if CPU_IDLE select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_BINFMT_ELF_STATE @@ -68,6 +70,9 @@ select HAVE_EXIT_THREAD select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_ARCH_HARDENED_USERCOPY + select ARCH_HAS_KCOV + select HAVE_GCC_PLUGINS + select HAVE_AVM_RTE menu "Machine selection" @@ -215,6 +220,7 @@ select BRCMSTB_L2_IRQ select IRQ_MIPS_CPU select DMA_NONCOHERENT + select DMA_UNMAP_POST_FLUSH select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN @@ -340,6 +346,7 @@ select CSRC_R4K select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select GENERIC_ISA_DMA + select DMA_UNMAP_POST_FLUSH select HAVE_PCSPKR_PLATFORM select IRQ_MIPS_CPU select I8253 @@ -373,8 +380,6 @@ bool "Lantiq based platforms" select DMA_NONCOHERENT select IRQ_MIPS_CPU - select CEVT_R4K - select CSRC_R4K select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN @@ -383,8 +388,9 @@ select SYS_SUPPORTS_MULTITHREADING select SYS_HAS_EARLY_PRINTK select GPIOLIB - select SWAP_IO_SPACE +## select SWAP_IO_SPACE select BOOT_RAW + select HAVE_MACH_CLKDEV select CLKDEV_LOOKUP select USE_OF select PINCTRL @@ -1132,6 +1138,9 @@ bool select NEED_DMA_MAP_STATE +config DMA_UNMAP_POST_FLUSH + bool + config NEED_DMA_MAP_STATE bool @@ -1156,6 +1165,10 @@ config MIPS_MACHINE def_bool n +config IMAGE_CMDLINE_HACK + bool "OpenWrt specific image command line hack" + default n + config NO_IOPORT_MAP def_bool n @@ -1656,6 +1669,7 @@ select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select DMA_UNMAP_POST_FLUSH help MIPS Technologies R10000-series processors. @@ -1760,6 +1774,37 @@ One of its primary benefits is an increase in the maximum size of lowmem (up to 3GB). If unsure, say 'N' here. +config LTQ_EVA_2GB + bool "EVA support for 2GB memory" + depends on CPU_MIPS32_3_5_EVA + depends on SOC_GRX500 + help + Choose this for EVA 2GB support. + +config LTQ_EVA_1GB + bool "EVA support for 1GB memory" + depends on CPU_MIPS32_3_5_EVA + depends on SOC_GRX500 + help + Choose this for EVA 1GB support. + +config LTQ_EVA_LEGACY + bool "EVA setting for legacy operation" + depends on CPU_MIPS32_3_5_EVA + depends on SOC_GRX500 + help + Choose this for EVA legacy(512MB) support + +config LTQ_EVA_LOAD_ADDR + hex "EVA load address" + depends on CPU_MIPS32_3_5_EVA + depends on SOC_GRX500 + default 0xffffffff20020000 if LTQ_EVA_2GB + default 0xffffffff60020000 if LTQ_EVA_1GB + default 0xffffffff80020000 + help + Define the kernel load address for LTQ EVA modes. + config CPU_MIPS32_R5_FEATURES bool "MIPS32 Release 5 Features" depends on SYS_HAS_CPU_MIPS32_R5 @@ -1901,9 +1946,11 @@ bool config SYS_HAS_CPU_MIPS32_R5 + select DMA_UNMAP_POST_FLUSH bool config SYS_HAS_CPU_MIPS32_R6 + select DMA_UNMAP_POST_FLUSH bool config SYS_HAS_CPU_MIPS64_R1 @@ -1913,6 +1960,7 @@ bool config SYS_HAS_CPU_MIPS64_R6 + select DMA_UNMAP_POST_FLUSH bool config SYS_HAS_CPU_R3000 @@ -2179,6 +2227,25 @@ endchoice +config MAX_ZONEDMA_SIZE + int "Maximum ZONE_DMA Size in (MB)" + depends on ZONE_DMA && SOC_GRX500 + range 16 256 + default "16" + help + Allows to specify the MAX size of ZONE_DMA . By default it is 16MB. + +config THREAD_SIZE_ORDER + int "Kernel stack size order (2^n)" + default 2 + help + Kernel stack size order (normaly 1) + On 4K page size: + 1 ==> 8K stack + 2 ==> 16K stack + 3 ==> 32K stack + + config FORCE_MAX_ZONEORDER int "Maximum zone order" range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB @@ -2253,7 +2320,7 @@ depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI - select SYNC_R4K + #select SYNC_R4K select MIPS_MT select SMP select SMP_UP @@ -2318,6 +2385,8 @@ default "y" depends on MIPS_VPE_LOADER && MIPS_CMP +source "arch/mips/avm_enh/Kconfig" + config MIPS_VPE_LOADER_MT bool default "y" @@ -2352,9 +2421,10 @@ bool "MIPS CMP framework support (DEPRECATED)" depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6 select SMP - select SYNC_R4K + select SYNC_R4K if (CEVT_R4K || CSRC_R4K) select SYS_SUPPORTS_SMP select WEAK_ORDERING + select SYS_SUPPORTS_HOTPLUG_CPU default n help Select this if you are using a bootloader which implements the "CMP @@ -2364,6 +2434,42 @@ Unless you have a specific need, you should use CONFIG_MIPS_CPS instead of this. +config LTQ_VMB + bool "Lantiq VPE Management Block (VMB)" + depends on MIPS_CMP && (SOC_GRX500 || MIPS_MALTA) + default n + help + Lantiq VPE Management Block support to launch Secondary FW/Linux + +config AVM_VMB + bool "VPE Management Block (VMB) - minmal version by AVM" + depends on MIPS_CMP && (SOC_GRX500 || MIPS_MALTA) && ! LTQ_VMB + default n + help + VPE Management Block support to launch Linux + +config LTQ_ITC + bool "Inter Thread Communication support (ITC)" + depends on MIPS_CMP && SOC_GRX500 + default n + help + Used to Synchronise Multiple TCs. Currently ITC cells are used a Semaphores. + +config LTQ_DYN_CPU_ALLOC + bool "Dynamic CPU allocation in vmb_cpu_alloc" + depends on LTQ_VMB + default n + help + Option to select CPU dynamically using vmb_cpu_alloc. This overrides the mapping on CPU to FW/Linux. + + +config BOOTCORE_LOAD_ADDR + hex "Boot core start address" + depends on SOC_TYPE_GRX500_TEP + default 0xffffffff88000000 + help + Used to give start address for Bootcore + config MIPS_CPS bool "MIPS Coherent Processing System support" depends on SYS_SUPPORTS_MIPS_CPS @@ -2460,6 +2566,12 @@ config CPU_HAS_RIXI bool +config CPU_HAS_DSP_ASE + bool + +config CPU_HAS_DSP2_ASE + bool + # # Vectored interrupt mode is an R2 feature # @@ -2629,6 +2741,16 @@ This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with EVA or 64-bit. The default is 16Mb. +config RANDOMIZE_BASE_MIN_ADDR + hex "Minimal kASLR address" if EXPERT + depends on RANDOMIZE_BASE + default "0x00000000" + ---help--- + When kASLR is active, this can be used to configure the minimal + address for the relocation. + If this is not 0, it will be used as base address instead of the + default load address of the kernel. + config NODES_SHIFT int default "6" @@ -2894,6 +3016,20 @@ If unsure, say N. +config MIPS_FPU_EMULATOR + bool "MIPS FPU Emulator" + default y + help + This option lets you disable the built-in MIPS FPU (Coprocessor 1) + emulator, which handles floating-point instructions on processors + without a hardware FPU. It is generally a good idea to keep the + emulator built-in, unless you are perfectly sure you have a + complete soft-float environment. With the emulator disabled, all + users of float operations will be killed with an illegal instr- + uction exception. + + Say Y, please. + config USE_OF bool select OF @@ -3184,6 +3320,19 @@ endmenu +# AVM Yield Extensions for RTE +config AVM_IPI_YIELD + def_bool y + depends on AVM_RTE + +config AVM_IRQ_HACK + bool "AVM IRQ Hack" + default no + help + This option will enable the irq_hack module which allows to acquire + hardware IRQs. If they are not actively used by hardware these + interrupts can e.g. be used to trigger action on specific CPUs. + source "net/Kconfig" source "drivers/Kconfig"