--- zzzz-none-000/linux-4.9.276/arch/mips/include/asm/mips-cm.h	2021-07-20 14:21:16.000000000 +0000
+++ falcon-5530-750/linux-4.9.276/arch/mips/include/asm/mips-cm.h	2023-04-05 08:19:00.000000000 +0000
@@ -22,6 +22,9 @@
 /* The base address of the CM L2-only sync region */
 extern void __iomem *mips_cm_l2sync_base;
 
+/* The base address of the custom GCR block */
+extern void __iomem *mips_cm_custom_base;
+
 /**
  * __mips_cm_phys_base - retrieve the physical base address of the CM
  *
@@ -112,6 +115,9 @@
 /* Size of the L2-only sync region */
 #define MIPS_CM_L2SYNC_SIZE	0x1000
 
+/* Total size of the custom GCR memory mapped registers */
+#define MIPS_CM_GCR_CUSTOM_SIZE	0x10000
+
 /* Macros to ease the creation of register access functions */
 #define BUILD_CM_R_(name, off)					\
 static inline unsigned long __iomem *addr_gcr_##name(void)	\
@@ -192,6 +198,8 @@
 BUILD_CM_RW(error_cause,	MIPS_CM_GCB_OFS + 0x48)
 BUILD_CM_RW(error_addr,		MIPS_CM_GCB_OFS + 0x50)
 BUILD_CM_RW(error_mult,		MIPS_CM_GCB_OFS + 0x58)
+BUILD_CM_RW(custom_base,	MIPS_CM_GCB_OFS + 0x60)
+BUILD_CM_RW(custom_status,	MIPS_CM_GCB_OFS + 0x68)
 BUILD_CM_RW(l2_only_sync_base,	MIPS_CM_GCB_OFS + 0x70)
 BUILD_CM_RW(gic_base,		MIPS_CM_GCB_OFS + 0x80)
 BUILD_CM_RW(cpc_base,		MIPS_CM_GCB_OFS + 0x88)
@@ -398,6 +406,16 @@
 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF	0
 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK	(_ULCAST_(0x1) << 0)
 
+/* GCR_Cx_CUSTOM_BASE register fields */
+#define CM_GCR_Cx_CUSTOM_BASE_CUSTOM_BASE_SHF	16
+#define CM_GCR_Cx_CUSTOM_BASE_CUSTOM_BASE_MSK	(_ULCAST_(0xffff) << 16)
+#define CM_GCR_Cx_CUSTOM_BASE_GGU_EN_SHF	0
+#define CM_GCR_Cx_CUSTOM_BASE_GGU_EN_MSK	(_ULCAST_(0x1) << 0)
+
+/* GCR_Cx_CUSTOM_STATUS register fields */
+#define CM_GCR_Cx_CUSTOM_STATUS_GGU_EX_SHF	0
+#define CM_GCR_Cx_CUSTOM_STATUS_GGU_EX_MSK	(_ULCAST_(0x1) << 0)
+
 /**
  * mips_cm_numcores - return the number of cores present in the system
  *