--- zzzz-none-000/linux-4.9.276/arch/mips/kernel/mips-cm.c	2021-07-20 14:21:16.000000000 +0000
+++ falcon-5530-750/linux-4.9.276/arch/mips/kernel/mips-cm.c	2023-04-05 08:19:00.000000000 +0000
@@ -16,6 +16,7 @@
 #include <asm/mipsregs.h>
 
 void __iomem *mips_cm_base;
+void __iomem *mips_cm_custom_base;
 void __iomem *mips_cm_l2sync_base;
 int mips_cm_is64;
 
@@ -232,6 +233,16 @@
 		return -ENODEV;
 	}
 
+	if (read_gcr_custom_status() & CM_GCR_Cx_CUSTOM_STATUS_GGU_EX_MSK && read_gcr_custom_base() & CM_GCR_Cx_CUSTOM_BASE_GGU_EN_MSK) {
+		addr = read_gcr_custom_base() & CM_GCR_Cx_CUSTOM_BASE_CUSTOM_BASE_MSK;
+		if (!addr)
+			return -ENODEV;
+
+		mips_cm_custom_base = ioremap_nocache(addr, MIPS_CM_GCR_CUSTOM_SIZE);
+		if (!mips_cm_custom_base)
+			return -ENXIO;
+	}
+
 	/* set default target to memory */
 	base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
 	base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;