--- zzzz-none-000/linux-4.9.276/arch/mips/pci/pci-lantiq.c	2021-07-20 14:21:16.000000000 +0000
+++ falcon-5530-750/linux-4.9.276/arch/mips/pci/pci-lantiq.c	2023-04-05 08:19:00.000000000 +0000
@@ -142,7 +142,10 @@
 
 	/* busy, i.e. configuration is not done, PCI access has to be retried */
 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
+
+	/* enable master only after configuration is done */
 	wmb();
+
 	/* BUS Master/IO/MEM access */
 	ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 
@@ -165,6 +168,8 @@
 	/* enable all external masters request */
 	temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 	ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
+
+	/* Make sure external master enabled */
 	wmb();
 
 	/* setup BAR memory regions */
@@ -182,14 +187,16 @@
 	ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
 	/* both TX and RX endian swap are enabled */
 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
+	/* Ensure endian setup done */
 	wmb();
 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
-		PCI_CR_BAR12MASK);
+		    PCI_CR_BAR12MASK);
 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
-		PCI_CR_BAR13MASK);
+		    PCI_CR_BAR13MASK);
 	/*use 8 dw burst length */
 	ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 	ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
+	/* enable irq only after configuration is done */
 	wmb();
 
 	/* setup irq line */
@@ -198,10 +205,11 @@
 
 	/* toggle reset pin */
 	if (gpio_is_valid(reset_gpio)) {
-		__gpio_set_value(reset_gpio, 0);
+		gpio_set_value(reset_gpio, 0);
+		/* Ensure reset takes effect */
 		wmb();
 		mdelay(1);
-		__gpio_set_value(reset_gpio, 1);
+		gpio_set_value(reset_gpio, 1);
 	}
 	return 0;
 }
@@ -244,10 +252,11 @@
 
 int __init pcibios_init(void)
 {
-	int ret = platform_driver_register(&ltq_pci_driver);
+	int ret;
+
+	ret = platform_driver_register(&ltq_pci_driver);
 	if (ret)
 		pr_info("pci-xway: Error registering platform driver!");
 	return ret;
 }
-
 arch_initcall(pcibios_init);