The application should write into * this bit, only after making sure that neither the * DMA engine is writing into the TxFIFO nor the MAC * is reading the data out of the FIFO.
The * application should wait until the core clears this * bit, before performing any operations. This bit * will takes 8 clocks (slowest of PHY or AHB clock) * to clear. */ unsigned txfflsh : 1; /** RxFIFO Flush (RxFFlsh) (Device and Host) * * The application can flush the entire Receive FIFO * using this bit.
The application must first * ensure that the core is not in the middle of a * transaction.
The application should write into * this bit, only after making sure that neither the * DMA engine is reading from the RxFIFO nor the MAC * is writing the data in to the FIFO.
The
* application should wait until the bit is cleared
* before performing any other operations. This bit
* will takes 8 clocks (slowest of PHY or AHB clock)
* to clear.
*/
unsigned rxfflsh : 1;
/** In Token Sequence Learning Queue Flush
* (INTknQFlsh) (Device Only)
*/
unsigned intknqflsh : 1;
/** Host Frame Counter Reset (Host Only)
*
* The application can reset the (micro)frame number
* counter inside the core, using this bit. When the
* (micro)frame counter is reset, the subsequent SOF
* sent out by the core, will have a (micro)frame
* number of 0.
*/
unsigned hstfrm : 1;
/** Hclk Soft Reset
*
* The application uses this bit to reset the control logic in
* the AHB clock domain. Only AHB clock domain pipelines are
* reset.
*/
unsigned hsftrst : 1;
/** Core Soft Reset (CSftRst) (Device and Host)
*
* The application can flush the control logic in the
* entire core using this bit. This bit resets the
* pipelines in the AHB Clock domain as well as the
* PHY Clock domain.
*
* The state machines are reset to an IDLE state, the
* control bits in the CSRs are cleared, all the
* transmit FIFOs and the receive FIFO are flushed.
*
* The status mask bits that control the generation of
* the interrupt, are cleared, to clear the
* interrupt. The interrupt status bits are not
* cleared, so the application can get the status of
* any events that occurred in the core after it has
* set this bit.
*
* Any transactions on the AHB are terminated as soon
* as possible following the protocol. Any
* transactions on the USB are terminated immediately.
*
* The configuration settings in the CSRs are
* unchanged, so the software doesn't have to
* reprogram these registers (Device
* Configuration/Host Configuration/Core System
* Configuration/Core PHY Configuration).
*
* The application can write to this bit, any time it
* wants to reset the core. This is a self clearing
* bit and the core clears this bit after all the
* necessary logic is reset in the core, which may
* take several clocks, depending on the current state
* of the core.
*/
unsigned csftrst : 1;
#else // __BIG_ENDIAN__
/** Core Soft Reset (CSftRst) (Device and Host)
*
* The application can flush the control logic in the
* entire core using this bit. This bit resets the
* pipelines in the AHB Clock domain as well as the
* PHY Clock domain.
*
* The state machines are reset to an IDLE state, the
* control bits in the CSRs are cleared, all the
* transmit FIFOs and the receive FIFO are flushed.
*
* The status mask bits that control the generation of
* the interrupt, are cleared, to clear the
* interrupt. The interrupt status bits are not
* cleared, so the application can get the status of
* any events that occurred in the core after it has
* set this bit.
*
* Any transactions on the AHB are terminated as soon
* as possible following the protocol. Any
* transactions on the USB are terminated immediately.
*
* The configuration settings in the CSRs are
* unchanged, so the software doesn't have to
* reprogram these registers (Device
* Configuration/Host Configuration/Core System
* Configuration/Core PHY Configuration).
*
* The application can write to this bit, any time it
* wants to reset the core. This is a self clearing
* bit and the core clears this bit after all the
* necessary logic is reset in the core, which may
* take several clocks, depending on the current state
* of the core.
*/
unsigned csftrst : 1;
/** Hclk Soft Reset
*
* The application uses this bit to reset the control logic in
* the AHB clock domain. Only AHB clock domain pipelines are
* reset.
*/
unsigned hsftrst : 1;
/** Host Frame Counter Reset (Host Only)
*
* The application can reset the (micro)frame number
* counter inside the core, using this bit. When the
* (micro)frame counter is reset, the subsequent SOF
* sent out by the core, will have a (micro)frame
* number of 0.
*/
unsigned hstfrm : 1;
/** In Token Sequence Learning Queue Flush
* (INTknQFlsh) (Device Only)
*/
unsigned intknqflsh : 1;
/** RxFIFO Flush (RxFFlsh) (Device and Host)
*
* The application can flush the entire Receive FIFO
* using this bit.
The application must first * ensure that the core is not in the middle of a * transaction.
The application should write into * this bit, only after making sure that neither the * DMA engine is reading from the RxFIFO nor the MAC * is writing the data in to the FIFO.
The * application should wait until the bit is cleared * before performing any other operations. This bit * will takes 8 clocks (slowest of PHY or AHB clock) * to clear. */ unsigned rxfflsh : 1; /** TxFIFO Flush (TxFFlsh) (Device and Host). * * This bit is used to selectively flush a single or * all transmit FIFOs. The application must first * ensure that the core is not in the middle of a * transaction.
The application should write into * this bit, only after making sure that neither the * DMA engine is writing into the TxFIFO nor the MAC * is reading the data out of the FIFO.
The * application should wait until the core clears this * bit, before performing any operations. This bit * will takes 8 clocks (slowest of PHY or AHB clock) * to clear. */ unsigned txfflsh : 1; /** TxFIFO Number (TxFNum) (Device and Host). * * This is the FIFO number which needs to be flushed, * using the TxFIFO Flush bit. This field should not * be changed until the TxFIFO Flush bit is cleared by * the core. * - 0x0 : Non Periodic TxFIFO Flush * - 0x1 : Periodic TxFIFO #1 Flush in device mode * or Periodic TxFIFO in host mode * - 0x2 : Periodic TxFIFO #2 Flush in device mode. * - ... * - 0xF : Periodic TxFIFO #15 Flush in device mode * - 0x10: Flush all the Transmit NonPeriodic and * Transmit Periodic FIFOs in the core */ unsigned txfnum : 5; /** Reserved */ unsigned reserved11_29 : 19; /** DMA Request Signal. Indicated DMA request is in * probress. Used for debug purpose. */ unsigned dmareq : 1; /** AHB Master Idle. Indicates the AHB Master State * Machine is in IDLE condition. */ unsigned ahbidle : 1; #endif // __BIG_ENDIAN__ }grstctl_data_b; /** * \brief This union represents the bit fields of the Core Reset Register * (GRSTCTL). Set/clear the bits using the bit fields then write the * d32 value to the register. */ typedef union grstctl_data { /** raw register data */ uint32_t d32; /** register bits */ grstctl_data_b b; } grstctl_t; /** * \brief The register bit fields of the Core Interrupt Mask * Register (GINTMSK). */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned wkupintr : 1; unsigned sessreqintr : 1; unsigned disconnect : 1; unsigned conidstschng : 1; unsigned reserved27 : 1; unsigned ptxfempty : 1; unsigned hcintr : 1; unsigned portintr : 1; unsigned reserved22_23 : 2; unsigned incomplisoout : 1; unsigned incomplisoin : 1; unsigned outepintr : 1; unsigned inepintr : 1; unsigned epmismatch : 1; unsigned reserved16 : 1; unsigned eopframe : 1; unsigned isooutdrop : 1; unsigned enumdone : 1; unsigned usbreset : 1; unsigned usbsuspend : 1; unsigned erlysuspend : 1; unsigned i2cintr : 1; unsigned reserved8 : 1; unsigned goutnakeff : 1; unsigned ginnakeff : 1; unsigned nptxfempty : 1; unsigned rxstsqlvl : 1; unsigned sofintr : 1; unsigned otgintr : 1; unsigned modemismatch : 1; unsigned reserved0 : 1; #else // __BIG_ENDIAN__ unsigned reserved0 : 1; unsigned modemismatch : 1; unsigned otgintr : 1; unsigned sofintr : 1; unsigned rxstsqlvl : 1; unsigned nptxfempty : 1; unsigned ginnakeff : 1; unsigned goutnakeff : 1; unsigned reserved8 : 1; unsigned i2cintr : 1; unsigned erlysuspend : 1; unsigned usbsuspend : 1; unsigned usbreset : 1; unsigned enumdone : 1; unsigned isooutdrop : 1; unsigned eopframe : 1; unsigned reserved16 : 1; unsigned epmismatch : 1; unsigned inepintr : 1; unsigned outepintr : 1; unsigned incomplisoin : 1; unsigned incomplisoout : 1; unsigned reserved22_23 : 2; unsigned portintr : 1; unsigned hcintr : 1; unsigned ptxfempty : 1; unsigned reserved27 : 1; unsigned conidstschng : 1; unsigned disconnect : 1; unsigned sessreqintr : 1; unsigned wkupintr : 1; #endif // __BIG_ENDIAN__ } gintmsk_data_b; /** * \brief This union represents the bit fields of the Core Interrupt Mask * Register (GINTMSK). Set/clear the bits using the bit fields then * write the d32 value to the register. */ typedef union gintmsk_data { /** raw register data */ uint32_t d32; /** register bits */ gintmsk_data_b b; } gintmsk_data_t; /** * \brief This register bit fields of the Core Interrupt Register * (GINTSTS). */ typedef struct { #define DWC_HOST_MODE 1 // winder add. #if defined(__BIG_ENDIAN__) unsigned wkupintr : 1; //31 unsigned sessreqintr : 1; //30 unsigned disconnect : 1; //29 unsigned conidstschng : 1; //28 unsigned reserved27 : 1; //27 unsigned ptxfempty : 1; //26 unsigned hcintr : 1; //25 unsigned portintr : 1; //24 unsigned reserved22_23 : 2;//223 unsigned incomplisoout : 1;//21 unsigned incomplisoin : 1; //20 unsigned outepintr : 1; //19 unsigned inepint: 1; //18 unsigned epmismatch : 1; //17 unsigned intokenrx : 1; //16 unsigned eopframe : 1; //15 unsigned isooutdrop : 1; //14 unsigned enumdone : 1; //13 unsigned usbreset : 1; //12 unsigned usbsuspend : 1; //11 unsigned erlysuspend : 1; //10 unsigned i2cintr : 1; //09 unsigned reserved8 : 1; //08 unsigned goutnakeff : 1; //07 unsigned ginnakeff : 1; //06 unsigned nptxfempty : 1; //05 unsigned rxstsqlvl : 1; //04 unsigned sofintr : 1; //03 unsigned otgintr : 1; //02 unsigned modemismatch : 1; //01 unsigned curmode : 1; //00 #else // __BIG_ENDIAN__ unsigned curmode : 1; unsigned modemismatch : 1; unsigned otgintr : 1; unsigned sofintr : 1; unsigned rxstsqlvl : 1; unsigned nptxfempty : 1; unsigned ginnakeff : 1; unsigned goutnakeff : 1; unsigned reserved8 : 1; unsigned i2cintr : 1; unsigned erlysuspend : 1; unsigned usbsuspend : 1; unsigned usbreset : 1; unsigned enumdone : 1; unsigned isooutdrop : 1; unsigned eopframe : 1; unsigned intokenrx : 1; unsigned epmismatch : 1; unsigned inepint: 1; unsigned outepintr : 1; unsigned incomplisoin : 1; unsigned incomplisoout : 1; unsigned reserved22_23 : 2; unsigned portintr : 1; unsigned hcintr : 1; unsigned ptxfempty : 1; unsigned reserved27 : 1; unsigned conidstschng : 1; unsigned disconnect : 1; unsigned sessreqintr : 1; unsigned wkupintr : 1; #endif // __BIG_ENDIAN__ } gintsts_data_b; /** * \brief This union represents the bit fields of the Core Interrupt Register * (GINTSTS). Set/clear the bits using the bit fields then write the * d32 value to the register. */ typedef union gintsts_data { /** raw register data */ uint32_t d32; #define DWC_SOF_INTR_MASK 0x0008 /** register bits */ gintsts_data_b b; } gintsts_data_t; /** * \brief The register bit fields in the Device Receive Status Read and * Pop Registers (GRXSTSR, GRXSTSP) */ typedef struct { #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet #if defined(__BIG_ENDIAN__) unsigned reserved : 7; unsigned fn : 4; unsigned pktsts : 4; unsigned dpid : 2; unsigned bcnt : 11; unsigned epnum : 4; #else // __BIG_ENDIAN__ unsigned epnum : 4; unsigned bcnt : 11; unsigned dpid : 2; unsigned pktsts : 4; unsigned fn : 4; unsigned reserved : 7; #endif // __BIG_ENDIAN__ } device_grxsts_data_b; /** * \brief This union represents the bit fields in the Device Receive Status Read and * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 * element then read out the bits using the bit elements. */ typedef union device_grxsts_data { /** raw register data */ uint32_t d32; /** register bits */ device_grxsts_data_b b; } device_grxsts_data_t; /** * \brief The register bit fields in the Host Receive Status Read and * Pop Registers (GRXSTSR, GRXSTSP). */ typedef struct { #if defined(__BIG_ENDIAN__) unsigned reserved : 11; unsigned pktsts : 4; unsigned dpid : 2; unsigned bcnt : 11; unsigned chnum : 4; #else // __BIG_ENDIAN__ unsigned chnum : 4; unsigned bcnt : 11; unsigned dpid : 2; unsigned pktsts : 4; unsigned reserved : 11; #endif // __BIG_ENDIAN__ } host_grxsts_data_b; /** * \brief This union represents the bit fields in the Host Receive Status Read and * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 * element then read out the bits using the bit elements. */ typedef union host_grxsts_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_GRXSTS_PKTSTS_IN 0x2 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 host_grxsts_data_b b; } host_grxsts_data_t; /** * \brief The bit fields in the FIFO Size Registers (HPTXFSIZ, * GNPTXFSIZ, DPTXFSIZn). */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned depth : 16; unsigned startaddr : 16; #else // __BIG_ENDIAN__ unsigned startaddr : 16; unsigned depth : 16; #endif // __BIG_ENDIAN__ } fifosize_data_b; /** * \brief This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, * GNPTXFSIZ, DPTXFSIZn). Read the register into the d32 element then * read out the bits using the bit elements. */ typedef union fifosize_data { /** raw register data */ uint32_t d32; /** register bits */ fifosize_data_b b; } fifosize_data_t; /** * \brief The bit fields in the Non-Periodic Transmit * FIFO/Queue Status Register (GNPTXSTS). */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 1; /** Top of the Non-Periodic Transmit Request Queue * - bit 24 - Terminate (Last entry for the selected * channel/EP) * - bits 26:25 - Token Type * - 2'b00 - IN/OUT * - 2'b01 - Zero Length OUT * - 2'b10 - PING/Complete Split * - 2'b11 - Channel Halt * - bits 30:27 - Channel/EP Number */ unsigned nptxqtop_chnep : 4; unsigned nptxqtop_token : 2; unsigned nptxqtop_terminate : 1; unsigned nptxqspcavail : 8; unsigned nptxfspcavail : 16; #else // __BIG_ENDIAN__ unsigned nptxfspcavail : 16; unsigned nptxqspcavail : 8; /** Top of the Non-Periodic Transmit Request Queue * - bit 24 - Terminate (Last entry for the selected * channel/EP) * - bits 26:25 - Token Type * - 2'b00 - IN/OUT * - 2'b01 - Zero Length OUT * - 2'b10 - PING/Complete Split * - 2'b11 - Channel Halt * - bits 30:27 - Channel/EP Number */ unsigned nptxqtop_terminate : 1; unsigned nptxqtop_token : 2; unsigned nptxqtop_chnep : 4; unsigned reserved : 1; #endif // __BIG_ENDIAN__ }gnptxsts_data_b; /** * \brief This union represents the bit fields in the Non-Periodic Transmit * FIFO/Queue Status Register (GNPTXSTS). Read the register into the * d32 element then read out the bits using the bit * elements. */ typedef union gnptxsts_data { /** raw register data */ uint32_t d32; /** register bits */ gnptxsts_data_b b; } gnptxsts_data_t; /** * \brief The bit fields in the I2C Control Register * (I2CCTL). */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned bsydne : 1; unsigned rw : 1; unsigned reserved : 2; unsigned i2cdevaddr : 2; unsigned i2csuspctl : 1; unsigned ack : 1; unsigned i2cen : 1; unsigned addr : 7; unsigned regaddr : 8; unsigned rwdata : 8; #else // __BIG_ENDIAN__ unsigned rwdata : 8; unsigned regaddr : 8; unsigned addr : 7; unsigned i2cen : 1; unsigned ack : 1; unsigned i2csuspctl : 1; unsigned i2cdevaddr : 2; unsigned reserved : 2; unsigned rw : 1; unsigned bsydne : 1; #endif // __BIG_ENDIAN__ } gi2cctl_data_b; /** * \brief This union represents the bit fields in the I2C Control Register * (I2CCTL). Read the register into the d32 element then read out the * bits using the bit elements. */ typedef union gi2cctl_data { /** raw register data */ uint32_t d32; /** register bits */ gi2cctl_data_b b; } gi2cctl_data_t; /** * \brief The bit fields in the User HW Config1 * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned ep_dir15 : 2; unsigned ep_dir14 : 2; unsigned ep_dir13 : 2; unsigned ep_dir12 : 2; unsigned ep_dir11 : 2; unsigned ep_dir10 : 2; unsigned ep_dir9 : 2; unsigned ep_dir8 : 2; unsigned ep_dir7 : 2; unsigned ep_dir6 : 2; unsigned ep_dir5 : 2; unsigned ep_dir4 : 2; unsigned ep_dir3 : 2; unsigned ep_dir2 : 2; unsigned ep_dir1 : 2; unsigned ep_dir0 : 2; #else // __BIG_ENDIAN__ unsigned ep_dir0 : 2; unsigned ep_dir1 : 2; unsigned ep_dir2 : 2; unsigned ep_dir3 : 2; unsigned ep_dir4 : 2; unsigned ep_dir5 : 2; unsigned ep_dir6 : 2; unsigned ep_dir7 : 2; unsigned ep_dir8 : 2; unsigned ep_dir9 : 2; unsigned ep_dir10 : 2; unsigned ep_dir11 : 2; unsigned ep_dir12 : 2; unsigned ep_dir13 : 2; unsigned ep_dir14 : 2; unsigned ep_dir15 : 2; #endif // __BIG_ENDIAN__ }hwcfg1_data_b; /** * \brief This union represents the bit fields in the User HW Config1 * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ typedef union hwcfg1_data { /** raw register data */ uint32_t d32; /** register bits */ hwcfg1_data_b b; } hwcfg1_data_t; /** * \brief The bit fields in the User HW Config2 * Register. */ typedef struct { /* GHWCFG2 */ // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved31 : 1; unsigned dev_token_q_depth : 5; unsigned host_perio_tx_q_depth : 2; unsigned nonperio_tx_q_depth : 2; unsigned rx_status_q_depth : 2; unsigned dynamic_fifo : 1; unsigned perio_ep_supported : 1; unsigned num_host_chan : 4; unsigned num_dev_ep : 4; unsigned fs_phy_type : 2; unsigned hs_phy_type : 2; unsigned point2point : 1; unsigned architecture : 2; unsigned op_mode : 3; #else // __BIG_ENDIAN__ /* GHWCFG2 */ unsigned op_mode : 3; unsigned architecture : 2; unsigned point2point : 1; unsigned hs_phy_type : 2; unsigned fs_phy_type : 2; unsigned num_dev_ep : 4; unsigned num_host_chan : 4; unsigned perio_ep_supported : 1; unsigned dynamic_fifo : 1; unsigned rx_status_q_depth : 2; unsigned nonperio_tx_q_depth : 2; unsigned host_perio_tx_q_depth : 2; unsigned dev_token_q_depth : 5; unsigned reserved31 : 1; #endif // __BIG_ENDIAN__ } hwcfg2_data_b; /** * \brief This union represents the bit fields in the User HW Config2 * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ typedef union hwcfg2_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 hwcfg2_data_b b; } hwcfg2_data_t; /** * \brief The bit fields in the User HW Config3 * Register. */ typedef struct { /* GHWCFG3 */ // winder add. #if defined(__BIG_ENDIAN__) unsigned dfifo_depth : 16; unsigned reserved15_13 : 3; unsigned ahb_phy_clock_synch : 1; unsigned synch_reset_type : 1; unsigned optional_features : 1; unsigned vendor_ctrl_if : 1; unsigned i2c : 1; unsigned otg_func : 1; unsigned packet_size_cntr_width : 3; unsigned xfer_size_cntr_width : 4; #else // __BIG_ENDIAN__ unsigned xfer_size_cntr_width : 4; unsigned packet_size_cntr_width : 3; unsigned otg_func : 1; unsigned i2c : 1; unsigned vendor_ctrl_if : 1; unsigned optional_features : 1; unsigned synch_reset_type : 1; unsigned ahb_phy_clock_synch : 1; unsigned reserved15_13 : 3; unsigned dfifo_depth : 16; #endif // __BIG_ENDIAN__ } hwcfg3_data_b; /** * \brief This union represents the bit fields in the User HW Config3 * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ typedef union hwcfg3_data { /** raw register data */ uint32_t d32; /** register bits */ hwcfg3_data_b b; } hwcfg3_data_t; /** * \brief The bit fields in the User HW Config4 * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved31_20 : 7; unsigned session_end_filt_en : 1; unsigned b_valid_filt_en : 1; unsigned a_valid_filt_en : 1; unsigned vbus_valid_filt_en : 1; unsigned iddig_filt_en : 1; unsigned num_dev_mode_ctrl_ep : 4; unsigned utmi_phy_data_width : 2; unsigned reserved13_06 : 8; unsigned min_ahb_freq : 1; unsigned power_optimiz : 1; unsigned num_dev_perio_in_ep : 4; #else // __BIG_ENDIAN__ unsigned num_dev_perio_in_ep : 4; unsigned power_optimiz : 1; unsigned min_ahb_freq : 9; unsigned utmi_phy_data_width : 2; unsigned num_dev_mode_ctrl_ep : 4; unsigned iddig_filt_en : 1; unsigned vbus_valid_filt_en : 1; unsigned a_valid_filt_en : 1; unsigned b_valid_filt_en : 1; unsigned session_end_filt_en : 1; unsigned reserved31_20 : 7; // winder change from 12 to 7. #endif // __BIG_ENDIAN__ } hwcfg4_data_b; /** * \brief This union represents the bit fields in the User HW Config4 * Register. Read the register into the d32 element then read * out the bits using the bit elements. */ typedef union hwcfg4_data { /** raw register data */ uint32_t d32; /** register bits */ hwcfg4_data_b b; } hwcfg4_data_t; //////////////////////////////////////////// // Device Registers /** * \brief Device Global Registers. Offsets 800h-BFFh * * The following structures define the size and relative field offsets * for the Device Mode Registers. * * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ typedef struct dwc_otg_dev_global_regs { /** Device Configuration Register. Offset 800h */ volatile uint32_t dcfg; /** Device Control Register. Offset: 804h */ volatile uint32_t dctl; /** Device Status Register (Read Only). Offset: 808h */ volatile uint32_t dsts; /** Reserved. Offset: 80Ch */ uint32_t unused; /** Device IN Endpoint Common Interrupt Mask * Register. Offset: 810h */ volatile uint32_t diepmsk; /** Device OUT Endpoint Common Interrupt Mask * Register. Offset: 814h */ volatile uint32_t doepmsk; /** Device All Endpoints Interrupt Register. Offset: 818h */ volatile uint32_t daint; /** Device All Endpoints Interrupt Mask Register. Offset: * 81Ch */ volatile uint32_t daintmsk; /** Device IN Token Queue Read Register-1 (Read Only). * Offset: 820h */ volatile uint32_t dtknqr1; /** Device IN Token Queue Read Register-2 (Read Only). * Offset: 824h */ volatile uint32_t dtknqr2; /** Device VBUS discharge Register. Offset: 828h */ volatile uint32_t dvbusdis; /** Device VBUS Pulse Register. Offset: 82Ch */ volatile uint32_t dvbuspulse; /** Device IN Token Queue Read Register-3 (Read Only). * Offset: 830h */ volatile uint32_t dtknqr3; /** Device IN Token Queue Read Register-4 (Read Only). * Offset: 834h */ volatile uint32_t dtknqr4; } dwc_otg_device_global_regs_t; /** * \brief The bit fields in the Device Configuration * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved31_23 : 9; /** In Endpoint Mis-match count */ unsigned epmscnt : 5; unsigned reserved13_17 : 5; /** Periodic Frame Interval */ unsigned perfrint : 2; /** Device Addresses */ unsigned devaddr : 7; unsigned reserved3 : 1; /** Non Zero Length Status OUT Handshake */ unsigned nzstsouthshk : 1; /** Device Speed */ unsigned devspd : 2; #else // __BIG_ENDIAN__ /** Device Speed */ unsigned devspd : 2; /** Non Zero Length Status OUT Handshake */ unsigned nzstsouthshk : 1; unsigned reserved3 : 1; /** Device Addresses */ unsigned devaddr : 7; /** Periodic Frame Interval */ unsigned perfrint : 2; unsigned reserved13_17 : 5; /** In Endpoint Mis-match count */ unsigned epmscnt : 4; #endif // __BIG_ENDIAN__ } dcfg_data_b; /** * \brief This union represents the bit fields in the Device Configuration * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. Write the * d32 member to the dcfg register. */ typedef union dcfg_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_DCFG_FRAME_INTERVAL_80 0 #define DWC_DCFG_FRAME_INTERVAL_85 1 #define DWC_DCFG_FRAME_INTERVAL_90 2 #define DWC_DCFG_FRAME_INTERVAL_95 3 #define DWC_DCFG_SEND_STALL 1 dcfg_data_b b; } dcfg_data_t; /** * \brief The bit fields in the Device Control * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 20; /** Power-On Programming Done */ unsigned pwronprgdone : 1; /** Clear Global OUT NAK */ unsigned cgoutnak : 1; /** Set Global OUT NAK */ unsigned sgoutnak : 1; /** Clear Global Non-Periodic IN NAK */ unsigned cgnpinnak : 1; /** Set Global Non-Periodic IN NAK */ unsigned sgnpinnak : 1; /** Test Control */ unsigned tstctl : 3; /** Global OUT NAK Status */ unsigned goutnaksts : 1; /** Global Non-Periodic IN NAK Status */ unsigned gnpinnaksts : 1; /** Soft Disconnect */ unsigned sftdiscon : 1; /** Remote Wakeup */ unsigned rmtwkupsig : 1; #else // __BIG_ENDIAN__ /** Remote Wakeup */ unsigned rmtwkupsig : 1; /** Soft Disconnect */ unsigned sftdiscon : 1; /** Global Non-Periodic IN NAK Status */ unsigned gnpinnaksts : 1; /** Global OUT NAK Status */ unsigned goutnaksts : 1; /** Test Control */ unsigned tstctl : 3; /** Set Global Non-Periodic IN NAK */ unsigned sgnpinnak : 1; /** Clear Global Non-Periodic IN NAK */ unsigned cgnpinnak : 1; /** Set Global OUT NAK */ unsigned sgoutnak : 1; /** Clear Global OUT NAK */ unsigned cgoutnak : 1; unsigned reserved : 21; #endif // __BIG_ENDIAN__ } dctl_data_b; /** * \brief This union represents the bit fields in the Device Control * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ typedef union dctl_data { /** raw register data */ uint32_t d32; /** register bits */ dctl_data_b b; } dctl_data_t; /** * \brief The bit fields in the Device Status Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved22_31 : 10; /** Frame or Microframe Number of the received SOF */ unsigned soffn : 14; unsigned reserved4_7: 4; /** Erratic Error */ unsigned errticerr : 1; /** Enumerated Speed */ unsigned enumspd : 2; /** Suspend Status */ unsigned suspsts : 1; #else // __BIG_ENDIAN__ /** Suspend Status */ unsigned suspsts : 1; /** Enumerated Speed */ unsigned enumspd : 2; /** Erratic Error */ unsigned errticerr : 1; unsigned reserved4_7: 4; /** Frame or Microframe Number of the received SOF */ unsigned soffn : 14; unsigned reserved22_31 : 10; #endif // __BIG_ENDIAN__ } dsts_data_b; /** * \brief This union represents the bit fields in the Device Status * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ typedef union dsts_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 dsts_data_b b; } dsts_data_t; /** * \brief The bit fields in the Device IN EP Interrupt * Register and the Device IN EP Common Mask Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved07_31 : 25; /** IN Endpoint HAK Effective mask */ unsigned inepnakeff : 1; /** IN Token Received with EP mismatch mask */ unsigned intknepmis : 1; /** IN Token received with TxF Empty mask */ unsigned intktxfemp : 1; /** TimeOUT Handshake mask (non-ISOC EPs) */ unsigned timeout : 1; /** AHB Error mask */ unsigned ahberr : 1; /** Endpoint disable mask */ unsigned epdisabled : 1; /** Transfer complete mask */ unsigned xfercompl : 1; #else // __BIG_ENDIAN__ /** Transfer complete mask */ unsigned xfercompl : 1; /** Endpoint disable mask */ unsigned epdisabled : 1; /** AHB Error mask */ unsigned ahberr : 1; /** TimeOUT Handshake mask (non-ISOC EPs) */ unsigned timeout : 1; /** IN Token received with TxF Empty mask */ unsigned intktxfemp : 1; /** IN Token Received with EP mismatch mask */ unsigned intknepmis : 1; /** IN Endpoint HAK Effective mask */ unsigned inepnakeff : 1; unsigned reserved07_31 : 25; #endif // __BIG_ENDIAN__ } diepint_data_b; /** * \brief This union represents the bit fields in the Device IN EP Interrupt * Register and the Device IN EP Common Mask Register. * * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ typedef union diepint_data { /** raw register data */ uint32_t d32; /** register bits */ diepint_data_b b; } diepint_data_t; /** * This union represents the bit fields in the Device IN EP Common * Interrupt Mask Register. */ typedef union diepint_data diepmsk_data_t; /** * \brief This union represents the bit fields in the Device OUT EP Interrupt * Registerand Device OUT EP Common Interrupt Mask Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved04_31 : 23; unsigned outpkterr : 1; unsigned reserved07 : 1; unsigned back2backsetup : 1; unsigned reserved05 : 1; /** OUT Token Received when Endpoint Disabled */ unsigned outtknepdis : 1; /** Setup Phase Done (contorl EPs) */ unsigned setup : 1; /** AHB Error */ unsigned ahberr : 1; /** Endpoint disable */ unsigned epdisabled : 1; /** Transfer complete */ unsigned xfercompl : 1; #else // __BIG_ENDIAN__ /** Transfer complete */ unsigned xfercompl : 1; /** Endpoint disable */ unsigned epdisabled : 1; /** AHB Error */ unsigned ahberr : 1; /** Setup Phase Done (contorl EPs) */ unsigned setup : 1; unsigned outtknepdis : 1; unsigned reserved05 : 1; unsigned back2backsetup : 1; unsigned reserved07 : 1; unsigned outpkterr : 1; unsigned reserved09_31 : 23; #endif // __BIG_ENDIAN__ } doepint_data_b; /** * \brief This union represents the bit fields in the Device OUT EP Interrupt * Registerand Device OUT EP Common Interrupt Mask Register. * * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ typedef union doepint_data { /** raw register data */ uint32_t d32; /** register bits */ doepint_data_b b; } doepint_data_t; /** * \brief This union represents the bit fields in the Device OUT EP Common * Interrupt Mask Register. */ typedef union doepint_data doepmsk_data_t; /** * \brief The bit fields in the Device All EP Interrupt * Registers. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** OUT Endpoint bits */ unsigned out : 16; /** IN Endpoint bits */ unsigned in : 16; #else // __BIG_ENDIAN__ /** IN Endpoint bits */ unsigned in : 16; /** OUT Endpoint bits */ unsigned out : 16; #endif // __BIG_ENDIAN__ } daint_data_ep; /** * \brief The bit fields in the Device All EP Mask Registers. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** OUT Endpoint bits */ unsigned outep15 : 1; unsigned outep14 : 1; unsigned outep13 : 1; unsigned outep12 : 1; unsigned outep11 : 1; unsigned outep10 : 1; unsigned outep9 : 1; unsigned outep8 : 1; unsigned outep7 : 1; unsigned outep6 : 1; unsigned outep5 : 1; unsigned outep4 : 1; unsigned outep3 : 1; unsigned outep2 : 1; unsigned outep1 : 1; unsigned outep0 : 1; /** IN Endpoint bits */ unsigned inep15 : 1; unsigned inep14 : 1; unsigned inep13 : 1; unsigned inep12 : 1; unsigned inep11 : 1; unsigned inep10 : 1; unsigned inep9 : 1; unsigned inep8 : 1; unsigned inep7 : 1; unsigned inep6 : 1; unsigned inep5 : 1; unsigned inep4 : 1; unsigned inep3 : 1; unsigned inep2 : 1; unsigned inep1 : 1; unsigned inep0 : 1; #else // __BIG_ENDIAN__ /** IN Endpoint bits */ unsigned inep0 : 1; unsigned inep1 : 1; unsigned inep2 : 1; unsigned inep3 : 1; unsigned inep4 : 1; unsigned inep5 : 1; unsigned inep6 : 1; unsigned inep7 : 1; unsigned inep8 : 1; unsigned inep9 : 1; unsigned inep10 : 1; unsigned inep11 : 1; unsigned inep12 : 1; unsigned inep13 : 1; unsigned inep14 : 1; unsigned inep15 : 1; /** OUT Endpoint bits */ unsigned outep0 : 1; unsigned outep1 : 1; unsigned outep2 : 1; unsigned outep3 : 1; unsigned outep4 : 1; unsigned outep5 : 1; unsigned outep6 : 1; unsigned outep7 : 1; unsigned outep8 : 1; unsigned outep9 : 1; unsigned outep10 : 1; unsigned outep11 : 1; unsigned outep12 : 1; unsigned outep13 : 1; unsigned outep14 : 1; unsigned outep15 : 1; #endif // __BIG_ENDIAN__ } daint_data_b; /** * \brief This union represents the bit fields in the Device All EP Interrupt * and Mask Registers. * - Read the register into the d32 member then set/clear the * bits using the bit elements. */ typedef union daint_data { /** raw register data */ uint32_t d32; /** register bits */ daint_data_ep ep; /** register bits */ daint_data_b b; } daint_data_t; /** * \brief The bit fields in the Device IN Token Queue * Read Registers. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** EP Numbers of IN Tokens 0 ... 4 */ unsigned epnums0_5 : 24; /** write pointer has wrapped. */ unsigned wrap_bit : 1; /** Reserved */ unsigned reserved05_06 : 2; /** In Token Queue Write Pointer */ unsigned intknwptr : 5; #else // __BIG_ENDIAN__ /** In Token Queue Write Pointer */ unsigned intknwptr : 5; /** Reserved */ unsigned reserved05_06 : 2; /** write pointer has wrapped. */ unsigned wrap_bit : 1; /** EP Numbers of IN Tokens 0 ... 4 */ unsigned epnums0_5 : 24; #endif // __BIG_ENDIAN__ }dtknq1_data_b; /** * \brief This union represents the bit fields in the Device IN Token Queue * Read Registers. * - Read the register into the d32 member. * - READ-ONLY Register */ typedef union dtknq1_data { /** raw register data */ uint32_t d32; /** register bits */ dtknq1_data_b b; } dtknq1_data_t; /** * \brief Device Logical IN Endpoint-Specific Registers. Offsets * 900h-AFCh * * There will be one set of endpoint registers per logical endpoint * implemented. * * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ typedef struct dwc_otg_dev_in_ep_regs { /** Device IN Endpoint Control Register. Offset:900h + * (ep_num * 20h) + 00h */ volatile uint32_t diepctl; /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ uint32_t reserved04; /** Device IN Endpoint Interrupt Register. Offset:900h + * (ep_num * 20h) + 08h */ volatile uint32_t diepint; /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ uint32_t reserved0C; /** Device IN Endpoint Transfer Size * Register. Offset:900h + (ep_num * 20h) + 10h */ volatile uint32_t dieptsiz; /** Device IN Endpoint DMA Address Register. Offset:900h + * (ep_num * 20h) + 14h */ volatile uint32_t diepdma; /** Reserved. Offset:900h + (ep_num * 20h) + 18h - 900h + * (ep_num * 20h) + 1Ch*/ uint32_t reserved18[2]; } dwc_otg_dev_in_ep_regs_t; /** * \brief Device Logical OUT Endpoint-Specific Registers. Offsets: * B00h-CFCh * * There will be one set of endpoint registers per logical endpoint * implemented. * * These registers are visible only in Device mode and must not be * accessed in Host mode, as the results are unknown. */ typedef struct dwc_otg_dev_out_ep_regs { /** Device OUT Endpoint Control Register. Offset:B00h + * (ep_num * 20h) + 00h */ volatile uint32_t doepctl; /** Device OUT Endpoint Frame number Register. Offset: * B00h + (ep_num * 20h) + 04h */ volatile uint32_t doepfn; /** Device OUT Endpoint Interrupt Register. Offset:B00h + * (ep_num * 20h) + 08h */ volatile uint32_t doepint; /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ uint32_t reserved0C; /** Device OUT Endpoint Transfer Size Register. Offset: * B00h + (ep_num * 20h) + 10h */ volatile uint32_t doeptsiz; /** Device OUT Endpoint DMA Address Register. Offset:B00h * + (ep_num * 20h) + 14h */ volatile uint32_t doepdma; /** Reserved. Offset:B00h + (ep_num * 20h) + 18h - B00h + * (ep_num * 20h) + 1Ch */ uint32_t unused[2]; } dwc_otg_dev_out_ep_regs_t; /** * \brief The bit fields in the Device EP Control * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** Endpoint Enable */ unsigned epena : 1; /** Endpoint Disable */ unsigned epdis : 1; /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) * Writing to this field sets the Endpoint DPID (DPID) * field in this register to DATA1 Set Odd * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) * Writing to this field sets the Even/Odd * (micro)frame (EO_FrNum) field to odd (micro) frame. */ unsigned setd1pid : 1; /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) * Writing to this field sets the Endpoint DPID (DPID) * field in this register to DATA0. Set Even * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) * Writing to this field sets the Even/Odd * (micro)frame (EO_FrNum) field to even (micro) * frame. */ unsigned setd0pid : 1; /** Set NAK */ unsigned snak : 1; /** Clear NAK */ unsigned cnak : 1; /** Tx Fifo Number * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ unsigned txfnum : 4; /** Stall Handshake */ unsigned stall : 1; /** Snoop Mode * OUT EPn/OUT EP0 * IN EPn/IN EP0 - reserved */ unsigned snp : 1; /** Endpoint Type * 2'b00: Control * 2'b01: Isochronous * 2'b10: Bulk * 2'b11: Interrupt */ unsigned eptype : 2; /** NAK Status */ unsigned naksts : 1; /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) * This field contains the PID of the packet going to * be received or transmitted on this endpoint. The * application should program the PID of the first * packet going to be received or transmitted on this * endpoint , after the endpoint is * activated. Application use the SetD1PID and * SetD0PID fields of this register to program either * D0 or D1 PID. * * The encoding for this field is * - 0: D0 * - 1: D1 */ unsigned dpid : 1; /** USB Active Endpoint */ unsigned usbactep : 1; /** Next Endpoint * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ unsigned nextep : 4; /** Maximum Packet Size * IN/OUT EPn * IN/OUT EP0 - 2 bits * 2'b00: 64 Bytes * 2'b01: 32 * 2'b10: 16 * 2'b11: 8 */ unsigned mps : 11; #else // __BIG_ENDIAN__ /** Maximum Packet Size * IN/OUT EPn * IN/OUT EP0 - 2 bits * 2'b00: 64 Bytes * 2'b01: 32 * 2'b10: 16 * 2'b11: 8 */ unsigned mps : 11; /** Next Endpoint * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ unsigned nextep : 4; /** USB Active Endpoint */ unsigned usbactep : 1; /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) * This field contains the PID of the packet going to * be received or transmitted on this endpoint. The * application should program the PID of the first * packet going to be received or transmitted on this * endpoint , after the endpoint is * activated. Application use the SetD1PID and * SetD0PID fields of this register to program either * D0 or D1 PID. * * The encoding for this field is * - 0: D0 * - 1: D1 */ unsigned dpid : 1; /** NAK Status */ unsigned naksts : 1; /** Endpoint Type * 2'b00: Control * 2'b01: Isochronous * 2'b10: Bulk * 2'b11: Interrupt */ unsigned eptype : 2; /** Snoop Mode * OUT EPn/OUT EP0 * IN EPn/IN EP0 - reserved */ unsigned snp : 1; /** Stall Handshake */ unsigned stall : 1; /** Tx Fifo Number * IN EPn/IN EP0 * OUT EPn/OUT EP0 - reserved */ unsigned txfnum : 4; /** Clear NAK */ unsigned cnak : 1; /** Set NAK */ unsigned snak : 1; /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) * Writing to this field sets the Endpoint DPID (DPID) * field in this register to DATA0. Set Even * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) * Writing to this field sets the Even/Odd * (micro)frame (EO_FrNum) field to even (micro) * frame. */ unsigned setd0pid : 1; /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) * Writing to this field sets the Endpoint DPID (DPID) * field in this register to DATA1 Set Odd * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) * Writing to this field sets the Even/Odd * (micro)frame (EO_FrNum) field to odd (micro) frame. */ unsigned setd1pid : 1; /** Endpoint Disable */ unsigned epdis : 1; /** Endpoint Enable */ unsigned epena : 1; #endif // __BIG_ENDIAN__ } depctl_data_b; /** * \brief This union represents the bit fields in the Device EP Control * Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ typedef union depctl_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_DEP0CTL_MPS_64 0 #define DWC_DEP0CTL_MPS_32 1 #define DWC_DEP0CTL_MPS_16 2 #define DWC_DEP0CTL_MPS_8 3 depctl_data_b b; } depctl_data_t; /** * \brief The bit fields in the Device EP Transfer * Size Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 1; /** Multi Count - Periodic IN endpoints */ unsigned mc : 2; /** Packet Count */ unsigned pktcnt : 10; /** Transfer size */ unsigned xfersize : 19; #else // __BIG_ENDIAN__ /** Transfer size */ unsigned xfersize : 19; /** Packet Count */ unsigned pktcnt : 10; /** Multi Count - Periodic IN endpoints */ unsigned mc : 2; unsigned reserved : 1; #endif // __BIG_ENDIAN__ } deptsiz_data_b; /** * \brief This union represents the bit fields in the Device EP Transfer * Size Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ typedef union deptsiz_data { /** raw register data */ uint32_t d32; /** register bits */ deptsiz_data_b b; } deptsiz_data_t; /** * \brief The bit fields in the Device EP 0 Transfer * Size Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved31 : 1; /**Setup Packet Count (DOEPTSIZ0 Only) */ unsigned supcnt : 2; /** Reserved */ unsigned reserved20_28 : 9; /** Packet Count */ unsigned pktcnt : 1; /** Reserved */ unsigned reserved7_18 : 12; /** Transfer size */ unsigned xfersize : 7; #else // __BIG_ENDIAN__ /** Transfer size */ unsigned xfersize : 7; /** Reserved */ unsigned reserved7_18 : 12; /** Packet Count */ unsigned pktcnt : 1; /** Reserved */ unsigned reserved20_28 : 9; /**Setup Packet Count (DOEPTSIZ0 Only) */ unsigned supcnt : 2; unsigned reserved31; #endif // __BIG_ENDIAN__ }deptsiz0_data_b; /** * \brief This union represents the bit fields in the Device EP 0 Transfer * Size Register. Read the register into the d32 member then * set/clear the bits using the bit elements. */ typedef union deptsiz0_data { /** raw register data */ uint32_t d32; /** register bits */ deptsiz0_data_b b ; } deptsiz0_data_t; /** Maximum number of Periodic FIFOs */ #define MAX_PERIO_FIFOS 15 /** Maximum number of Endpoints/HostChannels */ #define MAX_EPS_CHANNELS 16 /** * \brief The dwc_otg_dev_if structure contains information needed to manage * the DWC_otg controller acting in device mode. It represents the * programming view of the device-specific aspects of the controller. */ typedef struct dwc_otg_dev_if { /** Pointer to device Global registers. * Device Global Registers starting at offset 800h */ dwc_otg_device_global_regs_t *dev_global_regs; #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 /** * Device Logical IN Endpoint-Specific Registers 900h-AFCh */ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; #define DWC_DEV_IN_EP_REG_OFFSET 0x900 #define DWC_EP_REG_OFFSET 0x20 /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 /* Device configuration information*/ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ uint8_t num_eps; /**< Number of EPs range: 1-16 (includes EP0) */ uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */ /** Size of periodic FIFOs (Bytes) */ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; } dwc_otg_dev_if_t; ///////////////////////////////////////////////// // Host Mode Register Structures // /** * \brief The Host Global Registers structure defines the size and relative * field offsets for the Host Mode Global Registers. Host Global * Registers offsets 400h-7FFh. */ typedef struct dwc_otg_host_global_regs { /** Host Configuration Register. Offset: 400h */ volatile uint32_t hcfg; /** Host Frame Interval Register. Offset: 404h */ volatile uint32_t hfir; /** Host Frame Number / Frame Remaining Register. Offset: 408h */ volatile uint32_t hfnum; /** Reserved. Offset: 40Ch */ uint32_t reserved40C; /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ volatile uint32_t hptxsts; /** Host All Channels Interrupt Register. Offset: 414h */ volatile uint32_t haint; /** Host All Channels Interrupt Mask Register. Offset: 418h */ volatile uint32_t haintmsk; } dwc_otg_host_global_regs_t; /** * This union represents the bit fields in the Host Configuration Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** Reserved */ unsigned reserved31_03 : 29; /** FS/LS Only Support */ unsigned fslssupp : 1; /** FS/LS Phy Clock Select */ unsigned fslspclksel : 2; #else // __BIG_ENDIAN__ /** FS/LS Phy Clock Select */ unsigned fslspclksel : 2; /** FS/LS Only Support */ unsigned fslssupp : 1; #endif // __BIG_ENDIAN__ } hcfg_data_b; /** * This union represents the bit fields in the Host Configuration Register. * Read the register into the d32 member then set/clear the bits using * the bit elements. Write the d32 member to the hcfg register. */ typedef union hcfg_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_HCFG_30_60_MHZ 0 #define DWC_HCFG_48_MHZ 1 #define DWC_HCFG_6_MHZ 2 hcfg_data_b b; } hcfg_data_t; /** * \brief The bit fields in the Host Frame Remaing/Number * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 16; unsigned frint : 16; #else // __BIG_ENDIAN__ unsigned frint : 16; unsigned reserved : 16; #endif // __BIG_ENDIAN__ } hfir_data_b; /** * \brief This union represents the bit fields in the Host Frame Remaing/Number * Register. */ typedef union hfir_data { /** raw register data */ uint32_t d32; /** register bits */ hfir_data_b b; } hfir_data_t; /** * \brief The bit fields in the Host Frame Remaing/Number * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned frrem : 16; #define DWC_HFNUM_MAX_FRNUM 0x3FFF unsigned frnum : 16; #else // __BIG_ENDIAN__ unsigned frnum : 16; #define DWC_HFNUM_MAX_FRNUM 0x3FFF unsigned frrem : 16; #endif // __BIG_ENDIAN__ } hfnum_data_b; /** * \brief This union represents the bit fields in the Host Frame Remaing/Number * Register. */ typedef union hfnum_data { /** raw register data */ uint32_t d32; /** register bits */ hfnum_data_b b; } hfnum_data_t; typedef union hptxsts_data { /** raw register data */ uint32_t d32; /** register bits */ struct { // winder add. #if defined(__BIG_ENDIAN__) /** Top of the Periodic Transmit Request Queue * - bit 24 - Terminate (last entry for the selected channel) * - bits 26:25 - Token Type * - 2'b00 - Zero length * - 2'b01 - Ping * - 2'b10 - Disable * - bits 30:27 - Channel Number * - bit 31 - Odd/even microframe */ unsigned ptxqtop_odd : 1; unsigned ptxqtop_chnum : 4; unsigned ptxqtop_token : 2; unsigned ptxqtop_terminate : 1; unsigned ptxqspcavail : 8; unsigned ptxfspcavail : 16; #else // __BIG_ENDIAN__ unsigned ptxfspcavail : 16; unsigned ptxqspcavail : 8; /** Top of the Periodic Transmit Request Queue * - bit 24 - Terminate (last entry for the selected channel) * - bits 26:25 - Token Type * - 2'b00 - Zero length * - 2'b01 - Ping * - 2'b10 - Disable * - bits 30:27 - Channel Number * - bit 31 - Odd/even microframe */ unsigned ptxqtop_terminate : 1; unsigned ptxqtop_token : 2; unsigned ptxqtop_chnum : 4; unsigned ptxqtop_odd : 1; #endif // __BIG_ENDIAN__ } b; } hptxsts_data_t; /** * \brief This union represents the bit fields in the Host Port Control and Status * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved19_31 : 13; unsigned prtspd : 2; unsigned prttstctl : 4; unsigned prtpwr : 1; unsigned prtlnsts : 2; unsigned reserved9 : 1; unsigned prtrst : 1; unsigned prtsusp : 1; unsigned prtres : 1; unsigned prtovrcurrchng : 1; unsigned prtovrcurract : 1; unsigned prtenchng : 1; unsigned prtena : 1; unsigned prtconndet : 1; unsigned prtconnsts : 1; #else // __BIG_ENDIAN__ unsigned prtconnsts : 1; unsigned prtconndet : 1; unsigned prtena : 1; unsigned prtenchng : 1; unsigned prtovrcurract : 1; unsigned prtovrcurrchng : 1; unsigned prtres : 1; unsigned prtsusp : 1; unsigned prtrst : 1; unsigned reserved9 : 1; unsigned prtlnsts : 2; unsigned prtpwr : 1; unsigned prttstctl : 4; unsigned prtspd : 2; unsigned reserved19_31 : 13; #endif // __BIG_ENDIAN__ }hprt0_data_b; /** * \brief This union represents the bit fields in the Host Port Control and Status * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. Write the d32 member to the * hprt0 register. */ typedef union hprt0_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2 hprt0_data_b b; } hprt0_data_t; /** * \brief The bit fields in the Host All Interrupt * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 16; unsigned ch15 : 1; unsigned ch14 : 1; unsigned ch13 : 1; unsigned ch12 : 1; unsigned ch11 : 1; unsigned ch10 : 1; unsigned ch9 : 1; unsigned ch8 : 1; unsigned ch7 : 1; unsigned ch6 : 1; unsigned ch5 : 1; unsigned ch4 : 1; unsigned ch3 : 1; unsigned ch2 : 1; unsigned ch1 : 1; unsigned ch0 : 1; #else // __BIG_ENDIAN__ unsigned ch0 : 1; unsigned ch1 : 1; unsigned ch2 : 1; unsigned ch3 : 1; unsigned ch4 : 1; unsigned ch5 : 1; unsigned ch6 : 1; unsigned ch7 : 1; unsigned ch8 : 1; unsigned ch9 : 1; unsigned ch10 : 1; unsigned ch11 : 1; unsigned ch12 : 1; unsigned ch13 : 1; unsigned ch14 : 1; unsigned ch15 : 1; unsigned reserved : 16; #endif // __BIG_ENDIAN__ } haint_data_b; /** * \brief The bit fields in the Host All Interrupt * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 16; unsigned chint : 16; #else // __BIG_ENDIAN__ unsigned chint : 16; unsigned reserved : 16; #endif // __BIG_ENDIAN__ } haint_data_b2; /** * \brief This union represents the bit fields in the Host All Interrupt * Register. */ typedef union haint_data { /** raw register data */ uint32_t d32; /** register bits */ haint_data_b b; /** register bits */ haint_data_b2 b2; } haint_data_t; /** * \brief The bit fields in the Host All Interrupt * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 16; unsigned ch15 : 1; unsigned ch14 : 1; unsigned ch13 : 1; unsigned ch12 : 1; unsigned ch11 : 1; unsigned ch10 : 1; unsigned ch9 : 1; unsigned ch8 : 1; unsigned ch7 : 1; unsigned ch6 : 1; unsigned ch5 : 1; unsigned ch4 : 1; unsigned ch3 : 1; unsigned ch2 : 1; unsigned ch1 : 1; unsigned ch0 : 1; #else // __BIG_ENDIAN__ unsigned ch0 : 1; unsigned ch1 : 1; unsigned ch2 : 1; unsigned ch3 : 1; unsigned ch4 : 1; unsigned ch5 : 1; unsigned ch6 : 1; unsigned ch7 : 1; unsigned ch8 : 1; unsigned ch9 : 1; unsigned ch10 : 1; unsigned ch11 : 1; unsigned ch12 : 1; unsigned ch13 : 1; unsigned ch14 : 1; unsigned ch15 : 1; unsigned reserved : 16; #endif // __BIG_ENDIAN__ } haintmsk_data_b; /** * \brief The bit fields in the Host All Interrupt * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 16; unsigned chint : 16; #else // __BIG_ENDIAN__ unsigned chint : 16; unsigned reserved : 16; #endif // __BIG_ENDIAN__ } haintmsk_data_b2; /** * \brief This union represents the bit fields in the Host All Interrupt * Register. */ typedef union haintmsk_data { /** raw register data */ uint32_t d32; /** register bits */ haintmsk_data_b b; /** register bits */ haintmsk_data_b2 b2; } haintmsk_data_t; /** * \brief Host Channel Specific Registers. 500h-5FCh */ typedef struct dwc_otg_hc_regs { /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ volatile uint32_t hcchar; /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ volatile uint32_t hcsplt; /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ volatile uint32_t hcint; /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ volatile uint32_t hcintmsk; /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ volatile uint32_t hctsiz; /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ volatile uint32_t hcdma; /** Reserved. Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch */ uint32_t reserved[2]; } dwc_otg_hc_regs_t; /** * \brief The bit fields in the Host Channel Characteristics * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** Channel enable */ unsigned chen : 1; /** Channel disable */ unsigned chdis : 1; /** * Frame to transmit periodic transaction. * 0: even, 1: odd */ unsigned oddfrm : 1; /** Device address */ unsigned devaddr : 7; /** Packets per frame for periodic transfers. 0 is reserved. */ unsigned multicnt : 2; /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ unsigned eptype : 2; /** 0: Full/high speed device, 1: Low speed device */ unsigned lspddev : 1; unsigned reserved : 1; /** 0: OUT, 1: IN */ unsigned epdir : 1; /** Endpoint number */ unsigned epnum : 4; /** Maximum packet size in bytes */ unsigned mps : 11; #else // __BIG_ENDIAN__ /** Maximum packet size in bytes */ unsigned mps : 11; /** Endpoint number */ unsigned epnum : 4; /** 0: OUT, 1: IN */ unsigned epdir : 1; unsigned reserved : 1; /** 0: Full/high speed device, 1: Low speed device */ unsigned lspddev : 1; /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ unsigned eptype : 2; /** Packets per frame for periodic transfers. 0 is reserved. */ unsigned multicnt : 2; /** Device address */ unsigned devaddr : 7; /** * Frame to transmit periodic transaction. * 0: even, 1: odd */ unsigned oddfrm : 1; /** Channel disable */ unsigned chdis : 1; /** Channel enable */ unsigned chen : 1; #endif // __BIG_ENDIAN__ } hcchar_data_b; /** * \brief This union represents the bit fields in the Host Channel Characteristics * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. Write the d32 member to the * hcchar register. */ typedef union hcchar_data { /** raw register data */ uint32_t d32; /** register bits */ hcchar_data_b b; } hcchar_data_t; typedef union hcsplt_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_HCSPLIT_XACTPOS_MID 0 #define DWC_HCSPLIT_XACTPOS_END 1 #define DWC_HCSPLIT_XACTPOS_BEGIN 2 #define DWC_HCSPLIT_XACTPOS_ALL 3 struct { // winder add. #if defined(__BIG_ENDIAN__) /** Split Enble */ unsigned spltena : 1; /** Reserved */ unsigned reserved : 14; /** Do Complete Split */ unsigned compsplt : 1; /** Transaction Position */ unsigned xactpos : 2; /** Hub Address */ unsigned hubaddr : 7; /** Port Address */ unsigned prtaddr : 7; #else // __BIG_ENDIAN__ /** Port Address */ unsigned prtaddr : 7; /** Hub Address */ unsigned hubaddr : 7; /** Transaction Position */ unsigned xactpos : 2; /** Do Complete Split */ unsigned compsplt : 1; /** Reserved */ unsigned reserved : 14; /** Split Enble */ unsigned spltena : 1; #endif // __BIG_ENDIAN__ } b; } hcsplt_data_t; /** * \brief The bit fields in the Host All Interrupt * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** Reserved */ unsigned reserved : 21; /** Data Toggle Error */ unsigned datatglerr : 1; /** Frame Overrun */ unsigned frmovrun : 1; /** Babble Error */ unsigned bblerr : 1; /** Transaction Err */ unsigned xacterr : 1; /** NYET Response Received */ unsigned nyet : 1; /** ACK Response Received */ unsigned ack : 1; /** NAK Response Received */ unsigned nak : 1; /** STALL Response Received */ unsigned stall : 1; /** AHB Error */ unsigned ahberr : 1; /** Channel Halted */ unsigned chhltd : 1; /** Transfer Complete */ unsigned xfercomp : 1; #else // __BIG_ENDIAN__ /** Transfer Complete */ unsigned xfercomp : 1; /** Channel Halted */ unsigned chhltd : 1; /** AHB Error */ unsigned ahberr : 1; /** STALL Response Received */ unsigned stall : 1; /** NAK Response Received */ unsigned nak : 1; /** ACK Response Received */ unsigned ack : 1; /** NYET Response Received */ unsigned nyet : 1; /** Transaction Err */ unsigned xacterr : 1; /** Babble Error */ unsigned bblerr : 1; /** Frame Overrun */ unsigned frmovrun : 1; /** Data Toggle Error */ unsigned datatglerr : 1; /** Reserved */ unsigned reserved : 21; #endif // __BIG_ENDIAN__ }hcint_data_b; /** * \brief This union represents the bit fields in the Host All Interrupt * Register. */ typedef union hcint_data { /** raw register data */ uint32_t d32; /** register bits */ hcint_data_b b; } hcint_data_t; /** * \brief The bit fields in the Host Channel Transfer Size * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) /** Do PING protocol when 1 */ unsigned dopng : 1; /** * Packet ID for next data packet * 0: DATA0 * 1: DATA2 * 2: DATA1 * 3: MDATA (non-Control), SETUP (Control) */ unsigned pid : 2; /** Data packets to transfer */ unsigned pktcnt : 10; /** Total transfer size in bytes */ unsigned xfersize : 19; #else // __BIG_ENDIAN__ /** Total transfer size in bytes */ unsigned xfersize : 19; /** Data packets to transfer */ unsigned pktcnt : 10; /** * Packet ID for next data packet * 0: DATA0 * 1: DATA2 * 2: DATA1 * 3: MDATA (non-Control), SETUP (Control) */ unsigned pid : 2; /** Do PING protocol when 1 */ unsigned dopng : 1; #endif // __BIG_ENDIAN__ }hctsiz_data_b; /** * \brief This union represents the bit fields in the Host Channel Transfer Size * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. Write the d32 member to the * hcchar register. */ typedef union hctsiz_data { /** raw register data */ uint32_t d32; /** register bits */ #define DWC_HCTSIZ_DATA0 0 #define DWC_HCTSIZ_DATA1 2 #define DWC_HCTSIZ_DATA2 1 #define DWC_HCTSIZ_MDATA 3 #define DWC_HCTSIZ_SETUP 3 hctsiz_data_b b; } hctsiz_data_t; /** * \brief The bit fields in the Host Channel Interrupt Mask * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 21; unsigned datatglerr : 1; unsigned frmovrun : 1; unsigned bblerr : 1; unsigned xacterr : 1; unsigned nyet : 1; unsigned ack : 1; unsigned nak : 1; unsigned stall : 1; unsigned ahberr : 1; unsigned chhltd : 1; unsigned xfercompl : 1; #else // __BIG_ENDIAN__ unsigned xfercompl : 1; unsigned chhltd : 1; unsigned ahberr : 1; unsigned stall : 1; unsigned nak : 1; unsigned ack : 1; unsigned nyet : 1; unsigned xacterr : 1; unsigned bblerr : 1; unsigned frmovrun : 1; unsigned datatglerr : 1; unsigned reserved : 21; #endif // __BIG_ENDIAN__ }hcintmsk_data_b; /** * \brief This union represents the bit fields in the Host Channel Interrupt Mask * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. Write the d32 member to the * hcintmsk register. */ typedef union hcintmsk_data { /** raw register data */ uint32_t d32; /** register bits */ hcintmsk_data_b b; } hcintmsk_data_t; /** * \brief OTG Host Interface Structure. * * The OTG Host Interface Structure structure contains information * needed to manage the DWC_otg controller acting in host mode. It * represents the programming view of the host-specific aspects of the * controller. */ typedef struct dwc_otg_host_if { /** Host Global Registers starting at offset 400h.*/ dwc_otg_host_global_regs_t *host_global_regs; #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 /** Host Port 0 Control and Status Register */ volatile uint32_t *hprt0; #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 /** Host Channel Specific Registers at offsets 500h-5FCh. */ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 #define DWC_OTG_CHAN_REGS_OFFSET 0x20 /* Host configuration information */ /** Number of Host Channels (range: 1-16) */ uint8_t num_host_channels; /** Periodic EPs supported (0: no, 1: yes) */ uint8_t perio_eps_supported; /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ uint16_t perio_tx_fifo_size; } dwc_otg_host_if_t; /** * \brief The bit fields in the Power and Clock Gating Control * Register. */ typedef struct { // winder add. #if defined(__BIG_ENDIAN__) unsigned reserved : 27; /** PHY Suspended */ unsigned physuspended : 1; /** Reset Power Down Modules */ unsigned rstpdwnmodule : 1; /** Power Clamp */ unsigned pwrclmp : 1; /** Gate Hclk */ unsigned gatehclk : 1; /** Stop Pclk */ unsigned stoppclk : 1; #else // __BIG_ENDIAN__ /** Stop Pclk */ unsigned stoppclk : 1; /** Gate Hclk */ unsigned gatehclk : 1; /** Power Clamp */ unsigned pwrclmp : 1; /** Reset Power Down Modules */ unsigned rstpdwnmodule : 1; /** PHY Suspended */ unsigned physuspended : 1; unsigned reserved : 27; #endif // __BIG_ENDIAN__ } pcgcctl_data_b; /** * \brief This union represents the bit fields in the Power and Clock Gating Control * Register. Read the register into the d32 member then set/clear the * bits using the bit elements. */ typedef union pcgcctl_data { /** raw register data */ uint32_t d32; /** register bits */ pcgcctl_data_b b; } pcgcctl_data_t; #endif