/* Copyright (C) 2006 Ikanos Communications * See IKANOS_PROP_LICENSE.txt for license information. */ #include /* APU Base addresses from Host (CPE) point of view */ // CHECK ADDRESSES RIGHTNESS #if defined(IS_VX185) && IS_VX185 #define MAC1_BASE_ADDR 0xb9200000 #define MAC2_BASE_ADDR 0xb9210000 #define MAC3_BASE_ADDR 0xb9220000 #define SPA_BASE_ADDR 0xb9230000 #define BMU_BASE_ADDR 0xb9240000 #define PERI_BASE_ADDR 0xb9250000 #define ATM_BASE_ADDR MAC3_BASE_ADDR #define VDSL_BASE_ADDR MAC3_BASE_ADDR #define CLAP1_BASE_ADDR 0xb9260000 #define CLAP2_BASE_ADDR 0xb9270000 #define GIGE_MAC0_BASE_ADDRESS 0xb9160000 #define GIGE_MAC1_BASE_ADDRESS 0xb9170000 #define GIGE_MAC2_BASE_ADDRESS 0xb9180000 #define PERI_CSRS_BASE_ADDRESS 0xb91b0000 #else #if defined(IS_VX180) && IS_VX180 #define MAC1_BASE_ADDR 0xb9260000 #define MAC2_BASE_ADDR 0xb9270000 #else #define MAC1_BASE_ADDR 0xb9110000 #define MAC2_BASE_ADDR 0xb9150000 #endif #define PERI_BASE_ADDR 0xb91a0000 #define MAC3_BASE_ADDR 0xb9190000 #define SPA_BASE_ADDR 0xb9100000 #define BMU_BASE_ADDR 0xb9210000 #define ATM_BASE_ADDR MAC3_BASE_ADDR #define VDSL_BASE_ADDR 0xb9190000 #endif #define DMEM_AREA_OFFSET 0x8000 // Events Host CPU to AP #define CONFIGURATION_EVENT_BIT 0 #define CONFIGURATION_EVENT_VAL (1 << CONFIGURATION_EVENT_BIT) #define CONFIGURATION_EVENT (1 << CONFIGURATION_EVENT_BIT) #define STATISTICS_EVENT_BIT 1 #define STATISTICS_EVENT_VAL (1 << STATISTICS_EVENT_BIT) #define APQOS_EVENT_BIT 4 #define APQOS_EVENT_VAL (1 << APQOS_EVENT_BIT) #if defined(IS_VX185) && IS_VX185 #define AP_DWRR_CONFIG_EVT_BIT 4 #define AP_DWRR_CONFIG_EVT_VAL (1 << AP_DWRR_CONFIG_EVT_BIT) #endif #define BRK_DUMP_INFO_EVENT_BIT 14 #define BRK_DUMP_INFO_EVENT_VAL (1 << BRK_DUMP_INFO_EVENT_BIT) #define DMEM_EXCHANGE_EVENT_BIT 15 #define DMEM_EXCHANGE_EVENT_VAL (1 << DMEM_EXCHANGE_EVENT_BIT) #define AP_SUSPENSION_RESUME_EVENT_BIT 13 #define AP_SUSPENSION_RESUME_EVENT_VAL (1 << AP_SUSPENSION_RESUME_EVENT_BIT) #define AP_SOFT_RESET_EVENT_BIT 12 #define AP_SOFT_RESET_EVENT_VAL (1 << AP_SOFT_RESET_EVENT_BIT) #define AP_TRAFFIC_THROTTLING_EVENT_BIT 11 #define AP_TRAFFIC_THROTTLING_EVENT_VAL (1 << AP_TRAFFIC_THROTTLING_EVENT_BIT) #define AP_VDSL_CONFIG_EVENT_BIT 6 #define AP_VDSL_CONFIG_EVENT_VAL (1 << AP_VDSL_CONFIG_EVENT_BIT) #define AP_XDSL_ATM_CONFIG_EVENT_BIT 6 #define AP_XDSL_ATM_CONFIG_EVENT_VAL (1 << AP_XDSL_ATM_CONFIG_EVENT_BIT) #if defined(IS_VX185) && IS_VX185 #define AP_CLASS_UPDATE_XDSL_EVT_BIT 7 #define AP_CLASS_UPDATE_XDSL_EVT_VAL (1 << AP_CLASS_UPDATE_XDSL_EVT_BIT) /* The same Bit offset is used for both powermanagement & Rx/Tx Control */ #define AP_RX_DMA_FLOW_CTRL_EVENT_BIT 11 #define AP_RX_DMA_FLOW_CTRL_EVENT_VAL (1 << AP_RX_DMA_FLOW_CTRL_EVENT_BIT) #endif #define APQOS_TX_SLBQ_MAP_EVENT_BIT 9 /* only for VDSL AP */ #define APQOS_TX_SLBQ_MAP_EVENT_VAL (1 << APQOS_TX_SLBQ_MAP_EVENT_BIT) #define AP_IPCQQOS_INFO_DOWNLOAD_EVENT_BIT 8 #define AP_IPCQQOS_INFO_DOWNLOAD_EVENT_VAL (1 << AP_IPCQQOS_INFO_DOWNLOAD_EVENT_BIT) // Time out constants for events initiated by Host and responsed by AP #define DONT_WAIT_FOR_RESPONSE 0x0 #define WAIT_TILL_RESPONSE 0xffff #define WAIT_FOR_EVENT_TASK_SLEEP_TIME 0x10 // for AP DMem Read/Write opeartions #define MAX_SIZE_DMEM_EXCHANGE_BLOCK 0x100 #define WRITE_SIGN_BIT 12 // Highest bit that can pass // through dmemStructExchange