--- zzzz-none-000/linux-2.6.28.10/arch/mips/kernel/csrc-r4k.c	2009-05-02 18:54:43.000000000 +0000
+++ fusiv-7390-686/linux-2.6.28.10/arch/mips/kernel/csrc-r4k.c	2010-12-23 14:31:15.000000000 +0000
@@ -15,24 +15,118 @@
 	return read_c0_count();
 }
 
-static struct clocksource clocksource_mips = {
-	.name		= "MIPS",
-	.read		= c0_hpt_read,
-	.mask		= CLOCKSOURCE_MASK(32),
-	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+#define CLOCKSOURCE_DEFAULT         0
+#define CLOCKSOURCE_AR9_111MHZ      1
+#define CLOCKSOURCE_AR9_166MHZ      2
+#define CLOCKSOURCE_AR9_333MHZ      3
+#define CLOCKSOURCE_AR9_393MHZ      4
+#define CLOCKSOURCE_VR9_125MHZ      5
+#define CLOCKSOURCE_VR9_333MHZ      CLOCKSOURCE_AR9_333MHZ
+#define CLOCKSOURCE_VR9_393MHZ      CLOCKSOURCE_AR9_393MHZ
+#define CLOCKSOURCE_VR9_500MHZ      6
+
+struct clocksource clocksource_mips[] = {
+    [CLOCKSOURCE_DEFAULT] = {
+        .name  = "MIPS",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    // AR9-Takte
+    [CLOCKSOURCE_AR9_111MHZ] = {
+        .name  = "MIPS-111",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    [CLOCKSOURCE_AR9_166MHZ] = {
+        .name  = "MIPS-166",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    [CLOCKSOURCE_AR9_333MHZ] = {
+        .name  = "MIPS-333",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    [CLOCKSOURCE_AR9_393MHZ] = {
+        .name  = "MIPS-393",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    // VR9-Takte
+    [CLOCKSOURCE_VR9_125MHZ] = {
+        .name  = "MIPS-125",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    },
+    [CLOCKSOURCE_VR9_500MHZ] = {
+        .name  = "MIPS-500",
+        .read  = c0_hpt_read,
+        .mask  = CLOCKSOURCE_MASK(32),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+    }
 };
 
 int __init init_mips_clocksource(void)
 {
+    int i = 0;
 	if (!cpu_has_counter || !mips_hpt_frequency)
 		return -ENXIO;
 
 	/* Calculate a somewhat reasonable rating value */
-	clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+	clocksource_mips[i].rating = 200 + mips_hpt_frequency / 10000000;
 
-	clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+	clocksource_set_clock(&clocksource_mips[i], mips_hpt_frequency);
 
-	clocksource_register(&clocksource_mips);
+	clocksource_register(&clocksource_mips[i]);
+
+    for(i = 1 ; i < sizeof(clocksource_mips) / sizeof(clocksource_mips[0]) ; i++) {
+        unsigned long int freq;
+        switch(i) {
+#ifdef CONFIG_AR9
+            case CLOCKSOURCE_AR9_111MHZ: 
+                freq = 111111111UL / 2;
+                break;
+            case CLOCKSOURCE_AR9_166MHZ: 
+                freq = 166000000UL / 2;
+                break;
+            case CLOCKSOURCE_AR9_333MHZ: 
+                freq = 333333333UL / 2;
+                break;
+            case CLOCKSOURCE_AR9_393MHZ: 
+                freq = 394715332UL / 2;
+                break;
+#endif /*--- #ifdef CONFIG_AR9 ---*/
+
+#ifdef CONFIG_VR9
+            case CLOCKSOURCE_VR9_125MHZ: 
+                freq = 125000000UL / 2;
+                break;
+            case CLOCKSOURCE_VR9_333MHZ: 
+                freq = 333333333UL / 2;
+                break;
+            case CLOCKSOURCE_VR9_393MHZ: 
+                freq = 394715332UL / 2;
+                break;
+            case CLOCKSOURCE_VR9_500MHZ: 
+                freq = 500000000UL / 2;
+                break;
+#endif /*--- #ifdef CONFIG_VR9 ---*/
+            default:
+                freq = 0;
+                break;
+        }
+        if (freq) {
+            clocksource_mips[i].rating = 200 + freq / 1000000;
+            clocksource_set_clock(&clocksource_mips[i], freq );
+            clocksource_register(&clocksource_mips[i]);
+        }
+    }
 
 	return 0;
 }