/*
 *
 *   Copyright (C) 2016 AVM GmbH <fritzbox_info@avm.de>
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef _AVM_GIC_FIQ_H_
#define _AVM_GIC_FIQ_H_

#include <asm/avm_enh/avm_gic.h>
#include <asm/avm_enh/avm_smc_ids.h>

#define _ENABLE_SET_      1
#define _ENABLE_CLEAR_    1
#define _PENDING_SET_     1
#define _PENDING_CLEAR_   1
#define _TARGET_BITS_     8
#define _PRIORITY_BITS_   8
#define _CONFIG_BITS_     2
#define _SECURE_BITS_     1

#define groups_per_word(bits_per_group)   (32 / bits_per_group)
#define reg_offset(pinNr, bits_per_group) \
		((pinNr / (groups_per_word(bits_per_group))) << 2)
#define group(pinNr, bits_per_group) \
		(pinNr & ((groups_per_word(bits_per_group)) - 1))
#define to_shift(pinNr, bits_per_group) \
		((group(pinNr, bits_per_group)) * bits_per_group)
#define group_mask(bits_per_group) \
		((1U << bits_per_group) - 1)

typedef enum gic_reg_atomic_e {
	IS_NOT_ATOMIC,
	IS_ATOMIC
} gic_reg_atomic_t;


void avm_gic_fiq_init(void);

unsigned int avm_gic_fiq_nr_ints(void);
void __iomem *avm_gic_fiq_dist_base(void);
void __iomem *avm_gic_fiq_cpu_base(void);
unsigned int avm_gic_fiq_virq(unsigned int hwirq);
void reinit_GIC(void);

void avm_gic_fiq_enable(unsigned int pinNr, unsigned int cpu);
void avm_gic_fiq_disable(unsigned int pinNr, unsigned int cpu);
void avm_gic_fiq_configure(unsigned int pinNr, const struct cpumask *cpumask,
			   unsigned int prio, unsigned int config,
			   unsigned int mode);

static inline void __rte_gicd_write(uint32_t offset, uint32_t data)
{
	unsigned long arg1 = offset;
	unsigned long arg2 = data;

	asm volatile(
			".arch_extension sec\n"
			"mov	r0, %0\n"
			"mov	r1, %1\n"
			"mov	r2, %2\n"
			"smc	#0	@ switch to secure world\n"
			:
			: "r" (AVM_SMC_GICD_WRITE), "r" (arg1), "r" (arg2)
			: "r0", "r1", "r2", "memory", "cc"
			);
}

#define __write_en_gic_pin(pinNr, regtype, bits_to_use, val, is_atomic)	\
	(__rte_gicd_write((u32)(regtype + reg_offset(pinNr, bits_to_use)), \
	((val & (group_mask(bits_to_use))) << (to_shift(pinNr, bits_to_use)))))


static inline void __set_ICDISPR(unsigned int pinNr, unsigned int val,
					gic_reg_atomic_t is_atomic)
{
	__write_en_gic_pin(pinNr, OFFSET_ICDISPR, _PENDING_SET_, val,
				is_atomic);
}

void set_ICDISPR(unsigned int pinNr, unsigned int val,
				gic_reg_atomic_t is_atomic);
void avm_gic_fiq_raise_irq(unsigned int pinNr);
int avm_gic_fiq_is(unsigned int pinNr);
unsigned int avm_gic_fiq_get_ICCHPIR(void);
unsigned int get_ICDIPTR(unsigned int pinNr,
				gic_reg_atomic_t is_atomic);
void set_ICDIPTR(unsigned int pinNr, unsigned int val,
				gic_reg_atomic_t is_atomic);
void set_ICDICPR(unsigned int pinNr, unsigned int val,
				gic_reg_atomic_t is_atomic);
unsigned int get_ICDIPR(unsigned int pinNr,
				gic_reg_atomic_t is_atomic);
void set_ICDIPR(unsigned int pinNr, unsigned int val,
				gic_reg_atomic_t is_atomic);
unsigned int get_ICCIAR(gic_reg_atomic_t is_atomic);
void set_ICCEOIR(unsigned int val, unsigned int is_atomic);
unsigned int get_ICCPMR(gic_reg_atomic_t is_atomic);
void set_ICCPMR(unsigned int val, gic_reg_atomic_t is_atomic);

void set_ICDICER(unsigned int pinNr, unsigned int val,
					gic_reg_atomic_t is_atomic);
void set_ICDISER(unsigned int pinNr, unsigned int val,
					gic_reg_atomic_t is_atomic);
void set_ICCICR(unsigned int val);
unsigned int get_ICCIAR(gic_reg_atomic_t is_atomic);

#endif // #ifndef _AVM_GIC_FIQ_H_