/dts-v1/; /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include "qcom-ipq807x-soc.dtsi" #include "qcom-ipq807x-audio.dtsi" #include "qcom-ipq807x-hk-cpu.dtsi" #include "qcom-ipq807x-avm-common.dtsi" #include "../../../../include/linux/avm_hw_config_def.h" / { model = "AVM FRITZ!Box 4060"; avm_netdev_map { compatible = "avm,port_netdev"; lan1 { netdev = "eth0"; }; lan2 { netdev = "eth1"; }; lan3 { netdev = "eth2"; }; wan { netdev = "wan"; wanport; }; }; avm-rt-framework { compatible = "avm,rt_framework"; ipi-gic-sgi = <9>, <10>, <11>, <12>, <13>, <14>; }; }; &soc { mdio@90000 { #address-cells = <1>; #size-cells = <0>; pinctrl-0 = <&mdio_pins>; pinctrl-names = "default"; phy-reset-gpio = <&tlmm 37 0 &tlmm 43 1>; phy0: ethernet-phy@0 { reg = <0>; }; phy1: ethernet-phy@1 { reg = <1>; }; phy2: ethernet-phy@2 { reg = <2>; }; phy3: ethernet-phy@3 { reg = <3>; }; phy4: ethernet-phy@4 { reg = <4>; }; phy5: ethernet-phy@5 { reg = <28>; }; }; ess-switch@3a000000 { switch_cpu_bmp = <0x1>; /* cpu port bitmap */ switch_lan_bmp = <0x4E>; /* lan port bitmap */ switch_wan_bmp = <0x00>; /* wan port bitmap */ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0 - PORT_WRAPPER_PSGMII */ switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1 - PORT_WRAPPER_MAX */ switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2 - PORT_WRAPPER_SGMII_CHANNEL0 */ /* qca808x on uniphy2 supports SGMII and SGMII+ */ /* TODO: Setting this to 1 (enterprise) somehow blocks tx path * for ethernet? Why? */ bm_tick_mode = <0>; /* bm tick mode */ tm_tick_mode = <0>; /* tm tick mode */ link-polling-required = <1>; qcom,port_phyinfo { /* * Ports 3 and 4 are unused, but still need to have nodes * here because of qsdk init quirks. */ port@0 { port_id = <1>; phy_address = <0>; }; port@1 { port_id = <2>; phy_address = <1>; }; port@2 { port_id = <3>; phy_address = <2>; }; port@3 { /* unused */ port_id = <4>; phy_address = <3>; }; port@4 { /* unused */ port_id = <5>; phy_address = <4>; }; port@5 { port_id = <6>; phy_address = <28>; port_mac_sel = "QGMAC_PORT"; }; }; }; dp1 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <1>; reg = <0x3a001000 0x200>; qcom,mactype = <0>; /* QCOM GMAC */ local-mac-address = [000000000000]; macname = "maca"; devname = "eth2"; qcom,link-poll = <1>; qcom,phy-mdio-addr = <0>; phy-mode = "sgmii"; }; dp2 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <2>; reg = <0x3a001200 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; macname = "macb"; devname = "eth1"; qcom,link-poll = <1>; qcom,phy-mdio-addr = <1>; phy-mode = "sgmii"; }; dp3 { device_type = "network"; compatible = "qcom,nss-dp"; qcom,id = <3>; reg = <0x3a001400 0x200>; qcom,mactype = <0>; local-mac-address = [000000000000]; macname = "usb_rndis_mac"; devname = "eth0"; qcom,link-poll = <1>; qcom,phy-mdio-addr = <2>; phy-mode = "sgmii"; }; dp6 { device_type = "network"; /* Not used? */ compatible = "qcom,nss-dp"; qcom,id = <6>; /* MAC port */ reg = <0x3a007000 0x3fff>; qcom,mactype = <1>; /* Third party 10G/XGMAC */ local-mac-address = [000000000000]; macname = "macdsl"; devname = "wan"; qcom,link-poll = <1>; qcom,phy-mdio-addr = <28>; phy-mode = "sgmii"; /* Not used? */ }; }; &tlmm { pwm_pins: pwm_pinmux { mux_1 { pins = "gpio25"; function = "pwm02"; drive-strength = <8>; }; }; button_pins: button_pins { button_connect { pins = "gpio46"; function = "gpio"; bias-disable; }; }; hsuart_pins: hsuart_pins { mux { pins = "gpio47", "gpio48", "gpio49"; function = "blsp2_uart"; drive-strength = <8>; bias-disable; }; }; }; &serial_blsp4 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; status = "ok"; }; &serial_blsp2 { pinctrl-0 = <&hsuart_pins>; pinctrl-names = "default"; status = "ok"; }; #ifndef __IPQ_MEM_PROFILE_256_MB__ &nss_crypto { status = "ok"; }; #endif &msm_imem { status = "disabled"; }; &ssphy_0 { qcom,emulation = <1>; status = "ok"; }; &qusb_phy_0 { qcom,emulation = <1>; status = "ok"; }; &ssphy_1 { qcom,emulation = <1>; status = "ok"; }; &qusb_phy_1 { qcom,emulation = <1>; status = "ok"; }; &usb3_0 { status = "ok"; }; &usb3_1 { status = "disabled"; }; &cryptobam { status = "ok"; }; &crypto { status = "ok"; }; &i2c_0 { pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; status = "disabled"; }; &i2c_1 { status = "disabled"; }; &sdhc_1 { qcom,clk-rates = <400000 25000000 50000000 100000000 \ 192000000 384000000>; qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; qcom,nonremovable; status = "ok"; }; &qpic_bam { status = "ok"; }; &nand { pinctrl-0 = <&qpic_pins>; pinctrl-names = "default"; status = "disabled"; }; &sdhc_2 { qcom,clk-rates = <400000 25000000 50000000 100000000 \ 192000000>; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; pinctrl-0 = <&sd_pins>; pinctrl-names = "default"; cd-gpios = <&tlmm 63 1>; sd-ldo-gpios = <&tlmm 21 0>; vqmmc-supply = <&ldo11>; status = "ok"; }; &mdio_pins { /* PHY reset pins need to be open drain. */ rst { pins = "gpio37", "gpio43"; function = "gpio"; bias-disable; }; }; &qcom_q6v5_wcss { qcom,nosecure; }; &pcie0 { status = "disabled"; }; &pcie1 { status = "disabled"; };