/dts-v1/;
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "qcom-ipq5018.dtsi"

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Qualcomm Technologies, Inc. IPQ5018/MP-EMU";
	compatible = "qcom,ipq5018-emulation-c2", "qcom,ipq5018";
	interrupt-parent = <&intc>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		serial0 = &blsp1_uart1;
	};

	chosen {
		linux,initrd-end = <0x56000000>;
		linux,initrd-start = <0x54000000>;
		bootargs = "root=/dev/ram0 rw init=/init";
		stdout-path = "serial0";
	};

	soc {
		gcc: gcc@1800000 {
			gcc-use-dummy;
		};

		serial@78af000 {
			status = "ok";
		};

		timer {
			clock-frequency = <240000>;
		};

		qpic_bam: dma@7984000{
			status = "ok";
		};

		nand: qpic-nand@79b0000 {
			status = "ok";
		};

		spi_0: spi@78b5000 { /* BLSP1 QUP0 */
			status = "ok";

			m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0>;
				compatible = "n25q128a11";
				linux,modalias = "m25p80", "n25q128a11";
				spi-max-frequency = <50000000>;
				use-default-sizes;
			};
		};

		ess-instance {
			num_devices = <0x1>;
			#address-cells = <1>;
			#size-cells = <0>;
			ess-switch@0x39c00000 {
				qcom,emulation;
				switch_mac_mode = <0xf>; /* mac mode for uniphy instance*/
				qcom,port_phyinfo {
					port@0 {
						port_id = <1>;
						phy_address = <7>;
		                                forced-speed = <1000>;
                                                forced-duplex = <1>;
					};
					port@1 {
						port_id = <2>;
						phy_address = <1>;
						forced-speed = <1000>;
                                                forced-duplex = <1>;
					};
				};
			};
		};

		wifi0: wifi@c000000 {
			status = "disabled";
		};

		pcie_x1: pci@80000000 {
			is_emulation = <1>;
		};

		pcie_x2: pci@a0000000 {
			is_emulation = <1>;
		};

		nss0: nss@40000000 {
			qcom,low-frequency = <10000000>;
			qcom,mid-frequency = <10000000>;
			qcom,max-frequency = <10000000>;
		};

		dp1 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <1>;
			reg = <0x39C00000 0x10000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			qcom,mactype = <2>;
			local-mac-address = [000000000000];
			phy-mode = "sgmii";
		};

		dp2 {
			device_type = "network";
			compatible = "qcom,nss-dp";
			qcom,id = <2>;
			reg = <0x39D00000 0x10000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			qcom,mactype = <2>;
			local-mac-address = [000000000000];
			phy-mode = "sgmii";
		};

		qcom,test@0 {
			status = "ok";
		};

		pcie_x1_rp {
		        status = "ok";
				#address-cells = <5>;
				#size-cells = <0>;

			mhi_0: qcom,mhi@0 {
				reg = <0 0 0 0 0 >;
				qrtr_instance_id = <0x8001>;
			};
		};

		pcie_x2_rp {
		        status = "ok";
				#address-cells = <5>;
				#size-cells = <0>;

			mhi_1: qcom,mhi@1 {
				reg = <0 0 0 0 0 >;
				qrtr_instance_id = <0x8002>;
			};
		};
	};
};

&sdhc_1 {
	qcom,clk-rates = <400000 25000000 50000000 100000000 \
			 192000000 384000000>;
	qcom,bus-speed-mode = "DDR_1p8v";
	qcom,nonremovable;
	qcom,emulation = <1>;
	status = "ok";
};

&tlmm {
	pinctrl-0 = <&uart_pins>, <&pcie_x1_pins>, <&pcie_x2_pins>;
	pinctrl-names = "default";

	uart_pins: uart_pins {
		mux_0 {
			pins = "gpio20", "gpio21";
			function = "blsp0_uart0";
			bias-pull-down;
		};
		mux_1 {
			pins = "gpio10";
			function = "blsp1_uart0";
			bias-pull-down;
                };
		mux_2 {
			pins = "gpio11", "gpio12";
			function = "blsp1_uart0";
			bias-pull-down;
                };
		mux_3 {
			pins = "gpio13";
			function = "blsp1_uart0";
			bias-pull-down;
		};
	};

	pcie_x1_pins: pcie_x1_pins {
		mux_0 {
			pins = "gpio14";
			function = "gpio";
			output-low;
			bias-pull-down;
			drive-strength = <2>;
		};

		mux_1 {
			pins = "gpio15";
			function = "gpio";
			output-low;
			bias-pull-down;
			drive-strength = <2>;
		};

		mux_2 {
			pins = "gpio16";
			function = "gpio";
			input;
		};
	};

	pcie_x2_pins: pcie_x2_pins {
		mux_0 {
			pins = "gpio17";
			function = "gpio";
			output-low;
			bias-pull-down;
			drive-strength = <2>;
		};

		mux_1 {
			pins = "gpio18";
			function = "gpio";
			output-low;
			bias-pull-down;
			drive-strength = <2>;
		};

		mux_2 {
			pins = "gpio19";
			function = "gpio";
			input;
		};
	};
};

&tmc_etr {
	memory_region = <>;
	status = "disabled";
};

&dwc_0 {
	/delete-property/ snps,quirk-ref-clock-adjustment;
	snps,quirk-ref-clock-period = <0x32>;
	qcom,emulation = <1>;
};